1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PCI_IB_H 28 #define _SYS_PCI_IB_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/ddi_subrdefs.h> 37 #include <sys/pci_tools.h> 38 39 typedef uint8_t ib_ino_t; 40 typedef uint16_t ib_mondo_t; 41 typedef struct ib_ino_info ib_ino_info_t; 42 typedef uint8_t device_num_t; 43 typedef uint8_t interrupt_t; 44 45 /* 46 * interrupt block soft state structure: 47 * 48 * Each pci node may share an interrupt block structure with its peer 49 * node or have its own private interrupt block structure. 50 */ 51 typedef struct ib ib_t; 52 struct ib { 53 54 pci_t *ib_pci_p; /* link back to pci soft state */ 55 pci_ign_t ib_ign; /* interrupt group # */ 56 57 /* 58 * PCI slot and onboard I/O interrupt mapping register blocks addresses: 59 */ 60 uintptr_t ib_slot_intr_map_regs; 61 #define ib_intr_map_regs ib_slot_intr_map_regs 62 uintptr_t ib_obio_intr_map_regs; 63 64 /* 65 * PCI slot and onboard I/O clear interrupt register block addresses: 66 */ 67 uintptr_t ib_slot_clear_intr_regs; 68 uintptr_t ib_obio_clear_intr_regs; 69 70 /* 71 * UPA expansion slot interrupt mapping register addresses: 72 */ 73 volatile uint64_t *ib_upa_imr[2]; 74 uint64_t ib_upa_imr_state[2]; 75 76 /* 77 * Interrupt retry register address: 78 */ 79 volatile uint64_t *ib_intr_retry_timer_reg; 80 81 /* 82 * PCI slot and onboard I/O interrupt state diag register addresses: 83 */ 84 volatile uint64_t *ib_slot_intr_state_diag_reg; 85 volatile uint64_t *ib_obio_intr_state_diag_reg; 86 87 uint_t ib_max_ino; /* largest supported INO */ 88 ib_ino_info_t *ib_ino_lst; /* ino link list */ 89 kmutex_t ib_ino_lst_mutex; /* mutex for ino link list */ 90 kmutex_t ib_intr_lock; /* lock for internal intr */ 91 uint16_t ib_map_reg_counters[8]; /* counters for shared map */ 92 /* registers */ 93 }; 94 95 #define PCI_PULSE_INO 0x80000000 96 #define PSYCHO_MAX_INO 0x3f 97 #define SCHIZO_MAX_INO 0x37 98 #define PCI_INO_BITS 6 /* INO#s are 6 bits long */ 99 #define PCI_IGN_BITS 5 /* IGN#s are 5 bits long */ 100 101 /* 102 * The following structure represents an interrupt entry for an INO. 103 */ 104 typedef struct ih { 105 dev_info_t *ih_dip; /* devinfo structure */ 106 uint32_t ih_inum; /* interrupt number for this device */ 107 uint_t ih_intr_state; /* Only used for fixed interrupts */ 108 uint_t (*ih_handler)(); /* interrupt handler */ 109 caddr_t ih_handler_arg1; /* interrupt handler argument #1 */ 110 caddr_t ih_handler_arg2; /* interrupt handler argument #2 */ 111 ddi_acc_handle_t ih_config_handle; /* config space reg map handle */ 112 struct ih *ih_next; /* next entry in list */ 113 uint64_t ih_ticks; /* ticks spent in this handler */ 114 uint64_t ih_nsec; /* nsec spent in this handler */ 115 kstat_t *ih_ksp; 116 struct ib_ino_info *ih_ino_p; /* only for use by kstat */ 117 } ih_t; 118 119 /* Only used for fixed or legacy interrupts */ 120 #define PCI_INTR_STATE_DISABLE 0 /* disabled */ 121 #define PCI_INTR_STATE_ENABLE 1 /* enabled */ 122 123 /* 124 * ino structure : one per each psycho slot ino with interrupt registered 125 */ 126 struct ib_ino_info { 127 ib_ino_t ino_ino; /* INO number - 8 bit */ 128 uint8_t ino_slot_no; /* PCI slot number 0-8 */ 129 uint16_t ino_ih_size; /* size of the pci intrspec list */ 130 struct ib_ino_info *ino_next; 131 ih_t *ino_ih_head; /* intr spec (part of ppd) list head */ 132 ih_t *ino_ih_tail; /* intr spec (part of ppd) list tail */ 133 ih_t *ino_ih_start; /* starting point in intr spec list */ 134 ib_t *ino_ib_p; /* link back to interrupt block state */ 135 volatile uint64_t *ino_clr_reg; /* ino interrupt clear register */ 136 volatile uint64_t *ino_map_reg; /* ino interrupt mapping register */ 137 uint64_t ino_map_reg_save; /* = *ino_map_reg if saved */ 138 uint32_t ino_pil; /* PIL for this ino */ 139 volatile uint_t ino_unclaimed; /* number of unclaimed interrupts */ 140 clock_t ino_spurintr_begin; /* begin time of spurious intr series */ 141 int ino_established; /* ino has been associated with a cpu */ 142 uint32_t ino_cpuid; /* cpu that ino is targeting */ 143 int32_t ino_intr_weight; /* intr weight of devices sharing ino */ 144 uint64_t ino_mondo; /* store mondo number */ 145 }; 146 147 #define IB_INTR_WAIT 1 /* wait for interrupt completion */ 148 #define IB_INTR_NOWAIT 0 /* already handling intr, no wait */ 149 150 #define IB2CB(ib_p) ((ib_p)->ib_pci_p->pci_cb_p) 151 152 #define IB_MONDO_TO_INO(mondo) ((ib_ino_t)((mondo) & 0x3f)) 153 #define IB_INO_INTR_ON(reg_p) *(reg_p) |= COMMON_INTR_MAP_REG_VALID 154 #define IB_INO_INTR_OFF(reg_p) *(reg_p) &= ~COMMON_INTR_MAP_REG_VALID 155 #define IB_INO_INTR_RESET(reg_p) *(reg_p) = 0ull 156 #define IB_INO_INTR_STATE_REG(ib_p, ino) ((ino) & 0x20 ? \ 157 ib_p->ib_obio_intr_state_diag_reg : ib_p->ib_slot_intr_state_diag_reg) 158 #define IB_INO_INTR_PENDING(reg_p, ino) \ 159 (((*(reg_p) >> (((ino) & 0x1f) << 1)) & COMMON_CLEAR_INTR_REG_MASK) == \ 160 COMMON_CLEAR_INTR_REG_PENDING) 161 #define IB_INO_INTR_CLEAR(reg_p) *(reg_p) = COMMON_CLEAR_INTR_REG_IDLE 162 #define IB_INO_INTR_TRIG(reg_p) *(reg_p) = COMMON_CLEAR_INTR_REG_RECEIVED 163 #define IB_INO_INTR_PEND(reg_p) *(reg_p) = COMMON_CLEAR_INTR_REG_PENDING 164 #define IB_INO_INTR_ISON(imr) ((imr) >> 31) 165 #define IB_IMR2MONDO(imr) \ 166 ((imr) & (COMMON_INTR_MAP_REG_IGN | COMMON_INTR_MAP_REG_INO)) 167 168 #define IB_IS_OBIO_INO(ino) (ino & 0x20) 169 170 #ifdef _STARFIRE 171 /* 172 * returns a uniq ino per interrupt mapping register 173 * For on board devices, inos are not shared. But for plugin devices, 174 * return the 1st ino of the 4 that are sharing the same mapping register. 175 */ 176 #define IB_GET_MAPREG_INO(ino) \ 177 ((volatile uint64_t *)(uintptr_t)((ino & 0x20) ? \ 178 ino : ((ino >> 2) << 2))) 179 #endif /* _STARFIRE */ 180 181 #define IB_IGN_TO_MONDO(ign, ino) (((ign) << PCI_INO_BITS) | (ino)) 182 #define IB_INO_TO_MONDO(ib_p, ino) IB_IGN_TO_MONDO((ib_p)->ib_ign, ino) 183 184 extern void ib_create(pci_t *pci_p); 185 extern void ib_destroy(pci_t *pci_p); 186 extern void ib_configure(ib_t *ib_p); 187 extern uint64_t ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id); 188 extern void ib_intr_enable(pci_t *pci_p, ib_ino_t ino); 189 extern void ib_intr_disable(ib_t *ib_p, ib_ino_t ino, int wait); 190 extern void ib_nintr_clear(ib_t *ib_p, ib_ino_t ino); 191 extern void ib_suspend(ib_t *ib_p); 192 extern void ib_resume(ib_t *ib_p); 193 194 extern ib_ino_info_t *ib_locate_ino(ib_t *ib_p, ib_ino_t ino_num); 195 extern ib_ino_info_t *ib_new_ino(ib_t *ib_p, ib_ino_t ino_num, ih_t *ih_p); 196 extern void ib_delete_ino(ib_t *ib_p, ib_ino_info_t *ino_p); 197 extern void ib_free_ino_all(ib_t *ib_p); 198 extern int ib_update_intr_state(pci_t *pci_p, dev_info_t *rdip, 199 ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state); 200 extern void ib_ino_add_intr(pci_t *pci_p, ib_ino_info_t *ino_p, ih_t *ih_p); 201 extern void ib_ino_rem_intr(pci_t *pci_p, ib_ino_info_t *ino_p, ih_t *ih_p); 202 extern ih_t *ib_ino_locate_intr(ib_ino_info_t *ino_p, dev_info_t *dip, 203 uint32_t inum); 204 extern ih_t *ib_alloc_ih(dev_info_t *dip, uint32_t inum, 205 uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2), 206 caddr_t int_handler_arg1, caddr_t int_handler_arg2); 207 extern void ib_free_ih(ih_t *ih_p); 208 extern void ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino, 209 ib_ino_info_t *ino_p); 210 extern int ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino, 211 ib_ino_info_t *ino_p); 212 extern uint32_t ib_register_intr(ib_t *ib_p, ib_mondo_t mondo, uint_t pil, 213 uint_t (*handler)(caddr_t arg), caddr_t arg); 214 extern void ib_unregister_intr(ib_mondo_t mondo); 215 extern void ib_intr_dist_nintr(ib_t *ib_p, ib_ino_t ino, 216 volatile uint64_t *imr_p); 217 extern void ib_intr_dist_all(void *arg, int32_t max_weight, int32_t weight); 218 extern void ib_cpu_ticks_to_ih_nsec(ib_t *ib_p, ih_t *ih_p, uint32_t cpu_id); 219 extern uint8_t ib_get_ino_devs(ib_t *ib_p, uint32_t ino, uint8_t *devs_ret, 220 pcitool_intr_dev_t *devs); 221 extern void ib_log_new_cpu(ib_t *ib_p, uint32_t old_cpu_id, uint32_t new_cpu_id, 222 uint32_t ino); 223 224 extern int pci_pil[]; 225 226 #ifdef __cplusplus 227 } 228 #endif 229 230 #endif /* _SYS_PCI_IB_H */ 231