1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PCI_IB_H 28 #define _SYS_PCI_IB_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 #include <sys/ddi_subrdefs.h> 37 38 typedef uint8_t ib_ino_t; 39 typedef uint16_t ib_mondo_t; 40 typedef struct ib_ino_info ib_ino_info_t; 41 typedef uint8_t device_num_t; 42 typedef uint8_t interrupt_t; 43 44 /* 45 * interrupt block soft state structure: 46 * 47 * Each pci node may share an interrupt block structure with its peer 48 * node or have its own private interrupt block structure. 49 */ 50 typedef struct ib ib_t; 51 struct ib { 52 53 pci_t *ib_pci_p; /* link back to pci soft state */ 54 pci_ign_t ib_ign; /* interrupt group # */ 55 56 /* 57 * PCI slot and onboard I/O interrupt mapping register blocks addresses: 58 */ 59 uintptr_t ib_slot_intr_map_regs; 60 #define ib_intr_map_regs ib_slot_intr_map_regs 61 uintptr_t ib_obio_intr_map_regs; 62 63 /* 64 * PCI slot and onboard I/O clear interrupt register block addresses: 65 */ 66 uintptr_t ib_slot_clear_intr_regs; 67 uintptr_t ib_obio_clear_intr_regs; 68 69 /* 70 * UPA expansion slot interrupt mapping register addresses: 71 */ 72 volatile uint64_t *ib_upa_imr[2]; 73 uint64_t ib_upa_imr_state[2]; 74 75 /* 76 * Interrupt retry register address: 77 */ 78 volatile uint64_t *ib_intr_retry_timer_reg; 79 80 /* 81 * PCI slot and onboard I/O interrupt state diag register addresses: 82 */ 83 volatile uint64_t *ib_slot_intr_state_diag_reg; 84 volatile uint64_t *ib_obio_intr_state_diag_reg; 85 86 uint_t ib_max_ino; /* largest supported INO */ 87 ib_ino_info_t *ib_ino_lst; /* ino link list */ 88 kmutex_t ib_ino_lst_mutex; /* mutex for ino link list */ 89 kmutex_t ib_intr_lock; /* lock for internal intr */ 90 uint16_t ib_map_reg_counters[8]; /* counters for shared map */ 91 /* registers */ 92 }; 93 94 #define PCI_PULSE_INO 0x80000000 95 #define PSYCHO_MAX_INO 0x3f 96 #define SCHIZO_MAX_INO 0x37 97 #define PCI_INO_BITS 6 /* INO#s are 6 bits long */ 98 #define PCI_IGN_BITS 5 /* IGN#s are 5 bits long */ 99 100 /* 101 * The following structure represents an interrupt entry for an INO. 102 */ 103 typedef struct ih { 104 dev_info_t *ih_dip; /* devinfo structure */ 105 uint32_t ih_inum; /* interrupt number for this device */ 106 uint_t ih_intr_state; /* Only used for fixed interrupts */ 107 uint_t (*ih_handler)(); /* interrupt handler */ 108 caddr_t ih_handler_arg1; /* interrupt handler argument #1 */ 109 caddr_t ih_handler_arg2; /* interrupt handler argument #2 */ 110 ddi_acc_handle_t ih_config_handle; /* config space reg map handle */ 111 struct ih *ih_next; /* next entry in list */ 112 uint64_t ih_ticks; /* ticks spent in this handler */ 113 uint64_t ih_nsec; /* nsec spent in this handler */ 114 kstat_t *ih_ksp; 115 struct ib_ino_info *ih_ino_p; /* only for use by kstat */ 116 } ih_t; 117 118 /* Only used for fixed or legacy interrupts */ 119 #define PCI_INTR_STATE_DISABLE 0 /* disabled */ 120 #define PCI_INTR_STATE_ENABLE 1 /* enabled */ 121 122 /* 123 * ino structure : one per each psycho slot ino with interrupt registered 124 */ 125 struct ib_ino_info { 126 ib_ino_t ino_ino; /* INO number - 8 bit */ 127 uint8_t ino_slot_no; /* PCI slot number 0-8 */ 128 uint16_t ino_ih_size; /* size of the pci intrspec list */ 129 struct ib_ino_info *ino_next; 130 ih_t *ino_ih_head; /* intr spec (part of ppd) list head */ 131 ih_t *ino_ih_tail; /* intr spec (part of ppd) list tail */ 132 ih_t *ino_ih_start; /* starting point in intr spec list */ 133 ib_t *ino_ib_p; /* link back to interrupt block state */ 134 volatile uint64_t *ino_clr_reg; /* ino interrupt clear register */ 135 volatile uint64_t *ino_map_reg; /* ino interrupt mapping register */ 136 uint64_t ino_map_reg_save; /* = *ino_map_reg if saved */ 137 uint32_t ino_pil; /* PIL for this ino */ 138 volatile uint_t ino_unclaimed; /* number of unclaimed interrupts */ 139 clock_t ino_spurintr_begin; /* begin time of spurious intr series */ 140 int ino_established; /* ino has been associated with a cpu */ 141 uint32_t ino_cpuid; /* cpu that ino is targeting */ 142 int32_t ino_intr_weight; /* intr weight of devices sharing ino */ 143 }; 144 145 #define IB_INTR_WAIT 1 /* wait for interrupt completion */ 146 #define IB_INTR_NOWAIT 0 /* already handling intr, no wait */ 147 148 #define IB2CB(ib_p) ((ib_p)->ib_pci_p->pci_cb_p) 149 150 #define IB_MONDO_TO_INO(mondo) ((ib_ino_t)((mondo) & 0x3f)) 151 #define IB_INO_INTR_ON(reg_p) *(reg_p) |= COMMON_INTR_MAP_REG_VALID 152 #define IB_INO_INTR_OFF(reg_p) *(reg_p) &= ~COMMON_INTR_MAP_REG_VALID 153 #define IB_INO_INTR_RESET(reg_p) *(reg_p) = 0ull 154 #define IB_INO_INTR_STATE_REG(ib_p, ino) ((ino) & 0x20 ? \ 155 ib_p->ib_obio_intr_state_diag_reg : ib_p->ib_slot_intr_state_diag_reg) 156 #define IB_INO_INTR_PENDING(reg_p, ino) \ 157 (((*(reg_p) >> (((ino) & 0x1f) << 1)) & COMMON_CLEAR_INTR_REG_MASK) == \ 158 COMMON_CLEAR_INTR_REG_PENDING) 159 #define IB_INO_INTR_CLEAR(reg_p) *(reg_p) = COMMON_CLEAR_INTR_REG_IDLE 160 #define IB_INO_INTR_TRIG(reg_p) *(reg_p) = COMMON_CLEAR_INTR_REG_RECEIVED 161 #define IB_INO_INTR_PEND(reg_p) *(reg_p) = COMMON_CLEAR_INTR_REG_PENDING 162 #define IB_INO_INTR_ISON(imr) ((imr) >> 31) 163 #define IB_IMR2MONDO(imr) \ 164 ((imr) & (COMMON_INTR_MAP_REG_IGN | COMMON_INTR_MAP_REG_INO)) 165 166 #define IB_IS_OBIO_INO(ino) (ino & 0x20) 167 168 #ifdef _STARFIRE 169 /* 170 * returns a uniq ino per interrupt mapping register 171 * For on board devices, inos are not shared. But for plugin devices, 172 * return the 1st ino of the 4 that are sharing the same mapping register. 173 */ 174 #define IB_GET_MAPREG_INO(ino) \ 175 ((volatile uint64_t *)((ino & 0x20) ? ino : ((ino >> 2) << 2))) 176 #endif /* _STARFIRE */ 177 178 #define IB_IGN_TO_MONDO(ign, ino) (((ign) << PCI_INO_BITS) | (ino)) 179 #define IB_INO_TO_MONDO(ib_p, ino) IB_IGN_TO_MONDO((ib_p)->ib_ign, ino) 180 181 extern void ib_create(pci_t *pci_p); 182 extern void ib_destroy(pci_t *pci_p); 183 extern void ib_configure(ib_t *ib_p); 184 extern uint64_t ib_get_map_reg(ib_mondo_t mondo, uint32_t cpu_id); 185 extern void ib_intr_enable(pci_t *pci_p, ib_ino_t ino); 186 extern void ib_intr_disable(ib_t *ib_p, ib_ino_t ino, int wait); 187 extern void ib_nintr_clear(ib_t *ib_p, ib_ino_t ino); 188 extern void ib_suspend(ib_t *ib_p); 189 extern void ib_resume(ib_t *ib_p); 190 191 extern ib_ino_info_t *ib_locate_ino(ib_t *ib_p, ib_ino_t ino_num); 192 extern ib_ino_info_t *ib_new_ino(ib_t *ib_p, ib_ino_t ino_num, ih_t *ih_p); 193 extern void ib_delete_ino(ib_t *ib_p, ib_ino_info_t *ino_p); 194 extern void ib_free_ino_all(ib_t *ib_p); 195 extern int ib_update_intr_state(pci_t *pci_p, dev_info_t *rdip, 196 ddi_intr_handle_impl_t *hdlp, uint_t new_intr_state); 197 extern void ib_ino_add_intr(pci_t *pci_p, ib_ino_info_t *ino_p, ih_t *ih_p); 198 extern void ib_ino_rem_intr(pci_t *pci_p, ib_ino_info_t *ino_p, ih_t *ih_p); 199 extern ih_t *ib_ino_locate_intr(ib_ino_info_t *ino_p, dev_info_t *dip, 200 uint32_t inum); 201 extern ih_t *ib_alloc_ih(dev_info_t *dip, uint32_t inum, 202 uint_t (*int_handler)(caddr_t int_handler_arg1, caddr_t int_handler_arg2), 203 caddr_t int_handler_arg1, caddr_t int_handler_arg2); 204 extern void ib_free_ih(ih_t *ih_p); 205 extern void ib_ino_map_reg_share(ib_t *ib_p, ib_ino_t ino, 206 ib_ino_info_t *ino_p); 207 extern int ib_ino_map_reg_unshare(ib_t *ib_p, ib_ino_t ino, 208 ib_ino_info_t *ino_p); 209 extern uint32_t ib_register_intr(ib_t *ib_p, ib_mondo_t mondo, uint_t pil, 210 uint_t (*handler)(caddr_t arg), caddr_t arg); 211 extern void ib_unregister_intr(ib_mondo_t mondo); 212 extern void ib_intr_dist_nintr(ib_t *ib_p, ib_ino_t ino, 213 volatile uint64_t *imr_p); 214 extern void ib_intr_dist_all(void *arg, int32_t max_weight, int32_t weight); 215 216 extern int pci_pil[]; 217 218 #ifdef __cplusplus 219 } 220 #endif 221 222 #endif /* _SYS_PCI_IB_H */ 223