1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_MMU_H 27 #define _SYS_MMU_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Definitions for the SOFT MMU 37 */ 38 39 #define FAST_IMMU_MISS_TT 0x64 40 #define FAST_DMMU_MISS_TT 0x68 41 #define FAST_PROT_TT 0x6c 42 43 /* 44 * Constants defining alternate spaces 45 * and register layouts within them, 46 * and a few other interesting assembly constants. 47 */ 48 49 /* 50 * vaddr offsets of various registers 51 */ 52 #define MMU_TTARGET 0x00 /* TSB tag target */ 53 #define MMU_PCONTEXT 0x08 /* primary context number */ 54 #define MMU_SCONTEXT 0x10 /* secondary context number */ 55 #define MMU_SFSR 0x18 /* sync fault status reg */ 56 #define MMU_SFAR 0x20 /* sync fault addr reg */ 57 #define MMU_TSB 0x28 /* tsb base and config */ 58 #define MMU_TAG_ACCESS 0x30 /* tlb tag access */ 59 #define MMU_VAW 0x38 /* virtual watchpoint */ 60 #define MMU_PAW 0x40 /* physical watchpoint */ 61 #define MMU_TSB_PX 0x48 /* i/d tsb primary extension reg */ 62 #define MMU_TSB_SX 0x50 /* d tsb secondary extension reg */ 63 #define MMU_TSB_NX 0x58 /* i/d tsb nucleus extension reg */ 64 #define MMU_TAG_ACCESS_EXT 0x60 /* tlb tag access extension reg */ 65 #define MMU_SHARED_CONTEXT 0x68 /* SPARC64-VII shared context */ 66 67 68 69 /* 70 * Synchronous Fault Status Register Layout 71 * 72 * IMMU and DMMU maintain their own SFSR Register 73 * ______________________________________________________________________ 74 * | Reserved | ASI | Reserved | FT | E | Cntx | PRIV | W | OW | FV| 75 * |--------------|------|----------|----|---|------|------|---|----|---| 76 * 63 24 23 16 15 14 13 7 6 5 4 3 2 1 0 77 * 78 */ 79 #define SFSR_FV 0x00000001 /* fault valid */ 80 #define SFSR_OW 0x00000002 /* overwrite */ 81 #define SFSR_W 0x00000004 /* data write */ 82 #define SFSR_PR 0x00000008 /* privilege mode */ 83 #define SFSR_CTX 0x00000030 /* context id */ 84 #define SFSR_E 0x00000040 /* side-effect */ 85 #define SFSR_FT 0x00003F80 /* fault type mask */ 86 #define SFSR_ASI 0x00FF0000 /* ASI */ 87 88 /* 89 * Definition of FT (Fault Type) bit field of sfsr. 90 */ 91 #define FT_NONE 0x00 92 #define FT_PRIV 0x01 /* privilege violation */ 93 #define FT_SPEC_LD 0x02 /* speculative ld to e page */ 94 #define FT_ATOMIC_NC 0x04 /* atomic to nc page */ 95 #define FT_ILL_ALT 0x08 /* illegal lda/sta */ 96 #define FT_NFO 0x10 /* normal access to nfo page */ 97 #define FT_RANGE 0x20 /* dmmu or immu address out of range */ 98 #define FT_RANGE_REG 0x40 /* jump to reg out of range */ 99 #define SFSR_FT_SHIFT 7 /* amt. to shift right to get flt type */ 100 #define X_FAULT_TYPE(x) (((x) & SFSR_FT) >> SFSR_FT_SHIFT) 101 102 /* 103 * Defines for CT (ConText id) bit field of sfsr. 104 */ 105 #define CT_PRIMARY 0x0 /* primary */ 106 #define CT_SECONDARY 0x1 /* secondary */ 107 #define CT_NUCLEUS 0x2 /* nucleus */ 108 #define SFSR_CT_SHIFT 4 109 110 #define SFSR_ASI_SHIFT 16 111 112 /* 113 * MMU TAG TARGET register Layout 114 * 115 * +-----+---------+------+-------------------------+ 116 * | 000 | context | -- | virtual address [63:22] | 117 * +-----+---------+------+-------------------------+ 118 * 63 61 60 48 47 42 41 0 119 */ 120 #define TTARGET_CTX_SHIFT 48 121 #define TTARGET_VA_SHIFT 22 122 123 /* 124 * MMU TAG ACCESS register Layout 125 * 126 * +-------------------------+------------------+ 127 * | virtual address [63:13] | context [12:0] | 128 * +-------------------------+------------------+ 129 * 63 13 12 0 130 */ 131 #define TAGACC_CTX_MASK 0x1FFF 132 #define TAGACC_SHIFT 13 133 #define TAGACC_VADDR_MASK (~TAGACC_CTX_MASK) 134 #define TAGACC_CTX_LSHIFT (64 - TAGACC_SHIFT) 135 136 /* 137 * MMU DEMAP Register Layout 138 * 139 * +-------------------------+------+------+---------+-----+ 140 * | virtual address [63:13] | rsvd | type | context | 0 | 141 * +-------------------------+------+------+---------+-----+ 142 * 63 13 12 8 7 6 5 4 3 0 143 */ 144 #define DEMAP_PRIMARY (CT_PRIMARY << SFSR_CT_SHIFT) 145 #define DEMAP_SECOND (CT_SECONDARY << SFSR_CT_SHIFT) 146 #define DEMAP_NUCLEUS (CT_NUCLEUS << SFSR_CT_SHIFT) 147 #define DEMAP_TYPE_SHIFT 6 148 #define DEMAP_PAGE_TYPE (0 << DEMAP_TYPE_SHIFT) 149 #define DEMAP_CTX_TYPE (1 << DEMAP_TYPE_SHIFT) 150 #define DEMAP_ALL_TYPE (2 << DEMAP_TYPE_SHIFT) 151 152 /* 153 * TLB DATA ACCESS Address Layout 154 * 155 * +-------------+---------------+---+ 156 * + Not used | tlb entry | 0 | 157 * +-------------+---------------+---+ 158 * 63 9 8 3 2 0 159 */ 160 #define DTACC_SHIFT 0x3 161 #define DTACC_INC 0x8 162 163 /* 164 * TSB Register Layout 165 * 166 * split will always be 0. It will not be supported by software. 167 * 168 * +----------------------+-------+-----+-------+ 169 * + tsb_base va [63:13] | split | - | size | 170 * +----------------------+-------+-----+-------+ 171 * 63 13 12 11 3 2 0 172 */ 173 #define TSBBASE_SHIFT 13 174 #define TSB_SZ_MASK 0x7 175 176 /* 177 * MMU TAG READ register Layout 178 * 179 * +-------------------------+------------------+ 180 * | virtual address [63:13] | context [12:0] | 181 * +-------------------------+------------------+ 182 * 63 13 12 0 183 */ 184 #define TAGREAD_CTX_MASK 0x1FFF 185 #define TAGREAD_SHIFT 13 186 #define TAGREAD_VADDR_MASK (~TAGREAD_CTX_MASK) 187 188 /* 189 * MMU TAG ACCESS EXTENSION register Layout 190 * 191 * DTLB only 192 * +-----+-------+-------+-----+ 193 * | - | pgsz1 | pgsz0 | - | 194 * +-----+-------+-------+-----+ 195 * 63 21 19 18 16 15 0 196 */ 197 #define TAGACCEXT_SHIFT 16 198 #define TAGACCEXT_MKSZPAIR(SZ1, SZ0) (((SZ1) << 3) | (SZ0)) 199 200 /* 201 * SPARC64-VII tsb prefetch register layout and VAs 202 * 203 * +-------------------------+-+---------+-+--+------+ 204 * | virtual address [63:13] | | page_sz |V| |TSB_sz| 205 * +-------------------------+-+---------+-+--+------+ 206 * 63 13 11 9 8 5 0 207 */ 208 #define VA_UTSBPREF_8K 0x00 209 #define VA_UTSBPREF_4M 0x08 210 #define VA_KTSBPREF_8K 0x40 211 #define VA_KTSBPREF_4M 0x48 212 213 /* 214 * MMU PRIMARY/SECONDARY CONTEXT register 215 */ 216 #define CTXREG_CTX_MASK 0x1FFF 217 #define CTXREG_CTX_SHIFT 51 218 #define CTXREG_EXT_SHIFT 16 219 #define CTXREG_NEXT_SHIFT 58 220 221 /* 222 * The kernel always runs in KCONTEXT, and no user mappings 223 * are ever valid in it (so any user access pagefaults). 224 */ 225 #define KCONTEXT 0 226 227 /* 228 * FLUSH_ADDR is used in the flush instruction to guarantee stores to mmu 229 * registers complete. It is selected so it won't miss in the tlb. 230 */ 231 #define FLUSH_ADDR (KERNELBASE + 2 * MMU_PAGESIZE4M) 232 233 #ifdef __cplusplus 234 } 235 #endif 236 237 #endif /* _SYS_MMU_H */ 238