xref: /titanic_44/usr/src/uts/sun4u/sys/machsystm.h (revision 56b2bdd1f04d465cfe4a95b88ae5cba5884154e4)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright (c) 1993, 2010, Oracle and/or its affiliates. All rights reserved.
23  */
24 
25 #ifndef _SYS_MACHSYSTM_H
26 #define	_SYS_MACHSYSTM_H
27 
28 /*
29  * Numerous platform-dependent interfaces that don't seem to belong
30  * in any other header file.
31  *
32  * This file should not be included by code that purports to be
33  * platform-independent.
34  */
35 
36 #ifndef _ASM
37 #include <sys/types.h>
38 #include <sys/scb.h>
39 #include <sys/varargs.h>
40 #include <sys/machparam.h>
41 #include <sys/thread.h>
42 #include <vm/seg_enum.h>
43 #include <sys/processor.h>
44 #include <sys/sunddi.h>
45 #include <sys/memlist.h>
46 #include <sys/async.h>
47 #include <sys/errorq.h>
48 #endif /* _ASM */
49 
50 #ifdef __cplusplus
51 extern "C" {
52 #endif
53 
54 #ifdef _KERNEL
55 
56 #ifndef _ASM
57 /*
58  * The following enum types determine how interrupts are distributed
59  * on a sun4u system.
60  */
61 enum intr_policies {
62 	/*
63 	 * Target interrupt at the CPU running the add_intrspec
64 	 * thread. Also used to target all interrupts at the panicing
65 	 * CPU.
66 	 */
67 	INTR_CURRENT_CPU = 0,
68 
69 	/*
70 	 * Target all interrupts at the boot cpu
71 	 */
72 	INTR_BOOT_CPU,
73 
74 	/*
75 	 * Flat distribution of all interrupts
76 	 */
77 	INTR_FLAT_DIST,
78 
79 	/*
80 	 * Weighted distribution of all interrupts
81 	 */
82 	INTR_WEIGHTED_DIST
83 };
84 
85 
86 /*
87  * Structure that defines the interrupt distribution list. It contains
88  * enough info about the interrupt so that it can callback the parent
89  * nexus driver and retarget the interrupt to a different CPU.
90  */
91 struct intr_dist {
92 	struct intr_dist *next;	/* link to next in list */
93 	void (*func)(void *);	/* Callback function */
94 	void *arg;		/* Nexus parent callback arg 1 */
95 };
96 
97 /*
98  * Miscellaneous cpu_state changes
99  */
100 extern void power_down(const char *);
101 extern void do_shutdown(void);
102 
103 /*
104  * Number of seconds until power is shut off
105  */
106 extern int thermal_powerdown_delay;
107 
108 
109 /*
110  * prom-related
111  */
112 extern int obpdebug;
113 extern int forthdebug_supported;
114 extern uint_t tba_taken_over;
115 extern void forthdebug_init(void);
116 extern void init_vx_handler(void);
117 extern void kern_preprom(void);
118 extern void kern_postprom(void);
119 
120 /*
121  * externally (debugger or prom) initiated panic
122  */
123 extern struct regs sync_reg_buf;
124 extern uint64_t sync_tt;
125 extern void sync_handler(void);
126 
127 /*
128  * Trap-related
129  */
130 struct regs;
131 extern void trap(struct regs *rp, caddr_t addr, uint32_t type,
132     uint32_t mmu_fsr);
133 extern void *get_tba(void);
134 extern void *set_tba(void *);
135 extern caddr_t set_trap_table(void);
136 extern struct scb trap_table;
137 
138 struct panic_trap_info {
139 	struct regs *trap_regs;
140 	uint_t	trap_type;
141 	caddr_t trap_addr;
142 	uint_t	trap_mmu_fsr;
143 };
144 
145 /*
146  * misc. primitives
147  */
148 extern void debug_flush_windows(void);
149 extern void flush_windows(void);
150 extern int getprocessorid(void);
151 extern void reestablish_curthread(void);
152 
153 extern void stphys(uint64_t physaddr, int value);
154 extern int ldphys(uint64_t physaddr);
155 extern void stdphys(uint64_t physaddr, uint64_t value);
156 extern uint64_t lddphys(uint64_t physaddr);
157 
158 extern void stphysio(u_longlong_t physaddr, uint_t value);
159 extern uint_t ldphysio(u_longlong_t physaddr);
160 extern void sthphysio(u_longlong_t physaddr, ushort_t value);
161 extern ushort_t ldhphysio(u_longlong_t physaddr);
162 extern void stbphysio(u_longlong_t physaddr, uchar_t value);
163 extern uchar_t ldbphysio(u_longlong_t physaddr);
164 extern void stdphysio(u_longlong_t physaddr, u_longlong_t value);
165 extern u_longlong_t lddphysio(u_longlong_t physaddr);
166 
167 extern int pf_is_dmacapable(pfn_t);
168 
169 extern int dip_to_cpu_id(dev_info_t *dip, processorid_t *cpu_id);
170 
171 extern void set_cmp_error_steering(void);
172 
173 /*
174  * SPARCv9 %ver register and field definitions
175  */
176 
177 #define	ULTRA_VER_MANUF(x)	((x) >> 48)
178 #define	ULTRA_VER_IMPL(x)	(((x) >> 32) & 0xFFFF)
179 #define	ULTRA_VER_MASK(x)	(((x) >> 24) & 0xFF)
180 
181 extern uint64_t ultra_getver(void);
182 
183 /*
184  * bootup-time
185  */
186 extern int ncpunode;
187 extern int niobus;
188 
189 extern void segnf_init(void);
190 extern void kern_setup1(void);
191 extern void startup(void);
192 extern void post_startup(void);
193 extern void install_va_to_tte(void);
194 extern void setwstate(uint_t);
195 extern void create_va_to_tte(void);
196 extern int memscrub_init(void);
197 
198 extern void kcpc_hw_init(void);
199 extern void kcpc_hw_startup_cpu(ushort_t);
200 extern int kcpc_hw_load_pcbe(void);
201 
202 /*
203  * Interrupts
204  */
205 struct cpu;
206 extern struct cpu cpu0;
207 extern struct scb *set_tbr(struct scb *);
208 
209 extern uint_t disable_vec_intr(void);
210 extern void enable_vec_intr(uint_t);
211 extern void setintrenable(int);
212 
213 extern void intr_dist_add(void (*f)(void *), void *);
214 extern void intr_dist_rem(void (*f)(void *), void *);
215 extern void intr_dist_add_weighted(void (*f)(void *, int32_t, int32_t), void *);
216 extern void intr_dist_rem_weighted(void (*f)(void *, int32_t, int32_t), void *);
217 
218 extern uint32_t intr_dist_cpuid(void);
219 
220 void intr_dist_cpuid_add_device_weight(uint32_t cpuid, dev_info_t *dip,
221 		int32_t weight);
222 void intr_dist_cpuid_rem_device_weight(uint32_t cpuid, dev_info_t *dip);
223 
224 extern void intr_redist_all_cpus(void);
225 extern void intr_redist_all_cpus_shutdown(void);
226 
227 extern void send_dirint(int, int);
228 extern void setsoftint(uint64_t);
229 extern void setsoftint_tl1(uint64_t, uint64_t);
230 extern void siron(void);
231 extern void sir_on(int);
232 extern uint64_t getidsr(void);
233 extern void intr_enqueue_req(uint_t pil, uint64_t inum);
234 extern void intr_dequeue_req(uint_t pil, uint64_t inum);
235 extern void wr_clr_softint(uint_t);
236 
237 /*
238  * Time- and %tick-related
239  */
240 extern hrtime_t rdtick(void);
241 extern void tick_write_delta(uint64_t);
242 extern void tickcmpr_set(uint64_t);
243 extern void tickcmpr_reset(void);
244 extern void tickcmpr_disable(void);
245 extern int tickcmpr_disabled(void);
246 extern uint64_t cbe_level14_inum;
247 
248 /*
249  * Caches
250  */
251 extern int vac;
252 extern int cache;
253 extern int use_mp;
254 extern uint_t vac_mask;
255 extern uint64_t ecache_flushaddr;
256 extern int dcache_size;		/* Maximum dcache size */
257 extern int dcache_linesize;	/* Minimum dcache linesize */
258 extern int icache_size;		/* Maximum icache size */
259 extern int icache_linesize;	/* Minimum icache linesize */
260 extern int ecache_alignsize;	/* Maximum ecache linesize for struct align */
261 extern int ecache_size;		/* Maximum ecache size */
262 extern int ecache_associativity;	/* ecache associativity */
263 extern int ecache_setsize;	/* Maximum ecache setsize possible */
264 extern int cpu_setsize;		/* Maximum ecache setsize of configured cpus */
265 
266 /*
267  * VM
268  */
269 extern int do_pg_coloring;
270 extern int use_page_coloring;
271 extern uint_t vac_colors_mask;
272 
273 extern int ndata_alloc_page_freelists(struct memlist *, int);
274 extern int ndata_alloc_dmv(struct memlist *);
275 extern int ndata_alloc_tsbs(struct memlist *, pgcnt_t);
276 extern int ndata_alloc_hat(struct memlist *);
277 extern int ndata_alloc_kpm(struct memlist *, pgcnt_t);
278 extern int ndata_alloc_page_mutexs(struct memlist *ndata);
279 
280 extern size_t calc_pp_sz(pgcnt_t);
281 extern size_t calc_kpmpp_sz(pgcnt_t);
282 extern size_t calc_hmehash_sz(pgcnt_t);
283 extern size_t calc_pagehash_sz(pgcnt_t);
284 extern size_t calc_free_pagelist_sz(void);
285 
286 extern caddr_t alloc_hmehash(caddr_t);
287 extern caddr_t alloc_page_freelists(caddr_t);
288 
289 extern size_t page_ctrs_sz(void);
290 extern caddr_t page_ctrs_alloc(caddr_t);
291 extern void page_freelist_coalesce_all(int);
292 extern void ppmapinit(void);
293 extern void hwblkpagecopy(const void *, void *);
294 extern void hw_pa_bcopy32(uint64_t, uint64_t);
295 
296 extern int pp_slots;
297 extern int pp_consistent_coloring;
298 
299 /*
300  * ppcopy/hwblkpagecopy interaction.  See ppage.c.
301  */
302 #define	PPAGE_STORE_VCOLORING	0x1 /* use vcolors to maintain consistency */
303 #define	PPAGE_LOAD_VCOLORING	0x2 /* use vcolors to maintain consistency */
304 #define	PPAGE_STORES_POLLUTE	0x4 /* stores pollute VAC */
305 #define	PPAGE_LOADS_POLLUTE	0x8 /* loads pollute VAC */
306 
307 /*
308  * VIS-accelerated copy/zero
309  */
310 extern int use_hw_bcopy;
311 extern uint_t hw_copy_limit_1;
312 extern uint_t hw_copy_limit_2;
313 extern uint_t hw_copy_limit_4;
314 extern uint_t hw_copy_limit_8;
315 extern int use_hw_bzero;
316 
317 #ifdef CHEETAH
318 #define	VIS_COPY_THRESHOLD 256
319 #else
320 #define	VIS_COPY_THRESHOLD 900
321 #endif
322 
323 /*
324  * MP
325  */
326 extern void idle_other_cpus(void);
327 extern void resume_other_cpus(void);
328 extern void stop_other_cpus(void);
329 extern void idle_stop_xcall(void);
330 extern void set_idle_cpu(int);
331 extern void unset_idle_cpu(int);
332 extern void mp_cpu_quiesce(struct cpu *);
333 
334 /*
335  * Error handling
336  */
337 extern void set_error_enable(uint64_t neer);
338 extern void set_error_enable_tl1(uint64_t neer, uint64_t action);
339 extern uint64_t get_error_enable(void);
340 extern void get_asyncflt(uint64_t *afsr);
341 extern void set_asyncflt(uint64_t afsr);
342 extern void get_asyncaddr(uint64_t *afar);
343 extern void scrubphys(uint64_t paddr, int ecache_size);
344 extern void clearphys(uint64_t paddr, int ecache_size, int ecache_linesize);
345 extern void flushecacheline(uint64_t paddr, int ecache_size);
346 extern int ce_scrub_xdiag_recirc(struct async_flt *, errorq_t *,
347     errorq_elem_t *, size_t);
348 extern char *flt_to_error_type(struct async_flt *);
349 
350 /*
351  * Panic at TL > 0
352  */
353 extern uint64_t cpu_pa[];
354 extern void ptl1_init_cpu(struct cpu *);
355 
356 /*
357  * Constants which define the "hole" in the 64-bit sfmmu address space.
358  * These are set to specific values by the CPU module code.
359  */
360 extern caddr_t	hole_start, hole_end;
361 
362 /* kpm mapping window */
363 extern size_t	kpm_size;
364 extern uchar_t	kpm_size_shift;
365 extern caddr_t	kpm_vbase;
366 
367 #define	INVALID_VADDR(a)	(((a) >= hole_start && (a) < hole_end))
368 
369 extern void adjust_hw_copy_limits(int);
370 
371 #endif /* _ASM */
372 
373 /*
374  * Actions for set_error_enable_tl1
375  */
376 #define	EER_SET_ABSOLUTE	0x0
377 #define	EER_SET_SETBITS		0x1
378 #define	EER_SET_CLRBITS		0x2
379 
380 #endif /* _KERNEL */
381 
382 #ifdef __cplusplus
383 }
384 #endif
385 
386 #endif	/* _SYS_MACHSYSTM_H */
387