1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_MACHCPUVAR_H 28 #define _SYS_MACHCPUVAR_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <sys/intr.h> 33 #include <sys/clock.h> 34 #include <sys/machparam.h> 35 #include <sys/machpcb.h> 36 #include <sys/privregs.h> 37 #include <sys/machlock.h> 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 #ifndef _ASM 44 45 #include <sys/obpdefs.h> 46 #include <sys/async.h> 47 #include <sys/fm/protocol.h> 48 49 /* 50 * CPU state ptl1_panic save. 51 */ 52 typedef struct ptl1_trapregs { 53 uint32_t ptl1_tl; 54 uint32_t ptl1_tt; 55 uint64_t ptl1_tstate; 56 uint64_t ptl1_tpc; 57 uint64_t ptl1_tnpc; 58 } ptl1_trapregs_t; 59 60 typedef struct ptl1_regs { 61 ptl1_trapregs_t ptl1_trap_regs[PTL1_MAXTL]; 62 uint64_t ptl1_g1; 63 uint64_t ptl1_g2; 64 uint64_t ptl1_g3; 65 uint64_t ptl1_g4; 66 uint64_t ptl1_g5; 67 uint64_t ptl1_g6; 68 uint64_t ptl1_g7; 69 uint64_t ptl1_tick; 70 uint64_t ptl1_dmmu_sfar; 71 uint64_t ptl1_dmmu_sfsr; 72 uint64_t ptl1_dmmu_tag_access; 73 uint64_t ptl1_immu_sfsr; 74 uint64_t ptl1_immu_tag_access; 75 struct rwindow ptl1_rwindow[MAXWIN]; 76 uint32_t ptl1_softint; 77 uint16_t ptl1_pstate; 78 uint8_t ptl1_pil; 79 uint8_t ptl1_cwp; 80 uint8_t ptl1_wstate; 81 uint8_t ptl1_otherwin; 82 uint8_t ptl1_cleanwin; 83 uint8_t ptl1_cansave; 84 uint8_t ptl1_canrestore; 85 } ptl1_regs_t; 86 87 typedef struct ptl1_state { 88 ptl1_regs_t ptl1_regs; 89 uint32_t ptl1_entry_count; 90 uintptr_t ptl1_stktop; 91 ulong_t ptl1_stk[1]; 92 } ptl1_state_t; 93 94 /* 95 * Machine specific fields of the cpu struct 96 * defined in common/sys/cpuvar.h. 97 */ 98 struct machcpu { 99 struct machpcb *mpcb; 100 uint64_t mpcb_pa; 101 int mutex_ready; 102 int in_prom; 103 int tl1_hdlr; 104 uint16_t divisor; /* Estar %tick clock ratio */ 105 uint8_t intrcnt; /* number of back-to-back interrupts */ 106 u_longlong_t tmp1; /* per-cpu tmps */ 107 u_longlong_t tmp2; /* used in trap processing */ 108 109 struct intr_req intr_pool[INTR_PENDING_MAX]; /* intr pool */ 110 struct intr_req *intr_head[PIL_LEVELS]; /* intr que heads */ 111 struct intr_req *intr_tail[PIL_LEVELS]; /* intr que tails */ 112 int intr_pool_added; /* add'l intr pool */ 113 boolean_t poke_cpu_outstanding; 114 /* 115 * The cpu module allocates a private data structure for the 116 * E$ data, which is needed for the specific cpu type. 117 */ 118 void *cpu_private; /* ptr to cpu private data */ 119 120 ptl1_state_t ptl1_state; 121 122 uint64_t pil_high_start[HIGH_LEVELS]; /* high-level intrs */ 123 124 /* 125 * intrstat[][] is used to keep track of ticks used at a given pil 126 * level. intrstat[pil][0] is cumulative and exported via kstats. 127 * intrstat[pil][1] is used in intr_get_time() and is private. 128 * 2-dimensional array improves cache locality. 129 */ 130 131 uint64_t intrstat[PIL_MAX+1][2]; 132 kthread_t *startup_thread; 133 }; 134 135 typedef struct machcpu machcpu_t; 136 137 #define cpu_startup_thread cpu_m.startup_thread 138 139 /* 140 * Macro to access the "cpu private" data structure. 141 */ 142 #define CPU_PRIVATE(cp) ((cp)->cpu_m.cpu_private) 143 144 /* 145 * The OpenBoot Standalone Interface supplies the kernel with 146 * implementation dependent parameters through the devinfo/property mechanism 147 */ 148 #define MAXSYSNAME 20 149 150 /* 151 * Used to indicate busy/idle state of a cpu. 152 * msram field will be set with ECACHE_CPU_MIRROR if we are on 153 * mirrored sram module. 154 */ 155 #define ECACHE_CPU_IDLE 0x0 /* CPU is idle */ 156 #define ECACHE_CPU_BUSY 0x1 /* CPU is busy */ 157 #define ECACHE_CPU_MIRROR 0x2 /* E$ is mirrored */ 158 #define ECACHE_CPU_NON_MIRROR 0x3 /* E$ is not mirrored */ 159 160 /* 161 * A CPU FRU FMRI string minus the unum component. 162 */ 163 #define CPU_FRU_FMRI FM_FMRI_SCHEME_HC":///" \ 164 FM_FMRI_LEGACY_HC"=" 165 166 struct cpu_node { 167 char name[MAXSYSNAME]; 168 char fru_fmri[sizeof (CPU_FRU_FMRI) + UNUM_NAMLEN]; 169 int implementation; 170 int version; 171 int portid; 172 pnode_t nodeid; 173 uint64_t clock_freq; 174 uint_t tick_nsec_scale; 175 union { 176 int dummy; 177 } u_info; 178 int ecache_size; 179 int ecache_linesize; 180 int ecache_associativity; 181 int ecache_setsize; 182 ushort_t itlb_size; 183 ushort_t dtlb_size; 184 int msram; 185 uint64_t device_id; 186 }; 187 188 extern struct cpu_node cpunodes[]; 189 190 #endif /* _ASM */ 191 192 #ifdef __cplusplus 193 } 194 #endif 195 196 #endif /* _SYS_MACHCPUVAR_H */ 197