1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_STARCAT_H 27 #define _SYS_STARCAT_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Manifest constants of Starcat configuration 37 */ 38 39 #define STARCAT_BDSET_MAX 18 /* maximum number of boardsets */ 40 41 #define STARCAT_BDSET_MIN 1 /* minimum number of boardsets */ 42 43 #define STARCAT_BDSET_SLOT_MAX 2 /* maximum slots per boardset */ 44 45 #define STARCAT_SLOT0_CPU_MAX 8 /* max CPUs per slot 0 board */ 46 47 #define STARCAT_SLOT1_CPU_MAX 4 /* max CPUs per slot 1 board */ 48 49 #define STARCAT_BDSET_CPU_MAX 12 /* maximum CPUs per boardset */ 50 51 #define STARCAT_SLOT0_MEM_MAX 4 /* max mem units per slot 0 bd */ 52 53 #define STARCAT_SLOT1_MEM_MAX 0 /* max mem units per slot 1 bd */ 54 55 #define STARCAT_BDSET_MEM_MAX 4 /* max mem units per boardset */ 56 57 #define STARCAT_SLOT0_IO_MAX 0 /* max I/O ctrlrs per slot 0 bd */ 58 59 #define STARCAT_SLOT1_IO_MAX 2 /* max I/O ctrlrs per slot 1 bd */ 60 61 #define STARCAT_BDSET_IO_MAX 2 /* max I/O ctrlrs per boardset */ 62 63 #define STARCAT_TSB_PER_IO 2 /* each IO has two leaves */ 64 65 /* max prealloc spare tsb's */ 66 #define STARCAT_SPARE_TSB_MAX \ 67 (STARCAT_BDSET_MAX * STARCAT_BDSET_IO_MAX * STARCAT_TSB_PER_IO) 68 69 /* 70 * Data bearing mondo vector (DMV) support 71 * 72 * For Starcat, we need to add a few extra "hardware" dmv interrupts. 73 * These actually do not correspond to physical hardware but are used 74 * by Starcat IDN. 75 */ 76 #define STARCAT_DMV_EXTRA 4 77 #define STARCAT_DMV_HWINT (MAX_UPA + STARCAT_DMV_EXTRA) 78 #define STARCAT_DMV_IDN_BASE (MAX_UPA) 79 80 /* 81 * The CPU ID on starcat looks like this: 82 * 83 * 9 5 4 3 2 1 0 84 * -------------------------------------- 85 * | Expander | | Slot | Core | LPORT | 86 * -------------------------------------- 87 * 88 * Expander Starcat has STARCAT_BDSET_MAX (18) expanders. 89 * Slot Starcat has STARCAT_BDSET_SLOT_MAX (2) slots per expander. 90 * Slot 0 carries a CPU-MEM board which has 4 processor chips. 91 * Slot 1 carries an I/O board typically. But it can be 92 * configured to carry a MAXCAT board which has 2 processor 93 * chips on board. 94 * LPORT Port number within the slot for a chip. This is also the 95 * chip number within the slot. Note that Slot 1 can have only 96 * 2 chips, but this representation allows for 4. This is just 97 * the theoretical max. 98 * Core Core number within the chip. 99 * 100 * Currently, the maximum number of cores supported is 2 per chip (on 101 * Panther and Jaguar). 102 * 103 */ 104 /* 105 * Macros for manipulating CPU IDs 106 */ 107 #define STARCAT_CPUID_TO_EXPANDER(p) (((p) >> 5) & 0x1f) 108 #define STARCAT_CPUID_TO_BOARDSLOT(p) (((p) >> 3) & 0x1) 109 #define STARCAT_CPUID_TO_PORTID(p) ((p) & ~0x4) 110 #define STARCAT_CPUID_TO_COREID(p) (((p) >> 2) & 0x1) 111 #define STARCAT_CPUID_TO_CORE_BIT(p) ((p) & (0x1 << 2)) 112 #define STARCAT_CPUID_TO_AGENT(p) ((p) & 0x7) 113 #define STARCAT_CPUID_TO_LPORT(p) ((p) & 0x3) 114 115 #define MAKE_CPUID(e, s, a) \ 116 ((((e) & 0x1f) << 5) | (((s) & 0x1) << 3) | ((a) & 0x7)) 117 118 /* 119 * Definitions for decoding memory controller registers. These values 120 * are taken from Chapter 9 of the SPARCV9 JSP-1 US-III implementation 121 * supplement. 122 */ 123 124 /* Starcat has four banks of memory per MC */ 125 #define MAX_BANKS_PER_MC (4) 126 127 /* Use only low bits for local CPU MC ASI */ 128 #define MC_OFFSET_MASK (0xffu) 129 130 /* Shifts to access specific fields of the memdecode register */ 131 #define MC_VALID_SHIFT (63) /* Shift for valid bit */ 132 #define MC_UK_SHIFT (41) /* Shift for upper mask field */ 133 #define MC_UM_SHIFT (20) /* Shift for upper match field */ 134 #define PHYS2UM_SHIFT (26) /* UM field matches bits 42-26 of PA */ 135 136 /* Extract upper mask field from the decode register */ 137 #define MC_UK(memdec) (((memdec) >> MC_UK_SHIFT) & 0xfffu) 138 139 /* Extract upper match field from memdecode register */ 140 #define MC_UM(memdec) (((memdec) >> MC_UM_SHIFT) & 0x1fffffu) 141 142 /* Size of the range covered by the address mask field */ 143 #define MC_UK2SPAN(memdec) ((MC_UK(memdec) + 1) << PHYS2UM_SHIFT) 144 145 /* The base PA the memdecode register will respond to */ 146 #define MC_BASE(memdec) (MC_UM(memdec) & ~(MC_UK(memdec))) 147 148 149 /* 150 * Prototypes for functions 151 */ 152 153 extern int set_platform_max_ncpus(void); 154 extern int plat_max_boards(void); 155 extern int plat_max_cpu_units_per_board(void); 156 extern int plat_max_mem_units_per_board(void); 157 extern int plat_max_io_units_per_board(void); 158 extern uint64_t lddmcdecode(uint64_t); 159 160 161 #ifdef __cplusplus 162 } 163 #endif 164 165 #endif /* _SYS_STARCAT_H */ 166