1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2004 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_STARCAT_H 28 #define _SYS_STARCAT_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 37 /* 38 * Manifest constants of Starcat configuration 39 */ 40 41 #define STARCAT_BDSET_MAX 18 /* maximum number of boardsets */ 42 43 #define STARCAT_BDSET_MIN 1 /* minimum number of boardsets */ 44 45 #define STARCAT_BDSET_SLOT_MAX 2 /* maximum slots per boardset */ 46 47 #define STARCAT_SLOT0_CPU_MAX 8 /* max CPUs per slot 0 board */ 48 49 #define STARCAT_SLOT1_CPU_MAX 4 /* max CPUs per slot 1 board */ 50 51 #define STARCAT_BDSET_CPU_MAX 12 /* maximum CPUs per boardset */ 52 53 #define STARCAT_SLOT0_MEM_MAX 4 /* max mem units per slot 0 bd */ 54 55 #define STARCAT_SLOT1_MEM_MAX 0 /* max mem units per slot 1 bd */ 56 57 #define STARCAT_BDSET_MEM_MAX 4 /* max mem units per boardset */ 58 59 #define STARCAT_SLOT0_IO_MAX 0 /* max I/O ctrlrs per slot 0 bd */ 60 61 #define STARCAT_SLOT1_IO_MAX 2 /* max I/O ctrlrs per slot 1 bd */ 62 63 #define STARCAT_BDSET_IO_MAX 2 /* max I/O ctrlrs per boardset */ 64 65 #define STARCAT_TSB_PER_IO 2 /* each IO has two leaves */ 66 67 /* max prealloc spare tsb's */ 68 #define STARCAT_SPARE_TSB_MAX \ 69 (STARCAT_BDSET_MAX * STARCAT_BDSET_IO_MAX * STARCAT_TSB_PER_IO) 70 71 /* 72 * Data bearing mondo vector (DMV) support 73 * 74 * For Starcat, we need to add a few extra "hardware" dmv interrupts. 75 * These actually do not correspond to physical hardware but are used 76 * by Starcat IDN. 77 */ 78 #define STARCAT_DMV_EXTRA 4 79 #define STARCAT_DMV_HWINT (MAX_UPA + STARCAT_DMV_EXTRA) 80 #define STARCAT_DMV_IDN_BASE (MAX_UPA) 81 82 /* 83 * Macros for manipulating CPU IDs 84 */ 85 #define STARCAT_CPUID_TO_EXPANDER(p) (((p) >> 5) & 0x1f) 86 #define STARCAT_CPUID_TO_BOARDSLOT(p) (((p) >> 3) & 0x1) 87 #define STARCAT_CPUID_TO_PORTID(p) ((p) & ~0x4) 88 #define STARCAT_CPUID_TO_COREID(p) (((p) >> 2) & 0x1) 89 #define STARCAT_CPUID_TO_CORE_BIT(p) ((p) & (0x1 << 2)) 90 #define STARCAT_CPUID_TO_AGENT(p) ((p) & 0x7) 91 #define STARCAT_CPUID_TO_LPORT(p) ((p) & 0x3) 92 93 #define MAKE_CPUID(e, s, a) \ 94 ((((e) & 0x1f) << 5) | (((s) & 0x1) << 3) | ((a) & 0x7)) 95 96 /* 97 * Definitions for decoding memory controller registers. These values 98 * are taken from Chapter 9 of the SPARCV9 JSP-1 US-III implementation 99 * supplement. 100 */ 101 102 /* Starcat has four banks of memory per MC */ 103 #define MAX_BANKS_PER_MC (4) 104 105 /* Use only low bits for local CPU MC ASI */ 106 #define MC_OFFSET_MASK (0xffu) 107 108 /* Shifts to access specific fields of the memdecode register */ 109 #define MC_VALID_SHIFT (63) /* Shift for valid bit */ 110 #define MC_UK_SHIFT (41) /* Shift for upper mask field */ 111 #define MC_UM_SHIFT (20) /* Shift for upper match field */ 112 #define PHYS2UM_SHIFT (26) /* UM field matches bits 42-26 of PA */ 113 114 /* Extract upper mask field from the decode register */ 115 #define MC_UK(memdec) (((memdec) >> MC_UK_SHIFT) & 0xfffu) 116 117 /* Extract upper match field from memdecode register */ 118 #define MC_UM(memdec) (((memdec) >> MC_UM_SHIFT) & 0x1fffffu) 119 120 /* Size of the range covered by the address mask field */ 121 #define MC_UK2SPAN(memdec) ((MC_UK(memdec) + 1) << PHYS2UM_SHIFT) 122 123 /* The base PA the memdecode register will respond to */ 124 #define MC_BASE(memdec) (MC_UM(memdec) & ~(MC_UK(memdec))) 125 126 127 /* 128 * Prototypes for functions 129 */ 130 131 extern int set_platform_max_ncpus(void); 132 extern int plat_max_boards(void); 133 extern int plat_max_cpu_units_per_board(void); 134 extern int plat_max_mem_units_per_board(void); 135 extern int plat_max_io_units_per_board(void); 136 extern uint64_t lddmcdecode(uint64_t); 137 138 139 #ifdef __cplusplus 140 } 141 #endif 142 143 #endif /* _SYS_STARCAT_H */ 144