xref: /titanic_44/usr/src/uts/sun4u/serengeti/sys/sbdp_mem.h (revision 03831d35f7499c87d51205817c93e9a8d42c4bae)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _SBDP_MEM_H
28 #define	_SBDP_MEM_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 #ifdef	__cplusplus
33 extern "C" {
34 #endif
35 
36 #include <sys/sbd.h>
37 #include <sys/sbdp_priv.h>
38 
39 #define	SBDP_MAX_MCS_PER_NODE		4
40 #define	SBDP_MAX_MEM_NODES_PER_BOARD	4
41 
42 typedef uint64_t mc_dc_regs_t[SBDP_MAX_MCS_PER_NODE];
43 
44 typedef struct {
45 	int	board;
46 	pnode_t	*nodes;
47 	int	nmem;
48 } mem_op_t;
49 
50 typedef struct {
51 	uint_t	regspec_addr_hi;
52 	uint_t	regspec_addr_lo;
53 	uint_t	regspec_size_hi;
54 	uint_t	regspec_size_lo;
55 } mc_regspace;
56 
57 typedef struct {
58 	uint64_t	mc_decode[SBDP_MAX_MCS_PER_NODE];
59 	uint64_t	mc_memctl;
60 } mc_regs_t;
61 
62 /*
63  * Memory controller register offsets
64  */
65 #define	SG_MEM_TIMING1_CTL	0x400000
66 #define	SG_MEM_TIMING2_CTL	0x400008
67 #define	SG_MEM_TIMING3_CTL	0x400038
68 #define	SG_MEM_TIMING4_CTL	0x400040
69 #define	SG_MEM_DECODE0_ADR	0x400028
70 #define	SG_MEM_DECODE1_ADR	0x400010
71 #define	SG_MEM_DECODE2_ADR	0x400018
72 #define	SG_MEM_DECODE3_ADR	0x400020
73 #define	SG_MEM_CONTROL_ADR	0x400030
74 #define	SG_EMU_ACTIVITY_STATUS	0x400050
75 
76 /*
77  * Bit fields for the decode registers
78  */
79 #define	SG_DECODE_VALID		0x8000000000000000ull
80 #define	SG_DECODE_UK		0x001ffe0000000000ull
81 #define	SG_DECODE_UM		0x000001fffff00000ull
82 #define	SG_DECODE_LK		0x00000000000fc000ull
83 #define	SG_DECODE_LM		0x0000000000003f00ull
84 #define	SG_INVAL_UM		0x0000000ffff00000ull
85 #define	SG_SLICE_INFO		0x000001fc00000000ull
86 #define	SG_ALIGNMENT		0x800000000ULL
87 
88 
89 /*
90  * Memory Macros
91  */
92 #define	MC_MEMDEC0(mc_addr) \
93 	(mc_addr) | SG_MEM_DECODE0_ADR
94 #define	MC_MEMDEC1(mc_addr) \
95 	(mc_addr) | SG_MEM_DECODE1_ADR
96 #define	MC_MEMDEC2(mc_addr) \
97 	(mc_addr) | SG_MEM_DECODE2_ADR
98 #define	MC_MEMDEC3(mc_addr) \
99 	(mc_addr) | SG_MEM_DECODE3_ADR
100 #define	MC_ACTIVITY_STATUS(mc_addr) \
101 	(mc_addr) | SG_EMU_ACTIVITY_STATUS
102 
103 
104 /*
105  * Mappings to the array for the decode registers only
106  */
107 #define	SG_MC_DECODE_I		0
108 #define	SG_MC_DECODE_II		1
109 #define	SG_MC_DECODE_III	2
110 #define	SG_MC_DECODE_IV		3
111 /*
112  * Memory Macros
113  */
114 #define	SG_REG_2_OFFSET(num) \
115 	    ((num) == SG_MC_DECODE_I ? (uint64_t)SG_MEM_DECODE0_ADR : \
116 	    (num) == SG_MC_DECODE_II ? (uint64_t)SG_MEM_DECODE1_ADR : \
117 	    (num) == SG_MC_DECODE_III ? (uint64_t)SG_MEM_DECODE2_ADR : \
118 	    (num) == SG_MC_DECODE_IV ? (uint64_t)SG_MEM_DECODE3_ADR : \
119 	    (uint64_t)-1)
120 
121 #define	MC_VALID_SHIFT		63
122 #define	MC_UK_SHIFT		41
123 #define	MC_UM_SHIFT		20
124 #define	MC_LK_SHIFT		14
125 #define	MC_LM_SHIFT		8
126 #define	PHYS2UM_SHIFT		26
127 #define	MC_UK(memdec)		(((memdec) >> MC_UK_SHIFT) & 0xfffu)
128 #define	MC_LK(memdec)		(((memdec) >> MC_LK_SHIFT)& 0x3fu)
129 #define	MC_INTLV(memdec)	((~(MC_LK(memdec)) & 0xfu) + 1)
130 #define	MC_UK2SPAN(memdec)	((MC_UK(memdec) + 1) << PHYS2UM_SHIFT)
131 #define	MC_SPANMB(memdec)	(MC_UK2SPAN(memdec) >> 20)
132 #define	MC_UM(memdec)		(((memdec) >> MC_UM_SHIFT) & 0x1fffffu)
133 #define	MC_LM(memdec)		(((memdec) >> MC_LM_SHIFT) & 0x3f)
134 #define	MC_BASE(memdec)		(MC_UM(memdec) & ~(MC_UK(memdec)))
135 #define	MC_BASE2UM(base)	(((base) & 0x1fffffu) << MC_UM_SHIFT)
136 #define	SAF_MASK		0x000007ffff800000ull
137 #define	MC_OFFSET_MASK		0xffu
138 
139 /*
140  * Memory Slice information
141  */
142 #define	SG_SLICE_16G_SIZE	0x400000000ULL
143 #define	SG_SLICE_32G_SIZE	0x800000000ULL
144 #define	SG_SLICE_64G_SIZE	0x1000000000ULL
145 
146 /*
147  * Copy-rename info
148  */
149 
150 #define	SBDP_RENAME_MAXOP	(PAGESIZE / sizeof (sbdp_rename_script_t))
151 
152 /*
153  * Must be same size as sbdp_rename_script_t.
154  */
155 typedef struct {
156 	uint64_t	addr;
157 	uint_t		bd_id;
158 	pnode_t		node;
159 	uint_t		asi;
160 	uint_t		_filler;
161 } sbdp_mc_idle_script_t;
162 
163 typedef struct {
164 	uint64_t	masr_addr;
165 	uint64_t	masr;
166 	uint_t		asi;
167 	uint_t		_filler;
168 } sbdp_rename_script_t;
169 
170 typedef struct {
171 	sbdp_bd_t	*s_bdp;	/* pointer to src bd info */
172 	sbdp_bd_t	*t_bdp;	/* pointer to tgt bd info */
173 	sbdp_rename_script_t *script; 	/* points to the actual script */
174 	uint64_t	ret;
175 	sbdp_mc_idle_script_t *busy_mc;
176 } sbdp_cr_handle_t;
177 
178 
179 extern uint64_t lddsafaddr(uint64_t physaddr);
180 extern uint64_t lddmcdecode(uint64_t physaddr);
181 extern void stdmcdecode(uint64_t, uint64_t);
182 
183 int sbdp_is_mem(pnode_t node, void *arg);
184 #ifdef DEBUG
185 int sbdp_passthru_readmem(sbdp_handle_t *hp, void *);
186 int sbdp_passthru_prep_script(sbdp_handle_t *hp, void *);
187 #endif
188 
189 #ifdef	__cplusplus
190 }
191 #endif
192 
193 #endif	/* _SBDP_MEM_H */
194