1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_LIB4U_H 27 #define _SYS_PX_LIB4U_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 /* 36 * Errors returned. 37 */ 38 #define H_EOK 0 /* Successful return */ 39 #define H_ENOINTR 1 /* Invalid interrupt id */ 40 #define H_EINVAL 2 /* Invalid argument */ 41 #define H_ENOACCESS 3 /* No access to resource */ 42 #define H_EIO 4 /* I/O error */ 43 #define H_ENOTSUPPORTED 5 /* Function not supported */ 44 #define H_ENOMAP 6 /* Mapping is not valid, */ 45 /* no translation exists */ 46 47 /* 48 * Register base definitions. 49 * 50 * The specific numeric values for CSR, XBUS, Configuration, 51 * Interrupt blocks and other register bases. 52 */ 53 typedef enum { 54 PX_REG_CSR = 0, 55 PX_REG_XBC, 56 PX_REG_CFG, 57 PX_REG_IC, 58 PX_REG_MAX 59 } px_reg_bank_t; 60 61 /* 62 * Registers/state/variables that need to be saved and restored during 63 * suspend/resume. 64 * 65 * SUN4U px specific data structure. 66 */ 67 typedef struct pxu { 68 uint32_t chip_id; 69 uint8_t portid; 70 uint16_t tsb_cookie; 71 uint32_t tsb_size; 72 uint64_t *tsb_vaddr; 73 void *msiq_mapped_p; 74 75 /* Soft state for suspend/resume */ 76 uint64_t *pec_config_state; 77 uint64_t *mmu_config_state; 78 uint64_t *ib_intr_map; 79 uint64_t *ib_config_state; 80 uint64_t *xcb_config_state; 81 uint64_t *msiq_config_state; 82 83 /* sun4u specific vars */ 84 caddr_t px_address[4]; 85 ddi_acc_handle_t px_ac[4]; 86 } pxu_t; 87 88 /* 89 * Event Queue data structure. 90 */ 91 typedef struct eq_rec { 92 uint64_t eq_rec_rsvd0 : 1, /* DW 0 - 63 */ 93 eq_rec_fmt_type : 7, /* DW 0 - 62:56 */ 94 eq_rec_len : 10, /* DW 0 - 55:46 */ 95 eq_rec_addr0 : 14, /* DW 0 - 45:32 */ 96 eq_rec_rid : 16, /* DW 0 - 31:16 */ 97 eq_rec_data0 : 16; /* DW 0 - 15:00 */ 98 uint64_t eq_rec_addr1 : 48, /* DW 1 - 63:16 */ 99 eq_rec_data1 : 16; /* DW 1 - 15:0 */ 100 uint64_t eq_rec_rsvd[6]; /* DW 2-7 */ 101 } eq_rec_t; 102 103 /* 104 * EQ record type 105 * 106 * Upper 4 bits of eq_rec_fmt_type is used 107 * to identify the EQ record type. 108 */ 109 #define EQ_REC_MSG 0x6 /* MSG - 0x3X */ 110 #define EQ_REC_MSI32 0xB /* MSI32 - 0x58 */ 111 #define EQ_REC_MSI64 0xF /* MSI64 - 0x78 */ 112 113 /* EQ State */ 114 #define EQ_IDLE_STATE 0x1 /* IDLE */ 115 #define EQ_ACTIVE_STATE 0x2 /* ACTIVE */ 116 #define EQ_ERROR_STATE 0x4 /* ERROR */ 117 118 #define MMU_INVALID_TTE 0ull 119 #define MMU_TTE_VALID(tte) (((tte) & MMU_TTE_V) == MMU_TTE_V) 120 #define MMU_TTETOPA(x) ((x & 0x7ffffffffff) >> MMU_PAGE_SHIFT) 121 122 /* 123 * control register decoding 124 */ 125 /* tsb size: 0=1k 1=2k 2=4k 3=8k 4=16k 5=32k 6=64k 7=128k */ 126 #define MMU_CTL_TO_TSBSIZE(ctl) ((ctl) >> 16) 127 #define MMU_TSBSIZE_TO_TSBENTRIES(s) ((1 << (s)) << (13 - 3)) 128 129 /* 130 * For mmu bypass addresses, bit 43 specifies cacheability. 131 */ 132 #define MMU_BYPASS_NONCACHE (1ull << 43) 133 134 /* 135 * The following macros define the address ranges supported for DVMA 136 * and mmu bypass transfers. 137 */ 138 #define MMU_BYPASS_BASE 0xFFFC000000000000ull 139 #define MMU_BYPASS_END 0xFFFC01FFFFFFFFFFull 140 141 /* 142 * The following macros are for loading and unloading io tte 143 * entries. 144 */ 145 #define MMU_TTE_SIZE 8 146 #define MMU_TTE_V (1ull << 63) 147 #define MMU_TTE_W (1ull << 1) 148 149 #define INO_BITS 6 /* INO#s are 6 bits long */ 150 #define IGN_BITS 5 /* IGN#s are 5 bits long */ 151 #define INO_MASK 0x3F /* INO#s mask */ 152 #define IGN_MASK 0x1F /* IGN#s mask */ 153 154 #define ID_TO_IGN(portid) ((uint16_t)((portid) & IGN_MASK)) 155 #define ID_TO_NODEID(portid) ((uint16_t)((portid) >> IGN_BITS)) 156 #define DEVINO_TO_SYSINO(portid, devino) \ 157 ((ID_TO_NODEID(portid) << (IGN_BITS + INO_BITS)) | \ 158 ((ID_TO_IGN(portid) << INO_BITS) | (devino & INO_MASK))) 159 #define SYSINO_TO_DEVINO(sysino) (sysino & INO_MASK) 160 161 /* Interrupt states */ 162 #define INTERRUPT_IDLE_STATE 0 163 #define INTERRUPT_RECEIVED_STATE 1 164 #define INTERRUPT_PENDING_STATE 3 165 166 /* 167 * Defines for link width and max packet size for ACKBAK Latency Threshold Timer 168 * and TxLink Replay Timer Latency Table array sizes 169 * Num Link Width Packet Size 170 * 0 1 128 171 * 1 4 256 172 * 2 8 512 173 * 3 16 1024 174 * 4 - 2048 175 * 5 - 4096 176 */ 177 #define LINK_WIDTH_ARR_SIZE 4 178 #define LINK_MAX_PKT_ARR_SIZE 6 179 180 /* 181 * Defines for registers which have multi-bit fields. 182 */ 183 #define TLU_LINK_CONTROL_ASPM_DISABLED 0x0 184 #define TLU_LINK_CONTROL_ASPM_L0S_EN 0x1 185 #define TLU_LINK_CONTROL_ASPM_L1_EN 0x2 186 #define TLU_LINK_CONTROL_ASPM_L0S_L1_EN 0x3 187 188 #define TLU_CONTROL_CONFIG_DEFAULT 0x1 189 #define TLU_CONTROL_L0S_TIM_DEFAULT 0xdaull 190 #define TLU_CONTROL_MPS_MASK 0x1C 191 #define TLU_CONTROL_MPS_SHIFT 2 192 193 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_0 0x0 194 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_1 0x1 195 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_2 0x2 196 #define LPU_TXLINK_REPLAY_NUMBER_STATUS_RPLAY_NUM_3 0x3 197 198 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_TLPTR_DEFAULT 0xFFFFull 199 #define LPU_TXLINK_RETRY_FIFO_POINTER_RTRY_FIFO_HDPTR_DEFAULT 0x0ull 200 201 #define LPU_TXLINK_SEQUENCE_COUNTER_ACK_SEQ_CNTR_DEFAULT 0xFFF 202 #define LPU_TXLINK_SEQUENCE_COUNTER_NXT_TX_SEQ_CNTR_DEFAULT 0x0 203 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_MAX_ADDR_SEQ_CNT_MAX_ADDR_DEF 0x157 204 205 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_TLPTR_DEFAULT 0xFFF 206 #define LPU_TXLINK_SEQUENCE_COUNT_FIFO_POINTERS_SEQ_CNT_HDPTR_DEFAULT 0x0 207 208 #define LPU_LTSSM_CONFIG1_LTSSM_8_TO_DEFAULT 0x2 209 #define LPU_LTSSM_CONFIG1_LTSSM_20_TO_DEFAULT 0x5 210 #define LPU_LTSSM_CONFIG2_LTSSM_12_TO_DEFAULT 0x2DC6C0 211 #define LPU_LTSSM_CONFIG3_LTSSM_2_TO_DEFAULT 0x7A120 212 #define LPU_LTSSM_CONFIG4_DATA_RATE_DEFAULT 0x2 213 #define LPU_LTSSM_CONFIG4_N_FTS_DEFAULT 0x8c 214 215 /* LPU LTSSM states */ 216 #define LPU_LTSSM_L0 0x0 217 #define LPU_LTSSM_L1_IDLE 0x15 218 219 /* TLU Control register bits */ 220 #define TLU_REMAIN_DETECT_QUIET 8 221 222 /* PX BDF Shift in a Phyiscal Address - used FMA Fabric only */ 223 #define PX_PA_BDF_SHIFT 12 224 #define PX_BDF_TO_CFGADDR(bdf, offset) (((bdf) << PX_PA_BDF_SHIFT) + (offset)) 225 226 /* 227 * The sequence of the chip_type appearance is significant. 228 * There are code depending on it: PX_CHIP_TYPE(pxu_p) < PX_CHIP_FIRE. 229 */ 230 typedef enum { 231 PX_CHIP_UNIDENTIFIED = 0, 232 PX_CHIP_FIRE = 1 233 } px_chip_id_t; 234 235 /* 236 * [msb] [lsb] 237 * 0x00 <chip_type> <version#> <module-revision#> 238 */ 239 #define PX_CHIP_ID(t, v, m) (((t) << 16) | ((v) << 8) | (m)) 240 #define PX_ID_CHIP_TYPE(id) ((id) >> 16) 241 #define PX_CHIP_TYPE(pxu_p) PX_ID_CHIP_TYPE(PX_CHIP_ID((pxu_p)->chip_id)) 242 #define PX_CHIP_REV(pxu_p) PX_CHIP_ID(((pxu_p)->chip_id) & 0xFF) 243 #define PX_CHIP_VER(pxu_p) PX_CHIP_ID((((pxu_p)->chip_id) >> 8) & 0xFF) 244 245 /* 246 * Fire hardware specific version definitions. 247 */ 248 #define FIRE_VER_10 PX_CHIP_ID(PX_CHIP_FIRE, 0x01, 0x00) 249 #define FIRE_VER_20 PX_CHIP_ID(PX_CHIP_FIRE, 0x03, 0x00) 250 251 extern void hvio_cb_init(caddr_t xbc_csr_base, pxu_t *pxu_p); 252 extern void hvio_ib_init(caddr_t csr_base, pxu_t *pxu_p); 253 extern void hvio_mmu_init(caddr_t csr_base, pxu_t *pxu_p); 254 extern void hvio_pec_init(caddr_t csr_base, pxu_t *pxu_p); 255 256 extern uint64_t hvio_intr_devino_to_sysino(devhandle_t dev_hdl, pxu_t *pxu_p, 257 devino_t devino, sysino_t *sysino); 258 extern uint64_t hvio_intr_getvalid(devhandle_t dev_hdl, sysino_t sysino, 259 intr_valid_state_t *intr_valid_state); 260 extern uint64_t hvio_intr_setvalid(devhandle_t dev_hdl, sysino_t sysino, 261 intr_valid_state_t intr_valid_state); 262 extern uint64_t hvio_intr_getstate(devhandle_t dev_hdl, sysino_t sysino, 263 intr_state_t *intr_state); 264 extern uint64_t hvio_intr_setstate(devhandle_t dev_hdl, sysino_t sysino, 265 intr_state_t intr_state); 266 extern uint64_t hvio_intr_gettarget(devhandle_t dev_hdl, sysino_t sysino, 267 cpuid_t *cpuid); 268 extern uint64_t hvio_intr_settarget(devhandle_t dev_hdl, sysino_t sysino, 269 cpuid_t cpuid); 270 271 extern uint64_t hvio_iommu_map(devhandle_t dev_hdl, pxu_t *pxu_p, tsbid_t tsbid, 272 pages_t pages, io_attributes_t attr, void *addr, size_t pfn_index, 273 int flags); 274 extern uint64_t hvio_iommu_demap(devhandle_t dev_hdl, pxu_t *pxu_p, 275 tsbid_t tsbid, pages_t pages); 276 extern uint64_t hvio_iommu_getmap(devhandle_t dev_hdl, pxu_t *pxu_p, 277 tsbid_t tsbid, io_attributes_t *attr_p, r_addr_t *r_addr_p); 278 extern uint64_t hvio_iommu_getbypass(devhandle_t dev_hdl, r_addr_t ra, 279 io_attributes_t attr, io_addr_t *io_addr_p); 280 281 /* 282 * MSIQ Functions: 283 */ 284 extern uint64_t hvio_msiq_init(devhandle_t dev_hdl, pxu_t *pxu_p); 285 extern uint64_t hvio_msiq_getvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 286 pci_msiq_valid_state_t *msiq_valid_state); 287 extern uint64_t hvio_msiq_setvalid(devhandle_t dev_hdl, msiqid_t msiq_id, 288 pci_msiq_valid_state_t msiq_valid_state); 289 extern uint64_t hvio_msiq_getstate(devhandle_t dev_hdl, msiqid_t msiq_id, 290 pci_msiq_state_t *msiq_state); 291 extern uint64_t hvio_msiq_setstate(devhandle_t dev_hdl, msiqid_t msiq_id, 292 pci_msiq_state_t msiq_state); 293 extern uint64_t hvio_msiq_gethead(devhandle_t dev_hdl, msiqid_t msiq_id, 294 msiqhead_t *msiq_head); 295 extern uint64_t hvio_msiq_sethead(devhandle_t dev_hdl, msiqid_t msiq_id, 296 msiqhead_t msiq_head); 297 extern uint64_t hvio_msiq_gettail(devhandle_t dev_hdl, msiqid_t msiq_id, 298 msiqtail_t *msiq_tail); 299 300 /* 301 * MSI Functions: 302 */ 303 extern uint64_t hvio_msi_init(devhandle_t dev_hdl, uint64_t addr32, 304 uint64_t addr64); 305 extern uint64_t hvio_msi_getmsiq(devhandle_t dev_hdl, msinum_t msi_num, 306 msiqid_t *msiq_id); 307 extern uint64_t hvio_msi_setmsiq(devhandle_t dev_hdl, msinum_t msi_num, 308 msiqid_t msiq_id); 309 extern uint64_t hvio_msi_getvalid(devhandle_t dev_hdl, msinum_t msi_num, 310 pci_msi_valid_state_t *msi_valid_state); 311 extern uint64_t hvio_msi_setvalid(devhandle_t dev_hdl, msinum_t msi_num, 312 pci_msi_valid_state_t msi_valid_state); 313 extern uint64_t hvio_msi_getstate(devhandle_t dev_hdl, msinum_t msi_num, 314 pci_msi_state_t *msi_state); 315 extern uint64_t hvio_msi_setstate(devhandle_t dev_hdl, msinum_t msi_num, 316 pci_msi_state_t msi_state); 317 318 /* 319 * MSG Functions: 320 */ 321 extern uint64_t hvio_msg_getmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 322 msiqid_t *msiq_id); 323 extern uint64_t hvio_msg_setmsiq(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 324 msiqid_t msiq_id); 325 extern uint64_t hvio_msg_getvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 326 pcie_msg_valid_state_t *msg_valid_state); 327 extern uint64_t hvio_msg_setvalid(devhandle_t dev_hdl, pcie_msg_type_t msg_type, 328 pcie_msg_valid_state_t msg_valid_state); 329 330 /* 331 * Suspend/Resume Functions: 332 */ 333 extern uint64_t hvio_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 334 extern void hvio_resume(devhandle_t dev_hdl, 335 devino_t devino, pxu_t *pxu_p); 336 extern uint64_t hvio_cb_suspend(devhandle_t dev_hdl, pxu_t *pxu_p); 337 extern void hvio_cb_resume(devhandle_t pci_dev_hdl, devhandle_t xbus_dev_hdl, 338 devino_t devino, pxu_t *pxu_p); 339 extern int px_send_pme_turnoff(caddr_t csr_base); 340 extern int px_link_wait4l1idle(caddr_t csr_base); 341 extern int px_link_retrain(caddr_t csr_base); 342 extern void px_enable_detect_quiet(caddr_t csr_base); 343 344 extern void px_lib_clr_errs(px_t *px_p); 345 346 #ifdef __cplusplus 347 } 348 #endif 349 350 #endif /* _SYS_PX_LIB4U_H */ 351