1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/kmem.h> 30 #include <sys/conf.h> 31 #include <sys/ddi.h> 32 #include <sys/sunddi.h> 33 #include <sys/fm/protocol.h> 34 #include <sys/fm/util.h> 35 #include <sys/modctl.h> 36 #include <sys/disp.h> 37 #include <sys/stat.h> 38 #include <sys/ddi_impldefs.h> 39 #include <sys/vmem.h> 40 #include <sys/iommutsb.h> 41 #include <sys/cpuvar.h> 42 #include <sys/ivintr.h> 43 #include <sys/byteorder.h> 44 #include <sys/hotplug/pci/pciehpc.h> 45 #include <px_obj.h> 46 #include <pcie_pwr.h> 47 #include "px_tools_var.h" 48 #include <px_regs.h> 49 #include <px_csr.h> 50 #include <sys/machsystm.h> 51 #include "px_lib4u.h" 52 #include "px_err.h" 53 #include "oberon_regs.h" 54 55 #pragma weak jbus_stst_order 56 57 extern void jbus_stst_order(); 58 59 ulong_t px_mmu_dvma_end = 0xfffffffful; 60 uint_t px_ranges_phi_mask = 0xfffffffful; 61 uint64_t *px_oberon_ubc_scratch_regs; 62 uint64_t px_paddr_mask; 63 64 static int px_goto_l23ready(px_t *px_p); 65 static int px_goto_l0(px_t *px_p); 66 static int px_pre_pwron_check(px_t *px_p); 67 static uint32_t px_identity_init(px_t *px_p); 68 static boolean_t px_cpr_callb(void *arg, int code); 69 static uint_t px_cb_intr(caddr_t arg); 70 71 /* 72 * px_lib_map_registers 73 * 74 * This function is called from the attach routine to map the registers 75 * accessed by this driver. 76 * 77 * used by: px_attach() 78 * 79 * return value: DDI_FAILURE on failure 80 */ 81 int 82 px_lib_map_regs(pxu_t *pxu_p, dev_info_t *dip) 83 { 84 ddi_device_acc_attr_t attr; 85 px_reg_bank_t reg_bank = PX_REG_CSR; 86 87 DBG(DBG_ATTACH, dip, "px_lib_map_regs: pxu_p:0x%p, dip 0x%p\n", 88 pxu_p, dip); 89 90 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 91 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 92 attr.devacc_attr_endian_flags = DDI_NEVERSWAP_ACC; 93 94 /* 95 * PCI CSR Base 96 */ 97 if (ddi_regs_map_setup(dip, reg_bank, &pxu_p->px_address[reg_bank], 98 0, 0, &attr, &pxu_p->px_ac[reg_bank]) != DDI_SUCCESS) { 99 goto fail; 100 } 101 102 reg_bank++; 103 104 /* 105 * XBUS CSR Base 106 */ 107 if (ddi_regs_map_setup(dip, reg_bank, &pxu_p->px_address[reg_bank], 108 0, 0, &attr, &pxu_p->px_ac[reg_bank]) != DDI_SUCCESS) { 109 goto fail; 110 } 111 112 pxu_p->px_address[reg_bank] -= FIRE_CONTROL_STATUS; 113 114 done: 115 for (; reg_bank >= PX_REG_CSR; reg_bank--) { 116 DBG(DBG_ATTACH, dip, "reg_bank 0x%x address 0x%p\n", 117 reg_bank, pxu_p->px_address[reg_bank]); 118 } 119 120 return (DDI_SUCCESS); 121 122 fail: 123 cmn_err(CE_WARN, "%s%d: unable to map reg entry %d\n", 124 ddi_driver_name(dip), ddi_get_instance(dip), reg_bank); 125 126 for (reg_bank--; reg_bank >= PX_REG_CSR; reg_bank--) { 127 pxu_p->px_address[reg_bank] = NULL; 128 ddi_regs_map_free(&pxu_p->px_ac[reg_bank]); 129 } 130 131 return (DDI_FAILURE); 132 } 133 134 /* 135 * px_lib_unmap_regs: 136 * 137 * This routine unmaps the registers mapped by map_px_registers. 138 * 139 * used by: px_detach(), and error conditions in px_attach() 140 * 141 * return value: none 142 */ 143 void 144 px_lib_unmap_regs(pxu_t *pxu_p) 145 { 146 int i; 147 148 for (i = 0; i < PX_REG_MAX; i++) { 149 if (pxu_p->px_ac[i]) 150 ddi_regs_map_free(&pxu_p->px_ac[i]); 151 } 152 } 153 154 int 155 px_lib_dev_init(dev_info_t *dip, devhandle_t *dev_hdl) 156 { 157 158 caddr_t xbc_csr_base, csr_base; 159 px_dvma_range_prop_t px_dvma_range; 160 pxu_t *pxu_p; 161 uint8_t chip_mask; 162 px_t *px_p = DIP_TO_STATE(dip); 163 px_chip_type_t chip_type = px_identity_init(px_p); 164 165 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dip 0x%p", dip); 166 167 if (chip_type == PX_CHIP_UNIDENTIFIED) { 168 cmn_err(CE_WARN, "%s%d: Unrecognized Hardware Version\n", 169 NAMEINST(dip)); 170 return (DDI_FAILURE); 171 } 172 173 chip_mask = BITMASK(chip_type); 174 px_paddr_mask = (chip_type == PX_CHIP_FIRE) ? MMU_FIRE_PADDR_MASK : 175 MMU_OBERON_PADDR_MASK; 176 177 /* 178 * Allocate platform specific structure and link it to 179 * the px state structure. 180 */ 181 pxu_p = kmem_zalloc(sizeof (pxu_t), KM_SLEEP); 182 pxu_p->chip_type = chip_type; 183 pxu_p->portid = ddi_getprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 184 "portid", -1); 185 186 /* Map in the registers */ 187 if (px_lib_map_regs(pxu_p, dip) == DDI_FAILURE) { 188 kmem_free(pxu_p, sizeof (pxu_t)); 189 190 return (DDI_FAILURE); 191 } 192 193 xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 194 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 195 196 pxu_p->tsb_cookie = iommu_tsb_alloc(pxu_p->portid); 197 pxu_p->tsb_size = iommu_tsb_cookie_to_size(pxu_p->tsb_cookie); 198 pxu_p->tsb_vaddr = iommu_tsb_cookie_to_va(pxu_p->tsb_cookie); 199 200 pxu_p->tsb_paddr = va_to_pa(pxu_p->tsb_vaddr); 201 202 /* 203 * Create "virtual-dma" property to support child devices 204 * needing to know DVMA range. 205 */ 206 px_dvma_range.dvma_base = (uint32_t)px_mmu_dvma_end + 1 207 - ((pxu_p->tsb_size >> 3) << MMU_PAGE_SHIFT); 208 px_dvma_range.dvma_len = (uint32_t) 209 px_mmu_dvma_end - px_dvma_range.dvma_base + 1; 210 211 (void) ddi_prop_create(DDI_DEV_T_NONE, dip, DDI_PROP_CANSLEEP, 212 "virtual-dma", (caddr_t)&px_dvma_range, 213 sizeof (px_dvma_range_prop_t)); 214 /* 215 * Initilize all fire hardware specific blocks. 216 */ 217 hvio_cb_init(xbc_csr_base, pxu_p); 218 hvio_ib_init(csr_base, pxu_p); 219 hvio_pec_init(csr_base, pxu_p); 220 hvio_mmu_init(csr_base, pxu_p); 221 222 px_p->px_plat_p = (void *)pxu_p; 223 224 /* 225 * Initialize all the interrupt handlers 226 */ 227 switch (PX_CHIP_TYPE(pxu_p)) { 228 case PX_CHIP_OBERON: 229 /* 230 * Oberon hotplug uses SPARE3 field in ILU Error Log Enable 231 * register to indicate the status of leaf reset, 232 * we need to preserve the value of this bit, and keep it in 233 * px_ilu_log_mask to reflect the state of the bit 234 */ 235 if (CSR_BR(csr_base, ILU_ERROR_LOG_ENABLE, SPARE3)) 236 px_ilu_log_mask |= (1ull << 237 ILU_ERROR_LOG_ENABLE_SPARE3); 238 else 239 px_ilu_log_mask &= ~(1ull << 240 ILU_ERROR_LOG_ENABLE_SPARE3); 241 242 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE); 243 px_fabric_die_rc_ue |= PCIE_AER_UCE_UC; 244 break; 245 246 case PX_CHIP_FIRE: 247 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_ENABLE); 248 break; 249 250 default: 251 cmn_err(CE_WARN, "%s%d: PX primary bus Unknown\n", 252 ddi_driver_name(dip), ddi_get_instance(dip)); 253 return (DDI_FAILURE); 254 } 255 256 /* Initilize device handle */ 257 *dev_hdl = (devhandle_t)csr_base; 258 259 DBG(DBG_ATTACH, dip, "px_lib_dev_init: dev_hdl 0x%llx\n", *dev_hdl); 260 261 return (DDI_SUCCESS); 262 } 263 264 int 265 px_lib_dev_fini(dev_info_t *dip) 266 { 267 caddr_t csr_base; 268 uint8_t chip_mask; 269 px_t *px_p = DIP_TO_STATE(dip); 270 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 271 272 DBG(DBG_DETACH, dip, "px_lib_dev_fini: dip 0x%p\n", dip); 273 274 /* 275 * Deinitialize all the interrupt handlers 276 */ 277 switch (PX_CHIP_TYPE(pxu_p)) { 278 case PX_CHIP_OBERON: 279 case PX_CHIP_FIRE: 280 chip_mask = BITMASK(PX_CHIP_TYPE(pxu_p)); 281 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 282 px_err_reg_setup_pcie(chip_mask, csr_base, PX_ERR_DISABLE); 283 break; 284 285 default: 286 cmn_err(CE_WARN, "%s%d: PX primary bus Unknown\n", 287 ddi_driver_name(dip), ddi_get_instance(dip)); 288 return (DDI_FAILURE); 289 } 290 291 iommu_tsb_free(pxu_p->tsb_cookie); 292 293 px_lib_unmap_regs((pxu_t *)px_p->px_plat_p); 294 kmem_free(px_p->px_plat_p, sizeof (pxu_t)); 295 px_p->px_plat_p = NULL; 296 297 return (DDI_SUCCESS); 298 } 299 300 /*ARGSUSED*/ 301 int 302 px_lib_intr_devino_to_sysino(dev_info_t *dip, devino_t devino, 303 sysino_t *sysino) 304 { 305 px_t *px_p = DIP_TO_STATE(dip); 306 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 307 uint64_t ret; 308 309 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: dip 0x%p " 310 "devino 0x%x\n", dip, devino); 311 312 if ((ret = hvio_intr_devino_to_sysino(DIP_TO_HANDLE(dip), 313 pxu_p, devino, sysino)) != H_EOK) { 314 DBG(DBG_LIB_INT, dip, 315 "hvio_intr_devino_to_sysino failed, ret 0x%lx\n", ret); 316 return (DDI_FAILURE); 317 } 318 319 DBG(DBG_LIB_INT, dip, "px_lib_intr_devino_to_sysino: sysino 0x%llx\n", 320 *sysino); 321 322 return (DDI_SUCCESS); 323 } 324 325 /*ARGSUSED*/ 326 int 327 px_lib_intr_getvalid(dev_info_t *dip, sysino_t sysino, 328 intr_valid_state_t *intr_valid_state) 329 { 330 uint64_t ret; 331 332 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: dip 0x%p sysino 0x%llx\n", 333 dip, sysino); 334 335 if ((ret = hvio_intr_getvalid(DIP_TO_HANDLE(dip), 336 sysino, intr_valid_state)) != H_EOK) { 337 DBG(DBG_LIB_INT, dip, "hvio_intr_getvalid failed, ret 0x%lx\n", 338 ret); 339 return (DDI_FAILURE); 340 } 341 342 DBG(DBG_LIB_INT, dip, "px_lib_intr_getvalid: intr_valid_state 0x%x\n", 343 *intr_valid_state); 344 345 return (DDI_SUCCESS); 346 } 347 348 /*ARGSUSED*/ 349 int 350 px_lib_intr_setvalid(dev_info_t *dip, sysino_t sysino, 351 intr_valid_state_t intr_valid_state) 352 { 353 uint64_t ret; 354 355 DBG(DBG_LIB_INT, dip, "px_lib_intr_setvalid: dip 0x%p sysino 0x%llx " 356 "intr_valid_state 0x%x\n", dip, sysino, intr_valid_state); 357 358 if ((ret = hvio_intr_setvalid(DIP_TO_HANDLE(dip), 359 sysino, intr_valid_state)) != H_EOK) { 360 DBG(DBG_LIB_INT, dip, "hvio_intr_setvalid failed, ret 0x%lx\n", 361 ret); 362 return (DDI_FAILURE); 363 } 364 365 return (DDI_SUCCESS); 366 } 367 368 /*ARGSUSED*/ 369 int 370 px_lib_intr_getstate(dev_info_t *dip, sysino_t sysino, 371 intr_state_t *intr_state) 372 { 373 uint64_t ret; 374 375 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: dip 0x%p sysino 0x%llx\n", 376 dip, sysino); 377 378 if ((ret = hvio_intr_getstate(DIP_TO_HANDLE(dip), 379 sysino, intr_state)) != H_EOK) { 380 DBG(DBG_LIB_INT, dip, "hvio_intr_getstate failed, ret 0x%lx\n", 381 ret); 382 return (DDI_FAILURE); 383 } 384 385 DBG(DBG_LIB_INT, dip, "px_lib_intr_getstate: intr_state 0x%x\n", 386 *intr_state); 387 388 return (DDI_SUCCESS); 389 } 390 391 /*ARGSUSED*/ 392 int 393 px_lib_intr_setstate(dev_info_t *dip, sysino_t sysino, 394 intr_state_t intr_state) 395 { 396 uint64_t ret; 397 398 DBG(DBG_LIB_INT, dip, "px_lib_intr_setstate: dip 0x%p sysino 0x%llx " 399 "intr_state 0x%x\n", dip, sysino, intr_state); 400 401 if ((ret = hvio_intr_setstate(DIP_TO_HANDLE(dip), 402 sysino, intr_state)) != H_EOK) { 403 DBG(DBG_LIB_INT, dip, "hvio_intr_setstate failed, ret 0x%lx\n", 404 ret); 405 return (DDI_FAILURE); 406 } 407 408 return (DDI_SUCCESS); 409 } 410 411 /*ARGSUSED*/ 412 int 413 px_lib_intr_gettarget(dev_info_t *dip, sysino_t sysino, cpuid_t *cpuid) 414 { 415 px_t *px_p = DIP_TO_STATE(dip); 416 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 417 uint64_t ret; 418 419 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: dip 0x%p sysino 0x%llx\n", 420 dip, sysino); 421 422 if ((ret = hvio_intr_gettarget(DIP_TO_HANDLE(dip), pxu_p, 423 sysino, cpuid)) != H_EOK) { 424 DBG(DBG_LIB_INT, dip, "hvio_intr_gettarget failed, ret 0x%lx\n", 425 ret); 426 return (DDI_FAILURE); 427 } 428 429 DBG(DBG_LIB_INT, dip, "px_lib_intr_gettarget: cpuid 0x%x\n", cpuid); 430 431 return (DDI_SUCCESS); 432 } 433 434 /*ARGSUSED*/ 435 int 436 px_lib_intr_settarget(dev_info_t *dip, sysino_t sysino, cpuid_t cpuid) 437 { 438 px_t *px_p = DIP_TO_STATE(dip); 439 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 440 uint64_t ret; 441 442 DBG(DBG_LIB_INT, dip, "px_lib_intr_settarget: dip 0x%p sysino 0x%llx " 443 "cpuid 0x%x\n", dip, sysino, cpuid); 444 445 if ((ret = hvio_intr_settarget(DIP_TO_HANDLE(dip), pxu_p, 446 sysino, cpuid)) != H_EOK) { 447 DBG(DBG_LIB_INT, dip, "hvio_intr_settarget failed, ret 0x%lx\n", 448 ret); 449 return (DDI_FAILURE); 450 } 451 452 return (DDI_SUCCESS); 453 } 454 455 /*ARGSUSED*/ 456 int 457 px_lib_intr_reset(dev_info_t *dip) 458 { 459 devino_t ino; 460 sysino_t sysino; 461 462 DBG(DBG_LIB_INT, dip, "px_lib_intr_reset: dip 0x%p\n", dip); 463 464 /* Reset all Interrupts */ 465 for (ino = 0; ino < INTERRUPT_MAPPING_ENTRIES; ino++) { 466 if (px_lib_intr_devino_to_sysino(dip, ino, 467 &sysino) != DDI_SUCCESS) 468 return (BF_FATAL); 469 470 if (px_lib_intr_setstate(dip, sysino, 471 INTR_IDLE_STATE) != DDI_SUCCESS) 472 return (BF_FATAL); 473 } 474 475 return (BF_NONE); 476 } 477 478 /*ARGSUSED*/ 479 int 480 px_lib_iommu_map(dev_info_t *dip, tsbid_t tsbid, pages_t pages, 481 io_attributes_t attr, void *addr, size_t pfn_index, int flags) 482 { 483 px_t *px_p = DIP_TO_STATE(dip); 484 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 485 uint64_t ret; 486 487 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_map: dip 0x%p tsbid 0x%llx " 488 "pages 0x%x attr 0x%x addr 0x%p pfn_index 0x%llx flags 0x%x\n", 489 dip, tsbid, pages, attr, addr, pfn_index, flags); 490 491 if ((ret = hvio_iommu_map(px_p->px_dev_hdl, pxu_p, tsbid, pages, 492 attr, addr, pfn_index, flags)) != H_EOK) { 493 DBG(DBG_LIB_DMA, dip, 494 "px_lib_iommu_map failed, ret 0x%lx\n", ret); 495 return (DDI_FAILURE); 496 } 497 498 return (DDI_SUCCESS); 499 } 500 501 /*ARGSUSED*/ 502 int 503 px_lib_iommu_demap(dev_info_t *dip, tsbid_t tsbid, pages_t pages) 504 { 505 px_t *px_p = DIP_TO_STATE(dip); 506 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 507 uint64_t ret; 508 509 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_demap: dip 0x%p tsbid 0x%llx " 510 "pages 0x%x\n", dip, tsbid, pages); 511 512 if ((ret = hvio_iommu_demap(px_p->px_dev_hdl, pxu_p, tsbid, pages)) 513 != H_EOK) { 514 DBG(DBG_LIB_DMA, dip, 515 "px_lib_iommu_demap failed, ret 0x%lx\n", ret); 516 517 return (DDI_FAILURE); 518 } 519 520 return (DDI_SUCCESS); 521 } 522 523 /*ARGSUSED*/ 524 int 525 px_lib_iommu_getmap(dev_info_t *dip, tsbid_t tsbid, io_attributes_t *attr_p, 526 r_addr_t *r_addr_p) 527 { 528 px_t *px_p = DIP_TO_STATE(dip); 529 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 530 uint64_t ret; 531 532 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: dip 0x%p tsbid 0x%llx\n", 533 dip, tsbid); 534 535 if ((ret = hvio_iommu_getmap(DIP_TO_HANDLE(dip), pxu_p, tsbid, 536 attr_p, r_addr_p)) != H_EOK) { 537 DBG(DBG_LIB_DMA, dip, 538 "hvio_iommu_getmap failed, ret 0x%lx\n", ret); 539 540 return ((ret == H_ENOMAP) ? DDI_DMA_NOMAPPING:DDI_FAILURE); 541 } 542 543 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getmap: attr 0x%x r_addr 0x%llx\n", 544 *attr_p, *r_addr_p); 545 546 return (DDI_SUCCESS); 547 } 548 549 550 /* 551 * Checks dma attributes against system bypass ranges 552 * The bypass range is determined by the hardware. Return them so the 553 * common code can do generic checking against them. 554 */ 555 /*ARGSUSED*/ 556 int 557 px_lib_dma_bypass_rngchk(dev_info_t *dip, ddi_dma_attr_t *attr_p, 558 uint64_t *lo_p, uint64_t *hi_p) 559 { 560 px_t *px_p = DIP_TO_STATE(dip); 561 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 562 563 *lo_p = hvio_get_bypass_base(pxu_p); 564 *hi_p = hvio_get_bypass_end(pxu_p); 565 566 return (DDI_SUCCESS); 567 } 568 569 570 /*ARGSUSED*/ 571 int 572 px_lib_iommu_getbypass(dev_info_t *dip, r_addr_t ra, io_attributes_t attr, 573 io_addr_t *io_addr_p) 574 { 575 uint64_t ret; 576 px_t *px_p = DIP_TO_STATE(dip); 577 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 578 579 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: dip 0x%p ra 0x%llx " 580 "attr 0x%x\n", dip, ra, attr); 581 582 if ((ret = hvio_iommu_getbypass(DIP_TO_HANDLE(dip), pxu_p, ra, 583 attr, io_addr_p)) != H_EOK) { 584 DBG(DBG_LIB_DMA, dip, 585 "hvio_iommu_getbypass failed, ret 0x%lx\n", ret); 586 return (DDI_FAILURE); 587 } 588 589 DBG(DBG_LIB_DMA, dip, "px_lib_iommu_getbypass: io_addr 0x%llx\n", 590 *io_addr_p); 591 592 return (DDI_SUCCESS); 593 } 594 595 /* 596 * bus dma sync entry point. 597 */ 598 /*ARGSUSED*/ 599 int 600 px_lib_dma_sync(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 601 off_t off, size_t len, uint_t cache_flags) 602 { 603 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)handle; 604 px_t *px_p = DIP_TO_STATE(dip); 605 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 606 607 DBG(DBG_LIB_DMA, dip, "px_lib_dma_sync: dip 0x%p rdip 0x%p " 608 "handle 0x%llx off 0x%x len 0x%x flags 0x%x\n", 609 dip, rdip, handle, off, len, cache_flags); 610 611 /* 612 * No flush needed for Oberon 613 */ 614 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) 615 return (DDI_SUCCESS); 616 617 /* 618 * jbus_stst_order is found only in certain cpu modules. 619 * Just return success if not present. 620 */ 621 if (&jbus_stst_order == NULL) 622 return (DDI_SUCCESS); 623 624 if (!(mp->dmai_flags & PX_DMAI_FLAGS_INUSE)) { 625 cmn_err(CE_WARN, "%s%d: Unbound dma handle %p.", 626 ddi_driver_name(rdip), ddi_get_instance(rdip), (void *)mp); 627 628 return (DDI_FAILURE); 629 } 630 631 if (mp->dmai_flags & PX_DMAI_FLAGS_NOSYNC) 632 return (DDI_SUCCESS); 633 634 /* 635 * No flush needed when sending data from memory to device. 636 * Nothing to do to "sync" memory to what device would already see. 637 */ 638 if (!(mp->dmai_rflags & DDI_DMA_READ) || 639 ((cache_flags & PX_DMA_SYNC_DDI_FLAGS) == DDI_DMA_SYNC_FORDEV)) 640 return (DDI_SUCCESS); 641 642 /* 643 * Perform necessary cpu workaround to ensure jbus ordering. 644 * CPU's internal "invalidate FIFOs" are flushed. 645 */ 646 647 #if !defined(lint) 648 kpreempt_disable(); 649 #endif 650 jbus_stst_order(); 651 #if !defined(lint) 652 kpreempt_enable(); 653 #endif 654 return (DDI_SUCCESS); 655 } 656 657 /* 658 * MSIQ Functions: 659 */ 660 /*ARGSUSED*/ 661 int 662 px_lib_msiq_init(dev_info_t *dip) 663 { 664 px_t *px_p = DIP_TO_STATE(dip); 665 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 666 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 667 px_dvma_addr_t pg_index; 668 size_t size; 669 int ret; 670 671 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_init: dip 0x%p\n", dip); 672 673 /* 674 * Map the EQ memory into the Fire MMU (has to be 512KB aligned) 675 * and then initialize the base address register. 676 * 677 * Allocate entries from Fire IOMMU so that the resulting address 678 * is properly aligned. Calculate the index of the first allocated 679 * entry. Note: The size of the mapping is assumed to be a multiple 680 * of the page size. 681 */ 682 size = msiq_state_p->msiq_cnt * 683 msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 684 685 pxu_p->msiq_mapped_p = vmem_xalloc(px_p->px_mmu_p->mmu_dvma_map, 686 size, (512 * 1024), 0, 0, NULL, NULL, VM_NOSLEEP | VM_BESTFIT); 687 688 if (pxu_p->msiq_mapped_p == NULL) 689 return (DDI_FAILURE); 690 691 pg_index = MMU_PAGE_INDEX(px_p->px_mmu_p, 692 MMU_BTOP((ulong_t)pxu_p->msiq_mapped_p)); 693 694 if ((ret = px_lib_iommu_map(px_p->px_dip, PCI_TSBID(0, pg_index), 695 MMU_BTOP(size), PCI_MAP_ATTR_WRITE, msiq_state_p->msiq_buf_p, 696 0, MMU_MAP_BUF)) != DDI_SUCCESS) { 697 DBG(DBG_LIB_MSIQ, dip, 698 "hvio_msiq_init failed, ret 0x%lx\n", ret); 699 700 (void) px_lib_msiq_fini(dip); 701 return (DDI_FAILURE); 702 } 703 704 (void) hvio_msiq_init(DIP_TO_HANDLE(dip), pxu_p); 705 706 return (DDI_SUCCESS); 707 } 708 709 /*ARGSUSED*/ 710 int 711 px_lib_msiq_fini(dev_info_t *dip) 712 { 713 px_t *px_p = DIP_TO_STATE(dip); 714 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 715 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 716 px_dvma_addr_t pg_index; 717 size_t size; 718 719 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_fini: dip 0x%p\n", dip); 720 721 /* 722 * Unmap and free the EQ memory that had been mapped 723 * into the Fire IOMMU. 724 */ 725 size = msiq_state_p->msiq_cnt * 726 msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 727 728 pg_index = MMU_PAGE_INDEX(px_p->px_mmu_p, 729 MMU_BTOP((ulong_t)pxu_p->msiq_mapped_p)); 730 731 (void) px_lib_iommu_demap(px_p->px_dip, 732 PCI_TSBID(0, pg_index), MMU_BTOP(size)); 733 734 /* Free the entries from the Fire MMU */ 735 vmem_xfree(px_p->px_mmu_p->mmu_dvma_map, 736 (void *)pxu_p->msiq_mapped_p, size); 737 738 return (DDI_SUCCESS); 739 } 740 741 /*ARGSUSED*/ 742 int 743 px_lib_msiq_info(dev_info_t *dip, msiqid_t msiq_id, r_addr_t *ra_p, 744 uint_t *msiq_rec_cnt_p) 745 { 746 px_t *px_p = DIP_TO_STATE(dip); 747 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 748 size_t msiq_size; 749 750 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: dip 0x%p msiq_id 0x%x\n", 751 dip, msiq_id); 752 753 msiq_size = msiq_state_p->msiq_rec_cnt * sizeof (msiq_rec_t); 754 ra_p = (r_addr_t *)((caddr_t)msiq_state_p->msiq_buf_p + 755 (msiq_id * msiq_size)); 756 757 *msiq_rec_cnt_p = msiq_state_p->msiq_rec_cnt; 758 759 DBG(DBG_LIB_MSIQ, dip, "px_msiq_info: ra_p 0x%p msiq_rec_cnt 0x%x\n", 760 ra_p, *msiq_rec_cnt_p); 761 762 return (DDI_SUCCESS); 763 } 764 765 /*ARGSUSED*/ 766 int 767 px_lib_msiq_getvalid(dev_info_t *dip, msiqid_t msiq_id, 768 pci_msiq_valid_state_t *msiq_valid_state) 769 { 770 uint64_t ret; 771 772 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: dip 0x%p msiq_id 0x%x\n", 773 dip, msiq_id); 774 775 if ((ret = hvio_msiq_getvalid(DIP_TO_HANDLE(dip), 776 msiq_id, msiq_valid_state)) != H_EOK) { 777 DBG(DBG_LIB_MSIQ, dip, 778 "hvio_msiq_getvalid failed, ret 0x%lx\n", ret); 779 return (DDI_FAILURE); 780 } 781 782 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getvalid: msiq_valid_state 0x%x\n", 783 *msiq_valid_state); 784 785 return (DDI_SUCCESS); 786 } 787 788 /*ARGSUSED*/ 789 int 790 px_lib_msiq_setvalid(dev_info_t *dip, msiqid_t msiq_id, 791 pci_msiq_valid_state_t msiq_valid_state) 792 { 793 uint64_t ret; 794 795 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setvalid: dip 0x%p msiq_id 0x%x " 796 "msiq_valid_state 0x%x\n", dip, msiq_id, msiq_valid_state); 797 798 if ((ret = hvio_msiq_setvalid(DIP_TO_HANDLE(dip), 799 msiq_id, msiq_valid_state)) != H_EOK) { 800 DBG(DBG_LIB_MSIQ, dip, 801 "hvio_msiq_setvalid failed, ret 0x%lx\n", ret); 802 return (DDI_FAILURE); 803 } 804 805 return (DDI_SUCCESS); 806 } 807 808 /*ARGSUSED*/ 809 int 810 px_lib_msiq_getstate(dev_info_t *dip, msiqid_t msiq_id, 811 pci_msiq_state_t *msiq_state) 812 { 813 uint64_t ret; 814 815 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: dip 0x%p msiq_id 0x%x\n", 816 dip, msiq_id); 817 818 if ((ret = hvio_msiq_getstate(DIP_TO_HANDLE(dip), 819 msiq_id, msiq_state)) != H_EOK) { 820 DBG(DBG_LIB_MSIQ, dip, 821 "hvio_msiq_getstate failed, ret 0x%lx\n", ret); 822 return (DDI_FAILURE); 823 } 824 825 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_getstate: msiq_state 0x%x\n", 826 *msiq_state); 827 828 return (DDI_SUCCESS); 829 } 830 831 /*ARGSUSED*/ 832 int 833 px_lib_msiq_setstate(dev_info_t *dip, msiqid_t msiq_id, 834 pci_msiq_state_t msiq_state) 835 { 836 uint64_t ret; 837 838 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_setstate: dip 0x%p msiq_id 0x%x " 839 "msiq_state 0x%x\n", dip, msiq_id, msiq_state); 840 841 if ((ret = hvio_msiq_setstate(DIP_TO_HANDLE(dip), 842 msiq_id, msiq_state)) != H_EOK) { 843 DBG(DBG_LIB_MSIQ, dip, 844 "hvio_msiq_setstate failed, ret 0x%lx\n", ret); 845 return (DDI_FAILURE); 846 } 847 848 return (DDI_SUCCESS); 849 } 850 851 /*ARGSUSED*/ 852 int 853 px_lib_msiq_gethead(dev_info_t *dip, msiqid_t msiq_id, 854 msiqhead_t *msiq_head) 855 { 856 uint64_t ret; 857 858 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: dip 0x%p msiq_id 0x%x\n", 859 dip, msiq_id); 860 861 if ((ret = hvio_msiq_gethead(DIP_TO_HANDLE(dip), 862 msiq_id, msiq_head)) != H_EOK) { 863 DBG(DBG_LIB_MSIQ, dip, 864 "hvio_msiq_gethead failed, ret 0x%lx\n", ret); 865 return (DDI_FAILURE); 866 } 867 868 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gethead: msiq_head 0x%x\n", 869 *msiq_head); 870 871 return (DDI_SUCCESS); 872 } 873 874 /*ARGSUSED*/ 875 int 876 px_lib_msiq_sethead(dev_info_t *dip, msiqid_t msiq_id, 877 msiqhead_t msiq_head) 878 { 879 uint64_t ret; 880 881 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_sethead: dip 0x%p msiq_id 0x%x " 882 "msiq_head 0x%x\n", dip, msiq_id, msiq_head); 883 884 if ((ret = hvio_msiq_sethead(DIP_TO_HANDLE(dip), 885 msiq_id, msiq_head)) != H_EOK) { 886 DBG(DBG_LIB_MSIQ, dip, 887 "hvio_msiq_sethead failed, ret 0x%lx\n", ret); 888 return (DDI_FAILURE); 889 } 890 891 return (DDI_SUCCESS); 892 } 893 894 /*ARGSUSED*/ 895 int 896 px_lib_msiq_gettail(dev_info_t *dip, msiqid_t msiq_id, 897 msiqtail_t *msiq_tail) 898 { 899 uint64_t ret; 900 901 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: dip 0x%p msiq_id 0x%x\n", 902 dip, msiq_id); 903 904 if ((ret = hvio_msiq_gettail(DIP_TO_HANDLE(dip), 905 msiq_id, msiq_tail)) != H_EOK) { 906 DBG(DBG_LIB_MSIQ, dip, 907 "hvio_msiq_gettail failed, ret 0x%lx\n", ret); 908 return (DDI_FAILURE); 909 } 910 911 DBG(DBG_LIB_MSIQ, dip, "px_lib_msiq_gettail: msiq_tail 0x%x\n", 912 *msiq_tail); 913 914 return (DDI_SUCCESS); 915 } 916 917 /*ARGSUSED*/ 918 void 919 px_lib_get_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p, 920 msiq_rec_t *msiq_rec_p) 921 { 922 eq_rec_t *eq_rec_p = (eq_rec_t *)msiq_head_p; 923 924 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: dip 0x%p eq_rec_p 0x%p\n", 925 dip, eq_rec_p); 926 927 if (!eq_rec_p->eq_rec_fmt_type) { 928 /* Set msiq_rec_type to zero */ 929 msiq_rec_p->msiq_rec_type = 0; 930 931 return; 932 } 933 934 DBG(DBG_LIB_MSIQ, dip, "px_lib_get_msiq_rec: EQ RECORD, " 935 "eq_rec_rid 0x%llx eq_rec_fmt_type 0x%llx " 936 "eq_rec_len 0x%llx eq_rec_addr0 0x%llx " 937 "eq_rec_addr1 0x%llx eq_rec_data0 0x%llx " 938 "eq_rec_data1 0x%llx\n", eq_rec_p->eq_rec_rid, 939 eq_rec_p->eq_rec_fmt_type, eq_rec_p->eq_rec_len, 940 eq_rec_p->eq_rec_addr0, eq_rec_p->eq_rec_addr1, 941 eq_rec_p->eq_rec_data0, eq_rec_p->eq_rec_data1); 942 943 /* 944 * Only upper 4 bits of eq_rec_fmt_type is used 945 * to identify the EQ record type. 946 */ 947 switch (eq_rec_p->eq_rec_fmt_type >> 3) { 948 case EQ_REC_MSI32: 949 msiq_rec_p->msiq_rec_type = MSI32_REC; 950 951 msiq_rec_p->msiq_rec_data.msi.msi_data = 952 eq_rec_p->eq_rec_data0; 953 break; 954 case EQ_REC_MSI64: 955 msiq_rec_p->msiq_rec_type = MSI64_REC; 956 957 msiq_rec_p->msiq_rec_data.msi.msi_data = 958 eq_rec_p->eq_rec_data0; 959 break; 960 case EQ_REC_MSG: 961 msiq_rec_p->msiq_rec_type = MSG_REC; 962 963 msiq_rec_p->msiq_rec_data.msg.msg_route = 964 eq_rec_p->eq_rec_fmt_type & 7; 965 msiq_rec_p->msiq_rec_data.msg.msg_targ = eq_rec_p->eq_rec_rid; 966 msiq_rec_p->msiq_rec_data.msg.msg_code = eq_rec_p->eq_rec_data0; 967 break; 968 default: 969 cmn_err(CE_WARN, "%s%d: px_lib_get_msiq_rec: " 970 "0x%x is an unknown EQ record type", 971 ddi_driver_name(dip), ddi_get_instance(dip), 972 (int)eq_rec_p->eq_rec_fmt_type); 973 break; 974 } 975 976 msiq_rec_p->msiq_rec_rid = eq_rec_p->eq_rec_rid; 977 msiq_rec_p->msiq_rec_msi_addr = ((eq_rec_p->eq_rec_addr1 << 16) | 978 (eq_rec_p->eq_rec_addr0 << 2)); 979 } 980 981 /*ARGSUSED*/ 982 void 983 px_lib_clr_msiq_rec(dev_info_t *dip, msiqhead_t *msiq_head_p) 984 { 985 eq_rec_t *eq_rec_p = (eq_rec_t *)msiq_head_p; 986 987 DBG(DBG_LIB_MSIQ, dip, "px_lib_clr_msiq_rec: dip 0x%p eq_rec_p 0x%p\n", 988 dip, eq_rec_p); 989 990 if (eq_rec_p->eq_rec_fmt_type) { 991 /* Zero out eq_rec_fmt_type field */ 992 eq_rec_p->eq_rec_fmt_type = 0; 993 } 994 } 995 996 /* 997 * MSI Functions: 998 */ 999 /*ARGSUSED*/ 1000 int 1001 px_lib_msi_init(dev_info_t *dip) 1002 { 1003 px_t *px_p = DIP_TO_STATE(dip); 1004 px_msi_state_t *msi_state_p = &px_p->px_ib_p->ib_msi_state; 1005 uint64_t ret; 1006 1007 DBG(DBG_LIB_MSI, dip, "px_lib_msi_init: dip 0x%p\n", dip); 1008 1009 if ((ret = hvio_msi_init(DIP_TO_HANDLE(dip), 1010 msi_state_p->msi_addr32, msi_state_p->msi_addr64)) != H_EOK) { 1011 DBG(DBG_LIB_MSIQ, dip, "px_lib_msi_init failed, ret 0x%lx\n", 1012 ret); 1013 return (DDI_FAILURE); 1014 } 1015 1016 return (DDI_SUCCESS); 1017 } 1018 1019 /*ARGSUSED*/ 1020 int 1021 px_lib_msi_getmsiq(dev_info_t *dip, msinum_t msi_num, 1022 msiqid_t *msiq_id) 1023 { 1024 uint64_t ret; 1025 1026 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: dip 0x%p msi_num 0x%x\n", 1027 dip, msi_num); 1028 1029 if ((ret = hvio_msi_getmsiq(DIP_TO_HANDLE(dip), 1030 msi_num, msiq_id)) != H_EOK) { 1031 DBG(DBG_LIB_MSI, dip, 1032 "hvio_msi_getmsiq failed, ret 0x%lx\n", ret); 1033 return (DDI_FAILURE); 1034 } 1035 1036 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getmsiq: msiq_id 0x%x\n", 1037 *msiq_id); 1038 1039 return (DDI_SUCCESS); 1040 } 1041 1042 /*ARGSUSED*/ 1043 int 1044 px_lib_msi_setmsiq(dev_info_t *dip, msinum_t msi_num, 1045 msiqid_t msiq_id, msi_type_t msitype) 1046 { 1047 uint64_t ret; 1048 1049 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setmsiq: dip 0x%p msi_num 0x%x " 1050 "msq_id 0x%x\n", dip, msi_num, msiq_id); 1051 1052 if ((ret = hvio_msi_setmsiq(DIP_TO_HANDLE(dip), 1053 msi_num, msiq_id)) != H_EOK) { 1054 DBG(DBG_LIB_MSI, dip, 1055 "hvio_msi_setmsiq failed, ret 0x%lx\n", ret); 1056 return (DDI_FAILURE); 1057 } 1058 1059 return (DDI_SUCCESS); 1060 } 1061 1062 /*ARGSUSED*/ 1063 int 1064 px_lib_msi_getvalid(dev_info_t *dip, msinum_t msi_num, 1065 pci_msi_valid_state_t *msi_valid_state) 1066 { 1067 uint64_t ret; 1068 1069 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: dip 0x%p msi_num 0x%x\n", 1070 dip, msi_num); 1071 1072 if ((ret = hvio_msi_getvalid(DIP_TO_HANDLE(dip), 1073 msi_num, msi_valid_state)) != H_EOK) { 1074 DBG(DBG_LIB_MSI, dip, 1075 "hvio_msi_getvalid failed, ret 0x%lx\n", ret); 1076 return (DDI_FAILURE); 1077 } 1078 1079 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getvalid: msiq_id 0x%x\n", 1080 *msi_valid_state); 1081 1082 return (DDI_SUCCESS); 1083 } 1084 1085 /*ARGSUSED*/ 1086 int 1087 px_lib_msi_setvalid(dev_info_t *dip, msinum_t msi_num, 1088 pci_msi_valid_state_t msi_valid_state) 1089 { 1090 uint64_t ret; 1091 1092 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setvalid: dip 0x%p msi_num 0x%x " 1093 "msi_valid_state 0x%x\n", dip, msi_num, msi_valid_state); 1094 1095 if ((ret = hvio_msi_setvalid(DIP_TO_HANDLE(dip), 1096 msi_num, msi_valid_state)) != H_EOK) { 1097 DBG(DBG_LIB_MSI, dip, 1098 "hvio_msi_setvalid failed, ret 0x%lx\n", ret); 1099 return (DDI_FAILURE); 1100 } 1101 1102 return (DDI_SUCCESS); 1103 } 1104 1105 /*ARGSUSED*/ 1106 int 1107 px_lib_msi_getstate(dev_info_t *dip, msinum_t msi_num, 1108 pci_msi_state_t *msi_state) 1109 { 1110 uint64_t ret; 1111 1112 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: dip 0x%p msi_num 0x%x\n", 1113 dip, msi_num); 1114 1115 if ((ret = hvio_msi_getstate(DIP_TO_HANDLE(dip), 1116 msi_num, msi_state)) != H_EOK) { 1117 DBG(DBG_LIB_MSI, dip, 1118 "hvio_msi_getstate failed, ret 0x%lx\n", ret); 1119 return (DDI_FAILURE); 1120 } 1121 1122 DBG(DBG_LIB_MSI, dip, "px_lib_msi_getstate: msi_state 0x%x\n", 1123 *msi_state); 1124 1125 return (DDI_SUCCESS); 1126 } 1127 1128 /*ARGSUSED*/ 1129 int 1130 px_lib_msi_setstate(dev_info_t *dip, msinum_t msi_num, 1131 pci_msi_state_t msi_state) 1132 { 1133 uint64_t ret; 1134 1135 DBG(DBG_LIB_MSI, dip, "px_lib_msi_setstate: dip 0x%p msi_num 0x%x " 1136 "msi_state 0x%x\n", dip, msi_num, msi_state); 1137 1138 if ((ret = hvio_msi_setstate(DIP_TO_HANDLE(dip), 1139 msi_num, msi_state)) != H_EOK) { 1140 DBG(DBG_LIB_MSI, dip, 1141 "hvio_msi_setstate failed, ret 0x%lx\n", ret); 1142 return (DDI_FAILURE); 1143 } 1144 1145 return (DDI_SUCCESS); 1146 } 1147 1148 /* 1149 * MSG Functions: 1150 */ 1151 /*ARGSUSED*/ 1152 int 1153 px_lib_msg_getmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1154 msiqid_t *msiq_id) 1155 { 1156 uint64_t ret; 1157 1158 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getmsiq: dip 0x%p msg_type 0x%x\n", 1159 dip, msg_type); 1160 1161 if ((ret = hvio_msg_getmsiq(DIP_TO_HANDLE(dip), 1162 msg_type, msiq_id)) != H_EOK) { 1163 DBG(DBG_LIB_MSG, dip, 1164 "hvio_msg_getmsiq failed, ret 0x%lx\n", ret); 1165 return (DDI_FAILURE); 1166 } 1167 1168 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getmsiq: msiq_id 0x%x\n", 1169 *msiq_id); 1170 1171 return (DDI_SUCCESS); 1172 } 1173 1174 /*ARGSUSED*/ 1175 int 1176 px_lib_msg_setmsiq(dev_info_t *dip, pcie_msg_type_t msg_type, 1177 msiqid_t msiq_id) 1178 { 1179 uint64_t ret; 1180 1181 DBG(DBG_LIB_MSG, dip, "px_lib_msi_setstate: dip 0x%p msg_type 0x%x " 1182 "msiq_id 0x%x\n", dip, msg_type, msiq_id); 1183 1184 if ((ret = hvio_msg_setmsiq(DIP_TO_HANDLE(dip), 1185 msg_type, msiq_id)) != H_EOK) { 1186 DBG(DBG_LIB_MSG, dip, 1187 "hvio_msg_setmsiq failed, ret 0x%lx\n", ret); 1188 return (DDI_FAILURE); 1189 } 1190 1191 return (DDI_SUCCESS); 1192 } 1193 1194 /*ARGSUSED*/ 1195 int 1196 px_lib_msg_getvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1197 pcie_msg_valid_state_t *msg_valid_state) 1198 { 1199 uint64_t ret; 1200 1201 DBG(DBG_LIB_MSG, dip, "px_lib_msg_getvalid: dip 0x%p msg_type 0x%x\n", 1202 dip, msg_type); 1203 1204 if ((ret = hvio_msg_getvalid(DIP_TO_HANDLE(dip), msg_type, 1205 msg_valid_state)) != H_EOK) { 1206 DBG(DBG_LIB_MSG, dip, 1207 "hvio_msg_getvalid failed, ret 0x%lx\n", ret); 1208 return (DDI_FAILURE); 1209 } 1210 1211 DBG(DBG_LIB_MSI, dip, "px_lib_msg_getvalid: msg_valid_state 0x%x\n", 1212 *msg_valid_state); 1213 1214 return (DDI_SUCCESS); 1215 } 1216 1217 /*ARGSUSED*/ 1218 int 1219 px_lib_msg_setvalid(dev_info_t *dip, pcie_msg_type_t msg_type, 1220 pcie_msg_valid_state_t msg_valid_state) 1221 { 1222 uint64_t ret; 1223 1224 DBG(DBG_LIB_MSG, dip, "px_lib_msg_setvalid: dip 0x%p msg_type 0x%x " 1225 "msg_valid_state 0x%x\n", dip, msg_type, msg_valid_state); 1226 1227 if ((ret = hvio_msg_setvalid(DIP_TO_HANDLE(dip), msg_type, 1228 msg_valid_state)) != H_EOK) { 1229 DBG(DBG_LIB_MSG, dip, 1230 "hvio_msg_setvalid failed, ret 0x%lx\n", ret); 1231 return (DDI_FAILURE); 1232 } 1233 1234 return (DDI_SUCCESS); 1235 } 1236 1237 /* 1238 * Suspend/Resume Functions: 1239 * Currently unsupported by hypervisor 1240 */ 1241 int 1242 px_lib_suspend(dev_info_t *dip) 1243 { 1244 px_t *px_p = DIP_TO_STATE(dip); 1245 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1246 px_cb_t *cb_p = PX2CB(px_p); 1247 devhandle_t dev_hdl, xbus_dev_hdl; 1248 uint64_t ret = H_EOK; 1249 1250 DBG(DBG_DETACH, dip, "px_lib_suspend: dip 0x%p\n", dip); 1251 1252 dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR]; 1253 xbus_dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_XBC]; 1254 1255 if ((ret = hvio_suspend(dev_hdl, pxu_p)) != H_EOK) 1256 goto fail; 1257 1258 if (--cb_p->attachcnt == 0) { 1259 ret = hvio_cb_suspend(xbus_dev_hdl, pxu_p); 1260 if (ret != H_EOK) 1261 cb_p->attachcnt++; 1262 } 1263 1264 fail: 1265 return ((ret != H_EOK) ? DDI_FAILURE: DDI_SUCCESS); 1266 } 1267 1268 void 1269 px_lib_resume(dev_info_t *dip) 1270 { 1271 px_t *px_p = DIP_TO_STATE(dip); 1272 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1273 px_cb_t *cb_p = PX2CB(px_p); 1274 devhandle_t dev_hdl, xbus_dev_hdl; 1275 devino_t pec_ino = px_p->px_inos[PX_INTR_PEC]; 1276 devino_t xbc_ino = px_p->px_inos[PX_INTR_XBC]; 1277 1278 DBG(DBG_ATTACH, dip, "px_lib_resume: dip 0x%p\n", dip); 1279 1280 dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_CSR]; 1281 xbus_dev_hdl = (devhandle_t)pxu_p->px_address[PX_REG_XBC]; 1282 1283 if (++cb_p->attachcnt == 1) 1284 hvio_cb_resume(dev_hdl, xbus_dev_hdl, xbc_ino, pxu_p); 1285 1286 hvio_resume(dev_hdl, pec_ino, pxu_p); 1287 } 1288 1289 /* 1290 * Generate a unique Oberon UBC ID based on the Logicial System Board and 1291 * the IO Channel from the portid property field. 1292 */ 1293 static uint64_t 1294 oberon_get_ubc_id(dev_info_t *dip) 1295 { 1296 px_t *px_p = DIP_TO_STATE(dip); 1297 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1298 uint64_t ubc_id; 1299 1300 /* 1301 * Generate a unique 6 bit UBC ID using the 2 IO_Channel#[1:0] bits and 1302 * the 4 LSB_ID[3:0] bits from the Oberon's portid property. 1303 */ 1304 ubc_id = (((pxu_p->portid >> OBERON_PORT_ID_IOC) & 1305 OBERON_PORT_ID_IOC_MASK) | (((pxu_p->portid >> 1306 OBERON_PORT_ID_LSB) & OBERON_PORT_ID_LSB_MASK) 1307 << OBERON_UBC_ID_LSB)); 1308 1309 return (ubc_id); 1310 } 1311 1312 /* 1313 * Oberon does not have a UBC scratch register, so alloc an array of scratch 1314 * registers when needed and use a unique UBC ID as an index. This code 1315 * can be simplified if we use a pre-allocated array. They are currently 1316 * being dynamically allocated because it's only needed by the Oberon. 1317 */ 1318 static void 1319 oberon_set_cb(dev_info_t *dip, uint64_t val) 1320 { 1321 uint64_t ubc_id; 1322 1323 if (px_oberon_ubc_scratch_regs == NULL) 1324 px_oberon_ubc_scratch_regs = 1325 (uint64_t *)kmem_zalloc(sizeof (uint64_t)* 1326 OBERON_UBC_ID_MAX, KM_SLEEP); 1327 1328 ubc_id = oberon_get_ubc_id(dip); 1329 1330 px_oberon_ubc_scratch_regs[ubc_id] = val; 1331 1332 /* 1333 * Check if any scratch registers are still in use. If all scratch 1334 * registers are currently set to zero, then deallocate the scratch 1335 * register array. 1336 */ 1337 for (ubc_id = 0; ubc_id < OBERON_UBC_ID_MAX; ubc_id++) { 1338 if (px_oberon_ubc_scratch_regs[ubc_id] != NULL) 1339 return; 1340 } 1341 1342 /* 1343 * All scratch registers are set to zero so deallocate the scratch 1344 * register array and set the pointer to NULL. 1345 */ 1346 kmem_free(px_oberon_ubc_scratch_regs, 1347 (sizeof (uint64_t)*OBERON_UBC_ID_MAX)); 1348 1349 px_oberon_ubc_scratch_regs = NULL; 1350 } 1351 1352 /* 1353 * Oberon does not have a UBC scratch register, so use an allocated array of 1354 * scratch registers and use the unique UBC ID as an index into that array. 1355 */ 1356 static uint64_t 1357 oberon_get_cb(dev_info_t *dip) 1358 { 1359 uint64_t ubc_id; 1360 1361 if (px_oberon_ubc_scratch_regs == NULL) 1362 return (0); 1363 1364 ubc_id = oberon_get_ubc_id(dip); 1365 1366 return (px_oberon_ubc_scratch_regs[ubc_id]); 1367 } 1368 1369 /* 1370 * Misc Functions: 1371 * Currently unsupported by hypervisor 1372 */ 1373 static uint64_t 1374 px_get_cb(dev_info_t *dip) 1375 { 1376 px_t *px_p = DIP_TO_STATE(dip); 1377 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1378 1379 /* 1380 * Oberon does not currently have Scratchpad registers. 1381 */ 1382 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) 1383 return (oberon_get_cb(dip)); 1384 1385 return (CSR_XR((caddr_t)pxu_p->px_address[PX_REG_XBC], JBUS_SCRATCH_1)); 1386 } 1387 1388 static void 1389 px_set_cb(dev_info_t *dip, uint64_t val) 1390 { 1391 px_t *px_p = DIP_TO_STATE(dip); 1392 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1393 1394 /* 1395 * Oberon does not currently have Scratchpad registers. 1396 */ 1397 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 1398 oberon_set_cb(dip, val); 1399 return; 1400 } 1401 1402 CSR_XS((caddr_t)pxu_p->px_address[PX_REG_XBC], JBUS_SCRATCH_1, val); 1403 } 1404 1405 /*ARGSUSED*/ 1406 int 1407 px_lib_map_vconfig(dev_info_t *dip, 1408 ddi_map_req_t *mp, pci_config_offset_t off, 1409 pci_regspec_t *rp, caddr_t *addrp) 1410 { 1411 /* 1412 * No special config space access services in this layer. 1413 */ 1414 return (DDI_FAILURE); 1415 } 1416 1417 void 1418 px_lib_map_attr_check(ddi_map_req_t *mp) 1419 { 1420 ddi_acc_hdl_t *hp = mp->map_handlep; 1421 1422 /* fire does not accept byte masks from PIO store merge */ 1423 if (hp->ah_acc.devacc_attr_dataorder == DDI_STORECACHING_OK_ACC) 1424 hp->ah_acc.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 1425 } 1426 1427 void 1428 px_lib_clr_errs(px_t *px_p) 1429 { 1430 px_pec_t *pec_p = px_p->px_pec_p; 1431 dev_info_t *rpdip = px_p->px_dip; 1432 int err = PX_OK, ret; 1433 int acctype = pec_p->pec_safeacc_type; 1434 ddi_fm_error_t derr; 1435 1436 /* Create the derr */ 1437 bzero(&derr, sizeof (ddi_fm_error_t)); 1438 derr.fme_version = DDI_FME_VERSION; 1439 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 1440 derr.fme_flag = acctype; 1441 1442 if (acctype == DDI_FM_ERR_EXPECTED) { 1443 derr.fme_status = DDI_FM_NONFATAL; 1444 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, &derr); 1445 } 1446 1447 mutex_enter(&px_p->px_fm_mutex); 1448 1449 /* send ereport/handle/clear fire registers */ 1450 err = px_err_handle(px_p, &derr, PX_LIB_CALL, B_TRUE); 1451 1452 /* Check all child devices for errors */ 1453 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 1454 1455 mutex_exit(&px_p->px_fm_mutex); 1456 1457 /* 1458 * PX_FATAL_HW indicates a condition recovered from Fatal-Reset, 1459 * therefore it does not cause panic. 1460 */ 1461 if ((err & (PX_FATAL_GOS | PX_FATAL_SW)) || (ret == DDI_FM_FATAL)) 1462 PX_FM_PANIC("Fatal System Port Error has occurred\n"); 1463 } 1464 1465 #ifdef DEBUG 1466 int px_peekfault_cnt = 0; 1467 int px_pokefault_cnt = 0; 1468 #endif /* DEBUG */ 1469 1470 /*ARGSUSED*/ 1471 static int 1472 px_lib_do_poke(dev_info_t *dip, dev_info_t *rdip, 1473 peekpoke_ctlops_t *in_args) 1474 { 1475 px_t *px_p = DIP_TO_STATE(dip); 1476 px_pec_t *pec_p = px_p->px_pec_p; 1477 int err = DDI_SUCCESS; 1478 on_trap_data_t otd; 1479 1480 mutex_enter(&pec_p->pec_pokefault_mutex); 1481 pec_p->pec_ontrap_data = &otd; 1482 pec_p->pec_safeacc_type = DDI_FM_ERR_POKE; 1483 1484 /* Set up protected environment. */ 1485 if (!on_trap(&otd, OT_DATA_ACCESS)) { 1486 uintptr_t tramp = otd.ot_trampoline; 1487 1488 otd.ot_trampoline = (uintptr_t)&poke_fault; 1489 err = do_poke(in_args->size, (void *)in_args->dev_addr, 1490 (void *)in_args->host_addr); 1491 otd.ot_trampoline = tramp; 1492 } else 1493 err = DDI_FAILURE; 1494 1495 px_lib_clr_errs(px_p); 1496 1497 if (otd.ot_trap & OT_DATA_ACCESS) 1498 err = DDI_FAILURE; 1499 1500 /* Take down protected environment. */ 1501 no_trap(); 1502 1503 pec_p->pec_ontrap_data = NULL; 1504 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1505 mutex_exit(&pec_p->pec_pokefault_mutex); 1506 1507 #ifdef DEBUG 1508 if (err == DDI_FAILURE) 1509 px_pokefault_cnt++; 1510 #endif 1511 return (err); 1512 } 1513 1514 /*ARGSUSED*/ 1515 static int 1516 px_lib_do_caut_put(dev_info_t *dip, dev_info_t *rdip, 1517 peekpoke_ctlops_t *cautacc_ctlops_arg) 1518 { 1519 size_t size = cautacc_ctlops_arg->size; 1520 uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr; 1521 uintptr_t host_addr = cautacc_ctlops_arg->host_addr; 1522 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle; 1523 size_t repcount = cautacc_ctlops_arg->repcount; 1524 uint_t flags = cautacc_ctlops_arg->flags; 1525 1526 px_t *px_p = DIP_TO_STATE(dip); 1527 px_pec_t *pec_p = px_p->px_pec_p; 1528 int err = DDI_SUCCESS; 1529 1530 /* 1531 * Note that i_ndi_busop_access_enter ends up grabbing the pokefault 1532 * mutex. 1533 */ 1534 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1535 1536 pec_p->pec_ontrap_data = (on_trap_data_t *)hp->ahi_err->err_ontrap; 1537 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1538 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1539 1540 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1541 for (; repcount; repcount--) { 1542 switch (size) { 1543 1544 case sizeof (uint8_t): 1545 i_ddi_put8(hp, (uint8_t *)dev_addr, 1546 *(uint8_t *)host_addr); 1547 break; 1548 1549 case sizeof (uint16_t): 1550 i_ddi_put16(hp, (uint16_t *)dev_addr, 1551 *(uint16_t *)host_addr); 1552 break; 1553 1554 case sizeof (uint32_t): 1555 i_ddi_put32(hp, (uint32_t *)dev_addr, 1556 *(uint32_t *)host_addr); 1557 break; 1558 1559 case sizeof (uint64_t): 1560 i_ddi_put64(hp, (uint64_t *)dev_addr, 1561 *(uint64_t *)host_addr); 1562 break; 1563 } 1564 1565 host_addr += size; 1566 1567 if (flags == DDI_DEV_AUTOINCR) 1568 dev_addr += size; 1569 1570 px_lib_clr_errs(px_p); 1571 1572 if (pec_p->pec_ontrap_data->ot_trap & OT_DATA_ACCESS) { 1573 err = DDI_FAILURE; 1574 #ifdef DEBUG 1575 px_pokefault_cnt++; 1576 #endif 1577 break; 1578 } 1579 } 1580 } 1581 1582 i_ddi_notrap((ddi_acc_handle_t)hp); 1583 pec_p->pec_ontrap_data = NULL; 1584 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1585 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1586 hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED; 1587 1588 return (err); 1589 } 1590 1591 1592 int 1593 px_lib_ctlops_poke(dev_info_t *dip, dev_info_t *rdip, 1594 peekpoke_ctlops_t *in_args) 1595 { 1596 return (in_args->handle ? px_lib_do_caut_put(dip, rdip, in_args) : 1597 px_lib_do_poke(dip, rdip, in_args)); 1598 } 1599 1600 1601 /*ARGSUSED*/ 1602 static int 1603 px_lib_do_peek(dev_info_t *dip, peekpoke_ctlops_t *in_args) 1604 { 1605 px_t *px_p = DIP_TO_STATE(dip); 1606 px_pec_t *pec_p = px_p->px_pec_p; 1607 int err = DDI_SUCCESS; 1608 on_trap_data_t otd; 1609 1610 mutex_enter(&pec_p->pec_pokefault_mutex); 1611 pec_p->pec_safeacc_type = DDI_FM_ERR_PEEK; 1612 1613 if (!on_trap(&otd, OT_DATA_ACCESS)) { 1614 uintptr_t tramp = otd.ot_trampoline; 1615 1616 otd.ot_trampoline = (uintptr_t)&peek_fault; 1617 err = do_peek(in_args->size, (void *)in_args->dev_addr, 1618 (void *)in_args->host_addr); 1619 otd.ot_trampoline = tramp; 1620 } else 1621 err = DDI_FAILURE; 1622 1623 no_trap(); 1624 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1625 mutex_exit(&pec_p->pec_pokefault_mutex); 1626 1627 #ifdef DEBUG 1628 if (err == DDI_FAILURE) 1629 px_peekfault_cnt++; 1630 #endif 1631 return (err); 1632 } 1633 1634 1635 static int 1636 px_lib_do_caut_get(dev_info_t *dip, peekpoke_ctlops_t *cautacc_ctlops_arg) 1637 { 1638 size_t size = cautacc_ctlops_arg->size; 1639 uintptr_t dev_addr = cautacc_ctlops_arg->dev_addr; 1640 uintptr_t host_addr = cautacc_ctlops_arg->host_addr; 1641 ddi_acc_impl_t *hp = (ddi_acc_impl_t *)cautacc_ctlops_arg->handle; 1642 size_t repcount = cautacc_ctlops_arg->repcount; 1643 uint_t flags = cautacc_ctlops_arg->flags; 1644 1645 px_t *px_p = DIP_TO_STATE(dip); 1646 px_pec_t *pec_p = px_p->px_pec_p; 1647 int err = DDI_SUCCESS; 1648 1649 /* 1650 * Note that i_ndi_busop_access_enter ends up grabbing the pokefault 1651 * mutex. 1652 */ 1653 i_ndi_busop_access_enter(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1654 1655 pec_p->pec_ontrap_data = (on_trap_data_t *)hp->ahi_err->err_ontrap; 1656 pec_p->pec_safeacc_type = DDI_FM_ERR_EXPECTED; 1657 hp->ahi_err->err_expected = DDI_FM_ERR_EXPECTED; 1658 1659 if (repcount == 1) { 1660 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1661 i_ddi_caut_get(size, (void *)dev_addr, 1662 (void *)host_addr); 1663 } else { 1664 int i; 1665 uint8_t *ff_addr = (uint8_t *)host_addr; 1666 for (i = 0; i < size; i++) 1667 *ff_addr++ = 0xff; 1668 1669 err = DDI_FAILURE; 1670 #ifdef DEBUG 1671 px_peekfault_cnt++; 1672 #endif 1673 } 1674 } else { 1675 if (!i_ddi_ontrap((ddi_acc_handle_t)hp)) { 1676 for (; repcount; repcount--) { 1677 i_ddi_caut_get(size, (void *)dev_addr, 1678 (void *)host_addr); 1679 1680 host_addr += size; 1681 1682 if (flags == DDI_DEV_AUTOINCR) 1683 dev_addr += size; 1684 } 1685 } else { 1686 err = DDI_FAILURE; 1687 #ifdef DEBUG 1688 px_peekfault_cnt++; 1689 #endif 1690 } 1691 } 1692 1693 i_ddi_notrap((ddi_acc_handle_t)hp); 1694 pec_p->pec_ontrap_data = NULL; 1695 pec_p->pec_safeacc_type = DDI_FM_ERR_UNEXPECTED; 1696 i_ndi_busop_access_exit(hp->ahi_common.ah_dip, (ddi_acc_handle_t)hp); 1697 hp->ahi_err->err_expected = DDI_FM_ERR_UNEXPECTED; 1698 1699 return (err); 1700 } 1701 1702 /*ARGSUSED*/ 1703 int 1704 px_lib_ctlops_peek(dev_info_t *dip, dev_info_t *rdip, 1705 peekpoke_ctlops_t *in_args, void *result) 1706 { 1707 result = (void *)in_args->host_addr; 1708 return (in_args->handle ? px_lib_do_caut_get(dip, in_args) : 1709 px_lib_do_peek(dip, in_args)); 1710 } 1711 1712 /* 1713 * implements PPM interface 1714 */ 1715 int 1716 px_lib_pmctl(int cmd, px_t *px_p) 1717 { 1718 ASSERT((cmd & ~PPMREQ_MASK) == PPMREQ); 1719 switch (cmd) { 1720 case PPMREQ_PRE_PWR_OFF: 1721 /* 1722 * Currently there is no device power management for 1723 * the root complex (fire). When there is we need to make 1724 * sure that it is at full power before trying to send the 1725 * PME_Turn_Off message. 1726 */ 1727 DBG(DBG_PWR, px_p->px_dip, 1728 "ioctl: request to send PME_Turn_Off\n"); 1729 return (px_goto_l23ready(px_p)); 1730 1731 case PPMREQ_PRE_PWR_ON: 1732 DBG(DBG_PWR, px_p->px_dip, "ioctl: PRE_PWR_ON request\n"); 1733 return (px_pre_pwron_check(px_p)); 1734 1735 case PPMREQ_POST_PWR_ON: 1736 DBG(DBG_PWR, px_p->px_dip, "ioctl: POST_PWR_ON request\n"); 1737 return (px_goto_l0(px_p)); 1738 1739 default: 1740 return (DDI_FAILURE); 1741 } 1742 } 1743 1744 /* 1745 * sends PME_Turn_Off message to put the link in L2/L3 ready state. 1746 * called by px_ioctl. 1747 * returns DDI_SUCCESS or DDI_FAILURE 1748 * 1. Wait for link to be in L1 state (link status reg) 1749 * 2. write to PME_Turn_off reg to boradcast 1750 * 3. set timeout 1751 * 4. If timeout, return failure. 1752 * 5. If PM_TO_Ack, wait till link is in L2/L3 ready 1753 */ 1754 static int 1755 px_goto_l23ready(px_t *px_p) 1756 { 1757 pcie_pwr_t *pwr_p; 1758 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1759 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 1760 int ret = DDI_SUCCESS; 1761 clock_t end, timeleft; 1762 int mutex_held = 1; 1763 1764 /* If no PM info, return failure */ 1765 if (!PCIE_PMINFO(px_p->px_dip) || 1766 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1767 return (DDI_FAILURE); 1768 1769 mutex_enter(&pwr_p->pwr_lock); 1770 mutex_enter(&px_p->px_l23ready_lock); 1771 /* Clear the PME_To_ACK receieved flag */ 1772 px_p->px_pm_flags &= ~PX_PMETOACK_RECVD; 1773 /* 1774 * When P25 is the downstream device, after receiving 1775 * PME_To_ACK, fire will go to Detect state, which causes 1776 * the link down event. Inform FMA that this is expected. 1777 * In case of all other cards complaint with the pci express 1778 * spec, this will happen when the power is re-applied. FMA 1779 * code will clear this flag after one instance of LDN. Since 1780 * there will not be a LDN event for the spec compliant cards, 1781 * we need to clear the flag after receiving PME_To_ACK. 1782 */ 1783 px_p->px_pm_flags |= PX_LDN_EXPECTED; 1784 if (px_send_pme_turnoff(csr_base) != DDI_SUCCESS) { 1785 ret = DDI_FAILURE; 1786 goto l23ready_done; 1787 } 1788 px_p->px_pm_flags |= PX_PME_TURNOFF_PENDING; 1789 1790 end = ddi_get_lbolt() + drv_usectohz(px_pme_to_ack_timeout); 1791 while (!(px_p->px_pm_flags & PX_PMETOACK_RECVD)) { 1792 timeleft = cv_timedwait(&px_p->px_l23ready_cv, 1793 &px_p->px_l23ready_lock, end); 1794 /* 1795 * if cv_timedwait returns -1, it is either 1796 * 1) timed out or 1797 * 2) there was a pre-mature wakeup but by the time 1798 * cv_timedwait is called again end < lbolt i.e. 1799 * end is in the past. 1800 * 3) By the time we make first cv_timedwait call, 1801 * end < lbolt is true. 1802 */ 1803 if (timeleft == -1) 1804 break; 1805 } 1806 if (!(px_p->px_pm_flags & PX_PMETOACK_RECVD)) { 1807 /* 1808 * Either timedout or interrupt didn't get a 1809 * chance to grab the mutex and set the flag. 1810 * release the mutex and delay for sometime. 1811 * This will 1) give a chance for interrupt to 1812 * set the flag 2) creates a delay between two 1813 * consequetive requests. 1814 */ 1815 mutex_exit(&px_p->px_l23ready_lock); 1816 delay(drv_usectohz(50 * PX_MSEC_TO_USEC)); 1817 mutex_held = 0; 1818 if (!(px_p->px_pm_flags & PX_PMETOACK_RECVD)) { 1819 ret = DDI_FAILURE; 1820 DBG(DBG_PWR, px_p->px_dip, " Timed out while waiting" 1821 " for PME_TO_ACK\n"); 1822 } 1823 } 1824 px_p->px_pm_flags &= 1825 ~(PX_PME_TURNOFF_PENDING | PX_PMETOACK_RECVD | PX_LDN_EXPECTED); 1826 1827 l23ready_done: 1828 if (mutex_held) 1829 mutex_exit(&px_p->px_l23ready_lock); 1830 /* 1831 * Wait till link is in L1 idle, if sending PME_Turn_Off 1832 * was succesful. 1833 */ 1834 if (ret == DDI_SUCCESS) { 1835 if (px_link_wait4l1idle(csr_base) != DDI_SUCCESS) { 1836 DBG(DBG_PWR, px_p->px_dip, " Link is not at L1" 1837 " even though we received PME_To_ACK.\n"); 1838 /* 1839 * Workaround for hardware bug with P25. 1840 * Due to a hardware bug with P25, link state 1841 * will be Detect state rather than L1 after 1842 * link is transitioned to L23Ready state. Since 1843 * we don't know whether link is L23ready state 1844 * without Fire's state being L1_idle, we delay 1845 * here just to make sure that we wait till link 1846 * is transitioned to L23Ready state. 1847 */ 1848 delay(drv_usectohz(100 * PX_MSEC_TO_USEC)); 1849 } 1850 pwr_p->pwr_link_lvl = PM_LEVEL_L3; 1851 1852 } 1853 mutex_exit(&pwr_p->pwr_lock); 1854 return (ret); 1855 } 1856 1857 /* 1858 * Message interrupt handler intended to be shared for both 1859 * PME and PME_TO_ACK msg handling, currently only handles 1860 * PME_To_ACK message. 1861 */ 1862 uint_t 1863 px_pmeq_intr(caddr_t arg) 1864 { 1865 px_t *px_p = (px_t *)arg; 1866 1867 DBG(DBG_PWR, px_p->px_dip, " PME_To_ACK received \n"); 1868 mutex_enter(&px_p->px_l23ready_lock); 1869 cv_broadcast(&px_p->px_l23ready_cv); 1870 if (px_p->px_pm_flags & PX_PME_TURNOFF_PENDING) { 1871 px_p->px_pm_flags |= PX_PMETOACK_RECVD; 1872 } else { 1873 /* 1874 * This maybe the second ack received. If so then, 1875 * we should be receiving it during wait4L1 stage. 1876 */ 1877 px_p->px_pmetoack_ignored++; 1878 } 1879 mutex_exit(&px_p->px_l23ready_lock); 1880 return (DDI_INTR_CLAIMED); 1881 } 1882 1883 static int 1884 px_pre_pwron_check(px_t *px_p) 1885 { 1886 pcie_pwr_t *pwr_p; 1887 1888 /* If no PM info, return failure */ 1889 if (!PCIE_PMINFO(px_p->px_dip) || 1890 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1891 return (DDI_FAILURE); 1892 1893 /* 1894 * For the spec compliant downstream cards link down 1895 * is expected when the device is powered on. 1896 */ 1897 px_p->px_pm_flags |= PX_LDN_EXPECTED; 1898 return (pwr_p->pwr_link_lvl == PM_LEVEL_L3 ? DDI_SUCCESS : DDI_FAILURE); 1899 } 1900 1901 static int 1902 px_goto_l0(px_t *px_p) 1903 { 1904 pcie_pwr_t *pwr_p; 1905 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1906 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 1907 int ret = DDI_SUCCESS; 1908 uint64_t time_spent = 0; 1909 1910 /* If no PM info, return failure */ 1911 if (!PCIE_PMINFO(px_p->px_dip) || 1912 !(pwr_p = PCIE_NEXUS_PMINFO(px_p->px_dip))) 1913 return (DDI_FAILURE); 1914 1915 mutex_enter(&pwr_p->pwr_lock); 1916 /* 1917 * The following link retrain activity will cause LDN and LUP event. 1918 * Receiving LDN prior to receiving LUP is expected, not an error in 1919 * this case. Receiving LUP indicates link is fully up to support 1920 * powering up down stream device, and of course any further LDN and 1921 * LUP outside this context will be error. 1922 */ 1923 px_p->px_lup_pending = 1; 1924 if (px_link_retrain(csr_base) != DDI_SUCCESS) { 1925 ret = DDI_FAILURE; 1926 goto l0_done; 1927 } 1928 1929 /* LUP event takes the order of 15ms amount of time to occur */ 1930 for (; px_p->px_lup_pending && (time_spent < px_lup_poll_to); 1931 time_spent += px_lup_poll_interval) 1932 drv_usecwait(px_lup_poll_interval); 1933 if (px_p->px_lup_pending) 1934 ret = DDI_FAILURE; 1935 l0_done: 1936 px_enable_detect_quiet(csr_base); 1937 if (ret == DDI_SUCCESS) 1938 pwr_p->pwr_link_lvl = PM_LEVEL_L0; 1939 mutex_exit(&pwr_p->pwr_lock); 1940 return (ret); 1941 } 1942 1943 /* 1944 * Extract the drivers binding name to identify which chip we're binding to. 1945 * Whenever a new bus bridge is created, the driver alias entry should be 1946 * added here to identify the device if needed. If a device isn't added, 1947 * the identity defaults to PX_CHIP_UNIDENTIFIED. 1948 */ 1949 static uint32_t 1950 px_identity_init(px_t *px_p) 1951 { 1952 dev_info_t *dip = px_p->px_dip; 1953 char *name = ddi_binding_name(dip); 1954 uint32_t revision = 0; 1955 1956 revision = ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1957 "module-revision#", 0); 1958 1959 /* Check for Fire driver binding name */ 1960 if (strcmp(name, "pciex108e,80f0") == 0) { 1961 DBG(DBG_ATTACH, dip, "px_identity_init: %s%d: " 1962 "(FIRE), module-revision %d\n", NAMEINST(dip), 1963 revision); 1964 1965 return ((revision >= FIRE_MOD_REV_20) ? 1966 PX_CHIP_FIRE : PX_CHIP_UNIDENTIFIED); 1967 } 1968 1969 /* Check for Oberon driver binding name */ 1970 if (strcmp(name, "pciex108e,80f8") == 0) { 1971 DBG(DBG_ATTACH, dip, "px_identity_init: %s%d: " 1972 "(OBERON), module-revision %d\n", NAMEINST(dip), 1973 revision); 1974 1975 return (PX_CHIP_OBERON); 1976 } 1977 1978 DBG(DBG_ATTACH, dip, "%s%d: Unknown PCI Express Host bridge %s %x\n", 1979 ddi_driver_name(dip), ddi_get_instance(dip), name, revision); 1980 1981 return (PX_CHIP_UNIDENTIFIED); 1982 } 1983 1984 int 1985 px_err_add_intr(px_fault_t *px_fault_p) 1986 { 1987 dev_info_t *dip = px_fault_p->px_fh_dip; 1988 px_t *px_p = DIP_TO_STATE(dip); 1989 1990 VERIFY(add_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL, 1991 (intrfunc)px_fault_p->px_err_func, (caddr_t)px_fault_p, 1992 NULL, NULL) == 0); 1993 1994 px_ib_intr_enable(px_p, intr_dist_cpuid(), px_fault_p->px_intr_ino); 1995 1996 return (DDI_SUCCESS); 1997 } 1998 1999 void 2000 px_err_rem_intr(px_fault_t *px_fault_p) 2001 { 2002 dev_info_t *dip = px_fault_p->px_fh_dip; 2003 px_t *px_p = DIP_TO_STATE(dip); 2004 2005 px_ib_intr_disable(px_p->px_ib_p, px_fault_p->px_intr_ino, 2006 IB_INTR_WAIT); 2007 2008 VERIFY(rem_ivintr(px_fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 2009 } 2010 2011 /* 2012 * px_cb_add_intr() - Called from attach(9E) to create CB if not yet 2013 * created, to add CB interrupt vector always, but enable only once. 2014 */ 2015 int 2016 px_cb_add_intr(px_fault_t *fault_p) 2017 { 2018 px_t *px_p = DIP_TO_STATE(fault_p->px_fh_dip); 2019 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2020 px_cb_t *cb_p = (px_cb_t *)px_get_cb(fault_p->px_fh_dip); 2021 px_cb_list_t *pxl, *pxl_new; 2022 cpuid_t cpuid; 2023 2024 2025 if (cb_p == NULL) { 2026 cb_p = kmem_zalloc(sizeof (px_cb_t), KM_SLEEP); 2027 mutex_init(&cb_p->cb_mutex, NULL, MUTEX_DRIVER, NULL); 2028 cb_p->px_cb_func = px_cb_intr; 2029 pxu_p->px_cb_p = cb_p; 2030 px_set_cb(fault_p->px_fh_dip, (uint64_t)cb_p); 2031 2032 /* px_lib_dev_init allows only FIRE and OBERON */ 2033 px_err_reg_enable( 2034 (pxu_p->chip_type == PX_CHIP_FIRE) ? 2035 PX_ERR_JBC : PX_ERR_UBC, 2036 pxu_p->px_address[PX_REG_XBC]); 2037 } else 2038 pxu_p->px_cb_p = cb_p; 2039 2040 mutex_enter(&cb_p->cb_mutex); 2041 2042 VERIFY(add_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL, 2043 (intrfunc)cb_p->px_cb_func, (caddr_t)cb_p, NULL, NULL) == 0); 2044 2045 if (cb_p->pxl == NULL) { 2046 2047 cpuid = intr_dist_cpuid(), 2048 px_ib_intr_enable(px_p, cpuid, fault_p->px_intr_ino); 2049 2050 pxl = kmem_zalloc(sizeof (px_cb_list_t), KM_SLEEP); 2051 pxl->pxp = px_p; 2052 2053 cb_p->pxl = pxl; 2054 cb_p->sysino = fault_p->px_fh_sysino; 2055 cb_p->cpuid = cpuid; 2056 2057 } else { 2058 /* 2059 * Find the last pxl or 2060 * stop short at encoutering a redundent, or 2061 * both. 2062 */ 2063 pxl = cb_p->pxl; 2064 for (; !(pxl->pxp == px_p) && pxl->next; pxl = pxl->next); 2065 if (pxl->pxp == px_p) { 2066 cmn_err(CE_WARN, "px_cb_add_intr: reregister sysino " 2067 "%lx by px_p 0x%p\n", cb_p->sysino, (void *)px_p); 2068 return (DDI_FAILURE); 2069 } 2070 2071 /* add to linked list */ 2072 pxl_new = kmem_zalloc(sizeof (px_cb_list_t), KM_SLEEP); 2073 pxl_new->pxp = px_p; 2074 pxl->next = pxl_new; 2075 } 2076 cb_p->attachcnt++; 2077 2078 mutex_exit(&cb_p->cb_mutex); 2079 2080 return (DDI_SUCCESS); 2081 } 2082 2083 /* 2084 * px_cb_rem_intr() - Called from detach(9E) to remove its CB 2085 * interrupt vector, to shift proxy to the next available px, 2086 * or disable CB interrupt when itself is the last. 2087 */ 2088 void 2089 px_cb_rem_intr(px_fault_t *fault_p) 2090 { 2091 px_t *px_p = DIP_TO_STATE(fault_p->px_fh_dip), *pxp; 2092 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2093 px_cb_t *cb_p = PX2CB(px_p); 2094 px_cb_list_t *pxl, *prev; 2095 px_fault_t *f_p; 2096 2097 ASSERT(cb_p->pxl); 2098 2099 /* De-list the target px, move the next px up */ 2100 2101 mutex_enter(&cb_p->cb_mutex); 2102 2103 pxl = cb_p->pxl; 2104 if (pxl->pxp == px_p) { 2105 cb_p->pxl = pxl->next; 2106 } else { 2107 prev = pxl; 2108 pxl = pxl->next; 2109 for (; pxl && (pxl->pxp != px_p); prev = pxl, pxl = pxl->next); 2110 if (!pxl) { 2111 cmn_err(CE_WARN, "px_cb_rem_intr: can't find px_p 0x%p " 2112 "in registered CB list.", (void *)px_p); 2113 return; 2114 } 2115 prev->next = pxl->next; 2116 } 2117 kmem_free(pxl, sizeof (px_cb_list_t)); 2118 2119 if (fault_p->px_fh_sysino == cb_p->sysino) { 2120 px_ib_intr_disable(px_p->px_ib_p, fault_p->px_intr_ino, 2121 IB_INTR_WAIT); 2122 2123 if (cb_p->pxl) { 2124 pxp = cb_p->pxl->pxp; 2125 f_p = &pxp->px_cb_fault; 2126 cb_p->sysino = f_p->px_fh_sysino; 2127 2128 PX_INTR_ENABLE(pxp->px_dip, cb_p->sysino, cb_p->cpuid); 2129 (void) px_lib_intr_setstate(pxp->px_dip, cb_p->sysino, 2130 INTR_IDLE_STATE); 2131 } 2132 } 2133 2134 VERIFY(rem_ivintr(fault_p->px_fh_sysino, PX_ERR_PIL) == 0); 2135 pxu_p->px_cb_p = NULL; 2136 cb_p->attachcnt--; 2137 if (cb_p->pxl) { 2138 mutex_exit(&cb_p->cb_mutex); 2139 return; 2140 } 2141 mutex_exit(&cb_p->cb_mutex); 2142 2143 /* px_lib_dev_init allows only FIRE and OBERON */ 2144 px_err_reg_disable( 2145 (pxu_p->chip_type == PX_CHIP_FIRE) ? PX_ERR_JBC : PX_ERR_UBC, 2146 pxu_p->px_address[PX_REG_XBC]); 2147 2148 mutex_destroy(&cb_p->cb_mutex); 2149 px_set_cb(fault_p->px_fh_dip, 0ull); 2150 kmem_free(cb_p, sizeof (px_cb_t)); 2151 } 2152 2153 /* 2154 * px_cb_intr() - sun4u only, CB interrupt dispatcher 2155 */ 2156 uint_t 2157 px_cb_intr(caddr_t arg) 2158 { 2159 px_cb_t *cb_p = (px_cb_t *)arg; 2160 px_cb_list_t *pxl = cb_p->pxl; 2161 px_t *pxp = pxl ? pxl->pxp : NULL; 2162 px_fault_t *fault_p; 2163 2164 while (pxl && pxp && (pxp->px_state != PX_ATTACHED)) { 2165 pxl = pxl->next; 2166 pxp = (pxl) ? pxl->pxp : NULL; 2167 } 2168 2169 if (pxp) { 2170 fault_p = &pxp->px_cb_fault; 2171 return (fault_p->px_err_func((caddr_t)fault_p)); 2172 } else 2173 return (DDI_INTR_UNCLAIMED); 2174 } 2175 2176 /* 2177 * px_cb_intr_redist() - sun4u only, CB interrupt redistribution 2178 */ 2179 void 2180 px_cb_intr_redist(px_t *px_p) 2181 { 2182 px_fault_t *f_p = &px_p->px_cb_fault; 2183 px_cb_t *cb_p = PX2CB(px_p); 2184 devino_t ino = px_p->px_inos[PX_INTR_XBC]; 2185 cpuid_t cpuid; 2186 2187 mutex_enter(&cb_p->cb_mutex); 2188 2189 if (cb_p->sysino != f_p->px_fh_sysino) { 2190 mutex_exit(&cb_p->cb_mutex); 2191 return; 2192 } 2193 2194 cb_p->cpuid = cpuid = intr_dist_cpuid(); 2195 px_ib_intr_dist_en(px_p->px_dip, cpuid, ino, B_FALSE); 2196 2197 mutex_exit(&cb_p->cb_mutex); 2198 } 2199 2200 #ifdef FMA 2201 void 2202 px_fill_rc_status(px_fault_t *px_fault_p, pciex_rc_error_regs_t *rc_status) 2203 { 2204 /* populate the rc_status by reading the registers - TBD */ 2205 } 2206 #endif /* FMA */ 2207 2208 /* 2209 * Unprotected raw reads/writes of fabric device's config space. 2210 * Only used for temporary PCI-E Fabric Error Handling. 2211 */ 2212 uint32_t 2213 px_fab_get(px_t *px_p, pcie_req_id_t bdf, uint16_t offset) 2214 { 2215 px_ranges_t *rp = px_p->px_ranges_p; 2216 uint64_t range_prop, base_addr; 2217 int bank = PCI_REG_ADDR_G(PCI_ADDR_CONFIG); 2218 uint32_t val; 2219 2220 /* Get Fire's Physical Base Address */ 2221 range_prop = px_get_range_prop(px_p, rp, bank); 2222 2223 /* Get config space first. */ 2224 base_addr = range_prop + PX_BDF_TO_CFGADDR(bdf, offset); 2225 2226 val = ldphysio(base_addr); 2227 2228 return (LE_32(val)); 2229 } 2230 2231 void 2232 px_fab_set(px_t *px_p, pcie_req_id_t bdf, uint16_t offset, 2233 uint32_t val) { 2234 px_ranges_t *rp = px_p->px_ranges_p; 2235 uint64_t range_prop, base_addr; 2236 int bank = PCI_REG_ADDR_G(PCI_ADDR_CONFIG); 2237 2238 /* Get Fire's Physical Base Address */ 2239 range_prop = px_get_range_prop(px_p, rp, bank); 2240 2241 /* Get config space first. */ 2242 base_addr = range_prop + PX_BDF_TO_CFGADDR(bdf, offset); 2243 2244 stphysio(base_addr, LE_32(val)); 2245 } 2246 2247 /* 2248 * cpr callback 2249 * 2250 * disable fabric error msg interrupt prior to suspending 2251 * all device drivers; re-enable fabric error msg interrupt 2252 * after all devices are resumed. 2253 */ 2254 static boolean_t 2255 px_cpr_callb(void *arg, int code) 2256 { 2257 px_t *px_p = (px_t *)arg; 2258 px_ib_t *ib_p = px_p->px_ib_p; 2259 px_pec_t *pec_p = px_p->px_pec_p; 2260 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2261 caddr_t csr_base; 2262 devino_t ce_ino, nf_ino, f_ino; 2263 px_ino_t *ce_ino_p, *nf_ino_p, *f_ino_p; 2264 uint64_t imu_log_enable, imu_intr_enable; 2265 uint64_t imu_log_mask, imu_intr_mask; 2266 2267 ce_ino = px_msiqid_to_devino(px_p, pec_p->pec_corr_msg_msiq_id); 2268 nf_ino = px_msiqid_to_devino(px_p, pec_p->pec_non_fatal_msg_msiq_id); 2269 f_ino = px_msiqid_to_devino(px_p, pec_p->pec_fatal_msg_msiq_id); 2270 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 2271 2272 imu_log_enable = CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE); 2273 imu_intr_enable = CSR_XR(csr_base, IMU_INTERRUPT_ENABLE); 2274 2275 imu_log_mask = BITMASK(IMU_ERROR_LOG_ENABLE_FATAL_MES_NOT_EN_LOG_EN) | 2276 BITMASK(IMU_ERROR_LOG_ENABLE_NONFATAL_MES_NOT_EN_LOG_EN) | 2277 BITMASK(IMU_ERROR_LOG_ENABLE_COR_MES_NOT_EN_LOG_EN); 2278 2279 imu_intr_mask = 2280 BITMASK(IMU_INTERRUPT_ENABLE_FATAL_MES_NOT_EN_S_INT_EN) | 2281 BITMASK(IMU_INTERRUPT_ENABLE_NONFATAL_MES_NOT_EN_S_INT_EN) | 2282 BITMASK(IMU_INTERRUPT_ENABLE_COR_MES_NOT_EN_S_INT_EN) | 2283 BITMASK(IMU_INTERRUPT_ENABLE_FATAL_MES_NOT_EN_P_INT_EN) | 2284 BITMASK(IMU_INTERRUPT_ENABLE_NONFATAL_MES_NOT_EN_P_INT_EN) | 2285 BITMASK(IMU_INTERRUPT_ENABLE_COR_MES_NOT_EN_P_INT_EN); 2286 2287 switch (code) { 2288 case CB_CODE_CPR_CHKPT: 2289 /* disable imu rbne on corr/nonfatal/fatal errors */ 2290 CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, 2291 imu_log_enable & (~imu_log_mask)); 2292 2293 CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, 2294 imu_intr_enable & (~imu_intr_mask)); 2295 2296 /* disable CORR intr mapping */ 2297 px_ib_intr_disable(ib_p, ce_ino, IB_INTR_NOWAIT); 2298 2299 /* disable NON FATAL intr mapping */ 2300 px_ib_intr_disable(ib_p, nf_ino, IB_INTR_NOWAIT); 2301 2302 /* disable FATAL intr mapping */ 2303 px_ib_intr_disable(ib_p, f_ino, IB_INTR_NOWAIT); 2304 2305 break; 2306 2307 case CB_CODE_CPR_RESUME: 2308 mutex_enter(&ib_p->ib_ino_lst_mutex); 2309 2310 ce_ino_p = px_ib_locate_ino(ib_p, ce_ino); 2311 nf_ino_p = px_ib_locate_ino(ib_p, nf_ino); 2312 f_ino_p = px_ib_locate_ino(ib_p, f_ino); 2313 2314 /* enable CORR intr mapping */ 2315 if (ce_ino_p) 2316 px_ib_intr_enable(px_p, ce_ino_p->ino_cpuid, ce_ino); 2317 else 2318 cmn_err(CE_WARN, "px_cpr_callb: RESUME unable to " 2319 "reenable PCIe Correctable msg intr.\n"); 2320 2321 /* enable NON FATAL intr mapping */ 2322 if (nf_ino_p) 2323 px_ib_intr_enable(px_p, nf_ino_p->ino_cpuid, nf_ino); 2324 else 2325 cmn_err(CE_WARN, "px_cpr_callb: RESUME unable to " 2326 "reenable PCIe Non Fatal msg intr.\n"); 2327 2328 /* enable FATAL intr mapping */ 2329 if (f_ino_p) 2330 px_ib_intr_enable(px_p, f_ino_p->ino_cpuid, f_ino); 2331 else 2332 cmn_err(CE_WARN, "px_cpr_callb: RESUME unable to " 2333 "reenable PCIe Fatal msg intr.\n"); 2334 2335 mutex_exit(&ib_p->ib_ino_lst_mutex); 2336 2337 /* enable corr/nonfatal/fatal not enable error */ 2338 CSR_XS(csr_base, IMU_ERROR_LOG_ENABLE, (imu_log_enable | 2339 (imu_log_mask & px_imu_log_mask))); 2340 CSR_XS(csr_base, IMU_INTERRUPT_ENABLE, (imu_intr_enable | 2341 (imu_intr_mask & px_imu_intr_mask))); 2342 2343 break; 2344 } 2345 2346 return (B_TRUE); 2347 } 2348 2349 uint64_t 2350 px_get_rng_parent_hi_mask(px_t *px_p) 2351 { 2352 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2353 uint64_t mask; 2354 2355 switch (PX_CHIP_TYPE(pxu_p)) { 2356 case PX_CHIP_OBERON: 2357 mask = OBERON_RANGE_PROP_MASK; 2358 break; 2359 case PX_CHIP_FIRE: 2360 mask = PX_RANGE_PROP_MASK; 2361 break; 2362 default: 2363 mask = PX_RANGE_PROP_MASK; 2364 } 2365 2366 return (mask); 2367 } 2368 2369 /* 2370 * fetch chip's range propery's value 2371 */ 2372 uint64_t 2373 px_get_range_prop(px_t *px_p, px_ranges_t *rp, int bank) 2374 { 2375 uint64_t mask, range_prop; 2376 2377 mask = px_get_rng_parent_hi_mask(px_p); 2378 range_prop = (((uint64_t)(rp[bank].parent_high & mask)) << 32) | 2379 rp[bank].parent_low; 2380 2381 return (range_prop); 2382 } 2383 2384 /* 2385 * add cpr callback 2386 */ 2387 void 2388 px_cpr_add_callb(px_t *px_p) 2389 { 2390 px_p->px_cprcb_id = callb_add(px_cpr_callb, (void *)px_p, 2391 CB_CL_CPR_POST_USER, "px_cpr"); 2392 } 2393 2394 /* 2395 * remove cpr callback 2396 */ 2397 void 2398 px_cpr_rem_callb(px_t *px_p) 2399 { 2400 (void) callb_delete(px_p->px_cprcb_id); 2401 } 2402 2403 /*ARGSUSED*/ 2404 static uint_t 2405 px_hp_intr(caddr_t arg1, caddr_t arg2) 2406 { 2407 px_t *px_p = (px_t *)arg1; 2408 int rval; 2409 2410 rval = pciehpc_intr(px_p->px_dip); 2411 2412 #ifdef DEBUG 2413 if (rval == DDI_INTR_UNCLAIMED) 2414 cmn_err(CE_WARN, "%s%d: UNCLAIMED intr\n", 2415 ddi_driver_name(px_p->px_dip), 2416 ddi_get_instance(px_p->px_dip)); 2417 #endif 2418 2419 return (rval); 2420 } 2421 2422 int 2423 px_lib_hotplug_init(dev_info_t *dip, void *arg) 2424 { 2425 px_t *px_p = DIP_TO_STATE(dip); 2426 uint64_t ret; 2427 2428 if ((ret = hvio_hotplug_init(dip, arg)) == DDI_SUCCESS) { 2429 sysino_t sysino; 2430 2431 if (px_lib_intr_devino_to_sysino(px_p->px_dip, 2432 px_p->px_inos[PX_INTR_HOTPLUG], &sysino) != 2433 DDI_SUCCESS) { 2434 #ifdef DEBUG 2435 cmn_err(CE_WARN, "%s%d: devino_to_sysino fails\n", 2436 ddi_driver_name(px_p->px_dip), 2437 ddi_get_instance(px_p->px_dip)); 2438 #endif 2439 return (DDI_FAILURE); 2440 } 2441 2442 VERIFY(add_ivintr(sysino, PX_PCIEHP_PIL, 2443 (intrfunc)px_hp_intr, (caddr_t)px_p, NULL, NULL) == 0); 2444 } 2445 2446 return (ret); 2447 } 2448 2449 void 2450 px_lib_hotplug_uninit(dev_info_t *dip) 2451 { 2452 if (hvio_hotplug_uninit(dip) == DDI_SUCCESS) { 2453 px_t *px_p = DIP_TO_STATE(dip); 2454 sysino_t sysino; 2455 2456 if (px_lib_intr_devino_to_sysino(px_p->px_dip, 2457 px_p->px_inos[PX_INTR_HOTPLUG], &sysino) != 2458 DDI_SUCCESS) { 2459 #ifdef DEBUG 2460 cmn_err(CE_WARN, "%s%d: devino_to_sysino fails\n", 2461 ddi_driver_name(px_p->px_dip), 2462 ddi_get_instance(px_p->px_dip)); 2463 #endif 2464 return; 2465 } 2466 2467 VERIFY(rem_ivintr(sysino, PX_PCIEHP_PIL) == 0); 2468 } 2469 } 2470 2471 boolean_t 2472 px_lib_is_in_drain_state(px_t *px_p) 2473 { 2474 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 2475 caddr_t csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 2476 uint64_t drain_status; 2477 2478 if (PX_CHIP_TYPE(pxu_p) == PX_CHIP_OBERON) { 2479 drain_status = CSR_BR(csr_base, DRAIN_CONTROL_STATUS, DRAIN); 2480 } else { 2481 drain_status = CSR_BR(csr_base, TLU_STATUS, DRAIN); 2482 } 2483 2484 return (drain_status); 2485 } 2486