xref: /titanic_44/usr/src/uts/sun4u/io/px/px_err.h (revision 08a74c0d0f6c3b94aa21216885efa4387c3d375c)
1f8d2de6bSjchu /*
2f8d2de6bSjchu  * CDDL HEADER START
3f8d2de6bSjchu  *
4f8d2de6bSjchu  * The contents of this file are subject to the terms of the
525cf1a30Sjl139090  * Common Development and Distribution License (the "License").
625cf1a30Sjl139090  * You may not use this file except in compliance with the License.
7f8d2de6bSjchu  *
8f8d2de6bSjchu  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9f8d2de6bSjchu  * or http://www.opensolaris.org/os/licensing.
10f8d2de6bSjchu  * See the License for the specific language governing permissions
11f8d2de6bSjchu  * and limitations under the License.
12f8d2de6bSjchu  *
13f8d2de6bSjchu  * When distributing Covered Code, include this CDDL HEADER in each
14f8d2de6bSjchu  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15f8d2de6bSjchu  * If applicable, add the following below this CDDL HEADER, with the
16f8d2de6bSjchu  * fields enclosed by brackets "[]" replaced with your own identifying
17f8d2de6bSjchu  * information: Portions Copyright [yyyy] [name of copyright owner]
18f8d2de6bSjchu  *
19f8d2de6bSjchu  * CDDL HEADER END
20f8d2de6bSjchu  */
21f8d2de6bSjchu /*
2225cf1a30Sjl139090  * Copyright 2006 Sun Microsystems, Inc.  All rights reserved.
23f8d2de6bSjchu  * Use is subject to license terms.
24f8d2de6bSjchu  */
25f8d2de6bSjchu 
26f8d2de6bSjchu #ifndef	_SYS_PX_ERR_H
27f8d2de6bSjchu #define	_SYS_PX_ERR_H
28f8d2de6bSjchu 
29f8d2de6bSjchu #pragma ident	"%Z%%M%	%I%	%E% SMI"
30f8d2de6bSjchu 
31f8d2de6bSjchu #ifdef	__cplusplus
32f8d2de6bSjchu extern "C" {
33f8d2de6bSjchu #endif
34f8d2de6bSjchu 
35f8d2de6bSjchu typedef enum {
36f8d2de6bSjchu 	PX_ERR_JBC,
3725cf1a30Sjl139090 	PX_ERR_UBC,
38f8d2de6bSjchu 	PX_ERR_MMU,
39f8d2de6bSjchu 	PX_ERR_IMU,
40f8d2de6bSjchu 	PX_ERR_TLU_UE,
41f8d2de6bSjchu 	PX_ERR_TLU_CE,
42f8d2de6bSjchu 	PX_ERR_TLU_OE,
43f8d2de6bSjchu 	PX_ERR_ILU,
44f8d2de6bSjchu 	PX_ERR_LPU_LINK,
45f8d2de6bSjchu 	PX_ERR_LPU_PHY,
46f8d2de6bSjchu 	PX_ERR_LPU_RX,
47f8d2de6bSjchu 	PX_ERR_LPU_TX,
48f8d2de6bSjchu 	PX_ERR_LPU_LTSSM,
49f8d2de6bSjchu 	PX_ERR_LPU_GIGABLZ
50f8d2de6bSjchu } px_err_id_t;
51f8d2de6bSjchu 
52*08a74c0dSschwartz #define	PX_ERR_ENABLE	B_TRUE
53*08a74c0dSschwartz #define	PX_ERR_DISABLE	B_FALSE
54*08a74c0dSschwartz 
55*08a74c0dSschwartz void px_err_reg_enable(px_err_id_t reg_id, caddr_t csr_base);
56*08a74c0dSschwartz void px_err_reg_disable(px_err_id_t reg_id, caddr_t csr_base);
57*08a74c0dSschwartz void px_err_reg_setup_pcie(uint8_t chip_mask, caddr_t csr_base,
58*08a74c0dSschwartz     boolean_t enable);
59f8d2de6bSjchu 
6025cf1a30Sjl139090 #define	PX_ERR_EN_ALL			-1ull
6125cf1a30Sjl139090 #define	PX_ERR_MASK_NONE		0ull
6225cf1a30Sjl139090 
6325cf1a30Sjl139090 #define	LPU_INTR_ENABLE 0ull
6425cf1a30Sjl139090 #define	LPU_INTR_DISABLE -1ull
6525cf1a30Sjl139090 
6625cf1a30Sjl139090 extern uint64_t px_tlu_ue_intr_mask;
6725cf1a30Sjl139090 extern uint64_t px_tlu_ue_log_mask;
6825cf1a30Sjl139090 extern uint64_t px_tlu_ue_count_mask;
6925cf1a30Sjl139090 
7025cf1a30Sjl139090 extern uint64_t px_tlu_ce_intr_mask;
7125cf1a30Sjl139090 extern uint64_t px_tlu_ce_log_mask;
7225cf1a30Sjl139090 extern uint64_t px_tlu_ce_count_mask;
7325cf1a30Sjl139090 
7425cf1a30Sjl139090 extern uint64_t px_tlu_oe_intr_mask;
7525cf1a30Sjl139090 extern uint64_t px_tlu_oe_log_mask;
7625cf1a30Sjl139090 extern uint64_t px_tlu_oe_count_mask;
7725cf1a30Sjl139090 
7825cf1a30Sjl139090 extern uint64_t px_mmu_intr_mask;
7925cf1a30Sjl139090 extern uint64_t px_mmu_log_mask;
8025cf1a30Sjl139090 extern uint64_t px_mmu_count_mask;
8125cf1a30Sjl139090 
8225cf1a30Sjl139090 extern uint64_t px_imu_intr_mask;
8325cf1a30Sjl139090 extern uint64_t px_imu_log_mask;
8425cf1a30Sjl139090 extern uint64_t px_imu_count_mask;
8525cf1a30Sjl139090 
8625cf1a30Sjl139090 extern uint64_t px_ilu_intr_mask;
8725cf1a30Sjl139090 extern uint64_t px_ilu_log_mask;
8825cf1a30Sjl139090 extern uint64_t px_ilu_count_mask;
8925cf1a30Sjl139090 
90f8d2de6bSjchu #ifdef	__cplusplus
91f8d2de6bSjchu }
92f8d2de6bSjchu #endif
93f8d2de6bSjchu 
94f8d2de6bSjchu #endif	/* _SYS_PX_ERR_H */
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