1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * sun4u Fire Error Handling 30 */ 31 32 #include <sys/types.h> 33 #include <sys/ddi.h> 34 #include <sys/sunddi.h> 35 #include <sys/fm/protocol.h> 36 #include <sys/fm/util.h> 37 #include <sys/pcie.h> 38 #include <sys/pcie_impl.h> 39 #include "px_obj.h" 40 #include <px_regs.h> 41 #include <px_csr.h> 42 #include <sys/membar.h> 43 #include <sys/machcpuvar.h> 44 #include <sys/platform_module.h> 45 #include "pcie_pwr.h" 46 #include "px_lib4u.h" 47 #include "px_err.h" 48 #include "px_err_impl.h" 49 #include "oberon_regs.h" 50 51 uint64_t px_tlu_ue_intr_mask = PX_ERR_EN_ALL; 52 uint64_t px_tlu_ue_log_mask = PX_ERR_EN_ALL; 53 uint64_t px_tlu_ue_count_mask = PX_ERR_EN_ALL; 54 55 uint64_t px_tlu_ce_intr_mask = PX_ERR_MASK_NONE; 56 uint64_t px_tlu_ce_log_mask = PX_ERR_MASK_NONE; 57 uint64_t px_tlu_ce_count_mask = PX_ERR_MASK_NONE; 58 59 /* 60 * Do not enable Link Interrupts 61 */ 62 uint64_t px_tlu_oe_intr_mask = PX_ERR_EN_ALL & ~0x80000000800; 63 uint64_t px_tlu_oe_log_mask = PX_ERR_EN_ALL & ~0x80000000800; 64 uint64_t px_tlu_oe_count_mask = PX_ERR_EN_ALL; 65 66 uint64_t px_mmu_intr_mask = PX_ERR_EN_ALL; 67 uint64_t px_mmu_log_mask = PX_ERR_EN_ALL; 68 uint64_t px_mmu_count_mask = PX_ERR_EN_ALL; 69 70 uint64_t px_imu_intr_mask = PX_ERR_EN_ALL; 71 uint64_t px_imu_log_mask = PX_ERR_EN_ALL; 72 uint64_t px_imu_count_mask = PX_ERR_EN_ALL; 73 74 /* 75 * (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_S) | 76 * (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_P); 77 */ 78 uint64_t px_ilu_intr_mask = (((uint64_t)0x10 << 32) | 0x10); 79 uint64_t px_ilu_log_mask = (((uint64_t)0x10 << 32) | 0x10); 80 uint64_t px_ilu_count_mask = PX_ERR_EN_ALL; 81 82 uint64_t px_ubc_intr_mask = PX_ERR_EN_ALL; 83 uint64_t px_ubc_log_mask = PX_ERR_EN_ALL; 84 uint64_t px_ubc_count_mask = PX_ERR_EN_ALL; 85 86 uint64_t px_jbc_intr_mask = PX_ERR_EN_ALL; 87 uint64_t px_jbc_log_mask = PX_ERR_EN_ALL; 88 uint64_t px_jbc_count_mask = PX_ERR_EN_ALL; 89 90 /* 91 * LPU Intr Registers are reverse encoding from the registers above. 92 * 1 = disable 93 * 0 = enable 94 * 95 * Log and Count are however still the same. 96 */ 97 uint64_t px_lpul_intr_mask = LPU_INTR_DISABLE; 98 uint64_t px_lpul_log_mask = PX_ERR_EN_ALL; 99 uint64_t px_lpul_count_mask = PX_ERR_EN_ALL; 100 101 uint64_t px_lpup_intr_mask = LPU_INTR_DISABLE; 102 uint64_t px_lpup_log_mask = PX_ERR_EN_ALL; 103 uint64_t px_lpup_count_mask = PX_ERR_EN_ALL; 104 105 uint64_t px_lpur_intr_mask = LPU_INTR_DISABLE; 106 uint64_t px_lpur_log_mask = PX_ERR_EN_ALL; 107 uint64_t px_lpur_count_mask = PX_ERR_EN_ALL; 108 109 uint64_t px_lpux_intr_mask = LPU_INTR_DISABLE; 110 uint64_t px_lpux_log_mask = PX_ERR_EN_ALL; 111 uint64_t px_lpux_count_mask = PX_ERR_EN_ALL; 112 113 uint64_t px_lpus_intr_mask = LPU_INTR_DISABLE; 114 uint64_t px_lpus_log_mask = PX_ERR_EN_ALL; 115 uint64_t px_lpus_count_mask = PX_ERR_EN_ALL; 116 117 uint64_t px_lpug_intr_mask = LPU_INTR_DISABLE; 118 uint64_t px_lpug_log_mask = PX_ERR_EN_ALL; 119 uint64_t px_lpug_count_mask = PX_ERR_EN_ALL; 120 121 /* 122 * JBC error bit table 123 */ 124 #define JBC_BIT_DESC(bit, hdl, erpt) \ 125 JBC_INTERRUPT_STATUS_ ## bit ## _P, \ 126 0, \ 127 PX_ERR_BIT_HANDLE(hdl), \ 128 PX_ERPT_SEND(erpt), \ 129 PX_ERR_JBC_CLASS(bit) }, \ 130 { JBC_INTERRUPT_STATUS_ ## bit ## _S, \ 131 0, \ 132 PX_ERR_BIT_HANDLE(hdl), \ 133 PX_ERPT_SEND(erpt), \ 134 PX_ERR_JBC_CLASS(bit) 135 px_err_bit_desc_t px_err_jbc_tbl[] = { 136 /* JBC FATAL - see io erpt doc, section 1.1 */ 137 { JBC_BIT_DESC(MB_PEA, fatal_hw, jbc_fatal) }, 138 { JBC_BIT_DESC(CPE, fatal_hw, jbc_fatal) }, 139 { JBC_BIT_DESC(APE, fatal_hw, jbc_fatal) }, 140 { JBC_BIT_DESC(PIO_CPE, fatal_hw, jbc_fatal) }, 141 { JBC_BIT_DESC(JTCEEW, fatal_hw, jbc_fatal) }, 142 { JBC_BIT_DESC(JTCEEI, fatal_hw, jbc_fatal) }, 143 { JBC_BIT_DESC(JTCEER, fatal_hw, jbc_fatal) }, 144 145 /* JBC MERGE - see io erpt doc, section 1.2 */ 146 { JBC_BIT_DESC(MB_PER, jbc_merge, jbc_merge) }, 147 { JBC_BIT_DESC(MB_PEW, jbc_merge, jbc_merge) }, 148 149 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 150 { JBC_BIT_DESC(UE_ASYN, fatal_gos, jbc_in) }, 151 { JBC_BIT_DESC(CE_ASYN, non_fatal, jbc_in) }, 152 { JBC_BIT_DESC(JTE, fatal_gos, jbc_in) }, 153 { JBC_BIT_DESC(JBE, jbc_jbusint_in, jbc_in) }, 154 { JBC_BIT_DESC(JUE, jbc_jbusint_in, jbc_in) }, 155 { JBC_BIT_DESC(ICISE, fatal_gos, jbc_in) }, 156 { JBC_BIT_DESC(WR_DPE, jbc_jbusint_in, jbc_in) }, 157 { JBC_BIT_DESC(RD_DPE, jbc_jbusint_in, jbc_in) }, 158 { JBC_BIT_DESC(ILL_BMW, jbc_jbusint_in, jbc_in) }, 159 { JBC_BIT_DESC(ILL_BMR, jbc_jbusint_in, jbc_in) }, 160 { JBC_BIT_DESC(BJC, jbc_jbusint_in, jbc_in) }, 161 162 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 163 { JBC_BIT_DESC(IJP, fatal_gos, jbc_out) }, 164 165 /* 166 * JBC Dmcint ODCD - see io erpt doc, section 1.5 167 * 168 * Error bits which can be set via a bad PCItool access go through 169 * jbc_safe_acc instead. 170 */ 171 { JBC_BIT_DESC(PIO_UNMAP_RD, jbc_safe_acc, jbc_odcd) }, 172 { JBC_BIT_DESC(ILL_ACC_RD, jbc_safe_acc, jbc_odcd) }, 173 { JBC_BIT_DESC(PIO_UNMAP, jbc_safe_acc, jbc_odcd) }, 174 { JBC_BIT_DESC(PIO_DPE, jbc_dmcint_odcd, jbc_odcd) }, 175 { JBC_BIT_DESC(PIO_CPE, non_fatal, jbc_odcd) }, 176 { JBC_BIT_DESC(ILL_ACC, jbc_safe_acc, jbc_odcd) }, 177 178 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 179 { JBC_BIT_DESC(UNSOL_RD, non_fatal, jbc_idc) }, 180 { JBC_BIT_DESC(UNSOL_INTR, non_fatal, jbc_idc) }, 181 182 /* JBC CSR - see io erpt doc, section 1.7 */ 183 { JBC_BIT_DESC(EBUS_TO, jbc_csr, jbc_csr) } 184 }; 185 186 #define px_err_jbc_keys \ 187 (sizeof (px_err_jbc_tbl)) / (sizeof (px_err_bit_desc_t)) 188 189 /* 190 * UBC error bit table 191 */ 192 #define UBC_BIT_DESC(bit, hdl, erpt) \ 193 UBC_INTERRUPT_STATUS_ ## bit ## _P, \ 194 0, \ 195 PX_ERR_BIT_HANDLE(hdl), \ 196 PX_ERPT_SEND(erpt), \ 197 PX_ERR_UBC_CLASS(bit) }, \ 198 { UBC_INTERRUPT_STATUS_ ## bit ## _S, \ 199 0, \ 200 PX_ERR_BIT_HANDLE(hdl), \ 201 PX_ERPT_SEND(erpt), \ 202 PX_ERR_UBC_CLASS(bit) 203 px_err_bit_desc_t px_err_ubc_tbl[] = { 204 /* UBC FATAL */ 205 { UBC_BIT_DESC(DMARDUEA, non_fatal, ubc_fatal) }, 206 { UBC_BIT_DESC(DMAWTUEA, fatal_sw, ubc_fatal) }, 207 { UBC_BIT_DESC(MEMRDAXA, fatal_sw, ubc_fatal) }, 208 { UBC_BIT_DESC(MEMWTAXA, fatal_sw, ubc_fatal) }, 209 { UBC_BIT_DESC(DMARDUEB, non_fatal, ubc_fatal) }, 210 { UBC_BIT_DESC(DMAWTUEB, fatal_sw, ubc_fatal) }, 211 { UBC_BIT_DESC(MEMRDAXB, fatal_sw, ubc_fatal) }, 212 { UBC_BIT_DESC(MEMWTAXB, fatal_sw, ubc_fatal) }, 213 { UBC_BIT_DESC(PIOWTUE, fatal_sw, ubc_fatal) }, 214 { UBC_BIT_DESC(PIOWBEUE, fatal_sw, ubc_fatal) }, 215 { UBC_BIT_DESC(PIORBEUE, fatal_sw, ubc_fatal) } 216 }; 217 218 #define px_err_ubc_keys \ 219 (sizeof (px_err_ubc_tbl)) / (sizeof (px_err_bit_desc_t)) 220 221 222 char *ubc_class_eid_qualifier[] = { 223 "-mem", 224 "-channel", 225 "-cpu", 226 "-path" 227 }; 228 229 230 /* 231 * DMC error bit tables 232 */ 233 #define IMU_BIT_DESC(bit, hdl, erpt) \ 234 IMU_INTERRUPT_STATUS_ ## bit ## _P, \ 235 0, \ 236 PX_ERR_BIT_HANDLE(hdl), \ 237 PX_ERPT_SEND(erpt), \ 238 PX_ERR_DMC_CLASS(bit) }, \ 239 { IMU_INTERRUPT_STATUS_ ## bit ## _S, \ 240 0, \ 241 PX_ERR_BIT_HANDLE(hdl), \ 242 PX_ERPT_SEND(erpt), \ 243 PX_ERR_DMC_CLASS(bit) 244 px_err_bit_desc_t px_err_imu_tbl[] = { 245 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 246 { IMU_BIT_DESC(MSI_MAL_ERR, non_fatal, imu_rds) }, 247 { IMU_BIT_DESC(MSI_PAR_ERR, fatal_stuck, imu_rds) }, 248 { IMU_BIT_DESC(PMEACK_MES_NOT_EN, imu_rbne, imu_rds) }, 249 { IMU_BIT_DESC(PMPME_MES_NOT_EN, imu_pme, imu_rds) }, 250 { IMU_BIT_DESC(FATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 251 { IMU_BIT_DESC(NONFATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 252 { IMU_BIT_DESC(COR_MES_NOT_EN, imu_rbne, imu_rds) }, 253 { IMU_BIT_DESC(MSI_NOT_EN, imu_rbne, imu_rds) }, 254 255 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 256 { IMU_BIT_DESC(EQ_NOT_EN, imu_rbne, imu_rds) }, 257 258 /* DMC IMU - see io erpt doc, section 2.3 */ 259 { IMU_BIT_DESC(EQ_OVER, imu_eq_ovfl, imu) } 260 }; 261 262 #define px_err_imu_keys (sizeof (px_err_imu_tbl)) / (sizeof (px_err_bit_desc_t)) 263 264 /* mmu errors */ 265 #define MMU_BIT_DESC(bit, hdl, erpt) \ 266 MMU_INTERRUPT_STATUS_ ## bit ## _P, \ 267 0, \ 268 PX_ERR_BIT_HANDLE(hdl), \ 269 PX_ERPT_SEND(erpt), \ 270 PX_ERR_DMC_CLASS(bit) }, \ 271 { MMU_INTERRUPT_STATUS_ ## bit ## _S, \ 272 0, \ 273 PX_ERR_BIT_HANDLE(hdl), \ 274 PX_ERPT_SEND(erpt), \ 275 PX_ERR_DMC_CLASS(bit) 276 px_err_bit_desc_t px_err_mmu_tbl[] = { 277 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 278 { MMU_BIT_DESC(BYP_ERR, mmu_rbne, mmu_tfar_tfsr) }, 279 { MMU_BIT_DESC(BYP_OOR, mmu_tfa, mmu_tfar_tfsr) }, 280 { MMU_BIT_DESC(TRN_ERR, mmu_rbne, mmu_tfar_tfsr) }, 281 { MMU_BIT_DESC(TRN_OOR, mmu_tfa, mmu_tfar_tfsr) }, 282 { MMU_BIT_DESC(TTE_INV, mmu_tfa, mmu_tfar_tfsr) }, 283 { MMU_BIT_DESC(TTE_PRT, mmu_tfa, mmu_tfar_tfsr) }, 284 { MMU_BIT_DESC(TTC_DPE, mmu_tfa, mmu_tfar_tfsr) }, 285 { MMU_BIT_DESC(TBW_DME, mmu_tblwlk, mmu_tfar_tfsr) }, 286 { MMU_BIT_DESC(TBW_UDE, mmu_tblwlk, mmu_tfar_tfsr) }, 287 { MMU_BIT_DESC(TBW_ERR, mmu_tblwlk, mmu_tfar_tfsr) }, 288 { MMU_BIT_DESC(TBW_DPE, mmu_tblwlk, mmu_tfar_tfsr) }, 289 290 /* DMC MMU - see io erpt doc, section 2.5 */ 291 { MMU_BIT_DESC(TTC_CAE, non_fatal, mmu) } 292 }; 293 #define px_err_mmu_keys (sizeof (px_err_mmu_tbl)) / (sizeof (px_err_bit_desc_t)) 294 295 296 /* 297 * PEC error bit tables 298 */ 299 #define ILU_BIT_DESC(bit, hdl, erpt) \ 300 ILU_INTERRUPT_STATUS_ ## bit ## _P, \ 301 0, \ 302 PX_ERR_BIT_HANDLE(hdl), \ 303 PX_ERPT_SEND(erpt), \ 304 PX_ERR_PEC_CLASS(bit) }, \ 305 { ILU_INTERRUPT_STATUS_ ## bit ## _S, \ 306 0, \ 307 PX_ERR_BIT_HANDLE(hdl), \ 308 PX_ERPT_SEND(erpt), \ 309 PX_ERR_PEC_CLASS(bit) 310 px_err_bit_desc_t px_err_ilu_tbl[] = { 311 /* PEC ILU none - see io erpt doc, section 3.1 */ 312 { ILU_BIT_DESC(IHB_PE, fatal_gos, pec_ilu) } 313 }; 314 #define px_err_ilu_keys \ 315 (sizeof (px_err_ilu_tbl)) / (sizeof (px_err_bit_desc_t)) 316 317 /* 318 * PEC UE errors implementation is incomplete pending PCIE generic 319 * fabric rules. Must handle both PRIMARY and SECONDARY errors. 320 */ 321 /* pec ue errors */ 322 #define TLU_UC_BIT_DESC(bit, hdl, erpt) \ 323 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 324 0, \ 325 PX_ERR_BIT_HANDLE(hdl), \ 326 PX_ERPT_SEND(erpt), \ 327 PX_ERR_PEC_CLASS(bit) }, \ 328 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 329 0, \ 330 PX_ERR_BIT_HANDLE(hdl), \ 331 PX_ERPT_SEND(erpt), \ 332 PX_ERR_PEC_CLASS(bit) 333 #define TLU_UC_OB_BIT_DESC(bit, hdl, erpt) \ 334 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 335 0, \ 336 PX_ERR_BIT_HANDLE(hdl), \ 337 PX_ERPT_SEND(erpt), \ 338 PX_ERR_PEC_OB_CLASS(bit) }, \ 339 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 340 0, \ 341 PX_ERR_BIT_HANDLE(hdl), \ 342 PX_ERPT_SEND(erpt), \ 343 PX_ERR_PEC_CLASS(bit) 344 px_err_bit_desc_t px_err_tlu_ue_tbl[] = { 345 /* PCI-E Receive Uncorrectable Errors - see io erpt doc, section 3.2 */ 346 { TLU_UC_BIT_DESC(UR, pciex_ue, pciex_rx_ue) }, 347 { TLU_UC_BIT_DESC(UC, pciex_ue, pciex_rx_ue) }, 348 349 /* PCI-E Transmit Uncorrectable Errors - see io erpt doc, section 3.3 */ 350 { TLU_UC_OB_BIT_DESC(ECRC, pciex_ue, pciex_rx_ue) }, 351 { TLU_UC_BIT_DESC(CTO, pciex_ue, pciex_tx_ue) }, 352 { TLU_UC_BIT_DESC(ROF, pciex_ue, pciex_tx_ue) }, 353 354 /* PCI-E Rx/Tx Uncorrectable Errors - see io erpt doc, section 3.4 */ 355 { TLU_UC_BIT_DESC(MFP, pciex_ue, pciex_rx_tx_ue) }, 356 { TLU_UC_BIT_DESC(PP, pciex_ue, pciex_rx_tx_ue) }, 357 358 /* Other PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 359 { TLU_UC_BIT_DESC(FCP, pciex_ue, pciex_ue) }, 360 { TLU_UC_BIT_DESC(DLP, pciex_ue, pciex_ue) }, 361 { TLU_UC_BIT_DESC(TE, pciex_ue, pciex_ue) }, 362 363 /* Not used */ 364 { TLU_UC_BIT_DESC(CA, pciex_ue, do_not) } 365 }; 366 #define px_err_tlu_ue_keys \ 367 (sizeof (px_err_tlu_ue_tbl)) / (sizeof (px_err_bit_desc_t)) 368 369 370 /* 371 * PEC CE errors implementation is incomplete pending PCIE generic 372 * fabric rules. 373 */ 374 /* pec ce errors */ 375 #define TLU_CE_BIT_DESC(bit, hdl, erpt) \ 376 TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 377 0, \ 378 PX_ERR_BIT_HANDLE(hdl), \ 379 PX_ERPT_SEND(erpt), \ 380 PX_ERR_PEC_CLASS(bit) }, \ 381 { TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 382 0, \ 383 PX_ERR_BIT_HANDLE(hdl), \ 384 PX_ERPT_SEND(erpt), \ 385 PX_ERR_PEC_CLASS(bit) 386 px_err_bit_desc_t px_err_tlu_ce_tbl[] = { 387 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 388 { TLU_CE_BIT_DESC(RTO, pciex_ce, pciex_ce) }, 389 { TLU_CE_BIT_DESC(RNR, pciex_ce, pciex_ce) }, 390 { TLU_CE_BIT_DESC(BDP, pciex_ce, pciex_ce) }, 391 { TLU_CE_BIT_DESC(BTP, pciex_ce, pciex_ce) }, 392 { TLU_CE_BIT_DESC(RE, pciex_ce, pciex_ce) } 393 }; 394 #define px_err_tlu_ce_keys \ 395 (sizeof (px_err_tlu_ce_tbl)) / (sizeof (px_err_bit_desc_t)) 396 397 398 /* pec oe errors */ 399 #define TLU_OE_BIT_DESC(bit, hdl, erpt) \ 400 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 401 0, \ 402 PX_ERR_BIT_HANDLE(hdl), \ 403 PX_ERPT_SEND(erpt), \ 404 PX_ERR_PEC_CLASS(bit) }, \ 405 { TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _S, \ 406 0, \ 407 PX_ERR_BIT_HANDLE(hdl), \ 408 PX_ERPT_SEND(erpt), \ 409 PX_ERR_PEC_CLASS(bit) 410 #define TLU_OE_OB_BIT_DESC(bit, hdl, erpt) \ 411 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 412 0, \ 413 PX_ERR_BIT_HANDLE(hdl), \ 414 PX_ERPT_SEND(erpt), \ 415 PX_ERR_PEC_OB_CLASS(bit) }, \ 416 { TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _S, \ 417 0, \ 418 PX_ERR_BIT_HANDLE(hdl), \ 419 PX_ERPT_SEND(erpt), \ 420 PX_ERR_PEC_OB_CLASS(bit) 421 px_err_bit_desc_t px_err_tlu_oe_tbl[] = { 422 /* 423 * TLU Other Event Status (receive only) - see io erpt doc, section 3.7 424 */ 425 { TLU_OE_BIT_DESC(MRC, fatal_hw, pciex_rx_oe) }, 426 427 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 428 { TLU_OE_BIT_DESC(WUC, non_fatal, pciex_rx_tx_oe) }, 429 { TLU_OE_BIT_DESC(RUC, non_fatal, pciex_rx_tx_oe) }, 430 { TLU_OE_BIT_DESC(CRS, non_fatal, pciex_rx_tx_oe) }, 431 432 /* TLU Other Event - see io erpt doc, section 3.9 */ 433 { TLU_OE_BIT_DESC(IIP, fatal_gos, pciex_oe) }, 434 { TLU_OE_BIT_DESC(EDP, fatal_gos, pciex_oe) }, 435 { TLU_OE_BIT_DESC(EHP, fatal_gos, pciex_oe) }, 436 { TLU_OE_OB_BIT_DESC(TLUEITMO, fatal_gos, pciex_oe) }, 437 { TLU_OE_BIT_DESC(LIN, non_fatal, pciex_oe) }, 438 { TLU_OE_BIT_DESC(LRS, non_fatal, pciex_oe) }, 439 { TLU_OE_BIT_DESC(LDN, tlu_ldn, pciex_oe) }, 440 { TLU_OE_BIT_DESC(LUP, tlu_lup, pciex_oe) }, 441 { TLU_OE_BIT_DESC(ERU, fatal_gos, pciex_oe) }, 442 { TLU_OE_BIT_DESC(ERO, fatal_gos, pciex_oe) }, 443 { TLU_OE_BIT_DESC(EMP, fatal_gos, pciex_oe) }, 444 { TLU_OE_BIT_DESC(EPE, fatal_gos, pciex_oe) }, 445 { TLU_OE_BIT_DESC(ERP, fatal_gos, pciex_oe) }, 446 { TLU_OE_BIT_DESC(EIP, fatal_gos, pciex_oe) } 447 }; 448 449 #define px_err_tlu_oe_keys \ 450 (sizeof (px_err_tlu_oe_tbl)) / (sizeof (px_err_bit_desc_t)) 451 452 453 /* 454 * All the following tables below are for LPU Interrupts. These interrupts 455 * are *NOT* error interrupts, but event status interrupts. 456 * 457 * These events are probably of most interest to: 458 * o Hotplug 459 * o Power Management 460 * o etc... 461 * 462 * There are also a few events that would be interresting for FMA. 463 * Again none of the regiseters below state that an error has occured 464 * or that data has been lost. If anything, they give status that an 465 * error is *about* to occur. examples 466 * o INT_SKP_ERR - indicates clock between fire and child is too far 467 * off and is most unlikely able to compensate 468 * o INT_TX_PAR_ERR - A parity error occured in ONE lane. This is 469 * HW recoverable, but will like end up as a future 470 * fabric error as well. 471 * 472 * For now, we don't care about any of these errors and should be ignore, 473 * but cleared. 474 */ 475 476 /* LPU Link Interrupt Table */ 477 #define LPUL_BIT_DESC(bit, hdl, erpt) \ 478 LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 479 0, \ 480 NULL, \ 481 NULL, \ 482 "" 483 px_err_bit_desc_t px_err_lpul_tbl[] = { 484 { LPUL_BIT_DESC(LINK_ERR_ACT, NULL, NULL) } 485 }; 486 #define px_err_lpul_keys \ 487 (sizeof (px_err_lpul_tbl)) / (sizeof (px_err_bit_desc_t)) 488 489 /* LPU Physical Interrupt Table */ 490 #define LPUP_BIT_DESC(bit, hdl, erpt) \ 491 LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 492 0, \ 493 NULL, \ 494 NULL, \ 495 "" 496 px_err_bit_desc_t px_err_lpup_tbl[] = { 497 { LPUP_BIT_DESC(PHY_LAYER_ERR, NULL, NULL) } 498 }; 499 #define px_err_lpup_keys \ 500 (sizeof (px_err_lpup_tbl)) / (sizeof (px_err_bit_desc_t)) 501 502 /* LPU Receive Interrupt Table */ 503 #define LPUR_BIT_DESC(bit, hdl, erpt) \ 504 LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 505 0, \ 506 NULL, \ 507 NULL, \ 508 "" 509 px_err_bit_desc_t px_err_lpur_tbl[] = { 510 { LPUR_BIT_DESC(RCV_PHY, NULL, NULL) } 511 }; 512 #define px_err_lpur_keys \ 513 (sizeof (px_err_lpur_tbl)) / (sizeof (px_err_bit_desc_t)) 514 515 /* LPU Transmit Interrupt Table */ 516 #define LPUX_BIT_DESC(bit, hdl, erpt) \ 517 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 518 0, \ 519 NULL, \ 520 NULL, \ 521 "" 522 px_err_bit_desc_t px_err_lpux_tbl[] = { 523 { LPUX_BIT_DESC(UNMSK, NULL, NULL) } 524 }; 525 #define px_err_lpux_keys \ 526 (sizeof (px_err_lpux_tbl)) / (sizeof (px_err_bit_desc_t)) 527 528 /* LPU LTSSM Interrupt Table */ 529 #define LPUS_BIT_DESC(bit, hdl, erpt) \ 530 LPU_LTSSM_INTERRUPT_AND_STATUS_INT_ ## bit, \ 531 0, \ 532 NULL, \ 533 NULL, \ 534 "" 535 px_err_bit_desc_t px_err_lpus_tbl[] = { 536 { LPUS_BIT_DESC(ANY, NULL, NULL) } 537 }; 538 #define px_err_lpus_keys \ 539 (sizeof (px_err_lpus_tbl)) / (sizeof (px_err_bit_desc_t)) 540 541 /* LPU Gigablaze Glue Interrupt Table */ 542 #define LPUG_BIT_DESC(bit, hdl, erpt) \ 543 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_ ## bit, \ 544 0, \ 545 NULL, \ 546 NULL, \ 547 "" 548 px_err_bit_desc_t px_err_lpug_tbl[] = { 549 { LPUG_BIT_DESC(GLOBL_UNMSK, NULL, NULL) } 550 }; 551 #define px_err_lpug_keys \ 552 (sizeof (px_err_lpug_tbl)) / (sizeof (px_err_bit_desc_t)) 553 554 555 /* Mask and Tables */ 556 #define MnT6(pre) \ 557 B_FALSE, \ 558 &px_ ## pre ## _intr_mask, \ 559 &px_ ## pre ## _log_mask, \ 560 &px_ ## pre ## _count_mask, \ 561 px_err_ ## pre ## _tbl, \ 562 px_err_ ## pre ## _keys, \ 563 0 564 565 #define MnT6_ob(pre) \ 566 B_FALSE, \ 567 &px_ ## pre ## _intr_mask, \ 568 &px_ ## pre ## _log_mask, \ 569 &px_ ## pre ## _count_mask, \ 570 px_err_ ## pre ## _ob_tbl, \ 571 px_err_ ## pre ## _ob_keys, \ 572 0 573 574 /* LPU Registers Addresses */ 575 #define LR4(pre) \ 576 NULL, \ 577 LPU_ ## pre ## _INTERRUPT_MASK, \ 578 LPU_ ## pre ## _INTERRUPT_AND_STATUS, \ 579 LPU_ ## pre ## _INTERRUPT_AND_STATUS 580 581 /* LPU Registers Addresses with Irregularities */ 582 #define LR4_FIXME(pre) \ 583 NULL, \ 584 LPU_ ## pre ## _INTERRUPT_MASK, \ 585 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS, \ 586 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS 587 588 /* TLU Registers Addresses */ 589 #define TR4(pre) \ 590 TLU_ ## pre ## _LOG_ENABLE, \ 591 TLU_ ## pre ## _INTERRUPT_ENABLE, \ 592 TLU_ ## pre ## _INTERRUPT_STATUS, \ 593 TLU_ ## pre ## _STATUS_CLEAR 594 595 /* Registers Addresses for JBC, UBC, MMU, IMU and ILU */ 596 #define R4(pre) \ 597 pre ## _ERROR_LOG_ENABLE, \ 598 pre ## _INTERRUPT_ENABLE, \ 599 pre ## _INTERRUPT_STATUS, \ 600 pre ## _ERROR_STATUS_CLEAR 601 602 /* 603 * Register error handling tables. 604 * The ID Field (first field) is identified by an enum px_err_id_t. 605 * It is located in px_err.h 606 */ 607 px_err_reg_desc_t px_err_reg_tbl[] = { 608 { MnT6(jbc), R4(JBC), "JBC Error"}, 609 { MnT6(ubc), R4(UBC), "UBC Error"}, 610 { MnT6(mmu), R4(MMU), "MMU Error"}, 611 { MnT6(imu), R4(IMU), "IMU Error"}, 612 { MnT6(tlu_ue), TR4(UNCORRECTABLE_ERROR), "TLU UE"}, 613 { MnT6(tlu_ce), TR4(CORRECTABLE_ERROR), "TLU CE"}, 614 { MnT6(tlu_oe), TR4(OTHER_EVENT), "TLU OE"}, 615 { MnT6(ilu), R4(ILU), "ILU Error"}, 616 { MnT6(lpul), LR4(LINK_LAYER), "LPU Link Layer"}, 617 { MnT6(lpup), LR4_FIXME(PHY), "LPU Phy Layer"}, 618 { MnT6(lpur), LR4(RECEIVE_PHY), "LPU RX Phy Layer"}, 619 { MnT6(lpux), LR4(TRANSMIT_PHY), "LPU TX Phy Layer"}, 620 { MnT6(lpus), LR4(LTSSM), "LPU LTSSM"}, 621 { MnT6(lpug), LR4(GIGABLAZE_GLUE), "LPU GigaBlaze Glue"}, 622 }; 623 #define PX_ERR_REG_KEYS (sizeof (px_err_reg_tbl)) / (sizeof (px_err_reg_tbl[0])) 624 625 typedef struct px_err_ss { 626 uint64_t err_status[PX_ERR_REG_KEYS]; 627 } px_err_ss_t; 628 629 static void px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chk_cb); 630 static int px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, 631 px_err_ss_t *ss); 632 static int px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, 633 int err, int caller); 634 635 /* 636 * px_err_cb_intr: 637 * Interrupt handler for the JBC/UBC block. 638 * o lock 639 * o create derr 640 * o px_err_handle(leaf1, with cb) 641 * o px_err_handle(leaf2, without cb) 642 * o dispatch (leaf1) 643 * o dispatch (leaf2) 644 * o unlock 645 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 646 */ 647 uint_t 648 px_err_cb_intr(caddr_t arg) 649 { 650 px_fault_t *px_fault_p = (px_fault_t *)arg; 651 dev_info_t *rpdip = px_fault_p->px_fh_dip; 652 px_t *px_p = DIP_TO_STATE(rpdip); 653 int err = PX_OK; 654 int ret = DDI_FM_OK; 655 int fatal = 0; 656 ddi_fm_error_t derr; 657 658 /* Create the derr */ 659 bzero(&derr, sizeof (ddi_fm_error_t)); 660 derr.fme_version = DDI_FME_VERSION; 661 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 662 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 663 664 mutex_enter(&px_p->px_fm_mutex); 665 666 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, B_TRUE); 667 668 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 669 switch (ret) { 670 case DDI_FM_FATAL: 671 fatal++; 672 break; 673 case DDI_FM_NONFATAL: 674 case DDI_FM_UNKNOWN: 675 default: 676 break; 677 } 678 679 /* Set the intr state to idle for the leaf that received the mondo */ 680 681 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 682 INTR_IDLE_STATE); 683 684 mutex_exit(&px_p->px_fm_mutex); 685 686 /* 687 * PX_FATAL_HW error is diagnosed after system recovered from 688 * HW initiated reset, therefore no furthur handling is required. 689 */ 690 if (fatal || err & (PX_FATAL_GOS | PX_FATAL_SW)) 691 PX_FM_PANIC("Fatal System Bus Error has occurred\n"); 692 693 return (DDI_INTR_CLAIMED); 694 } 695 696 697 /* 698 * px_err_dmc_pec_intr: 699 * Interrupt handler for the DMC/PEC block. 700 * o lock 701 * o create derr 702 * o px_err_handle(leaf, with cb) 703 * o dispatch (leaf) 704 * o unlock 705 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 706 */ 707 uint_t 708 px_err_dmc_pec_intr(caddr_t arg) 709 { 710 px_fault_t *px_fault_p = (px_fault_t *)arg; 711 dev_info_t *rpdip = px_fault_p->px_fh_dip; 712 px_t *px_p = DIP_TO_STATE(rpdip); 713 int err = PX_OK; 714 int ret = DDI_FM_OK; 715 ddi_fm_error_t derr; 716 717 /* Create the derr */ 718 bzero(&derr, sizeof (ddi_fm_error_t)); 719 derr.fme_version = DDI_FME_VERSION; 720 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 721 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 722 723 mutex_enter(&px_p->px_fm_mutex); 724 725 /* send ereport/handle/clear fire registers */ 726 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, B_TRUE); 727 728 /* Check all child devices for errors */ 729 if (!px_lib_is_in_drain_state(px_p)) { 730 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 731 } 732 733 /* Set the interrupt state to idle */ 734 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 735 INTR_IDLE_STATE); 736 737 mutex_exit(&px_p->px_fm_mutex); 738 739 /* 740 * PX_FATAL_HW indicates a condition recovered from Fatal-Reset, 741 * therefore it does not cause panic. 742 */ 743 if ((err & (PX_FATAL_GOS | PX_FATAL_SW)) || (ret == DDI_FM_FATAL)) 744 PX_FM_PANIC("Fatal System Port Error has occurred\n"); 745 746 return (DDI_INTR_CLAIMED); 747 } 748 749 /* 750 * Error register are being handled by px_hlib xxx_init functions. 751 * They are also called again by px_err_add_intr for mondo62 and 63 752 * from px_cb_attach and px_attach 753 */ 754 void 755 px_err_reg_enable(px_t *px_p, px_err_id_t id) 756 { 757 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 758 uint64_t intr_mask = *reg_desc->intr_mask_p; 759 uint64_t log_mask = *reg_desc->log_mask_p; 760 caddr_t csr_base; 761 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 762 763 /* Get the correct CSR BASE */ 764 if (PX_ERR_XBC(id)) 765 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 766 else 767 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 768 769 reg_desc->enabled = B_TRUE; 770 771 /* Enable logs if it exists */ 772 if (reg_desc->log_addr != NULL) 773 CSR_XS(csr_base, reg_desc->log_addr, log_mask); 774 775 /* 776 * For readability you in code you set 1 to enable an interrupt. 777 * But in Fire it's backwards. You set 1 to *disable* an intr. 778 * Reverse the user tunable intr mask field. 779 * 780 * Disable All Errors 781 * Clear All Errors 782 * Enable Errors 783 */ 784 CSR_XS(csr_base, reg_desc->enable_addr, 0); 785 CSR_XS(csr_base, reg_desc->clear_addr, -1); 786 CSR_XS(csr_base, reg_desc->enable_addr, intr_mask); 787 DBG(DBG_ATTACH, NULL, "%s Mask: 0x%llx\n", 788 reg_desc->msg, CSR_XR(csr_base, reg_desc->enable_addr)); 789 DBG(DBG_ATTACH, NULL, "%s Status: 0x%llx\n", 790 reg_desc->msg, CSR_XR(csr_base, reg_desc->status_addr)); 791 DBG(DBG_ATTACH, NULL, "%s Clear: 0x%llx\n", 792 reg_desc->msg, CSR_XR(csr_base, reg_desc->clear_addr)); 793 if (reg_desc->log_addr != NULL) { 794 DBG(DBG_ATTACH, NULL, "%s Log: 0x%llx\n", 795 reg_desc->msg, CSR_XR(csr_base, reg_desc->log_addr)); 796 } 797 } 798 799 void 800 px_err_reg_disable(px_t *px_p, px_err_id_t id) 801 { 802 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 803 caddr_t csr_base; 804 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 805 806 /* Get the correct CSR BASE */ 807 if (PX_ERR_XBC(id)) 808 csr_base = (caddr_t)(uintptr_t)pxu_p->px_address[PX_REG_XBC]; 809 else 810 csr_base = (caddr_t)(uintptr_t)pxu_p->px_address[PX_REG_CSR]; 811 812 reg_desc->enabled = B_FALSE; 813 814 switch (id) { 815 case PX_ERR_JBC: 816 case PX_ERR_UBC: 817 case PX_ERR_MMU: 818 case PX_ERR_IMU: 819 case PX_ERR_TLU_UE: 820 case PX_ERR_TLU_CE: 821 case PX_ERR_TLU_OE: 822 case PX_ERR_ILU: 823 if (reg_desc->log_addr != NULL) { 824 CSR_XS(csr_base, reg_desc->log_addr, 0); 825 } 826 CSR_XS(csr_base, reg_desc->enable_addr, 0); 827 break; 828 case PX_ERR_LPU_LINK: 829 case PX_ERR_LPU_PHY: 830 case PX_ERR_LPU_RX: 831 case PX_ERR_LPU_TX: 832 case PX_ERR_LPU_LTSSM: 833 case PX_ERR_LPU_GIGABLZ: 834 if (reg_desc->log_addr != NULL) { 835 CSR_XS(csr_base, reg_desc->log_addr, -1); 836 } 837 CSR_XS(csr_base, reg_desc->enable_addr, -1); 838 break; 839 } 840 } 841 842 /* 843 * px_err_handle: 844 * Common function called by trap, mondo and fabric intr. 845 * o Snap shot current fire registers 846 * o check for safe access 847 * o send ereport and clear snap shot registers 848 * o check severity of snap shot registers 849 * 850 * @param px_p leaf in which to check access 851 * @param derr fm err data structure to be updated 852 * @param caller PX_TRAP_CALL | PX_INTR_CALL 853 * @param chk_cb whether to handle cb registers 854 * @return err PX_OK | PX_NONFATAL | 855 * PX_FATAL_GOS | PX_FATAL_HW | PX_STUCK_FATAL 856 */ 857 int 858 px_err_handle(px_t *px_p, ddi_fm_error_t *derr, int caller, 859 boolean_t chk_cb) 860 { 861 px_err_ss_t ss; 862 int err = PX_OK; 863 864 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 865 866 /* snap shot the current fire registers */ 867 px_err_snapshot(px_p, &ss, chk_cb); 868 869 /* check for safe access */ 870 px_err_safeacc_check(px_p, derr); 871 872 /* send ereports/handle/clear registers */ 873 err = px_err_erpt_and_clr(px_p, derr, &ss); 874 875 /* check for error severity */ 876 err = px_err_check_severity(px_p, derr, err, caller); 877 878 /* Mark the On Trap Handle if an error occured */ 879 if (err != PX_OK) { 880 px_pec_t *pec_p = px_p->px_pec_p; 881 on_trap_data_t *otd = pec_p->pec_ontrap_data; 882 883 if ((otd != NULL) && (otd->ot_prot & OT_DATA_ACCESS)) 884 otd->ot_trap |= OT_DATA_ACCESS; 885 } 886 887 return (err); 888 } 889 890 /* 891 * Static function 892 */ 893 894 /* 895 * px_err_snapshot: 896 * Take a current snap shot of all the fire error registers. This includes 897 * JBC/UBC, DMC, and PEC, unless chk_cb == false; 898 * 899 * @param px_p leaf in which to take the snap shot. 900 * @param ss pre-allocated memory to store the snap shot. 901 * @param chk_cb boolean on whether to store jbc/ubc register. 902 */ 903 static void 904 px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chk_cb) 905 { 906 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 907 caddr_t xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 908 caddr_t pec_csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 909 px_err_reg_desc_t *reg_desc; 910 int reg_id; 911 912 switch (PX_CHIP_TYPE(pxu_p)) { 913 case PX_CHIP_OBERON: 914 reg_id = PX_ERR_UBC; 915 break; 916 case PX_CHIP_FIRE: 917 reg_id = PX_ERR_JBC; 918 break; 919 default: 920 DBG(DBG_ERR_INTR, NULL, "px_err_snapshot - " 921 "unknown chip type: 0x%x\n", PX_CHIP_TYPE(pxu_p)); 922 reg_id = 0; 923 break; 924 } 925 926 /* snapshot CB interrupt status */ 927 if (chk_cb == B_TRUE) { 928 reg_desc = &px_err_reg_tbl[reg_id]; 929 /* Only look at enabled groups. */ 930 if (reg_desc->enabled == B_TRUE) { 931 ss->err_status[reg_id] = CSR_XR(xbc_csr_base, 932 reg_desc->status_addr); 933 } 934 } else { 935 ss->err_status[reg_id] = 0; 936 } 937 938 /* snapshot DMC/PEC interrupt status */ 939 for (reg_id = 2; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 940 reg_desc = &px_err_reg_tbl[reg_id]; 941 /* Only look at enabled groups. */ 942 if (reg_desc->enabled == B_TRUE) { 943 ss->err_status[reg_id] = CSR_XR(pec_csr_base, 944 reg_desc->status_addr); 945 } 946 } 947 } 948 949 /* 950 * px_err_erpt_and_clr: 951 * This function does the following thing to all the fire registers based 952 * on an earlier snap shot. 953 * o Send ereport 954 * o Handle the error 955 * o Clear the error 956 * 957 * @param px_p leaf in which to take the snap shot. 958 * @param derr fm err in which the ereport is to be based on 959 * @param ss pre-allocated memory to store the snap shot. 960 */ 961 static int 962 px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, px_err_ss_t *ss) 963 { 964 dev_info_t *rpdip = px_p->px_dip; 965 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 966 caddr_t csr_base; 967 px_err_reg_desc_t *err_reg_tbl; 968 px_err_bit_desc_t *err_bit_tbl; 969 px_err_bit_desc_t *err_bit_desc; 970 971 uint64_t *log_mask, *count_mask; 972 uint64_t status_addr, clear_addr; 973 uint64_t ss_reg; 974 975 int (*err_handler)(); 976 int (*erpt_handler)(); 977 int reg_id, key; 978 int err = PX_OK; 979 int biterr; 980 981 ASSERT(MUTEX_HELD(&px_p->px_fm_mutex)); 982 983 /* send erport/handle/clear JBC errors */ 984 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 985 /* Get the correct register description table */ 986 err_reg_tbl = &px_err_reg_tbl[reg_id]; 987 988 /* Only look at enabled groups. */ 989 if (err_reg_tbl->enabled != B_TRUE) 990 continue; 991 992 /* Get the correct CSR BASE */ 993 if (PX_ERR_XBC(reg_id)) 994 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 995 else 996 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 997 998 /* Get pointers to masks and register addresses */ 999 log_mask = err_reg_tbl->log_mask_p; 1000 count_mask = err_reg_tbl->count_mask_p; 1001 status_addr = err_reg_tbl->status_addr; 1002 clear_addr = err_reg_tbl->clear_addr; 1003 ss_reg = ss->err_status[reg_id]; 1004 1005 /* Get the register BIT description table */ 1006 err_bit_tbl = err_reg_tbl->err_bit_tbl; 1007 1008 /* For each known bit in the register send erpt and handle */ 1009 for (key = 0; key < err_reg_tbl->err_bit_keys; key += 1) { 1010 /* Get the bit description table for this register */ 1011 err_bit_desc = &err_bit_tbl[key]; 1012 1013 /* 1014 * If the ss_reg is set for this bit, 1015 * send ereport and handle 1016 */ 1017 if (BIT_TST(ss_reg, err_bit_desc->bit)) { 1018 /* Increment the counter if necessary */ 1019 if (BIT_TST(*count_mask, err_bit_desc->bit)) { 1020 err_bit_desc->counter++; 1021 } 1022 1023 /* Error Handle for this bit */ 1024 err_handler = err_bit_desc->err_handler; 1025 if (err_handler) { 1026 biterr = err_handler(rpdip, 1027 csr_base, 1028 derr, 1029 err_reg_tbl, 1030 err_bit_desc); 1031 err |= biterr; 1032 } 1033 1034 /* Send the ereport if it's an UNEXPECTED err */ 1035 erpt_handler = err_bit_desc->erpt_handler; 1036 if ((derr->fme_flag == DDI_FM_ERR_UNEXPECTED) && 1037 (biterr != PX_OK)) { 1038 if (erpt_handler) 1039 (void) erpt_handler(rpdip, 1040 csr_base, 1041 ss_reg, 1042 derr, 1043 err_bit_desc->bit, 1044 err_bit_desc->class_name); 1045 } 1046 } 1047 } 1048 /* Print register status */ 1049 if (ss_reg & *log_mask) 1050 DBG(DBG_ERR_INTR, rpdip, "<%x>=%16llx %s\n", 1051 status_addr, ss_reg, err_reg_tbl->msg); 1052 1053 /* Clear the register and error */ 1054 CSR_XS(csr_base, clear_addr, ss_reg); 1055 } 1056 1057 return (err); 1058 } 1059 1060 /* 1061 * px_err_check_severity: 1062 * Check the severity of the fire error based on an earlier snapshot 1063 * 1064 * @param px_p leaf in which to take the snap shot. 1065 * @param derr fm err in which the ereport is to be based on 1066 * @param ss pre-allocated memory to store the snap shot. 1067 */ 1068 static int 1069 px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, int err, int caller) 1070 { 1071 px_pec_t *pec_p = px_p->px_pec_p; 1072 boolean_t is_safeacc = B_FALSE; 1073 1074 /* nothing to do if called with no error */ 1075 if (err == PX_OK) 1076 return (err); 1077 1078 /* Cautious access error handling */ 1079 switch (derr->fme_flag) { 1080 case DDI_FM_ERR_EXPECTED: 1081 if (caller == PX_TRAP_CALL) { 1082 /* 1083 * for ddi_caut_get treat all events as nonfatal 1084 * The trampoline will set err_ena = 0, 1085 * err_status = NONFATAL. 1086 */ 1087 derr->fme_status = DDI_FM_NONFATAL; 1088 is_safeacc = B_TRUE; 1089 } else { 1090 /* 1091 * For ddi_caut_put treat all events as nonfatal. Here 1092 * we have the handle and can call ndi_fm_acc_err_set(). 1093 */ 1094 derr->fme_status = DDI_FM_NONFATAL; 1095 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 1096 is_safeacc = B_TRUE; 1097 } 1098 break; 1099 case DDI_FM_ERR_PEEK: 1100 case DDI_FM_ERR_POKE: 1101 /* 1102 * For ddi_peek/poke treat all events as nonfatal. 1103 */ 1104 is_safeacc = B_TRUE; 1105 break; 1106 default: 1107 is_safeacc = B_FALSE; 1108 } 1109 1110 /* 1111 * The third argument "err" is passed in as error status from checking 1112 * Fire register, re-adjust error status from safe access. 1113 */ 1114 if (is_safeacc && !(err & PX_FATAL_GOS)) 1115 return (PX_NONFATAL); 1116 1117 return (err); 1118 } 1119 1120 /* predefined convenience functions */ 1121 /* ARGSUSED */ 1122 int 1123 px_err_fatal_hw_handle(dev_info_t *rpdip, caddr_t csr_base, 1124 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1125 px_err_bit_desc_t *err_bit_descr) 1126 { 1127 return (PX_FATAL_HW); 1128 } 1129 1130 /* ARGSUSED */ 1131 int 1132 px_err_fatal_gos_handle(dev_info_t *rpdip, caddr_t csr_base, 1133 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1134 px_err_bit_desc_t *err_bit_descr) 1135 { 1136 return (PX_FATAL_GOS); 1137 } 1138 1139 /* ARGSUSED */ 1140 int 1141 px_err_fatal_stuck_handle(dev_info_t *rpdip, caddr_t csr_base, 1142 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1143 px_err_bit_desc_t *err_bit_descr) 1144 { 1145 return (PX_STUCK_FATAL); 1146 } 1147 1148 /* ARGSUSED */ 1149 int 1150 px_err_fatal_sw_handle(dev_info_t *rpdip, caddr_t csr_base, 1151 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1152 px_err_bit_desc_t *err_bit_descr) 1153 { 1154 return (PX_FATAL_SW); 1155 } 1156 1157 /* ARGSUSED */ 1158 int 1159 px_err_non_fatal_handle(dev_info_t *rpdip, caddr_t csr_base, 1160 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1161 px_err_bit_desc_t *err_bit_descr) 1162 { 1163 return (PX_NONFATAL); 1164 } 1165 1166 /* ARGSUSED */ 1167 int 1168 px_err_ok_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 1169 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 1170 { 1171 return (PX_OK); 1172 } 1173 1174 /* ARGSUSED */ 1175 int 1176 px_err_unknown_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 1177 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 1178 { 1179 return (PX_ERR_UNKNOWN); 1180 } 1181 1182 /* ARGSUSED */ 1183 PX_ERPT_SEND_DEC(do_not) 1184 { 1185 return (PX_OK); 1186 } 1187 1188 /* UBC FATAL - see io erpt doc, section 1.1 */ 1189 /* ARGSUSED */ 1190 PX_ERPT_SEND_DEC(ubc_fatal) 1191 { 1192 char buf[FM_MAX_CLASS]; 1193 uint64_t memory_ue_log, marked; 1194 char unum[FM_MAX_CLASS]; 1195 int unum_length; 1196 uint64_t device_id = 0; 1197 uint8_t cpu_version = 0; 1198 nvlist_t *resource = NULL; 1199 1200 unum[0] = '\0'; 1201 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1202 1203 memory_ue_log = CSR_XR(csr_base, UBC_MEMORY_UE_LOG); 1204 marked = (memory_ue_log >> UBC_MEMORY_UE_LOG_MARKED) & 1205 UBC_MEMORY_UE_LOG_MARKED_MASK; 1206 1207 if ((strstr(class_name, "ubc.piowtue") != NULL) || 1208 (strstr(class_name, "ubc.piowbeue") != NULL) || 1209 (strstr(class_name, "ubc.piorbeue") != NULL) || 1210 (strstr(class_name, "ubc.dmarduea") != NULL) || 1211 (strstr(class_name, "ubc.dmardueb") != NULL)) { 1212 int eid = (memory_ue_log >> UBC_MEMORY_UE_LOG_EID) & 1213 UBC_MEMORY_UE_LOG_EID_MASK; 1214 (void) strncat(buf, ubc_class_eid_qualifier[eid], 1215 FM_MAX_CLASS); 1216 1217 if (eid == UBC_EID_MEM) { 1218 uint64_t phys_addr = memory_ue_log & 1219 MMU_OBERON_PADDR_MASK; 1220 uint64_t offset = (uint64_t)-1; 1221 1222 resource = fm_nvlist_create(NULL); 1223 if (&plat_get_mem_unum) { 1224 if ((plat_get_mem_unum(0, 1225 phys_addr, 0, B_TRUE, 0, unum, 1226 FM_MAX_CLASS, &unum_length)) != 0) 1227 unum[0] = '\0'; 1228 } 1229 fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, 1230 NULL, unum, NULL, offset); 1231 1232 } else if (eid == UBC_EID_CPU) { 1233 int cpuid = (marked & UBC_MARKED_MAX_CPUID_MASK); 1234 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1235 1236 resource = fm_nvlist_create(NULL); 1237 cpu_version = cpunodes[cpuid].version; 1238 device_id = cpunodes[cpuid].device_id; 1239 (void) snprintf(sbuf, sizeof (sbuf), "%lX", 1240 device_id); 1241 (void) fm_fmri_cpu_set(resource, 1242 FM_CPU_SCHEME_VERSION, NULL, cpuid, 1243 &cpu_version, sbuf); 1244 } 1245 } 1246 1247 if (resource) { 1248 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1249 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1250 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1251 OBERON_UBC_ELE, DATA_TYPE_UINT64, 1252 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE), 1253 OBERON_UBC_IE, DATA_TYPE_UINT64, 1254 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), 1255 OBERON_UBC_IS, DATA_TYPE_UINT64, 1256 CSR_XR(csr_base, UBC_INTERRUPT_STATUS), 1257 OBERON_UBC_ESS, DATA_TYPE_UINT64, 1258 CSR_XR(csr_base, UBC_ERROR_STATUS_SET), 1259 OBERON_UBC_MUE, DATA_TYPE_UINT64, memory_ue_log, 1260 OBERON_UBC_UNUM, DATA_TYPE_STRING, unum, 1261 OBERON_UBC_DID, DATA_TYPE_UINT64, device_id, 1262 OBERON_UBC_CPUV, DATA_TYPE_UINT32, cpu_version, 1263 OBERON_UBC_RESOURCE, DATA_TYPE_NVLIST, resource, 1264 NULL); 1265 fm_nvlist_destroy(resource, FM_NVA_FREE); 1266 } else { 1267 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1268 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1269 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1270 OBERON_UBC_ELE, DATA_TYPE_UINT64, 1271 CSR_XR(csr_base, UBC_ERROR_LOG_ENABLE), 1272 OBERON_UBC_IE, DATA_TYPE_UINT64, 1273 CSR_XR(csr_base, UBC_INTERRUPT_ENABLE), 1274 OBERON_UBC_IS, DATA_TYPE_UINT64, 1275 CSR_XR(csr_base, UBC_INTERRUPT_STATUS), 1276 OBERON_UBC_ESS, DATA_TYPE_UINT64, 1277 CSR_XR(csr_base, UBC_ERROR_STATUS_SET), 1278 OBERON_UBC_MUE, DATA_TYPE_UINT64, memory_ue_log, 1279 OBERON_UBC_UNUM, DATA_TYPE_STRING, unum, 1280 OBERON_UBC_DID, DATA_TYPE_UINT64, device_id, 1281 OBERON_UBC_CPUV, DATA_TYPE_UINT32, cpu_version, 1282 NULL); 1283 } 1284 1285 return (PX_OK); 1286 } 1287 1288 /* JBC FATAL - see io erpt doc, section 1.1 */ 1289 PX_ERPT_SEND_DEC(jbc_fatal) 1290 { 1291 char buf[FM_MAX_CLASS]; 1292 boolean_t pri = PX_ERR_IS_PRI(bit); 1293 1294 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1295 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1296 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1297 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1298 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1299 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1300 FIRE_JBC_IE, DATA_TYPE_UINT64, 1301 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1302 FIRE_JBC_IS, DATA_TYPE_UINT64, 1303 ss_reg, 1304 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1305 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1306 FIRE_JBC_FEL1, DATA_TYPE_UINT64, 1307 CSR_XR(csr_base, FATAL_ERROR_LOG_1), 1308 FIRE_JBC_FEL2, DATA_TYPE_UINT64, 1309 CSR_XR(csr_base, FATAL_ERROR_LOG_2), 1310 NULL); 1311 1312 return (PX_OK); 1313 } 1314 1315 /* JBC MERGE - see io erpt doc, section 1.2 */ 1316 PX_ERPT_SEND_DEC(jbc_merge) 1317 { 1318 char buf[FM_MAX_CLASS]; 1319 boolean_t pri = PX_ERR_IS_PRI(bit); 1320 1321 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1322 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1323 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1324 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1325 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1326 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1327 FIRE_JBC_IE, DATA_TYPE_UINT64, 1328 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1329 FIRE_JBC_IS, DATA_TYPE_UINT64, 1330 ss_reg, 1331 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1332 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1333 FIRE_JBC_MTEL, DATA_TYPE_UINT64, 1334 CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG), 1335 NULL); 1336 1337 return (PX_OK); 1338 } 1339 1340 /* 1341 * JBC Merge buffer nonfatal errors: 1342 * Merge buffer parity error (rd_buf): dma:read:M:nonfatal 1343 * Merge buffer parity error (wr_buf): dma:write:M:nonfatal 1344 */ 1345 /* ARGSUSED */ 1346 int 1347 px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 1348 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1349 px_err_bit_desc_t *err_bit_descr) 1350 { 1351 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1352 uint64_t paddr; 1353 int ret; 1354 1355 if (!pri) 1356 return (PX_FATAL_GOS); 1357 1358 paddr = CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG); 1359 paddr &= MERGE_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1360 1361 ret = px_handle_lookup( 1362 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1363 1364 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1365 } 1366 1367 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 1368 PX_ERPT_SEND_DEC(jbc_in) 1369 { 1370 char buf[FM_MAX_CLASS]; 1371 boolean_t pri = PX_ERR_IS_PRI(bit); 1372 1373 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1374 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1375 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1376 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1377 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1378 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1379 FIRE_JBC_IE, DATA_TYPE_UINT64, 1380 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1381 FIRE_JBC_IS, DATA_TYPE_UINT64, 1382 ss_reg, 1383 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1384 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1385 FIRE_JBC_JITEL1, DATA_TYPE_UINT64, 1386 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG), 1387 FIRE_JBC_JITEL2, DATA_TYPE_UINT64, 1388 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG_2), 1389 NULL); 1390 1391 return (PX_OK); 1392 } 1393 1394 /* 1395 * JBC Jbusint IN nonfatal errors: PA logged in Jbusint In Transaction Error 1396 * Log Reg[42:0]. 1397 * CE async fault error: nonfatal 1398 * Jbus bus error: dma::nonfatal 1399 * Jbus unmapped error: pio|dma:rdwr:M:nonfatal 1400 * Write data parity error: pio/write:M:nonfatal 1401 * Read data parity error: pio/read:M:nonfatal 1402 * Illegal NCWR bytemask: pio:write:M:nonfatal 1403 * Illegal NCRD bytemask: pio:write:M:nonfatal 1404 * Invalid jbus transaction: nonfatal 1405 */ 1406 /* ARGSUSED */ 1407 int 1408 px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 1409 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1410 px_err_bit_desc_t *err_bit_descr) 1411 { 1412 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1413 uint64_t paddr; 1414 int ret; 1415 1416 if (!pri) 1417 return (PX_FATAL_GOS); 1418 1419 paddr = CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG); 1420 paddr &= JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1421 1422 ret = px_handle_lookup( 1423 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1424 1425 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1426 } 1427 1428 1429 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 1430 PX_ERPT_SEND_DEC(jbc_out) 1431 { 1432 char buf[FM_MAX_CLASS]; 1433 boolean_t pri = PX_ERR_IS_PRI(bit); 1434 1435 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1436 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1437 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1438 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1439 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1440 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1441 FIRE_JBC_IE, DATA_TYPE_UINT64, 1442 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1443 FIRE_JBC_IS, DATA_TYPE_UINT64, 1444 ss_reg, 1445 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1446 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1447 FIRE_JBC_JOTEL1, DATA_TYPE_UINT64, 1448 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG), 1449 FIRE_JBC_JOTEL2, DATA_TYPE_UINT64, 1450 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG_2), 1451 NULL); 1452 1453 return (PX_OK); 1454 } 1455 1456 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 1457 PX_ERPT_SEND_DEC(jbc_odcd) 1458 { 1459 char buf[FM_MAX_CLASS]; 1460 boolean_t pri = PX_ERR_IS_PRI(bit); 1461 1462 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1463 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1464 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1465 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1466 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1467 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1468 FIRE_JBC_IE, DATA_TYPE_UINT64, 1469 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1470 FIRE_JBC_IS, DATA_TYPE_UINT64, 1471 ss_reg, 1472 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1473 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1474 FIRE_JBC_DMC_ODCD, DATA_TYPE_UINT64, 1475 CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG), 1476 NULL); 1477 1478 return (PX_OK); 1479 } 1480 1481 /* 1482 * JBC Dmcint ODCO nonfatal errer handling - 1483 * PIO data parity error: pio:write:M:nonfatal 1484 */ 1485 /* ARGSUSED */ 1486 int 1487 px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 1488 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1489 px_err_bit_desc_t *err_bit_descr) 1490 { 1491 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1492 uint64_t paddr; 1493 int ret; 1494 1495 if (!pri) 1496 return (PX_FATAL_GOS); 1497 1498 paddr = CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG); 1499 paddr &= DMCINT_ODCD_ERROR_LOG_ADDRESS_MASK; 1500 1501 ret = px_handle_lookup( 1502 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1503 1504 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1505 } 1506 1507 /* Does address in DMCINT error log register match address of pcitool access? */ 1508 static boolean_t 1509 px_jbc_pcitool_addr_match(dev_info_t *rpdip, caddr_t csr_base) 1510 { 1511 px_t *px_p = DIP_TO_STATE(rpdip); 1512 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 1513 caddr_t pcitool_addr = pxu_p->pcitool_addr; 1514 caddr_t errlog_addr = 1515 (caddr_t)CSR_FR(csr_base, DMCINT_ODCD_ERROR_LOG, ADDRESS); 1516 1517 return (pcitool_addr == errlog_addr); 1518 } 1519 1520 /* 1521 * JBC Dmcint ODCD errer handling for errors which are forgivable during a safe 1522 * access. (This will be most likely be a PCItool access.) If not a safe 1523 * access context, treat like jbc_dmcint_odcd. 1524 * Unmapped PIO read error: pio:read:M:nonfatal 1525 * Unmapped PIO write error: pio:write:M:nonfatal 1526 * Invalid PIO write to PCIe cfg/io, csr, ebus or i2c bus: pio:write:nonfatal 1527 * Invalid PIO read to PCIe cfg/io, csr, ebus or i2c bus: pio:read:nonfatal 1528 */ 1529 /* ARGSUSED */ 1530 int 1531 px_err_jbc_safe_acc_handle(dev_info_t *rpdip, caddr_t csr_base, 1532 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1533 px_err_bit_desc_t *err_bit_descr) 1534 { 1535 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1536 1537 if (!pri) 1538 return (PX_FATAL_GOS); 1539 /* 1540 * Got an error which is forgivable during a PCItool access. 1541 * 1542 * Don't do handler check since the error may otherwise be unfairly 1543 * attributed to a device. Just return. 1544 * 1545 * Note: There is a hole here in that a legitimate error can come in 1546 * while a PCItool access is in play and be forgiven. This is possible 1547 * though not likely. 1548 */ 1549 if ((derr->fme_flag != DDI_FM_ERR_UNEXPECTED) && 1550 (px_jbc_pcitool_addr_match(rpdip, csr_base))) 1551 return (PX_FATAL_SW); 1552 1553 return (px_err_jbc_dmcint_odcd_handle(rpdip, csr_base, derr, 1554 err_reg_descr, err_bit_descr)); 1555 } 1556 1557 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1558 PX_ERPT_SEND_DEC(jbc_idc) 1559 { 1560 char buf[FM_MAX_CLASS]; 1561 boolean_t pri = PX_ERR_IS_PRI(bit); 1562 1563 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1564 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1565 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1566 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1567 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1568 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1569 FIRE_JBC_IE, DATA_TYPE_UINT64, 1570 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1571 FIRE_JBC_IS, DATA_TYPE_UINT64, 1572 ss_reg, 1573 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1574 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1575 FIRE_JBC_DMC_IDC, DATA_TYPE_UINT64, 1576 CSR_XR(csr_base, DMCINT_IDC_ERROR_LOG), 1577 NULL); 1578 1579 return (PX_OK); 1580 } 1581 1582 /* JBC CSR - see io erpt doc, section 1.7 */ 1583 PX_ERPT_SEND_DEC(jbc_csr) 1584 { 1585 char buf[FM_MAX_CLASS]; 1586 boolean_t pri = PX_ERR_IS_PRI(bit); 1587 1588 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1589 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1590 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1591 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1592 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1593 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1594 FIRE_JBC_IE, DATA_TYPE_UINT64, 1595 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1596 FIRE_JBC_IS, DATA_TYPE_UINT64, 1597 ss_reg, 1598 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1599 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1600 "jbc-error-reg", DATA_TYPE_UINT64, 1601 CSR_XR(csr_base, CSR_ERROR_LOG), 1602 NULL); 1603 1604 return (PX_OK); 1605 } 1606 1607 /* 1608 * JBC CSR errer handling - 1609 * Ebus ready timeout error: pio:rdwr:M:nonfatal 1610 */ 1611 /* ARGSUSED */ 1612 int 1613 px_err_jbc_csr_handle(dev_info_t *rpdip, caddr_t csr_base, 1614 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1615 px_err_bit_desc_t *err_bit_descr) 1616 { 1617 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1618 uint64_t paddr; 1619 int ret; 1620 1621 if (!pri) 1622 return (PX_FATAL_GOS); 1623 1624 paddr = CSR_XR(csr_base, CSR_ERROR_LOG); 1625 paddr &= CSR_ERROR_LOG_ADDRESS_MASK; 1626 1627 ret = px_handle_lookup( 1628 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1629 1630 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1631 } 1632 1633 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1634 1635 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 1636 PX_ERPT_SEND_DEC(imu_rds) 1637 { 1638 char buf[FM_MAX_CLASS]; 1639 boolean_t pri = PX_ERR_IS_PRI(bit); 1640 1641 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1642 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1643 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1644 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1645 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1646 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1647 FIRE_IMU_IE, DATA_TYPE_UINT64, 1648 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1649 FIRE_IMU_IS, DATA_TYPE_UINT64, 1650 ss_reg, 1651 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1652 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1653 FIRE_IMU_RDS, DATA_TYPE_UINT64, 1654 CSR_XR(csr_base, IMU_RDS_ERROR_LOG), 1655 NULL); 1656 1657 return (PX_OK); 1658 } 1659 1660 /* imu function to handle all Received but Not Enabled errors */ 1661 /* ARGSUSED */ 1662 int 1663 px_err_imu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1664 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1665 px_err_bit_desc_t *err_bit_descr) 1666 { 1667 uint64_t imu_log_enable, imu_intr_enable; 1668 int mask = BITMASK(err_bit_descr->bit); 1669 int err = PX_NONFATAL; 1670 1671 imu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1672 imu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1673 1674 /* 1675 * If matching bit is not set, meaning corresponding rbne not 1676 * enabled, then receiving it indicates some sort of malfunction 1677 * possibly in hardware. 1678 * 1679 * Other wise, software may have intentionally disabled certain 1680 * errors for a period of time within which the occuring of the 1681 * disabled errors become rbne, that is non fatal. 1682 */ 1683 1684 if (!(imu_log_enable & imu_intr_enable & mask)) 1685 err = PX_FATAL_GOS; 1686 1687 return (err); 1688 } 1689 1690 /* 1691 * No platforms uses PME. Any PME received is simply logged 1692 * for analysis. 1693 */ 1694 /* ARGSUSED */ 1695 int 1696 px_err_imu_pme_handle(dev_info_t *rpdip, caddr_t csr_base, 1697 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1698 px_err_bit_desc_t *err_bit_descr) 1699 { 1700 px_t *px_p = DIP_TO_STATE(rpdip); 1701 1702 px_p->px_pme_ignored++; 1703 return (PX_NONFATAL); 1704 } 1705 1706 /* handle EQ overflow */ 1707 /* ARGSUSED */ 1708 int 1709 px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 1710 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1711 px_err_bit_desc_t *err_bit_descr) 1712 { 1713 px_t *px_p = DIP_TO_STATE(rpdip); 1714 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 1715 msiqid_t eqno; 1716 pci_msiq_state_t msiq_state; 1717 int err = PX_NONFATAL; 1718 int i; 1719 1720 eqno = msiq_state_p->msiq_1st_msiq_id; 1721 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 1722 if (px_lib_msiq_getstate(rpdip, eqno, &msiq_state) == 1723 DDI_SUCCESS) { 1724 if (msiq_state == PCI_MSIQ_STATE_ERROR) { 1725 err = PX_FATAL_GOS; 1726 } 1727 } 1728 } 1729 1730 return (err); 1731 } 1732 1733 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 1734 PX_ERPT_SEND_DEC(imu_scs) 1735 { 1736 char buf[FM_MAX_CLASS]; 1737 boolean_t pri = PX_ERR_IS_PRI(bit); 1738 1739 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1740 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1741 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1742 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1743 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1744 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1745 FIRE_IMU_IE, DATA_TYPE_UINT64, 1746 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1747 FIRE_IMU_IS, DATA_TYPE_UINT64, 1748 ss_reg, 1749 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1750 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1751 FIRE_IMU_SCS, DATA_TYPE_UINT64, 1752 CSR_XR(csr_base, IMU_SCS_ERROR_LOG), 1753 NULL); 1754 1755 return (PX_OK); 1756 } 1757 1758 /* DMC IMU - see io erpt doc, section 2.3 */ 1759 PX_ERPT_SEND_DEC(imu) 1760 { 1761 char buf[FM_MAX_CLASS]; 1762 boolean_t pri = PX_ERR_IS_PRI(bit); 1763 1764 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1765 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1766 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1767 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1768 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1769 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1770 FIRE_IMU_IE, DATA_TYPE_UINT64, 1771 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1772 FIRE_IMU_IS, DATA_TYPE_UINT64, 1773 ss_reg, 1774 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1775 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1776 NULL); 1777 1778 return (PX_OK); 1779 } 1780 1781 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 1782 PX_ERPT_SEND_DEC(mmu_tfar_tfsr) 1783 { 1784 char buf[FM_MAX_CLASS]; 1785 boolean_t pri = PX_ERR_IS_PRI(bit); 1786 1787 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1788 1789 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1790 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1791 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1792 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1793 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1794 FIRE_MMU_IE, DATA_TYPE_UINT64, 1795 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1796 FIRE_MMU_IS, DATA_TYPE_UINT64, 1797 ss_reg, 1798 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1799 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1800 FIRE_MMU_TFAR, DATA_TYPE_UINT64, 1801 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS), 1802 FIRE_MMU_TFSR, DATA_TYPE_UINT64, 1803 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS), 1804 NULL); 1805 1806 return (PX_OK); 1807 } 1808 1809 /* DMC MMU - see io erpt doc, section 2.5 */ 1810 PX_ERPT_SEND_DEC(mmu) 1811 { 1812 char buf[FM_MAX_CLASS]; 1813 boolean_t pri = PX_ERR_IS_PRI(bit); 1814 1815 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1816 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1817 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1818 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1819 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1820 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1821 FIRE_MMU_IE, DATA_TYPE_UINT64, 1822 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1823 FIRE_MMU_IS, DATA_TYPE_UINT64, 1824 ss_reg, 1825 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1826 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1827 NULL); 1828 1829 return (PX_OK); 1830 } 1831 1832 /* imu function to handle all Received but Not Enabled errors */ 1833 int 1834 px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1835 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1836 px_err_bit_desc_t *err_bit_descr) 1837 { 1838 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1839 uint64_t mmu_log_enable, mmu_intr_enable; 1840 uint64_t mask = BITMASK(err_bit_descr->bit); 1841 uint64_t mmu_tfa, mmu_ctrl; 1842 uint64_t mmu_enable_bit = 0; 1843 int err = PX_NONFATAL; 1844 int ret; 1845 1846 mmu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1847 mmu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1848 1849 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1850 mmu_ctrl = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1851 1852 switch (err_bit_descr->bit) { 1853 case MMU_INTERRUPT_STATUS_BYP_ERR_P: 1854 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_BE); 1855 break; 1856 case MMU_INTERRUPT_STATUS_TRN_ERR_P: 1857 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_TE); 1858 break; 1859 default: 1860 mmu_enable_bit = 0; 1861 break; 1862 } 1863 1864 /* 1865 * If the interrupts are enabled and Translation/Bypass Enable bit 1866 * was set, then panic. This error should not have occured. 1867 */ 1868 if (mmu_log_enable & mmu_intr_enable & 1869 (mmu_ctrl & mmu_enable_bit)) { 1870 err = PX_FATAL_GOS; 1871 } else { 1872 if (!pri) 1873 return (PX_FATAL_GOS); 1874 1875 ret = px_handle_lookup( 1876 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1877 err = (ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL; 1878 1879 /* 1880 * S/W bug - this error should always be enabled 1881 */ 1882 1883 /* enable error & intr reporting for this bit */ 1884 CSR_XS(csr_base, MMU_ERROR_LOG_ENABLE, mmu_log_enable | mask); 1885 CSR_XS(csr_base, MMU_INTERRUPT_ENABLE, mmu_intr_enable | mask); 1886 1887 /* enable translation access/bypass enable */ 1888 CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, 1889 mmu_ctrl | mmu_enable_bit); 1890 } 1891 1892 return (err); 1893 } 1894 1895 /* Generic error handling functions that involve MMU Translation Fault Addr */ 1896 /* ARGSUSED */ 1897 int 1898 px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 1899 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1900 px_err_bit_desc_t *err_bit_descr) 1901 { 1902 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1903 uint64_t mmu_tfa; 1904 uint_t ret; 1905 1906 if (!pri) 1907 return (PX_FATAL_GOS); 1908 1909 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1910 ret = px_handle_lookup( 1911 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1912 1913 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1914 } 1915 1916 /* MMU Table walk errors */ 1917 /* ARGSUSED */ 1918 int 1919 px_err_mmu_tblwlk_handle(dev_info_t *rpdip, caddr_t csr_base, 1920 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1921 px_err_bit_desc_t *err_bit_descr) 1922 { 1923 boolean_t pri = PX_ERR_IS_PRI(err_bit_descr->bit); 1924 uint64_t mmu_tfa; 1925 uint_t ret; 1926 1927 if (!pri) 1928 return (PX_FATAL_GOS); 1929 1930 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1931 ret = px_handle_lookup( 1932 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1933 1934 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1935 } 1936 1937 /* 1938 * TLU LUP event - if caused by power management activity, then it is expected. 1939 * In all other cases, it is an error. 1940 */ 1941 /* ARGSUSED */ 1942 int 1943 px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 1944 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1945 px_err_bit_desc_t *err_bit_descr) 1946 { 1947 px_t *px_p = DIP_TO_STATE(rpdip); 1948 1949 /* 1950 * power management code is currently the only segment that sets 1951 * px_lup_pending to indicate its expectation for a healthy LUP 1952 * event. For all other occasions, LUP event should be flaged as 1953 * error condition. 1954 */ 1955 return ((atomic_cas_32(&px_p->px_lup_pending, 1, 0) == 0) ? 1956 PX_NONFATAL : PX_OK); 1957 } 1958 1959 /* 1960 * TLU LDN event - if caused by power management activity, then it is expected. 1961 * In all other cases, it is an error. 1962 */ 1963 /* ARGSUSED */ 1964 int 1965 px_err_tlu_ldn_handle(dev_info_t *rpdip, caddr_t csr_base, 1966 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1967 px_err_bit_desc_t *err_bit_descr) 1968 { 1969 px_t *px_p = DIP_TO_STATE(rpdip); 1970 return ((px_p->px_pm_flags & PX_LDN_EXPECTED) ? PX_OK : PX_NONFATAL); 1971 } 1972 1973 /* PEC ILU none - see io erpt doc, section 3.1 */ 1974 PX_ERPT_SEND_DEC(pec_ilu) 1975 { 1976 char buf[FM_MAX_CLASS]; 1977 boolean_t pri = PX_ERR_IS_PRI(bit); 1978 1979 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1980 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1981 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1982 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 1983 FIRE_ILU_ELE, DATA_TYPE_UINT64, 1984 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE), 1985 FIRE_ILU_IE, DATA_TYPE_UINT64, 1986 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE), 1987 FIRE_ILU_IS, DATA_TYPE_UINT64, 1988 ss_reg, 1989 FIRE_ILU_ESS, DATA_TYPE_UINT64, 1990 CSR_XR(csr_base, ILU_ERROR_STATUS_SET), 1991 NULL); 1992 1993 return (PX_OK); 1994 } 1995 1996 /* PCIEX UE Errors */ 1997 /* ARGSUSED */ 1998 int 1999 px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 2000 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 2001 px_err_bit_desc_t *err_bit_descr) 2002 { 2003 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 2004 2005 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ue_gos) ? 2006 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ue, 2007 px_fabric_die_rc_ue_gos)); 2008 } 2009 2010 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.2 */ 2011 PX_ERPT_SEND_DEC(pciex_rx_ue) 2012 { 2013 char buf[FM_MAX_CLASS]; 2014 boolean_t pri = PX_ERR_IS_PRI(bit); 2015 2016 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2017 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2018 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2019 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2020 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2021 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2022 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2023 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2024 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2025 ss_reg, 2026 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2027 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2028 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2029 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 2030 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2031 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 2032 NULL); 2033 2034 return (PX_OK); 2035 } 2036 2037 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.3 */ 2038 PX_ERPT_SEND_DEC(pciex_tx_ue) 2039 { 2040 char buf[FM_MAX_CLASS]; 2041 boolean_t pri = PX_ERR_IS_PRI(bit); 2042 2043 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2044 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2045 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2046 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2047 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2048 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2049 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2050 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2051 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2052 ss_reg, 2053 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2054 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2055 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 2056 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 2057 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 2058 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 2059 NULL); 2060 2061 return (PX_OK); 2062 } 2063 2064 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.4 */ 2065 PX_ERPT_SEND_DEC(pciex_rx_tx_ue) 2066 { 2067 char buf[FM_MAX_CLASS]; 2068 boolean_t pri = PX_ERR_IS_PRI(bit); 2069 2070 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2071 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2072 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2073 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2074 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2075 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2076 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2077 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2078 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2079 ss_reg, 2080 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2081 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2082 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2083 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 2084 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2085 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 2086 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 2087 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 2088 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 2089 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 2090 NULL); 2091 2092 return (PX_OK); 2093 } 2094 2095 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 2096 PX_ERPT_SEND_DEC(pciex_ue) 2097 { 2098 char buf[FM_MAX_CLASS]; 2099 boolean_t pri = PX_ERR_IS_PRI(bit); 2100 2101 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2102 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2103 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2104 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2105 FIRE_TLU_UELE, DATA_TYPE_UINT64, 2106 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 2107 FIRE_TLU_UIE, DATA_TYPE_UINT64, 2108 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 2109 FIRE_TLU_UIS, DATA_TYPE_UINT64, 2110 ss_reg, 2111 FIRE_TLU_UESS, DATA_TYPE_UINT64, 2112 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 2113 NULL); 2114 2115 return (PX_OK); 2116 } 2117 2118 /* PCIEX UE Errors */ 2119 /* ARGSUSED */ 2120 int 2121 px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 2122 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 2123 px_err_bit_desc_t *err_bit_descr) 2124 { 2125 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 2126 2127 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ce_gos) ? 2128 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ce, 2129 px_fabric_die_rc_ce_gos)); 2130 } 2131 2132 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 2133 PX_ERPT_SEND_DEC(pciex_ce) 2134 { 2135 char buf[FM_MAX_CLASS]; 2136 boolean_t pri = PX_ERR_IS_PRI(bit); 2137 2138 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2139 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2140 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2141 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2142 FIRE_TLU_CELE, DATA_TYPE_UINT64, 2143 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE), 2144 FIRE_TLU_CIE, DATA_TYPE_UINT64, 2145 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE), 2146 FIRE_TLU_CIS, DATA_TYPE_UINT64, 2147 ss_reg, 2148 FIRE_TLU_CESS, DATA_TYPE_UINT64, 2149 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_SET), 2150 NULL); 2151 2152 return (PX_OK); 2153 } 2154 2155 /* TLU Other Event Status (receive only) - see io erpt doc, section 3.7 */ 2156 PX_ERPT_SEND_DEC(pciex_rx_oe) 2157 { 2158 char buf[FM_MAX_CLASS]; 2159 boolean_t pri = PX_ERR_IS_PRI(bit); 2160 2161 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2162 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2163 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2164 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2165 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2166 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2167 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2168 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2169 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2170 ss_reg, 2171 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2172 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2173 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 2174 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 2175 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 2176 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 2177 NULL); 2178 2179 return (PX_OK); 2180 } 2181 2182 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 2183 PX_ERPT_SEND_DEC(pciex_rx_tx_oe) 2184 { 2185 char buf[FM_MAX_CLASS]; 2186 boolean_t pri = PX_ERR_IS_PRI(bit); 2187 2188 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2189 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2190 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2191 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2192 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2193 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2194 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2195 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2196 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2197 ss_reg, 2198 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2199 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2200 FIRE_TLU_ROEEH1L, DATA_TYPE_UINT64, 2201 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 2202 FIRE_TLU_ROEEH2L, DATA_TYPE_UINT64, 2203 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 2204 FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, 2205 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG), 2206 FIRE_TLU_TOEEH2L, DATA_TYPE_UINT64, 2207 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG), 2208 NULL); 2209 2210 return (PX_OK); 2211 } 2212 2213 /* TLU Other Event - see io erpt doc, section 3.9 */ 2214 PX_ERPT_SEND_DEC(pciex_oe) 2215 { 2216 char buf[FM_MAX_CLASS]; 2217 boolean_t pri = PX_ERR_IS_PRI(bit); 2218 2219 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 2220 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 2221 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 2222 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, pri, 2223 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 2224 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 2225 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 2226 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 2227 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 2228 ss_reg, 2229 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 2230 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 2231 NULL); 2232 2233 return (PX_OK); 2234 } 2235