1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * sun4u Fire Error Handling 31 */ 32 33 #include <sys/types.h> 34 #include <sys/ddi.h> 35 #include <sys/sunddi.h> 36 #include <sys/fm/protocol.h> 37 #include <sys/fm/util.h> 38 #include <sys/pcie.h> 39 #include <sys/pcie_impl.h> 40 #include "px_obj.h" 41 #include <px_regs.h> 42 #include <px_csr.h> 43 #include <sys/membar.h> 44 #include "pcie_pwr.h" 45 #include "px_lib4u.h" 46 #include "px_err.h" 47 #include "px_err_impl.h" 48 49 /* 50 * JBC error bit table 51 */ 52 #define JBC_BIT_DESC(bit, hdl, erpt) \ 53 JBC_INTERRUPT_STATUS_ ## bit ## _P, \ 54 0, \ 55 PX_ERR_BIT_HANDLE(hdl), \ 56 PX_ERPT_SEND(erpt), \ 57 PX_ERR_JBC_CLASS(bit) 58 px_err_bit_desc_t px_err_cb_tbl[] = { 59 /* JBC FATAL - see io erpt doc, section 1.1 */ 60 { JBC_BIT_DESC(MB_PEA, fatal_hw, jbc_fatal) }, 61 { JBC_BIT_DESC(CPE, fatal_hw, jbc_fatal) }, 62 { JBC_BIT_DESC(APE, fatal_hw, jbc_fatal) }, 63 { JBC_BIT_DESC(PIO_CPE, fatal_hw, jbc_fatal) }, 64 { JBC_BIT_DESC(JTCEEW, fatal_hw, jbc_fatal) }, 65 { JBC_BIT_DESC(JTCEEI, fatal_hw, jbc_fatal) }, 66 { JBC_BIT_DESC(JTCEER, fatal_hw, jbc_fatal) }, 67 68 /* JBC MERGE - see io erpt doc, section 1.2 */ 69 { JBC_BIT_DESC(MB_PER, jbc_merge, jbc_merge) }, 70 { JBC_BIT_DESC(MB_PEW, jbc_merge, jbc_merge) }, 71 72 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 73 { JBC_BIT_DESC(UE_ASYN, fatal_gos, jbc_in) }, 74 { JBC_BIT_DESC(CE_ASYN, jbc_jbusint_in, jbc_in) }, 75 { JBC_BIT_DESC(JTE, fatal_gos, jbc_in) }, 76 { JBC_BIT_DESC(JBE, jbc_jbusint_in, jbc_in) }, 77 { JBC_BIT_DESC(JUE, jbc_jbusint_in, jbc_in) }, 78 { JBC_BIT_DESC(ICISE, fatal_gos, jbc_in) }, 79 { JBC_BIT_DESC(WR_DPE, jbc_jbusint_in, jbc_in) }, 80 { JBC_BIT_DESC(RD_DPE, jbc_jbusint_in, jbc_in) }, 81 { JBC_BIT_DESC(ILL_BMW, jbc_jbusint_in, jbc_in) }, 82 { JBC_BIT_DESC(ILL_BMR, jbc_jbusint_in, jbc_in) }, 83 { JBC_BIT_DESC(BJC, jbc_jbusint_in, jbc_in) }, 84 85 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 86 { JBC_BIT_DESC(IJP, fatal_gos, jbc_out) }, 87 88 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 89 { JBC_BIT_DESC(PIO_UNMAP_RD, jbc_dmcint_odcd, jbc_odcd) }, 90 { JBC_BIT_DESC(ILL_ACC_RD, jbc_dmcint_odcd, jbc_odcd) }, 91 { JBC_BIT_DESC(PIO_UNMAP, jbc_dmcint_odcd, jbc_odcd) }, 92 { JBC_BIT_DESC(PIO_DPE, jbc_dmcint_odcd, jbc_odcd) }, 93 { JBC_BIT_DESC(PIO_CPE, non_fatal, jbc_odcd) }, 94 { JBC_BIT_DESC(ILL_ACC, jbc_dmcint_odcd, jbc_odcd) }, 95 96 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 97 { JBC_BIT_DESC(UNSOL_RD, non_fatal, jbc_idc) }, 98 { JBC_BIT_DESC(UNSOL_INTR, non_fatal, jbc_idc) }, 99 100 /* JBC CSR - see io erpt doc, section 1.7 */ 101 { JBC_BIT_DESC(EBUS_TO, jbc_csr, jbc_csr) } 102 }; 103 104 #define px_err_cb_keys \ 105 (sizeof (px_err_cb_tbl)) / (sizeof (px_err_bit_desc_t)) 106 107 /* 108 * DMC error bit tables 109 */ 110 #define IMU_BIT_DESC(bit, hdl, erpt) \ 111 IMU_INTERRUPT_STATUS_ ## bit ## _P, \ 112 0, \ 113 PX_ERR_BIT_HANDLE(hdl), \ 114 PX_ERPT_SEND(erpt), \ 115 PX_ERR_DMC_CLASS(bit) 116 px_err_bit_desc_t px_err_imu_tbl[] = { 117 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 118 { IMU_BIT_DESC(MSI_MAL_ERR, non_fatal, imu_rds) }, 119 { IMU_BIT_DESC(MSI_PAR_ERR, fatal_stuck, imu_rds) }, 120 { IMU_BIT_DESC(PMEACK_MES_NOT_EN, imu_rbne, imu_rds) }, 121 { IMU_BIT_DESC(PMPME_MES_NOT_EN, imu_pme, imu_rds) }, 122 { IMU_BIT_DESC(FATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 123 { IMU_BIT_DESC(NONFATAL_MES_NOT_EN, imu_rbne, imu_rds) }, 124 { IMU_BIT_DESC(COR_MES_NOT_EN, imu_rbne, imu_rds) }, 125 { IMU_BIT_DESC(MSI_NOT_EN, imu_rbne, imu_rds) }, 126 127 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 128 { IMU_BIT_DESC(EQ_NOT_EN, imu_rbne, imu_rds) }, 129 130 /* DMC IMU - see io erpt doc, section 2.3 */ 131 { IMU_BIT_DESC(EQ_OVER, imu_eq_ovfl, imu) } 132 }; 133 134 #define px_err_imu_keys (sizeof (px_err_imu_tbl)) / (sizeof (px_err_bit_desc_t)) 135 136 /* mmu errors */ 137 #define MMU_BIT_DESC(bit, hdl, erpt) \ 138 MMU_INTERRUPT_STATUS_ ## bit ## _P, \ 139 0, \ 140 PX_ERR_BIT_HANDLE(hdl), \ 141 PX_ERPT_SEND(erpt), \ 142 PX_ERR_DMC_CLASS(bit) 143 px_err_bit_desc_t px_err_mmu_tbl[] = { 144 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 145 { MMU_BIT_DESC(BYP_ERR, mmu_rbne, mmu_tfar_tfsr) }, 146 { MMU_BIT_DESC(BYP_OOR, mmu_tfa, mmu_tfar_tfsr) }, 147 { MMU_BIT_DESC(TRN_ERR, mmu_rbne, mmu_tfar_tfsr) }, 148 { MMU_BIT_DESC(TRN_OOR, mmu_tfa, mmu_tfar_tfsr) }, 149 { MMU_BIT_DESC(TTE_INV, mmu_tfa, mmu_tfar_tfsr) }, 150 { MMU_BIT_DESC(TTE_PRT, mmu_tfa, mmu_tfar_tfsr) }, 151 { MMU_BIT_DESC(TTC_DPE, mmu_tfa, mmu_tfar_tfsr) }, 152 { MMU_BIT_DESC(TBW_DME, mmu_tblwlk, mmu_tfar_tfsr) }, 153 { MMU_BIT_DESC(TBW_UDE, mmu_tblwlk, mmu_tfar_tfsr) }, 154 { MMU_BIT_DESC(TBW_ERR, mmu_tblwlk, mmu_tfar_tfsr) }, 155 { MMU_BIT_DESC(TBW_DPE, mmu_tblwlk, mmu_tfar_tfsr) }, 156 157 /* DMC MMU - see io erpt doc, section 2.5 */ 158 { MMU_BIT_DESC(TTC_CAE, non_fatal, mmu) } 159 }; 160 #define px_err_mmu_keys (sizeof (px_err_mmu_tbl)) / (sizeof (px_err_bit_desc_t)) 161 162 /* 163 * PEC error bit tables 164 */ 165 #define ILU_BIT_DESC(bit, hdl, erpt) \ 166 ILU_INTERRUPT_STATUS_ ## bit ## _P, \ 167 0, \ 168 PX_ERR_BIT_HANDLE(hdl), \ 169 PX_ERPT_SEND(erpt), \ 170 PX_ERR_PEC_CLASS(bit) 171 px_err_bit_desc_t px_err_ilu_tbl[] = { 172 /* PEC ILU none - see io erpt doc, section 3.1 */ 173 { ILU_BIT_DESC(IHB_PE, fatal_gos, pec_ilu) } 174 }; 175 #define px_err_ilu_keys \ 176 (sizeof (px_err_ilu_tbl)) / (sizeof (px_err_bit_desc_t)) 177 178 /* 179 * PEC UE errors implementation is incomplete pending PCIE generic 180 * fabric rules. Must handle both PRIMARY and SECONDARY errors. 181 */ 182 /* pec ue errors */ 183 #define TLU_UC_BIT_DESC(bit, hdl, erpt) \ 184 TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 185 0, \ 186 PX_ERR_BIT_HANDLE(hdl), \ 187 PX_ERPT_SEND(erpt), \ 188 PX_ERR_PEC_CLASS(bit) }, \ 189 { TLU_UNCORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 190 0, \ 191 PX_ERR_BIT_HANDLE(hdl), \ 192 PX_ERPT_SEND(erpt), \ 193 PX_ERR_PEC_CLASS(bit) 194 px_err_bit_desc_t px_err_tlu_ue_tbl[] = { 195 /* PCI-E Receive Uncorrectable Errors - see io erpt doc, section 3.2 */ 196 { TLU_UC_BIT_DESC(UR, pciex_ue, pciex_rx_ue) }, 197 { TLU_UC_BIT_DESC(UC, pciex_ue, pciex_rx_ue) }, 198 199 /* PCI-E Transmit Uncorrectable Errors - see io erpt doc, section 3.3 */ 200 { TLU_UC_BIT_DESC(CTO, pciex_ue, pciex_tx_ue) }, 201 { TLU_UC_BIT_DESC(ROF, pciex_ue, pciex_tx_ue) }, 202 203 /* PCI-E Rx/Tx Uncorrectable Errors - see io erpt doc, section 3.4 */ 204 { TLU_UC_BIT_DESC(MFP, pciex_ue, pciex_rx_tx_ue) }, 205 { TLU_UC_BIT_DESC(PP, pciex_ue, pciex_rx_tx_ue) }, 206 207 /* Other PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 208 { TLU_UC_BIT_DESC(FCP, pciex_ue, pciex_ue) }, 209 { TLU_UC_BIT_DESC(DLP, pciex_ue, pciex_ue) }, 210 { TLU_UC_BIT_DESC(TE, pciex_ue, pciex_ue) }, 211 212 /* Not used */ 213 { TLU_UC_BIT_DESC(CA, pciex_ue, do_not) } 214 }; 215 #define px_err_tlu_ue_keys \ 216 (sizeof (px_err_tlu_ue_tbl)) / (sizeof (px_err_bit_desc_t)) 217 218 /* 219 * PEC CE errors implementation is incomplete pending PCIE generic 220 * fabric rules. 221 */ 222 /* pec ce errors */ 223 #define TLU_CE_BIT_DESC(bit, hdl, erpt) \ 224 TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _P, \ 225 0, \ 226 PX_ERR_BIT_HANDLE(hdl), \ 227 PX_ERPT_SEND(erpt), \ 228 PX_ERR_PEC_CLASS(bit) }, \ 229 { TLU_CORRECTABLE_ERROR_STATUS_CLEAR_ ## bit ## _S, \ 230 0, \ 231 PX_ERR_BIT_HANDLE(hdl), \ 232 PX_ERPT_SEND(erpt), \ 233 PX_ERR_PEC_CLASS(bit) 234 px_err_bit_desc_t px_err_tlu_ce_tbl[] = { 235 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 236 { TLU_CE_BIT_DESC(RTO, pciex_ce, pciex_ce) }, 237 { TLU_CE_BIT_DESC(RNR, pciex_ce, pciex_ce) }, 238 { TLU_CE_BIT_DESC(BDP, pciex_ce, pciex_ce) }, 239 { TLU_CE_BIT_DESC(BTP, pciex_ce, pciex_ce) }, 240 { TLU_CE_BIT_DESC(RE, pciex_ce, pciex_ce) } 241 }; 242 #define px_err_tlu_ce_keys \ 243 (sizeof (px_err_tlu_ce_tbl)) / (sizeof (px_err_bit_desc_t)) 244 245 /* pec oe errors */ 246 #define TLU_OE_BIT_DESC(bit, hdl, erpt) \ 247 TLU_OTHER_EVENT_STATUS_CLEAR_ ## bit ## _P, \ 248 0, \ 249 PX_ERR_BIT_HANDLE(hdl), \ 250 PX_ERPT_SEND(erpt), \ 251 PX_ERR_PEC_CLASS(bit) 252 px_err_bit_desc_t px_err_tlu_oe_tbl[] = { 253 /* 254 * TLU Other Event Status (receive only) - see io erpt doc, section 3.7 255 */ 256 { TLU_OE_BIT_DESC(MRC, fatal_hw, pciex_rx_oe) }, 257 258 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 259 { TLU_OE_BIT_DESC(WUC, non_fatal, pciex_rx_tx_oe) }, 260 { TLU_OE_BIT_DESC(RUC, non_fatal, pciex_rx_tx_oe) }, 261 { TLU_OE_BIT_DESC(CRS, non_fatal, pciex_rx_tx_oe) }, 262 263 /* TLU Other Event - see io erpt doc, section 3.9 */ 264 { TLU_OE_BIT_DESC(IIP, fatal_gos, pciex_oe) }, 265 { TLU_OE_BIT_DESC(EDP, fatal_gos, pciex_oe) }, 266 { TLU_OE_BIT_DESC(EHP, fatal_gos, pciex_oe) }, 267 { TLU_OE_BIT_DESC(LIN, non_fatal, pciex_oe) }, 268 { TLU_OE_BIT_DESC(LRS, non_fatal, pciex_oe) }, 269 { TLU_OE_BIT_DESC(LDN, non_fatal, pciex_ldn) }, 270 { TLU_OE_BIT_DESC(LUP, tlu_lup, pciex_lup) }, 271 { TLU_OE_BIT_DESC(ERU, fatal_gos, pciex_oe) }, 272 { TLU_OE_BIT_DESC(ERO, fatal_gos, pciex_oe) }, 273 { TLU_OE_BIT_DESC(EMP, fatal_gos, pciex_oe) }, 274 { TLU_OE_BIT_DESC(EPE, fatal_gos, pciex_oe) }, 275 { TLU_OE_BIT_DESC(ERP, fatal_gos, pciex_oe) }, 276 { TLU_OE_BIT_DESC(EIP, fatal_gos, pciex_oe) } 277 }; 278 279 #define px_err_tlu_oe_keys \ 280 (sizeof (px_err_tlu_oe_tbl)) / (sizeof (px_err_bit_desc_t)) 281 282 /* 283 * All the following tables below are for LPU Interrupts. These interrupts 284 * are *NOT* error interrupts, but event status interrupts. 285 * 286 * These events are probably of most interest to: 287 * o Hotplug 288 * o Power Management 289 * o etc... 290 * 291 * There are also a few events that would be interresting for FMA. 292 * Again none of the regiseters below state that an error has occured 293 * or that data has been lost. If anything, they give status that an 294 * error is *about* to occur. examples 295 * o INT_SKP_ERR - indicates clock between fire and child is too far 296 * off and is most unlikely able to compensate 297 * o INT_TX_PAR_ERR - A parity error occured in ONE lane. This is 298 * HW recoverable, but will like end up as a future 299 * fabric error as well. 300 * 301 * For now, we don't care about any of these errors and should be ignore, 302 * but cleared. 303 */ 304 305 /* LPU Link Interrupt Table */ 306 #define LPUL_BIT_DESC(bit, hdl, erpt) \ 307 LPU_LINK_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 308 0, \ 309 NULL, \ 310 NULL, \ 311 "" 312 px_err_bit_desc_t px_err_lpul_tbl[] = { 313 { LPUL_BIT_DESC(LINK_ERR_ACT, NULL, NULL) } 314 }; 315 #define px_err_lpul_keys \ 316 (sizeof (px_err_lpul_tbl)) / (sizeof (px_err_bit_desc_t)) 317 318 /* LPU Physical Interrupt Table */ 319 #define LPUP_BIT_DESC(bit, hdl, erpt) \ 320 LPU_PHY_LAYER_INTERRUPT_AND_STATUS_INT_ ## bit, \ 321 0, \ 322 NULL, \ 323 NULL, \ 324 "" 325 px_err_bit_desc_t px_err_lpup_tbl[] = { 326 { LPUP_BIT_DESC(PHY_LAYER_ERR, NULL, NULL) } 327 }; 328 #define px_err_lpup_keys \ 329 (sizeof (px_err_lpup_tbl)) / (sizeof (px_err_bit_desc_t)) 330 331 /* LPU Receive Interrupt Table */ 332 #define LPUR_BIT_DESC(bit, hdl, erpt) \ 333 LPU_RECEIVE_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 334 0, \ 335 NULL, \ 336 NULL, \ 337 "" 338 px_err_bit_desc_t px_err_lpur_tbl[] = { 339 { LPUR_BIT_DESC(RCV_PHY, NULL, NULL) } 340 }; 341 #define px_err_lpur_keys \ 342 (sizeof (px_err_lpur_tbl)) / (sizeof (px_err_bit_desc_t)) 343 344 /* LPU Transmit Interrupt Table */ 345 #define LPUX_BIT_DESC(bit, hdl, erpt) \ 346 LPU_TRANSMIT_PHY_INTERRUPT_AND_STATUS_INT_ ## bit, \ 347 0, \ 348 NULL, \ 349 NULL, \ 350 "" 351 px_err_bit_desc_t px_err_lpux_tbl[] = { 352 { LPUX_BIT_DESC(UNMSK, NULL, NULL) } 353 }; 354 #define px_err_lpux_keys \ 355 (sizeof (px_err_lpux_tbl)) / (sizeof (px_err_bit_desc_t)) 356 357 /* LPU LTSSM Interrupt Table */ 358 #define LPUS_BIT_DESC(bit, hdl, erpt) \ 359 LPU_LTSSM_INTERRUPT_AND_STATUS_INT_ ## bit, \ 360 0, \ 361 NULL, \ 362 NULL, \ 363 "" 364 px_err_bit_desc_t px_err_lpus_tbl[] = { 365 { LPUS_BIT_DESC(ANY, NULL, NULL) } 366 }; 367 #define px_err_lpus_keys \ 368 (sizeof (px_err_lpus_tbl)) / (sizeof (px_err_bit_desc_t)) 369 370 /* LPU Gigablaze Glue Interrupt Table */ 371 #define LPUG_BIT_DESC(bit, hdl, erpt) \ 372 LPU_GIGABLAZE_GLUE_INTERRUPT_AND_STATUS_INT_ ## bit, \ 373 0, \ 374 NULL, \ 375 NULL, \ 376 "" 377 px_err_bit_desc_t px_err_lpug_tbl[] = { 378 { LPUG_BIT_DESC(GLOBL_UNMSK, NULL, NULL) } 379 }; 380 #define px_err_lpug_keys \ 381 (sizeof (px_err_lpug_tbl)) / (sizeof (px_err_bit_desc_t)) 382 383 384 /* Mask and Tables */ 385 #define MnT6(pre) \ 386 B_FALSE, \ 387 &px_ ## pre ## _intr_mask, \ 388 &px_ ## pre ## _log_mask, \ 389 &px_ ## pre ## _count_mask, \ 390 px_err_ ## pre ## _tbl, \ 391 px_err_ ## pre ## _keys, \ 392 0 393 394 /* LPU Registers Addresses */ 395 #define LR4(pre) \ 396 NULL, \ 397 LPU_ ## pre ## _INTERRUPT_MASK, \ 398 LPU_ ## pre ## _INTERRUPT_AND_STATUS, \ 399 LPU_ ## pre ## _INTERRUPT_AND_STATUS 400 401 /* LPU Registers Addresses with Irregularities */ 402 #define LR4_FIXME(pre) \ 403 NULL, \ 404 LPU_ ## pre ## _INTERRUPT_MASK, \ 405 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS, \ 406 LPU_ ## pre ## _LAYER_INTERRUPT_AND_STATUS 407 408 /* TLU Registers Addresses */ 409 #define TR4(pre) \ 410 TLU_ ## pre ## _LOG_ENABLE, \ 411 TLU_ ## pre ## _INTERRUPT_ENABLE, \ 412 TLU_ ## pre ## _INTERRUPT_STATUS, \ 413 TLU_ ## pre ## _STATUS_CLEAR 414 415 /* Registers Addresses for JBC, MMU, IMU and ILU */ 416 #define R4(pre) \ 417 pre ## _ERROR_LOG_ENABLE, \ 418 pre ## _INTERRUPT_ENABLE, \ 419 pre ## _INTERRUPT_STATUS, \ 420 pre ## _ERROR_STATUS_CLEAR 421 422 /* 423 * Register error handling tables. 424 * The ID Field (first field) is identified by an enum px_err_id_t. 425 * It is located in px_err.h 426 */ 427 px_err_reg_desc_t px_err_reg_tbl[] = { 428 { MnT6(cb), R4(JBC), "JBC Error"}, 429 { MnT6(mmu), R4(MMU), "MMU Error"}, 430 { MnT6(imu), R4(IMU), "IMU Error"}, 431 { MnT6(tlu_ue), TR4(UNCORRECTABLE_ERROR), "TLU UE"}, 432 { MnT6(tlu_ce), TR4(CORRECTABLE_ERROR), "TLU CE"}, 433 { MnT6(tlu_oe), TR4(OTHER_EVENT), "TLU OE"}, 434 { MnT6(ilu), R4(ILU), "ILU Error"}, 435 { MnT6(lpul), LR4(LINK_LAYER), "LPU Link Layer"}, 436 { MnT6(lpup), LR4_FIXME(PHY), "LPU Phy Layer"}, 437 { MnT6(lpur), LR4(RECEIVE_PHY), "LPU RX Phy Layer"}, 438 { MnT6(lpux), LR4(TRANSMIT_PHY), "LPU TX Phy Layer"}, 439 { MnT6(lpus), LR4(LTSSM), "LPU LTSSM"}, 440 { MnT6(lpug), LR4(GIGABLAZE_GLUE), "LPU GigaBlaze Glue"} 441 }; 442 #define PX_ERR_REG_KEYS (sizeof (px_err_reg_tbl)) / (sizeof (px_err_reg_tbl[0])) 443 444 typedef struct px_err_ss { 445 uint64_t err_status[PX_ERR_REG_KEYS]; 446 } px_err_ss_t; 447 448 static void px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chkjbc); 449 static int px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, 450 px_err_ss_t *ss); 451 static int px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, 452 int err, int caller); 453 454 /* 455 * px_err_cb_intr: 456 * Interrupt handler for the JBC block. 457 * o lock 458 * o create derr 459 * o px_err_handle(leaf1, with jbc) 460 * o px_err_handle(leaf2, without jbc) 461 * o dispatch (leaf1) 462 * o dispatch (leaf2) 463 * o unlock 464 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 465 */ 466 uint_t 467 px_err_cb_intr(caddr_t arg) 468 { 469 px_fault_t *px_fault_p = (px_fault_t *)arg; 470 dev_info_t *rpdip = px_fault_p->px_fh_dip; 471 dev_info_t *leafdip; 472 px_t *px_p = DIP_TO_STATE(rpdip); 473 px_cb_t *cb_p = px_p->px_cb_p; 474 int err = PX_OK; 475 int ret = DDI_FM_OK; 476 int fatal = 0; 477 int nonfatal = 0; 478 int unknown = 0; 479 int i; 480 boolean_t chkjbc = B_TRUE; 481 ddi_fm_error_t derr; 482 483 /* Create the derr */ 484 bzero(&derr, sizeof (ddi_fm_error_t)); 485 derr.fme_version = DDI_FME_VERSION; 486 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 487 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 488 489 mutex_enter(&cb_p->xbc_fm_mutex); 490 491 /* send ereport/handle/clear for ALL fire leaves */ 492 for (i = 0; i < PX_CB_MAX_LEAF; i++) { 493 if ((px_p = cb_p->xbc_px_list[i]) == NULL) 494 continue; 495 496 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, chkjbc); 497 chkjbc = B_FALSE; 498 } 499 500 /* Check all child devices for errors on ALL fire leaves */ 501 for (i = 0; i < PX_CB_MAX_LEAF; i++) { 502 if ((px_p = cb_p->xbc_px_list[i]) != NULL) { 503 leafdip = px_p->px_dip; 504 ret = ndi_fm_handler_dispatch(leafdip, NULL, &derr); 505 switch (ret) { 506 case DDI_FM_FATAL: 507 fatal++; 508 break; 509 case DDI_FM_NONFATAL: 510 nonfatal++; 511 break; 512 case DDI_FM_UNKNOWN: 513 unknown++; 514 break; 515 default: 516 break; 517 } 518 } 519 } 520 521 /* Set the intr state to idle for the leaf that received the mondo */ 522 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 523 INTR_IDLE_STATE); 524 525 mutex_exit(&cb_p->xbc_fm_mutex); 526 527 /* 528 * PX_FATAL_HW error is diagnosed after system recovered from 529 * HW initiated reset, therefore no furthur handling is required. 530 */ 531 if (fatal || err & (PX_FATAL_GOS | PX_FATAL_SW)) 532 PX_FM_PANIC("Fatal System Bus Error has occurred\n"); 533 534 return (DDI_INTR_CLAIMED); 535 } 536 537 /* 538 * px_err_dmc_pec_intr: 539 * Interrupt handler for the DMC/PEC block. 540 * o lock 541 * o create derr 542 * o px_err_handle(leaf, with jbc) 543 * o dispatch (leaf) 544 * o unlock 545 * o handle error: fatal? fm_panic() : return INTR_CLAIMED) 546 */ 547 uint_t 548 px_err_dmc_pec_intr(caddr_t arg) 549 { 550 px_fault_t *px_fault_p = (px_fault_t *)arg; 551 dev_info_t *rpdip = px_fault_p->px_fh_dip; 552 px_t *px_p = DIP_TO_STATE(rpdip); 553 px_cb_t *cb_p = px_p->px_cb_p; 554 int err = PX_OK; 555 int ret = DDI_FM_OK; 556 ddi_fm_error_t derr; 557 558 /* Create the derr */ 559 bzero(&derr, sizeof (ddi_fm_error_t)); 560 derr.fme_version = DDI_FME_VERSION; 561 derr.fme_ena = fm_ena_generate(0, FM_ENA_FMT1); 562 derr.fme_flag = DDI_FM_ERR_UNEXPECTED; 563 564 mutex_enter(&cb_p->xbc_fm_mutex); 565 566 /* send ereport/handle/clear fire registers */ 567 err |= px_err_handle(px_p, &derr, PX_INTR_CALL, B_TRUE); 568 569 /* Check all child devices for errors */ 570 ret = ndi_fm_handler_dispatch(rpdip, NULL, &derr); 571 572 /* Set the interrupt state to idle */ 573 (void) px_lib_intr_setstate(rpdip, px_fault_p->px_fh_sysino, 574 INTR_IDLE_STATE); 575 576 mutex_exit(&cb_p->xbc_fm_mutex); 577 578 /* 579 * PX_FATAL_HW indicates a condition recovered from Fatal-Reset, 580 * therefore it does not cause panic. 581 */ 582 if ((err & (PX_FATAL_GOS | PX_FATAL_SW)) || (ret == DDI_FM_FATAL)) 583 PX_FM_PANIC("Fatal System Port Error has occurred\n"); 584 585 return (DDI_INTR_CLAIMED); 586 } 587 588 /* 589 * Error register are being handled by px_hlib xxx_init functions. 590 * They are also called again by px_err_add_intr for mondo62 and 63 591 * from px_cb_attach and px_attach 592 */ 593 void 594 px_err_reg_enable(px_t *px_p, px_err_id_t id) 595 { 596 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 597 uint64_t intr_mask = *reg_desc->intr_mask_p; 598 uint64_t log_mask = *reg_desc->log_mask_p; 599 caddr_t csr_base; 600 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 601 602 if (id == PX_ERR_JBC) 603 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 604 else 605 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 606 607 reg_desc->enabled = B_TRUE; 608 609 /* Enable logs if it exists */ 610 if (reg_desc->log_addr != NULL) 611 CSR_XS(csr_base, reg_desc->log_addr, log_mask); 612 613 /* 614 * For readability you in code you set 1 to enable an interrupt. 615 * But in Fire it's backwards. You set 1 to *disable* an intr. 616 * Reverse the user tunable intr mask field. 617 * 618 * Disable All Errors 619 * Clear All Errors 620 * Enable Errors 621 */ 622 CSR_XS(csr_base, reg_desc->enable_addr, 0); 623 CSR_XS(csr_base, reg_desc->clear_addr, -1); 624 CSR_XS(csr_base, reg_desc->enable_addr, intr_mask); 625 DBG(DBG_ATTACH, NULL, "%s Mask: 0x%llx\n", 626 reg_desc->msg, CSR_XR(csr_base, reg_desc->enable_addr)); 627 DBG(DBG_ATTACH, NULL, "%s Status: 0x%llx\n", 628 reg_desc->msg, CSR_XR(csr_base, reg_desc->status_addr)); 629 DBG(DBG_ATTACH, NULL, "%s Clear: 0x%llx\n", 630 reg_desc->msg, CSR_XR(csr_base, reg_desc->clear_addr)); 631 if (reg_desc->log_addr != NULL) { 632 DBG(DBG_ATTACH, NULL, "%s Log: 0x%llx\n", 633 reg_desc->msg, CSR_XR(csr_base, reg_desc->log_addr)); 634 } 635 } 636 637 void 638 px_err_reg_disable(px_t *px_p, px_err_id_t id) 639 { 640 px_err_reg_desc_t *reg_desc = &px_err_reg_tbl[id]; 641 caddr_t csr_base; 642 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 643 644 if (id == PX_ERR_JBC) 645 csr_base = (caddr_t)(uintptr_t)pxu_p->px_address[PX_REG_XBC]; 646 else 647 csr_base = (caddr_t)(uintptr_t)pxu_p->px_address[PX_REG_CSR]; 648 649 reg_desc->enabled = B_FALSE; 650 651 switch (id) { 652 case PX_ERR_JBC: 653 case PX_ERR_MMU: 654 case PX_ERR_IMU: 655 case PX_ERR_TLU_UE: 656 case PX_ERR_TLU_CE: 657 case PX_ERR_TLU_OE: 658 case PX_ERR_ILU: 659 if (reg_desc->log_addr != NULL) { 660 CSR_XS(csr_base, reg_desc->log_addr, 0); 661 } 662 CSR_XS(csr_base, reg_desc->enable_addr, 0); 663 break; 664 case PX_ERR_LPU_LINK: 665 case PX_ERR_LPU_PHY: 666 case PX_ERR_LPU_RX: 667 case PX_ERR_LPU_TX: 668 case PX_ERR_LPU_LTSSM: 669 case PX_ERR_LPU_GIGABLZ: 670 if (reg_desc->log_addr != NULL) { 671 CSR_XS(csr_base, reg_desc->log_addr, -1); 672 } 673 CSR_XS(csr_base, reg_desc->enable_addr, -1); 674 break; 675 } 676 } 677 678 /* 679 * px_err_handle: 680 * Common function called by trap, mondo and fabric intr. 681 * o Snap shot current fire registers 682 * o check for safe access 683 * o send ereport and clear snap shot registers 684 * o check severity of snap shot registers 685 * 686 * @param px_p leaf in which to check access 687 * @param derr fm err data structure to be updated 688 * @param caller PX_TRAP_CALL | PX_INTR_CALL 689 * @param chkjbc whether to handle jbc registers 690 * @return err PX_OK | PX_NONFATAL | 691 * PX_FATAL_GOS | PX_FATAL_HW | PX_STUCK_FATAL 692 */ 693 int 694 px_err_handle(px_t *px_p, ddi_fm_error_t *derr, int caller, 695 boolean_t chkjbc) 696 { 697 px_cb_t *cb_p = px_p->px_cb_p; /* for fm_mutex */ 698 px_err_ss_t ss; 699 int err = PX_OK; 700 701 ASSERT(MUTEX_HELD(&cb_p->xbc_fm_mutex)); 702 703 /* snap shot the current fire registers */ 704 px_err_snapshot(px_p, &ss, chkjbc); 705 706 /* check for safe access */ 707 px_err_safeacc_check(px_p, derr); 708 709 /* send ereports/handle/clear registers */ 710 err = px_err_erpt_and_clr(px_p, derr, &ss); 711 712 /* check for error severity */ 713 err = px_err_check_severity(px_p, derr, err, caller); 714 715 /* Mark the On Trap Handle if an error occured */ 716 if (err != PX_OK) { 717 px_pec_t *pec_p = px_p->px_pec_p; 718 on_trap_data_t *otd = pec_p->pec_ontrap_data; 719 720 if ((otd != NULL) && (otd->ot_prot & OT_DATA_ACCESS)) 721 otd->ot_trap |= OT_DATA_ACCESS; 722 } 723 724 return (err); 725 } 726 727 /* 728 * Static function 729 */ 730 731 /* 732 * px_err_snapshot: 733 * Take a current snap shot of all the fire error registers. This includes 734 * JBC, DMC, and PEC, unless chkjbc == false; 735 * 736 * @param px_p leaf in which to take the snap shot. 737 * @param ss pre-allocated memory to store the snap shot. 738 * @param chkjbc boolean on whether to store jbc register. 739 */ 740 static void 741 px_err_snapshot(px_t *px_p, px_err_ss_t *ss, boolean_t chkjbc) 742 { 743 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 744 caddr_t xbc_csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 745 caddr_t pec_csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 746 px_err_reg_desc_t *reg_desc; 747 int reg_id; 748 749 /* snapshot JBC interrupt status */ 750 reg_id = PX_ERR_JBC; 751 if (chkjbc == B_TRUE) { 752 reg_desc = &px_err_reg_tbl[reg_id]; 753 ss->err_status[reg_id] = CSR_XR(xbc_csr_base, 754 reg_desc->status_addr); 755 } else { 756 ss->err_status[reg_id] = 0; 757 } 758 759 /* snapshot DMC/PEC interrupt status */ 760 for (reg_id = 1; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 761 reg_desc = &px_err_reg_tbl[reg_id]; 762 ss->err_status[reg_id] = CSR_XR(pec_csr_base, 763 reg_desc->status_addr); 764 } 765 } 766 767 /* 768 * px_err_erpt_and_clr: 769 * This function does the following thing to all the fire registers based 770 * on an earlier snap shot. 771 * o Send ereport 772 * o Handle the error 773 * o Clear the error 774 * 775 * @param px_p leaf in which to take the snap shot. 776 * @param derr fm err in which the ereport is to be based on 777 * @param ss pre-allocated memory to store the snap shot. 778 */ 779 static int 780 px_err_erpt_and_clr(px_t *px_p, ddi_fm_error_t *derr, px_err_ss_t *ss) 781 { 782 dev_info_t *rpdip = px_p->px_dip; 783 px_cb_t *cb_p = px_p->px_cb_p; /* for fm_mutex */ 784 pxu_t *pxu_p = (pxu_t *)px_p->px_plat_p; 785 caddr_t csr_base; 786 px_err_reg_desc_t *err_reg_tbl; 787 px_err_bit_desc_t *err_bit_tbl; 788 px_err_bit_desc_t *err_bit_desc; 789 790 uint64_t *log_mask, *count_mask; 791 uint64_t status_addr, clear_addr; 792 uint64_t ss_reg; 793 794 int (*err_handler)(); 795 int (*erpt_handler)(); 796 int reg_id, key; 797 int err = PX_OK; 798 799 ASSERT(MUTEX_HELD(&cb_p->xbc_fm_mutex)); 800 801 /* send erport/handle/clear JBC errors */ 802 for (reg_id = 0; reg_id < PX_ERR_REG_KEYS; reg_id += 1) { 803 /* Get the correct register description table */ 804 err_reg_tbl = &px_err_reg_tbl[reg_id]; 805 806 /* Get the correct CSR BASE */ 807 if (reg_id == PX_ERR_JBC) { 808 csr_base = (caddr_t)pxu_p->px_address[PX_REG_XBC]; 809 } else { 810 csr_base = (caddr_t)pxu_p->px_address[PX_REG_CSR]; 811 } 812 813 /* Get pointers to masks and register addresses */ 814 log_mask = err_reg_tbl->log_mask_p; 815 count_mask = err_reg_tbl->count_mask_p; 816 status_addr = err_reg_tbl->status_addr; 817 clear_addr = err_reg_tbl->clear_addr; 818 ss_reg = ss->err_status[reg_id]; 819 820 /* Get the register BIT description table */ 821 err_bit_tbl = err_reg_tbl->err_bit_tbl; 822 823 /* For each known bit in the register send erpt and handle */ 824 for (key = 0; key < err_reg_tbl->err_bit_keys; key += 1) { 825 /* Get the bit description table for this register */ 826 err_bit_desc = &err_bit_tbl[key]; 827 828 /* 829 * If the ss_reg is set for this bit, 830 * send ereport and handle 831 */ 832 if (BIT_TST(ss_reg, err_bit_desc->bit)) { 833 /* Increment the counter if necessary */ 834 if (BIT_TST(*count_mask, err_bit_desc->bit)) { 835 err_bit_desc->counter++; 836 } 837 838 /* Error Handle for this bit */ 839 err_handler = err_bit_desc->err_handler; 840 if (err_handler) 841 err |= err_handler(rpdip, 842 csr_base, 843 derr, 844 err_reg_tbl, 845 err_bit_desc); 846 847 /* Send the ereport if it's an UNEXPECTED err */ 848 erpt_handler = err_bit_desc->erpt_handler; 849 if (derr->fme_flag == DDI_FM_ERR_UNEXPECTED) { 850 if (erpt_handler) 851 (void) erpt_handler(rpdip, 852 csr_base, 853 ss_reg, 854 derr, 855 err_bit_desc->class_name); 856 } 857 } 858 859 } 860 861 /* Print register status */ 862 if (ss_reg & *log_mask) 863 DBG(DBG_ERR_INTR, rpdip, "<%x>=%16llx %s\n", 864 status_addr, ss_reg, err_reg_tbl->msg); 865 866 /* Clear the register and error */ 867 CSR_XS(csr_base, clear_addr, ss_reg); 868 } 869 870 return (err); 871 } 872 873 /* 874 * px_err_check_severity: 875 * Check the severity of the fire error based on an earlier snapshot 876 * 877 * @param px_p leaf in which to take the snap shot. 878 * @param derr fm err in which the ereport is to be based on 879 * @param ss pre-allocated memory to store the snap shot. 880 */ 881 static int 882 px_err_check_severity(px_t *px_p, ddi_fm_error_t *derr, int err, int caller) 883 { 884 px_pec_t *pec_p = px_p->px_pec_p; 885 boolean_t is_safeacc = B_FALSE; 886 887 /* nothing to do if called with no error */ 888 if (err == PX_OK) 889 return (err); 890 891 /* Cautious access error handling */ 892 switch (derr->fme_flag) { 893 case DDI_FM_ERR_EXPECTED: 894 if (caller == PX_TRAP_CALL) { 895 /* 896 * for ddi_caut_get treat all events as nonfatal 897 * The trampoline will set err_ena = 0, 898 * err_status = NONFATAL. 899 */ 900 derr->fme_status = DDI_FM_NONFATAL; 901 is_safeacc = B_TRUE; 902 } else { 903 /* 904 * For ddi_caut_put treat all events as nonfatal. Here 905 * we have the handle and can call ndi_fm_acc_err_set(). 906 */ 907 derr->fme_status = DDI_FM_NONFATAL; 908 ndi_fm_acc_err_set(pec_p->pec_acc_hdl, derr); 909 is_safeacc = B_TRUE; 910 } 911 break; 912 case DDI_FM_ERR_PEEK: 913 case DDI_FM_ERR_POKE: 914 /* 915 * For ddi_peek/poke treat all events as nonfatal. 916 */ 917 is_safeacc = B_TRUE; 918 break; 919 default: 920 is_safeacc = B_FALSE; 921 } 922 923 /* 924 * The third argument "err" is passed in as error status from checking 925 * Fire register, re-adjust error status from safe access. 926 */ 927 if (is_safeacc && !(err & PX_FATAL_GOS)) 928 return (PX_NONFATAL); 929 930 return (err); 931 } 932 933 /* predefined convenience functions */ 934 /* ARGSUSED */ 935 int 936 px_err_fatal_hw_handle(dev_info_t *rpdip, caddr_t csr_base, 937 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 938 px_err_bit_desc_t *err_bit_descr) 939 { 940 return (PX_FATAL_HW); 941 } 942 943 /* ARGSUSED */ 944 int 945 px_err_fatal_gos_handle(dev_info_t *rpdip, caddr_t csr_base, 946 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 947 px_err_bit_desc_t *err_bit_descr) 948 { 949 return (PX_FATAL_GOS); 950 } 951 952 /* ARGSUSED */ 953 int 954 px_err_fatal_stuck_handle(dev_info_t *rpdip, caddr_t csr_base, 955 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 956 px_err_bit_desc_t *err_bit_descr) 957 { 958 return (PX_STUCK_FATAL); 959 } 960 961 /* ARGSUSED */ 962 int 963 px_err_fatal_sw_handle(dev_info_t *rpdip, caddr_t csr_base, 964 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 965 px_err_bit_desc_t *err_bit_descr) 966 { 967 return (PX_FATAL_SW); 968 } 969 970 /* ARGSUSED */ 971 int 972 px_err_non_fatal_handle(dev_info_t *rpdip, caddr_t csr_base, 973 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 974 px_err_bit_desc_t *err_bit_descr) 975 { 976 return (PX_NONFATAL); 977 } 978 979 /* ARGSUSED */ 980 int 981 px_err_ok_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 982 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 983 { 984 return (PX_OK); 985 } 986 987 /* ARGSUSED */ 988 int 989 px_err_unknown_handle(dev_info_t *rpdip, caddr_t csr_base, ddi_fm_error_t *derr, 990 px_err_reg_desc_t *err_reg_descr, px_err_bit_desc_t *err_bit_descr) 991 { 992 return (PX_ERR_UNKNOWN); 993 } 994 995 /* ARGSUSED */ 996 PX_ERPT_SEND_DEC(do_not) 997 { 998 return (PX_OK); 999 } 1000 1001 1002 /* JBC FATAL - see io erpt doc, section 1.1 */ 1003 PX_ERPT_SEND_DEC(jbc_fatal) 1004 { 1005 char buf[FM_MAX_CLASS]; 1006 1007 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1008 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1009 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1010 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1011 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1012 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1013 FIRE_JBC_IE, DATA_TYPE_UINT64, 1014 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1015 FIRE_JBC_IS, DATA_TYPE_UINT64, 1016 ss_reg, 1017 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1018 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1019 FIRE_JBC_FEL1, DATA_TYPE_UINT64, 1020 CSR_XR(csr_base, FATAL_ERROR_LOG_1), 1021 FIRE_JBC_FEL2, DATA_TYPE_UINT64, 1022 CSR_XR(csr_base, FATAL_ERROR_LOG_2), 1023 NULL); 1024 1025 return (PX_OK); 1026 } 1027 1028 /* JBC MERGE - see io erpt doc, section 1.2 */ 1029 PX_ERPT_SEND_DEC(jbc_merge) 1030 { 1031 char buf[FM_MAX_CLASS]; 1032 1033 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1034 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1035 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1036 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1037 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1038 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1039 FIRE_JBC_IE, DATA_TYPE_UINT64, 1040 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1041 FIRE_JBC_IS, DATA_TYPE_UINT64, 1042 ss_reg, 1043 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1044 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1045 FIRE_JBC_MTEL, DATA_TYPE_UINT64, 1046 CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG), 1047 NULL); 1048 1049 return (PX_OK); 1050 } 1051 1052 /* 1053 * JBC Merge buffer nonfatal errors: 1054 * Merge buffer parity error (rd_buf): dma:read:M:nonfatal 1055 * Merge buffer parity error (wr_buf): dma:write:M:nonfatal 1056 */ 1057 /* ARGSUSED */ 1058 int 1059 px_err_jbc_merge_handle(dev_info_t *rpdip, caddr_t csr_base, 1060 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1061 px_err_bit_desc_t *err_bit_descr) 1062 { 1063 uint64_t paddr; 1064 int ret; 1065 1066 paddr = CSR_XR(csr_base, MERGE_TRANSACTION_ERROR_LOG); 1067 paddr &= MERGE_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1068 1069 ret = px_handle_lookup( 1070 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1071 1072 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1073 } 1074 1075 /* JBC Jbusint IN - see io erpt doc, section 1.3 */ 1076 PX_ERPT_SEND_DEC(jbc_in) 1077 { 1078 char buf[FM_MAX_CLASS]; 1079 1080 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1081 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1082 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1083 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1084 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1085 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1086 FIRE_JBC_IE, DATA_TYPE_UINT64, 1087 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1088 FIRE_JBC_IS, DATA_TYPE_UINT64, 1089 ss_reg, 1090 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1091 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1092 FIRE_JBC_JITEL1, DATA_TYPE_UINT64, 1093 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG), 1094 FIRE_JBC_JITEL2, DATA_TYPE_UINT64, 1095 CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG_2), 1096 NULL); 1097 1098 return (PX_OK); 1099 } 1100 1101 /* 1102 * JBC Jbusint IN nonfatal errors: PA logged in Jbusint In Transaction Error 1103 * Log Reg[42:0]. 1104 * CE async fault error: nonfatal 1105 * Jbus bus error: dma::nonfatal 1106 * Jbus unmapped error: pio|dma:rdwr:M:nonfatal 1107 * Write data parity error: pio/write:M:nonfatal 1108 * Read data parity error: pio/read:M:nonfatal 1109 * Illegal NCWR bytemask: pio:write:M:nonfatal 1110 * Illegal NCRD bytemask: pio:write:M:nonfatal 1111 * Invalid jbus transaction: nonfatal 1112 */ 1113 /* ARGSUSED */ 1114 int 1115 px_err_jbc_jbusint_in_handle(dev_info_t *rpdip, caddr_t csr_base, 1116 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1117 px_err_bit_desc_t *err_bit_descr) 1118 { 1119 uint64_t paddr; 1120 int ret; 1121 1122 paddr = CSR_XR(csr_base, JBCINT_IN_TRANSACTION_ERROR_LOG); 1123 paddr &= JBCINT_IN_TRANSACTION_ERROR_LOG_ADDRESS_MASK; 1124 1125 ret = px_handle_lookup( 1126 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1127 1128 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1129 } 1130 1131 1132 /* JBC Jbusint Out - see io erpt doc, section 1.4 */ 1133 PX_ERPT_SEND_DEC(jbc_out) 1134 { 1135 char buf[FM_MAX_CLASS]; 1136 1137 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1138 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1139 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1140 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1141 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1142 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1143 FIRE_JBC_IE, DATA_TYPE_UINT64, 1144 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1145 FIRE_JBC_IS, DATA_TYPE_UINT64, 1146 ss_reg, 1147 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1148 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1149 FIRE_JBC_JOTEL1, DATA_TYPE_UINT64, 1150 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG), 1151 FIRE_JBC_JOTEL2, DATA_TYPE_UINT64, 1152 CSR_XR(csr_base, JBCINT_OUT_TRANSACTION_ERROR_LOG_2), 1153 NULL); 1154 1155 return (PX_OK); 1156 } 1157 1158 /* JBC Dmcint ODCD - see io erpt doc, section 1.5 */ 1159 PX_ERPT_SEND_DEC(jbc_odcd) 1160 { 1161 char buf[FM_MAX_CLASS]; 1162 1163 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1164 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1165 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1166 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1167 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1168 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1169 FIRE_JBC_IE, DATA_TYPE_UINT64, 1170 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1171 FIRE_JBC_IS, DATA_TYPE_UINT64, 1172 ss_reg, 1173 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1174 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1175 FIRE_JBC_DMC_ODCD, DATA_TYPE_UINT64, 1176 CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG), 1177 NULL); 1178 1179 return (PX_OK); 1180 } 1181 1182 /* 1183 * JBC Dmcint ODCO nonfatal errer handling - 1184 * Unmapped PIO read error: pio:read:M:nonfatal 1185 * Unmapped PIO write error: pio:write:M:nonfatal 1186 * PIO data parity error: pio:write:M:nonfatal 1187 * Invalid PIO write to PCIe cfg/io, csr, ebus or i2c bus: pio:write:nonfatal 1188 * Invalid PIO read to PCIe cfg/io, csr, ebus or i2c bus: pio:read:nonfatal 1189 */ 1190 /* ARGSUSED */ 1191 int 1192 px_err_jbc_dmcint_odcd_handle(dev_info_t *rpdip, caddr_t csr_base, 1193 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1194 px_err_bit_desc_t *err_bit_descr) 1195 { 1196 uint64_t paddr; 1197 int ret; 1198 1199 paddr = CSR_XR(csr_base, DMCINT_ODCD_ERROR_LOG); 1200 paddr &= DMCINT_ODCD_ERROR_LOG_ADDRESS_MASK; 1201 1202 ret = px_handle_lookup( 1203 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1204 1205 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1206 } 1207 1208 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1209 PX_ERPT_SEND_DEC(jbc_idc) 1210 { 1211 char buf[FM_MAX_CLASS]; 1212 1213 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1214 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1215 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1216 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1217 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1218 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1219 FIRE_JBC_IE, DATA_TYPE_UINT64, 1220 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1221 FIRE_JBC_IS, DATA_TYPE_UINT64, 1222 ss_reg, 1223 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1224 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1225 FIRE_JBC_DMC_IDC, DATA_TYPE_UINT64, 1226 CSR_XR(csr_base, DMCINT_IDC_ERROR_LOG), 1227 NULL); 1228 1229 return (PX_OK); 1230 } 1231 1232 /* JBC CSR - see io erpt doc, section 1.7 */ 1233 PX_ERPT_SEND_DEC(jbc_csr) 1234 { 1235 char buf[FM_MAX_CLASS]; 1236 1237 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1238 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1239 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1240 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1241 FIRE_JBC_ELE, DATA_TYPE_UINT64, 1242 CSR_XR(csr_base, JBC_ERROR_LOG_ENABLE), 1243 FIRE_JBC_IE, DATA_TYPE_UINT64, 1244 CSR_XR(csr_base, JBC_INTERRUPT_ENABLE), 1245 FIRE_JBC_IS, DATA_TYPE_UINT64, 1246 ss_reg, 1247 FIRE_JBC_ESS, DATA_TYPE_UINT64, 1248 CSR_XR(csr_base, JBC_ERROR_STATUS_SET), 1249 "jbc-error-reg", DATA_TYPE_UINT64, 1250 CSR_XR(csr_base, CSR_ERROR_LOG), 1251 NULL); 1252 1253 return (PX_OK); 1254 } 1255 1256 /* 1257 * JBC CSR errer handling - 1258 * Ebus ready timeout error: pio:rdwr:M:nonfatal 1259 */ 1260 /* ARGSUSED */ 1261 int 1262 px_err_jbc_csr_handle(dev_info_t *rpdip, caddr_t csr_base, 1263 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1264 px_err_bit_desc_t *err_bit_descr) 1265 { 1266 uint64_t paddr; 1267 int ret; 1268 1269 paddr = CSR_XR(csr_base, CSR_ERROR_LOG); 1270 paddr &= CSR_ERROR_LOG_ADDRESS_MASK; 1271 1272 ret = px_handle_lookup( 1273 rpdip, DMA_HANDLE, derr->fme_ena, (void *)paddr); 1274 1275 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1276 } 1277 1278 /* JBC Dmcint IDC - see io erpt doc, section 1.6 */ 1279 1280 /* DMC IMU RDS - see io erpt doc, section 2.1 */ 1281 PX_ERPT_SEND_DEC(imu_rds) 1282 { 1283 char buf[FM_MAX_CLASS]; 1284 1285 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1286 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1287 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1288 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1289 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1290 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1291 FIRE_IMU_IE, DATA_TYPE_UINT64, 1292 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1293 FIRE_IMU_IS, DATA_TYPE_UINT64, 1294 ss_reg, 1295 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1296 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1297 FIRE_IMU_RDS, DATA_TYPE_UINT64, 1298 CSR_XR(csr_base, IMU_RDS_ERROR_LOG), 1299 NULL); 1300 1301 return (PX_OK); 1302 } 1303 1304 /* imu function to handle all Received but Not Enabled errors */ 1305 /* ARGSUSED */ 1306 int 1307 px_err_imu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1308 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1309 px_err_bit_desc_t *err_bit_descr) 1310 { 1311 uint64_t imu_log_enable, imu_intr_enable; 1312 int mask = BITMASK(err_bit_descr->bit); 1313 int err = PX_NONFATAL; 1314 1315 imu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1316 imu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1317 1318 /* 1319 * If matching bit is not set, meaning corresponding rbne not 1320 * enabled, then receiving it indicates some sort of malfunction 1321 * possibly in hardware. 1322 * 1323 * Other wise, software may have intentionally disabled certain 1324 * errors for a period of time within which the occuring of the 1325 * disabled errors become rbne, that is non fatal. 1326 */ 1327 if (!(imu_log_enable & imu_intr_enable & mask)) 1328 err = PX_FATAL_SW; 1329 1330 return (err); 1331 } 1332 1333 /* 1334 * No platforms uses PME. Any PME received is simply logged 1335 * for analysis. 1336 */ 1337 /* ARGSUSED */ 1338 int 1339 px_err_imu_pme_handle(dev_info_t *rpdip, caddr_t csr_base, 1340 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1341 px_err_bit_desc_t *err_bit_descr) 1342 { 1343 px_t *px_p = DIP_TO_STATE(rpdip); 1344 1345 px_p->px_pme_ignored++; 1346 return (PX_NONFATAL); 1347 } 1348 1349 /* handle EQ overflow */ 1350 /* ARGSUSED */ 1351 int 1352 px_err_imu_eq_ovfl_handle(dev_info_t *rpdip, caddr_t csr_base, 1353 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1354 px_err_bit_desc_t *err_bit_descr) 1355 { 1356 px_t *px_p = DIP_TO_STATE(rpdip); 1357 px_msiq_state_t *msiq_state_p = &px_p->px_ib_p->ib_msiq_state; 1358 msiqid_t eqno; 1359 pci_msiq_state_t msiq_state; 1360 int err = PX_NONFATAL; 1361 int i; 1362 1363 eqno = msiq_state_p->msiq_1st_msiq_id; 1364 for (i = 0; i < msiq_state_p->msiq_cnt; i++) { 1365 if (px_lib_msiq_getstate(rpdip, eqno, &msiq_state) == 1366 DDI_SUCCESS) { 1367 if (msiq_state == PCI_MSIQ_STATE_ERROR) { 1368 err = PX_FATAL_SW; 1369 } 1370 } 1371 } 1372 1373 return (err); 1374 } 1375 1376 /* DMC IMU SCS - see io erpt doc, section 2.2 */ 1377 PX_ERPT_SEND_DEC(imu_scs) 1378 { 1379 char buf[FM_MAX_CLASS]; 1380 1381 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1382 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1383 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1384 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1385 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1386 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1387 FIRE_IMU_IE, DATA_TYPE_UINT64, 1388 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1389 FIRE_IMU_IS, DATA_TYPE_UINT64, 1390 ss_reg, 1391 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1392 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1393 FIRE_IMU_SCS, DATA_TYPE_UINT64, 1394 CSR_XR(csr_base, IMU_SCS_ERROR_LOG), 1395 NULL); 1396 1397 return (PX_OK); 1398 } 1399 1400 /* DMC IMU - see io erpt doc, section 2.3 */ 1401 PX_ERPT_SEND_DEC(imu) 1402 { 1403 char buf[FM_MAX_CLASS]; 1404 1405 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1406 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1407 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1408 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1409 FIRE_IMU_ELE, DATA_TYPE_UINT64, 1410 CSR_XR(csr_base, IMU_ERROR_LOG_ENABLE), 1411 FIRE_IMU_IE, DATA_TYPE_UINT64, 1412 CSR_XR(csr_base, IMU_INTERRUPT_ENABLE), 1413 FIRE_IMU_IS, DATA_TYPE_UINT64, 1414 ss_reg, 1415 FIRE_IMU_ESS, DATA_TYPE_UINT64, 1416 CSR_XR(csr_base, IMU_ERROR_STATUS_SET), 1417 NULL); 1418 1419 return (PX_OK); 1420 } 1421 1422 /* DMC MMU TFAR/TFSR - see io erpt doc, section 2.4 */ 1423 PX_ERPT_SEND_DEC(mmu_tfar_tfsr) 1424 { 1425 char buf[FM_MAX_CLASS]; 1426 1427 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1428 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1429 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1430 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1431 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1432 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1433 FIRE_MMU_IE, DATA_TYPE_UINT64, 1434 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1435 FIRE_MMU_IS, DATA_TYPE_UINT64, 1436 ss_reg, 1437 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1438 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1439 FIRE_MMU_TFAR, DATA_TYPE_UINT64, 1440 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS), 1441 FIRE_MMU_TFSR, DATA_TYPE_UINT64, 1442 CSR_XR(csr_base, MMU_TRANSLATION_FAULT_STATUS), 1443 NULL); 1444 1445 return (PX_OK); 1446 } 1447 1448 /* DMC MMU - see io erpt doc, section 2.5 */ 1449 PX_ERPT_SEND_DEC(mmu) 1450 { 1451 char buf[FM_MAX_CLASS]; 1452 1453 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1454 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1455 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1456 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1457 FIRE_MMU_ELE, DATA_TYPE_UINT64, 1458 CSR_XR(csr_base, MMU_ERROR_LOG_ENABLE), 1459 FIRE_MMU_IE, DATA_TYPE_UINT64, 1460 CSR_XR(csr_base, MMU_INTERRUPT_ENABLE), 1461 FIRE_MMU_IS, DATA_TYPE_UINT64, 1462 ss_reg, 1463 FIRE_MMU_ESS, DATA_TYPE_UINT64, 1464 CSR_XR(csr_base, MMU_ERROR_STATUS_SET), 1465 NULL); 1466 1467 return (PX_OK); 1468 } 1469 1470 /* imu function to handle all Received but Not Enabled errors */ 1471 int 1472 px_err_mmu_rbne_handle(dev_info_t *rpdip, caddr_t csr_base, 1473 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1474 px_err_bit_desc_t *err_bit_descr) 1475 { 1476 uint64_t mmu_log_enable, mmu_intr_enable; 1477 uint64_t mask = BITMASK(err_bit_descr->bit); 1478 uint64_t mmu_tfa, mmu_ctrl; 1479 uint64_t mmu_enable_bit = 0; 1480 int err = PX_NONFATAL; 1481 int ret; 1482 1483 mmu_log_enable = CSR_XR(csr_base, err_reg_descr->log_addr); 1484 mmu_intr_enable = CSR_XR(csr_base, err_reg_descr->enable_addr); 1485 1486 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1487 mmu_ctrl = CSR_XR(csr_base, MMU_CONTROL_AND_STATUS); 1488 1489 switch (err_bit_descr->bit) { 1490 case MMU_INTERRUPT_STATUS_BYP_ERR_P: 1491 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_BE); 1492 break; 1493 case MMU_INTERRUPT_STATUS_TRN_ERR_P: 1494 mmu_enable_bit = BITMASK(MMU_CONTROL_AND_STATUS_TE); 1495 break; 1496 default: 1497 mmu_enable_bit = 0; 1498 break; 1499 } 1500 1501 /* 1502 * If the interrupts are enabled and Translation/Bypass Enable bit 1503 * was set, then panic. This error should not have occured. 1504 */ 1505 if (mmu_log_enable & mmu_intr_enable & 1506 (mmu_ctrl & mmu_enable_bit)) { 1507 err = PX_FATAL_SW; 1508 } else { 1509 ret = px_handle_lookup( 1510 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1511 err = (ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL; 1512 1513 /* 1514 * S/W bug - this error should always be enabled 1515 */ 1516 1517 /* enable error & intr reporting for this bit */ 1518 CSR_XS(csr_base, MMU_ERROR_LOG_ENABLE, mmu_log_enable | mask); 1519 CSR_XS(csr_base, MMU_INTERRUPT_ENABLE, mmu_intr_enable | mask); 1520 1521 /* enable translation access/bypass enable */ 1522 CSR_XS(csr_base, MMU_CONTROL_AND_STATUS, 1523 mmu_ctrl | mmu_enable_bit); 1524 } 1525 1526 return (err); 1527 } 1528 1529 /* Generic error handling functions that involve MMU Translation Fault Addr */ 1530 /* ARGSUSED */ 1531 int 1532 px_err_mmu_tfa_handle(dev_info_t *rpdip, caddr_t csr_base, 1533 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1534 px_err_bit_desc_t *err_bit_descr) 1535 { 1536 uint64_t mmu_tfa; 1537 uint_t ret; 1538 1539 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1540 ret = px_handle_lookup( 1541 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1542 1543 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1544 } 1545 1546 /* MMU Table walk errors */ 1547 /* ARGSUSED */ 1548 int 1549 px_err_mmu_tblwlk_handle(dev_info_t *rpdip, caddr_t csr_base, 1550 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1551 px_err_bit_desc_t *err_bit_descr) 1552 { 1553 uint64_t mmu_tfa; 1554 uint_t ret; 1555 1556 mmu_tfa = CSR_XR(csr_base, MMU_TRANSLATION_FAULT_ADDRESS); 1557 ret = px_handle_lookup( 1558 rpdip, DMA_HANDLE, derr->fme_ena, (void *)mmu_tfa); 1559 1560 return ((ret == DDI_FM_FATAL) ? PX_FATAL_GOS : PX_NONFATAL); 1561 } 1562 1563 /* 1564 * TLU LUP event - power management code is interested in this event. 1565 */ 1566 /* ARGSUSED */ 1567 int 1568 px_err_tlu_lup_handle(dev_info_t *rpdip, caddr_t csr_base, 1569 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1570 px_err_bit_desc_t *err_bit_descr) 1571 { 1572 px_t *px_p = DIP_TO_STATE(rpdip); 1573 1574 /* 1575 * Existense of pm info indicates the power management 1576 * is interested in this event. 1577 */ 1578 if (!PCIE_PMINFO(rpdip) || !PCIE_NEXUS_PMINFO(rpdip)) 1579 return (PX_OK); 1580 1581 mutex_enter(&px_p->px_lup_lock); 1582 px_p->px_lupsoft_pending++; 1583 mutex_exit(&px_p->px_lup_lock); 1584 1585 /* 1586 * Post a soft interrupt to wake up threads waiting for this. 1587 */ 1588 ddi_trigger_softintr(px_p->px_lupsoft_id); 1589 1590 return (PX_OK); 1591 } 1592 1593 /* PEC ILU none - see io erpt doc, section 3.1 */ 1594 PX_ERPT_SEND_DEC(pec_ilu) 1595 { 1596 char buf[FM_MAX_CLASS]; 1597 1598 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1599 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1600 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1601 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1602 FIRE_ILU_ELE, DATA_TYPE_UINT64, 1603 CSR_XR(csr_base, ILU_ERROR_LOG_ENABLE), 1604 FIRE_ILU_IE, DATA_TYPE_UINT64, 1605 CSR_XR(csr_base, ILU_INTERRUPT_ENABLE), 1606 FIRE_ILU_IS, DATA_TYPE_UINT64, 1607 ss_reg, 1608 FIRE_ILU_ESS, DATA_TYPE_UINT64, 1609 CSR_XR(csr_base, ILU_ERROR_STATUS_SET), 1610 NULL); 1611 1612 return (PX_OK); 1613 } 1614 1615 /* PCIEX UE Errors */ 1616 /* ARGSUSED */ 1617 int 1618 px_err_pciex_ue_handle(dev_info_t *rpdip, caddr_t csr_base, 1619 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1620 px_err_bit_desc_t *err_bit_descr) 1621 { 1622 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 1623 1624 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ue_gos) ? 1625 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ue, 1626 px_fabric_die_rc_ue_gos)); 1627 } 1628 1629 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.2 */ 1630 PX_ERPT_SEND_DEC(pciex_rx_ue) 1631 { 1632 char buf[FM_MAX_CLASS]; 1633 1634 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1635 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1636 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1637 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1638 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1639 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1640 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1641 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1642 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1643 ss_reg, 1644 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1645 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1646 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1647 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 1648 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1649 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 1650 NULL); 1651 1652 return (PX_OK); 1653 } 1654 1655 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.3 */ 1656 PX_ERPT_SEND_DEC(pciex_tx_ue) 1657 { 1658 char buf[FM_MAX_CLASS]; 1659 1660 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1661 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1662 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1663 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1664 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1665 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1666 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1667 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1668 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1669 ss_reg, 1670 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1671 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1672 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 1673 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 1674 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 1675 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 1676 NULL); 1677 1678 return (PX_OK); 1679 } 1680 1681 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.4 */ 1682 PX_ERPT_SEND_DEC(pciex_rx_tx_ue) 1683 { 1684 char buf[FM_MAX_CLASS]; 1685 1686 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1687 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1688 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1689 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1690 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1691 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1692 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1693 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1694 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1695 ss_reg, 1696 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1697 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1698 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1699 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER1_LOG), 1700 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1701 CSR_XR(csr_base, TLU_RECEIVE_UNCORRECTABLE_ERROR_HEADER2_LOG), 1702 FIRE_TLU_TUEH1L, DATA_TYPE_UINT64, 1703 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER1_LOG), 1704 FIRE_TLU_TUEH2L, DATA_TYPE_UINT64, 1705 CSR_XR(csr_base, TLU_TRANSMIT_UNCORRECTABLE_ERROR_HEADER2_LOG), 1706 NULL); 1707 1708 return (PX_OK); 1709 } 1710 1711 /* PCI-E Uncorrectable Errors - see io erpt doc, section 3.5 */ 1712 PX_ERPT_SEND_DEC(pciex_ue) 1713 { 1714 char buf[FM_MAX_CLASS]; 1715 1716 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1717 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1718 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1719 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1720 FIRE_TLU_UELE, DATA_TYPE_UINT64, 1721 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_LOG_ENABLE), 1722 FIRE_TLU_UIE, DATA_TYPE_UINT64, 1723 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_INTERRUPT_ENABLE), 1724 FIRE_TLU_UIS, DATA_TYPE_UINT64, 1725 ss_reg, 1726 FIRE_TLU_UESS, DATA_TYPE_UINT64, 1727 CSR_XR(csr_base, TLU_UNCORRECTABLE_ERROR_STATUS_SET), 1728 NULL); 1729 1730 return (PX_OK); 1731 } 1732 1733 /* PCIEX UE Errors */ 1734 /* ARGSUSED */ 1735 int 1736 px_err_pciex_ce_handle(dev_info_t *rpdip, caddr_t csr_base, 1737 ddi_fm_error_t *derr, px_err_reg_desc_t *err_reg_descr, 1738 px_err_bit_desc_t *err_bit_descr) 1739 { 1740 uint32_t mask = (uint32_t)BITMASK(err_bit_descr->bit); 1741 1742 return ((err_bit_descr->bit >= 32 && px_fabric_die_rc_ce_gos) ? 1743 PX_FATAL_GOS : PX_FABRIC_ERR_SEV(mask, px_fabric_die_rc_ce, 1744 px_fabric_die_rc_ce_gos)); 1745 } 1746 1747 /* PCI-E Correctable Errors - see io erpt doc, section 3.6 */ 1748 PX_ERPT_SEND_DEC(pciex_ce) 1749 { 1750 char buf[FM_MAX_CLASS]; 1751 1752 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1753 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1754 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1755 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1756 FIRE_TLU_CELE, DATA_TYPE_UINT64, 1757 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_LOG_ENABLE), 1758 FIRE_TLU_CIE, DATA_TYPE_UINT64, 1759 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_INTERRUPT_ENABLE), 1760 FIRE_TLU_CIS, DATA_TYPE_UINT64, 1761 ss_reg, 1762 FIRE_TLU_CESS, DATA_TYPE_UINT64, 1763 CSR_XR(csr_base, TLU_CORRECTABLE_ERROR_STATUS_SET), 1764 NULL); 1765 1766 return (PX_OK); 1767 } 1768 1769 /* TLU Other Event Status (receive only) - see io erpt doc, section 3.7 */ 1770 PX_ERPT_SEND_DEC(pciex_rx_oe) 1771 { 1772 char buf[FM_MAX_CLASS]; 1773 1774 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1775 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1776 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1777 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1778 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1779 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1780 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1781 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1782 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1783 ss_reg, 1784 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1785 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1786 FIRE_TLU_RUEH1L, DATA_TYPE_UINT64, 1787 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 1788 FIRE_TLU_RUEH2L, DATA_TYPE_UINT64, 1789 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 1790 NULL); 1791 1792 return (PX_OK); 1793 } 1794 1795 /* TLU Other Event Status (rx + tx) - see io erpt doc, section 3.8 */ 1796 PX_ERPT_SEND_DEC(pciex_rx_tx_oe) 1797 { 1798 char buf[FM_MAX_CLASS]; 1799 1800 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1801 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1802 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1803 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1804 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1805 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1806 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1807 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1808 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1809 ss_reg, 1810 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1811 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1812 FIRE_TLU_ROEEH1L, DATA_TYPE_UINT64, 1813 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER1_LOG), 1814 FIRE_TLU_ROEEH2L, DATA_TYPE_UINT64, 1815 CSR_XR(csr_base, TLU_RECEIVE_OTHER_EVENT_HEADER2_LOG), 1816 FIRE_TLU_TOEEH1L, DATA_TYPE_UINT64, 1817 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER1_LOG), 1818 FIRE_TLU_TOEEH2L, DATA_TYPE_UINT64, 1819 CSR_XR(csr_base, TLU_TRANSMIT_OTHER_EVENT_HEADER2_LOG), 1820 NULL); 1821 1822 return (PX_OK); 1823 } 1824 1825 /* TLU Other Event - see io erpt doc, section 3.9 */ 1826 PX_ERPT_SEND_DEC(pciex_oe) 1827 { 1828 char buf[FM_MAX_CLASS]; 1829 1830 (void) snprintf(buf, FM_MAX_CLASS, "%s", class_name); 1831 ddi_fm_ereport_post(rpdip, buf, derr->fme_ena, 1832 DDI_NOSLEEP, FM_VERSION, DATA_TYPE_UINT8, 0, 1833 FIRE_PRIMARY, DATA_TYPE_BOOLEAN_VALUE, B_TRUE, 1834 FIRE_TLU_OEELE, DATA_TYPE_UINT64, 1835 CSR_XR(csr_base, TLU_OTHER_EVENT_LOG_ENABLE), 1836 FIRE_TLU_OEIE, DATA_TYPE_UINT64, 1837 CSR_XR(csr_base, TLU_OTHER_EVENT_INTERRUPT_ENABLE), 1838 FIRE_TLU_OEIS, DATA_TYPE_UINT64, 1839 ss_reg, 1840 FIRE_TLU_OEESS, DATA_TYPE_UINT64, 1841 CSR_XR(csr_base, TLU_OTHER_EVENT_STATUS_SET), 1842 NULL); 1843 1844 return (PX_OK); 1845 } 1846 1847 /* TLU Other Event - Link Down see io erpt doc, section 3.9 */ 1848 PX_ERPT_SEND_DEC(pciex_ldn) 1849 { 1850 px_t *px_p = DIP_TO_STATE(rpdip); 1851 1852 /* 1853 * Don't post ereport, if ldn event is due to 1854 * power management. 1855 */ 1856 if (px_p->px_pm_flags & PX_LDN_EXPECTED) { 1857 px_p->px_pm_flags &= ~PX_LDN_EXPECTED; 1858 return (PX_OK); 1859 } 1860 return (PX_ERPT_SEND(pciex_oe)(rpdip, csr_base, ss_reg, derr, 1861 class_name)); 1862 1863 } 1864 1865 /* TLU Other Event - Link Up see io erpt doc, section 3.9 */ 1866 PX_ERPT_SEND_DEC(pciex_lup) 1867 { 1868 px_t *px_p = DIP_TO_STATE(rpdip); 1869 1870 /* 1871 * Don't post ereport, if lup event is due to 1872 * power management. 1873 */ 1874 if (px_p->px_pm_flags & PX_LUP_EXPECTED) { 1875 px_p->px_pm_flags &= ~PX_LUP_EXPECTED; 1876 return (PX_OK); 1877 } 1878 1879 return (PX_ERPT_SEND(pciex_oe)(rpdip, csr_base, ss_reg, derr, 1880 class_name)); 1881 } 1882