1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2008 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * Support for Olympus-C (SPARC64-VI) and Jupiter (SPARC64-VII). 28 */ 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <sys/types.h> 33 #include <sys/systm.h> 34 #include <sys/ddi.h> 35 #include <sys/sysmacros.h> 36 #include <sys/archsystm.h> 37 #include <sys/vmsystm.h> 38 #include <sys/machparam.h> 39 #include <sys/machsystm.h> 40 #include <sys/machthread.h> 41 #include <sys/cpu.h> 42 #include <sys/cmp.h> 43 #include <sys/elf_SPARC.h> 44 #include <vm/vm_dep.h> 45 #include <vm/hat_sfmmu.h> 46 #include <vm/seg_kpm.h> 47 #include <vm/seg_kmem.h> 48 #include <sys/cpuvar.h> 49 #include <sys/opl_olympus_regs.h> 50 #include <sys/opl_module.h> 51 #include <sys/async.h> 52 #include <sys/cmn_err.h> 53 #include <sys/debug.h> 54 #include <sys/dditypes.h> 55 #include <sys/cpu_module.h> 56 #include <sys/sysmacros.h> 57 #include <sys/intreg.h> 58 #include <sys/clock.h> 59 #include <sys/platform_module.h> 60 #include <sys/ontrap.h> 61 #include <sys/panic.h> 62 #include <sys/memlist.h> 63 #include <sys/ndifm.h> 64 #include <sys/ddifm.h> 65 #include <sys/fm/protocol.h> 66 #include <sys/fm/util.h> 67 #include <sys/fm/cpu/SPARC64-VI.h> 68 #include <sys/dtrace.h> 69 #include <sys/watchpoint.h> 70 #include <sys/promif.h> 71 72 /* 73 * Internal functions. 74 */ 75 static int cpu_sync_log_err(void *flt); 76 static void cpu_payload_add_aflt(struct async_flt *, nvlist_t *, nvlist_t *); 77 static void opl_cpu_sync_error(struct regs *, ulong_t, ulong_t, uint_t, uint_t); 78 static int cpu_flt_in_memory(opl_async_flt_t *, uint64_t); 79 static int prom_SPARC64VII_support_enabled(void); 80 static void opl_ta3(); 81 static int plat_prom_preserve_kctx_is_supported(void); 82 83 /* 84 * Error counters resetting interval. 85 */ 86 static int opl_async_check_interval = 60; /* 1 min */ 87 88 uint_t cpu_impl_dual_pgsz = 1; 89 90 /* 91 * PA[22:0] represent Displacement in Jupiter 92 * configuration space. 93 */ 94 uint_t root_phys_addr_lo_mask = 0x7fffffu; 95 96 /* 97 * set in /etc/system to control logging of user BERR/TO's 98 */ 99 int cpu_berr_to_verbose = 0; 100 101 /* 102 * Set to 1 if booted with all Jupiter cpus (all-Jupiter features enabled). 103 */ 104 int cpu_alljupiter = 0; 105 106 /* 107 * The sfmmu_cext field to be used by processes in a shared context domain. 108 */ 109 static uchar_t shctx_cext = TAGACCEXT_MKSZPAIR(DEFAULT_ISM_PAGESZC, TTE8K); 110 111 static int min_ecache_size; 112 static uint_t priv_hcl_1; 113 static uint_t priv_hcl_2; 114 static uint_t priv_hcl_4; 115 static uint_t priv_hcl_8; 116 117 /* 118 * Olympus error log 119 */ 120 static opl_errlog_t *opl_err_log; 121 122 /* 123 * OPL ta 3 save area. 124 */ 125 char *opl_ta3_save; 126 127 /* 128 * UE is classified into four classes (MEM, CHANNEL, CPU, PATH). 129 * No any other ecc_type_info insertion is allowed in between the following 130 * four UE classess. 131 */ 132 ecc_type_to_info_t ecc_type_to_info[] = { 133 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 134 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 135 FM_EREPORT_CPU_UE_MEM, 136 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 137 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 138 FM_EREPORT_CPU_UE_CHANNEL, 139 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 140 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 141 FM_EREPORT_CPU_UE_CPU, 142 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 143 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 144 FM_EREPORT_CPU_UE_PATH, 145 SFSR_BERR, "BERR ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 146 "Bus Error", FM_EREPORT_PAYLOAD_SYNC, 147 FM_EREPORT_CPU_BERR, 148 SFSR_TO, "TO ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 149 "Bus Timeout", FM_EREPORT_PAYLOAD_SYNC, 150 FM_EREPORT_CPU_BTO, 151 SFSR_TLB_MUL, "TLB_MUL ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 152 "TLB MultiHit", FM_EREPORT_PAYLOAD_SYNC, 153 FM_EREPORT_CPU_MTLB, 154 SFSR_TLB_PRT, "TLB_PRT ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 155 "TLB Parity", FM_EREPORT_PAYLOAD_SYNC, 156 FM_EREPORT_CPU_TLBP, 157 158 UGESR_IAUG_CRE, "IAUG_CRE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 159 "IAUG CRE", FM_EREPORT_PAYLOAD_URGENT, 160 FM_EREPORT_CPU_CRE, 161 UGESR_IAUG_TSBCTXT, "IAUG_TSBCTXT", 162 OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 163 "IAUG TSBCTXT", FM_EREPORT_PAYLOAD_URGENT, 164 FM_EREPORT_CPU_TSBCTX, 165 UGESR_IUG_TSBP, "IUG_TSBP", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 166 "IUG TSBP", FM_EREPORT_PAYLOAD_URGENT, 167 FM_EREPORT_CPU_TSBP, 168 UGESR_IUG_PSTATE, "IUG_PSTATE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 169 "IUG PSTATE", FM_EREPORT_PAYLOAD_URGENT, 170 FM_EREPORT_CPU_PSTATE, 171 UGESR_IUG_TSTATE, "IUG_TSTATE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 172 "IUG TSTATE", FM_EREPORT_PAYLOAD_URGENT, 173 FM_EREPORT_CPU_TSTATE, 174 UGESR_IUG_F, "IUG_F", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 175 "IUG FREG", FM_EREPORT_PAYLOAD_URGENT, 176 FM_EREPORT_CPU_IUG_F, 177 UGESR_IUG_R, "IUG_R", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 178 "IUG RREG", FM_EREPORT_PAYLOAD_URGENT, 179 FM_EREPORT_CPU_IUG_R, 180 UGESR_AUG_SDC, "AUG_SDC", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 181 "AUG SDC", FM_EREPORT_PAYLOAD_URGENT, 182 FM_EREPORT_CPU_SDC, 183 UGESR_IUG_WDT, "IUG_WDT", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 184 "IUG WDT", FM_EREPORT_PAYLOAD_URGENT, 185 FM_EREPORT_CPU_WDT, 186 UGESR_IUG_DTLB, "IUG_DTLB", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 187 "IUG DTLB", FM_EREPORT_PAYLOAD_URGENT, 188 FM_EREPORT_CPU_DTLB, 189 UGESR_IUG_ITLB, "IUG_ITLB", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 190 "IUG ITLB", FM_EREPORT_PAYLOAD_URGENT, 191 FM_EREPORT_CPU_ITLB, 192 UGESR_IUG_COREERR, "IUG_COREERR", 193 OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 194 "IUG COREERR", FM_EREPORT_PAYLOAD_URGENT, 195 FM_EREPORT_CPU_CORE, 196 UGESR_MULTI_DAE, "MULTI_DAE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 197 "MULTI DAE", FM_EREPORT_PAYLOAD_URGENT, 198 FM_EREPORT_CPU_DAE, 199 UGESR_MULTI_IAE, "MULTI_IAE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 200 "MULTI IAE", FM_EREPORT_PAYLOAD_URGENT, 201 FM_EREPORT_CPU_IAE, 202 UGESR_MULTI_UGE, "MULTI_UGE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 203 "MULTI UGE", FM_EREPORT_PAYLOAD_URGENT, 204 FM_EREPORT_CPU_UGE, 205 0, NULL, 0, 0, 206 NULL, 0, 0, 207 }; 208 209 int (*p2get_mem_info)(int synd_code, uint64_t paddr, 210 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 211 int *segsp, int *banksp, int *mcidp); 212 213 214 /* 215 * Setup trap handlers for 0xA, 0x32, 0x40 trap types 216 * and "ta 3" and "ta 4". 217 */ 218 void 219 cpu_init_trap(void) 220 { 221 OPL_SET_TRAP(tt0_iae, opl_serr_instr); 222 OPL_SET_TRAP(tt1_iae, opl_serr_instr); 223 OPL_SET_TRAP(tt0_dae, opl_serr_instr); 224 OPL_SET_TRAP(tt1_dae, opl_serr_instr); 225 OPL_SET_TRAP(tt0_asdat, opl_ugerr_instr); 226 OPL_SET_TRAP(tt1_asdat, opl_ugerr_instr); 227 OPL_SET_TRAP(tt0_flushw, opl_ta3_instr); 228 OPL_PATCH_28(opl_cleanw_patch, opl_ta4_instr); 229 } 230 231 static int 232 getintprop(pnode_t node, char *name, int deflt) 233 { 234 int value; 235 236 switch (prom_getproplen(node, name)) { 237 case sizeof (int): 238 (void) prom_getprop(node, name, (caddr_t)&value); 239 break; 240 241 default: 242 value = deflt; 243 break; 244 } 245 246 return (value); 247 } 248 249 /* 250 * Set the magic constants of the implementation. 251 */ 252 /*ARGSUSED*/ 253 void 254 cpu_fiximp(pnode_t dnode) 255 { 256 int i, a; 257 extern int vac_size, vac_shift; 258 extern uint_t vac_mask; 259 260 static struct { 261 char *name; 262 int *var; 263 int defval; 264 } prop[] = { 265 "l1-dcache-size", &dcache_size, OPL_DCACHE_SIZE, 266 "l1-dcache-line-size", &dcache_linesize, OPL_DCACHE_LSIZE, 267 "l1-icache-size", &icache_size, OPL_ICACHE_SIZE, 268 "l1-icache-line-size", &icache_linesize, OPL_ICACHE_LSIZE, 269 "l2-cache-size", &ecache_size, OPL_ECACHE_SIZE, 270 "l2-cache-line-size", &ecache_alignsize, OPL_ECACHE_LSIZE, 271 "l2-cache-associativity", &ecache_associativity, OPL_ECACHE_NWAY 272 }; 273 274 for (i = 0; i < sizeof (prop) / sizeof (prop[0]); i++) 275 *prop[i].var = getintprop(dnode, prop[i].name, prop[i].defval); 276 277 ecache_setsize = ecache_size / ecache_associativity; 278 279 vac_size = OPL_VAC_SIZE; 280 vac_mask = MMU_PAGEMASK & (vac_size - 1); 281 i = 0; a = vac_size; 282 while (a >>= 1) 283 ++i; 284 vac_shift = i; 285 shm_alignment = vac_size; 286 vac = 1; 287 } 288 289 /* 290 * Enable features for Jupiter-only domains. 291 */ 292 void 293 cpu_fix_alljupiter(void) 294 { 295 if (!prom_SPARC64VII_support_enabled()) { 296 /* 297 * Do not enable all-Jupiter features and do not turn on 298 * the cpu_alljupiter flag. 299 */ 300 return; 301 } 302 303 cpu_alljupiter = 1; 304 305 /* 306 * Enable ima hwcap for Jupiter-only domains. DR will prevent 307 * addition of Olympus-C to all-Jupiter domains to preserve ima 308 * hwcap semantics. 309 */ 310 cpu_hwcap_flags |= AV_SPARC_IMA; 311 312 /* 313 * Enable shared context support. 314 */ 315 shctx_on = 1; 316 } 317 318 #ifdef OLYMPUS_C_REV_B_ERRATA_XCALL 319 /* 320 * Quick and dirty way to redefine locally in 321 * OPL the value of IDSR_BN_SETS to 31 instead 322 * of the standard 32 value. This is to workaround 323 * REV_B of Olympus_c processor's problem in handling 324 * more than 31 xcall broadcast. 325 */ 326 #undef IDSR_BN_SETS 327 #define IDSR_BN_SETS 31 328 #endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */ 329 330 void 331 send_mondo_set(cpuset_t set) 332 { 333 int lo, busy, nack, shipped = 0; 334 uint16_t i, cpuids[IDSR_BN_SETS]; 335 uint64_t idsr, nackmask = 0, busymask, curnack, curbusy; 336 uint64_t starttick, endtick, tick, lasttick; 337 #if (NCPU > IDSR_BN_SETS) 338 int index = 0; 339 int ncpuids = 0; 340 #endif 341 #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 342 int bn_sets = IDSR_BN_SETS; 343 uint64_t ver; 344 345 ASSERT(NCPU > bn_sets); 346 #endif 347 348 ASSERT(!CPUSET_ISNULL(set)); 349 starttick = lasttick = gettick(); 350 351 #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 352 ver = ultra_getver(); 353 if (((ULTRA_VER_IMPL(ver)) == OLYMPUS_C_IMPL) && 354 ((OLYMPUS_REV_MASK(ver)) == OLYMPUS_C_A)) 355 bn_sets = 1; 356 #endif 357 358 #if (NCPU <= IDSR_BN_SETS) 359 for (i = 0; i < NCPU; i++) 360 if (CPU_IN_SET(set, i)) { 361 shipit(i, shipped); 362 nackmask |= IDSR_NACK_BIT(shipped); 363 cpuids[shipped++] = i; 364 CPUSET_DEL(set, i); 365 if (CPUSET_ISNULL(set)) 366 break; 367 } 368 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 369 #else 370 for (i = 0; i < NCPU; i++) 371 if (CPU_IN_SET(set, i)) { 372 ncpuids++; 373 374 /* 375 * Ship only to the first (IDSR_BN_SETS) CPUs. If we 376 * find we have shipped to more than (IDSR_BN_SETS) 377 * CPUs, set "index" to the highest numbered CPU in 378 * the set so we can ship to other CPUs a bit later on. 379 */ 380 #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 381 if (shipped < bn_sets) { 382 #else 383 if (shipped < IDSR_BN_SETS) { 384 #endif 385 shipit(i, shipped); 386 nackmask |= IDSR_NACK_BIT(shipped); 387 cpuids[shipped++] = i; 388 CPUSET_DEL(set, i); 389 if (CPUSET_ISNULL(set)) 390 break; 391 } else 392 index = (int)i; 393 } 394 395 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids); 396 #endif 397 398 busymask = IDSR_NACK_TO_BUSY(nackmask); 399 busy = nack = 0; 400 endtick = starttick + xc_tick_limit; 401 for (;;) { 402 idsr = getidsr(); 403 #if (NCPU <= IDSR_BN_SETS) 404 if (idsr == 0) 405 break; 406 #else 407 if (idsr == 0 && shipped == ncpuids) 408 break; 409 #endif 410 tick = gettick(); 411 /* 412 * If there is a big jump between the current tick 413 * count and lasttick, we have probably hit a break 414 * point. Adjust endtick accordingly to avoid panic. 415 */ 416 if (tick > (lasttick + xc_tick_jump_limit)) 417 endtick += (tick - lasttick); 418 lasttick = tick; 419 if (tick > endtick) { 420 if (panic_quiesce) 421 return; 422 cmn_err(CE_CONT, "send mondo timeout [%d NACK %d " 423 "BUSY]\nIDSR 0x%" PRIx64 " cpuids:", 424 nack, busy, idsr); 425 #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 426 for (i = 0; i < bn_sets; i++) { 427 #else 428 for (i = 0; i < IDSR_BN_SETS; i++) { 429 #endif 430 if (idsr & (IDSR_NACK_BIT(i) | 431 IDSR_BUSY_BIT(i))) { 432 cmn_err(CE_CONT, " 0x%x", cpuids[i]); 433 } 434 } 435 cmn_err(CE_CONT, "\n"); 436 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 437 } 438 curnack = idsr & nackmask; 439 curbusy = idsr & busymask; 440 441 #ifdef OLYMPUS_C_REV_B_ERRATA_XCALL 442 /* 443 * Only proceed to send more xcalls if all the 444 * cpus in the previous IDSR_BN_SETS were completed. 445 */ 446 if (curbusy) { 447 busy++; 448 continue; 449 } 450 #endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */ 451 452 #if (NCPU > IDSR_BN_SETS) 453 if (shipped < ncpuids) { 454 uint64_t cpus_left; 455 uint16_t next = (uint16_t)index; 456 457 cpus_left = ~(IDSR_NACK_TO_BUSY(curnack) | curbusy) & 458 busymask; 459 460 if (cpus_left) { 461 do { 462 /* 463 * Sequence through and ship to the 464 * remainder of the CPUs in the system 465 * (e.g. other than the first 466 * (IDSR_BN_SETS)) in reverse order. 467 */ 468 lo = lowbit(cpus_left) - 1; 469 i = IDSR_BUSY_IDX(lo); 470 shipit(next, i); 471 shipped++; 472 cpuids[i] = next; 473 474 /* 475 * If we've processed all the CPUs, 476 * exit the loop now and save 477 * instructions. 478 */ 479 if (shipped == ncpuids) 480 break; 481 482 for ((index = ((int)next - 1)); 483 index >= 0; index--) 484 if (CPU_IN_SET(set, index)) { 485 next = (uint16_t)index; 486 break; 487 } 488 489 cpus_left &= ~(1ull << lo); 490 } while (cpus_left); 491 continue; 492 } 493 } 494 #endif 495 #ifndef OLYMPUS_C_REV_B_ERRATA_XCALL 496 if (curbusy) { 497 busy++; 498 continue; 499 } 500 #endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */ 501 #ifdef SEND_MONDO_STATS 502 { 503 int n = gettick() - starttick; 504 if (n < 8192) 505 x_nack_stimes[n >> 7]++; 506 } 507 #endif 508 while (gettick() < (tick + sys_clock_mhz)) 509 ; 510 do { 511 lo = lowbit(curnack) - 1; 512 i = IDSR_NACK_IDX(lo); 513 shipit(cpuids[i], i); 514 curnack &= ~(1ull << lo); 515 } while (curnack); 516 nack++; 517 busy = 0; 518 } 519 #ifdef SEND_MONDO_STATS 520 { 521 int n = gettick() - starttick; 522 if (n < 8192) 523 x_set_stimes[n >> 7]++; 524 else 525 x_set_ltimes[(n >> 13) & 0xf]++; 526 } 527 x_set_cpus[shipped]++; 528 #endif 529 } 530 531 /* 532 * Cpu private initialization. 533 */ 534 void 535 cpu_init_private(struct cpu *cp) 536 { 537 if (!((IS_OLYMPUS_C(cpunodes[cp->cpu_id].implementation)) || 538 (IS_JUPITER(cpunodes[cp->cpu_id].implementation)))) { 539 cmn_err(CE_PANIC, "CPU%d Impl %d: Only SPARC64-VI(I) is " 540 "supported", cp->cpu_id, 541 cpunodes[cp->cpu_id].implementation); 542 } 543 544 adjust_hw_copy_limits(cpunodes[cp->cpu_id].ecache_size); 545 } 546 547 void 548 cpu_setup(void) 549 { 550 extern int at_flags; 551 extern int cpc_has_overflow_intr; 552 uint64_t cpu0_log; 553 extern uint64_t opl_cpu0_err_log; 554 555 /* 556 * Initialize Error log Scratch register for error handling. 557 */ 558 559 cpu0_log = va_to_pa(&opl_cpu0_err_log); 560 opl_error_setup(cpu0_log); 561 562 /* 563 * Enable MMU translating multiple page sizes for 564 * sITLB and sDTLB. 565 */ 566 opl_mpg_enable(); 567 568 /* 569 * Setup chip-specific trap handlers. 570 */ 571 cpu_init_trap(); 572 573 cache |= (CACHE_VAC | CACHE_PTAG | CACHE_IOCOHERENT); 574 575 at_flags = EF_SPARC_32PLUS | EF_SPARC_SUN_US1 | EF_SPARC_SUN_US3; 576 577 /* 578 * Due to the number of entries in the fully-associative tlb 579 * this may have to be tuned lower than in spitfire. 580 */ 581 pp_slots = MIN(8, MAXPP_SLOTS); 582 583 /* 584 * Block stores do not invalidate all pages of the d$, pagecopy 585 * et. al. need virtual translations with virtual coloring taken 586 * into consideration. prefetch/ldd will pollute the d$ on the 587 * load side. 588 */ 589 pp_consistent_coloring = PPAGE_STORE_VCOLORING | PPAGE_LOADS_POLLUTE; 590 591 if (use_page_coloring) { 592 do_pg_coloring = 1; 593 } 594 595 isa_list = 596 "sparcv9+vis2 sparcv9+vis sparcv9 " 597 "sparcv8plus+vis2 sparcv8plus+vis sparcv8plus " 598 "sparcv8 sparcv8-fsmuld sparcv7 sparc"; 599 600 cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2 | 601 AV_SPARC_POPC | AV_SPARC_FMAF; 602 603 /* 604 * On SPARC64-VI, there's no hole in the virtual address space 605 */ 606 hole_start = hole_end = 0; 607 608 /* 609 * The kpm mapping window. 610 * kpm_size: 611 * The size of a single kpm range. 612 * The overall size will be: kpm_size * vac_colors. 613 * kpm_vbase: 614 * The virtual start address of the kpm range within the kernel 615 * virtual address space. kpm_vbase has to be kpm_size aligned. 616 */ 617 kpm_size = (size_t)(128ull * 1024 * 1024 * 1024 * 1024); /* 128TB */ 618 kpm_size_shift = 47; 619 kpm_vbase = (caddr_t)0x8000000000000000ull; /* 8EB */ 620 kpm_smallpages = 1; 621 622 /* 623 * The traptrace code uses either %tick or %stick for 624 * timestamping. We have %stick so we can use it. 625 */ 626 traptrace_use_stick = 1; 627 628 /* 629 * SPARC64-VI has a performance counter overflow interrupt 630 */ 631 cpc_has_overflow_intr = 1; 632 633 /* 634 * Declare that this architecture/cpu combination does not support 635 * fpRAS. 636 */ 637 fpras_implemented = 0; 638 } 639 640 /* 641 * Called by setcpudelay 642 */ 643 void 644 cpu_init_tick_freq(void) 645 { 646 /* 647 * For SPARC64-VI we want to use the system clock rate as 648 * the basis for low level timing, due to support of mixed 649 * speed CPUs and power managment. 650 */ 651 if (system_clock_freq == 0) 652 cmn_err(CE_PANIC, "setcpudelay: invalid system_clock_freq"); 653 654 sys_tick_freq = system_clock_freq; 655 } 656 657 #ifdef SEND_MONDO_STATS 658 uint32_t x_one_stimes[64]; 659 uint32_t x_one_ltimes[16]; 660 uint32_t x_set_stimes[64]; 661 uint32_t x_set_ltimes[16]; 662 uint32_t x_set_cpus[NCPU]; 663 uint32_t x_nack_stimes[64]; 664 #endif 665 666 /* 667 * Note: A version of this function is used by the debugger via the KDI, 668 * and must be kept in sync with this version. Any changes made to this 669 * function to support new chips or to accomodate errata must also be included 670 * in the KDI-specific version. See us3_kdi.c. 671 */ 672 void 673 send_one_mondo(int cpuid) 674 { 675 int busy, nack; 676 uint64_t idsr, starttick, endtick, tick, lasttick; 677 uint64_t busymask; 678 679 CPU_STATS_ADDQ(CPU, sys, xcalls, 1); 680 starttick = lasttick = gettick(); 681 shipit(cpuid, 0); 682 endtick = starttick + xc_tick_limit; 683 busy = nack = 0; 684 busymask = IDSR_BUSY; 685 for (;;) { 686 idsr = getidsr(); 687 if (idsr == 0) 688 break; 689 690 tick = gettick(); 691 /* 692 * If there is a big jump between the current tick 693 * count and lasttick, we have probably hit a break 694 * point. Adjust endtick accordingly to avoid panic. 695 */ 696 if (tick > (lasttick + xc_tick_jump_limit)) 697 endtick += (tick - lasttick); 698 lasttick = tick; 699 if (tick > endtick) { 700 if (panic_quiesce) 701 return; 702 cmn_err(CE_PANIC, "send mondo timeout (target 0x%x) " 703 "[%d NACK %d BUSY]", cpuid, nack, busy); 704 } 705 706 if (idsr & busymask) { 707 busy++; 708 continue; 709 } 710 drv_usecwait(1); 711 shipit(cpuid, 0); 712 nack++; 713 busy = 0; 714 } 715 #ifdef SEND_MONDO_STATS 716 { 717 int n = gettick() - starttick; 718 if (n < 8192) 719 x_one_stimes[n >> 7]++; 720 else 721 x_one_ltimes[(n >> 13) & 0xf]++; 722 } 723 #endif 724 } 725 726 /* 727 * init_mmu_page_sizes is set to one after the bootup time initialization 728 * via mmu_init_mmu_page_sizes, to indicate that mmu_page_sizes has a 729 * valid value. 730 * 731 * mmu_disable_ism_large_pages and mmu_disable_large_pages are the mmu-specific 732 * versions of disable_ism_large_pages and disable_large_pages, and feed back 733 * into those two hat variables at hat initialization time. 734 * 735 */ 736 int init_mmu_page_sizes = 0; 737 738 static uint_t mmu_disable_large_pages = 0; 739 static uint_t mmu_disable_ism_large_pages = ((1 << TTE64K) | 740 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 741 static uint_t mmu_disable_auto_data_large_pages = ((1 << TTE64K) | 742 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 743 static uint_t mmu_disable_auto_text_large_pages = ((1 << TTE64K) | 744 (1 << TTE512K)); 745 746 /* 747 * Re-initialize mmu_page_sizes and friends, for SPARC64-VI mmu support. 748 * Called during very early bootup from check_cpus_set(). 749 * Can be called to verify that mmu_page_sizes are set up correctly. 750 * 751 * Set Olympus defaults. We do not use the function parameter. 752 */ 753 /*ARGSUSED*/ 754 int 755 mmu_init_mmu_page_sizes(int32_t not_used) 756 { 757 if (!init_mmu_page_sizes) { 758 mmu_page_sizes = MMU_PAGE_SIZES; 759 mmu_hashcnt = MAX_HASHCNT; 760 mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE; 761 mmu_exported_pagesize_mask = (1 << TTE8K) | 762 (1 << TTE64K) | (1 << TTE512K) | (1 << TTE4M) | 763 (1 << TTE32M) | (1 << TTE256M); 764 init_mmu_page_sizes = 1; 765 return (0); 766 } 767 return (1); 768 } 769 770 /* SPARC64-VI worst case DTLB parameters */ 771 #ifndef LOCKED_DTLB_ENTRIES 772 #define LOCKED_DTLB_ENTRIES 5 /* 2 user TSBs, 2 nucleus, + OBP */ 773 #endif 774 #define TOTAL_DTLB_ENTRIES 32 775 #define AVAIL_32M_ENTRIES 0 776 #define AVAIL_256M_ENTRIES 0 777 #define AVAIL_DTLB_ENTRIES (TOTAL_DTLB_ENTRIES - LOCKED_DTLB_ENTRIES) 778 static uint64_t ttecnt_threshold[MMU_PAGE_SIZES] = { 779 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES, 780 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES, 781 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES}; 782 783 /* 784 * The function returns the mmu-specific values for the 785 * hat's disable_large_pages, disable_ism_large_pages, and 786 * disable_auto_data_large_pages and 787 * disable_text_data_large_pages variables. 788 */ 789 uint_t 790 mmu_large_pages_disabled(uint_t flag) 791 { 792 uint_t pages_disable = 0; 793 extern int use_text_pgsz64K; 794 extern int use_text_pgsz512K; 795 796 if (flag == HAT_LOAD) { 797 pages_disable = mmu_disable_large_pages; 798 } else if (flag == HAT_LOAD_SHARE) { 799 pages_disable = mmu_disable_ism_large_pages; 800 } else if (flag == HAT_AUTO_DATA) { 801 pages_disable = mmu_disable_auto_data_large_pages; 802 } else if (flag == HAT_AUTO_TEXT) { 803 pages_disable = mmu_disable_auto_text_large_pages; 804 if (use_text_pgsz512K) { 805 pages_disable &= ~(1 << TTE512K); 806 } 807 if (use_text_pgsz64K) { 808 pages_disable &= ~(1 << TTE64K); 809 } 810 } 811 return (pages_disable); 812 } 813 814 /* 815 * mmu_init_large_pages is called with the desired ism_pagesize parameter. 816 * It may be called from set_platform_defaults, if some value other than 4M 817 * is desired. mmu_ism_pagesize is the tunable. If it has a bad value, 818 * then only warn, since it would be bad form to panic due to a user typo. 819 * 820 * The function re-initializes the mmu_disable_ism_large_pages variable. 821 */ 822 void 823 mmu_init_large_pages(size_t ism_pagesize) 824 { 825 826 switch (ism_pagesize) { 827 case MMU_PAGESIZE4M: 828 mmu_disable_ism_large_pages = ((1 << TTE64K) | 829 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 830 mmu_disable_auto_data_large_pages = ((1 << TTE64K) | 831 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 832 shctx_cext = TAGACCEXT_MKSZPAIR(TTE4M, TTE8K); 833 break; 834 case MMU_PAGESIZE32M: 835 mmu_disable_ism_large_pages = ((1 << TTE64K) | 836 (1 << TTE512K) | (1 << TTE256M)); 837 mmu_disable_auto_data_large_pages = ((1 << TTE64K) | 838 (1 << TTE512K) | (1 << TTE4M) | (1 << TTE256M)); 839 adjust_data_maxlpsize(ism_pagesize); 840 shctx_cext = TAGACCEXT_MKSZPAIR(TTE32M, TTE8K); 841 break; 842 case MMU_PAGESIZE256M: 843 mmu_disable_ism_large_pages = ((1 << TTE64K) | 844 (1 << TTE512K) | (1 << TTE32M)); 845 mmu_disable_auto_data_large_pages = ((1 << TTE64K) | 846 (1 << TTE512K) | (1 << TTE4M) | (1 << TTE32M)); 847 adjust_data_maxlpsize(ism_pagesize); 848 shctx_cext = TAGACCEXT_MKSZPAIR(TTE256M, TTE8K); 849 break; 850 default: 851 cmn_err(CE_WARN, "Unrecognized mmu_ism_pagesize value 0x%lx", 852 ism_pagesize); 853 break; 854 } 855 } 856 857 /* 858 * Function to reprogram the TLBs when page sizes used 859 * by a process change significantly. 860 */ 861 static void 862 mmu_setup_page_sizes(struct hat *hat, uint64_t *ttecnt, uint8_t *tmp_pgsz) 863 { 864 uint8_t pgsz0, pgsz1; 865 866 /* 867 * Don't program 2nd dtlb for kernel and ism hat 868 */ 869 ASSERT(hat->sfmmu_ismhat == NULL); 870 ASSERT(hat != ksfmmup); 871 872 /* 873 * hat->sfmmu_pgsz[] is an array whose elements 874 * contain a sorted order of page sizes. Element 875 * 0 is the most commonly used page size, followed 876 * by element 1, and so on. 877 * 878 * ttecnt[] is an array of per-page-size page counts 879 * mapped into the process. 880 * 881 * If the HAT's choice for page sizes is unsuitable, 882 * we can override it here. The new values written 883 * to the array will be handed back to us later to 884 * do the actual programming of the TLB hardware. 885 * 886 */ 887 pgsz0 = (uint8_t)MIN(tmp_pgsz[0], tmp_pgsz[1]); 888 pgsz1 = (uint8_t)MAX(tmp_pgsz[0], tmp_pgsz[1]); 889 890 /* 891 * This implements PAGESIZE programming of the sTLB 892 * if large TTE counts don't exceed the thresholds. 893 */ 894 if (ttecnt[pgsz0] < ttecnt_threshold[pgsz0]) 895 pgsz0 = page_szc(MMU_PAGESIZE); 896 if (ttecnt[pgsz1] < ttecnt_threshold[pgsz1]) 897 pgsz1 = page_szc(MMU_PAGESIZE); 898 tmp_pgsz[0] = pgsz0; 899 tmp_pgsz[1] = pgsz1; 900 /* otherwise, accept what the HAT chose for us */ 901 } 902 903 /* 904 * The HAT calls this function when an MMU context is allocated so that we 905 * can reprogram the large TLBs appropriately for the new process using 906 * the context. 907 * 908 * The caller must hold the HAT lock. 909 */ 910 void 911 mmu_set_ctx_page_sizes(struct hat *hat) 912 { 913 uint8_t pgsz0, pgsz1; 914 uint8_t new_cext; 915 916 ASSERT(sfmmu_hat_lock_held(hat)); 917 /* 918 * Don't program 2nd dtlb for kernel and ism hat 919 */ 920 if (hat->sfmmu_ismhat || hat == ksfmmup) 921 return; 922 923 /* 924 * If supported, reprogram the TLBs to a larger pagesize. 925 */ 926 if (hat->sfmmu_scdp != NULL) { 927 new_cext = shctx_cext; 928 } else { 929 pgsz0 = hat->sfmmu_pgsz[0]; 930 pgsz1 = hat->sfmmu_pgsz[1]; 931 ASSERT(pgsz0 < mmu_page_sizes); 932 ASSERT(pgsz1 < mmu_page_sizes); 933 new_cext = TAGACCEXT_MKSZPAIR(pgsz1, pgsz0); 934 } 935 if (hat->sfmmu_cext != new_cext) { 936 #ifdef DEBUG 937 int i; 938 /* 939 * assert cnum should be invalid, this is because pagesize 940 * can only be changed after a proc's ctxs are invalidated. 941 */ 942 for (i = 0; i < max_mmu_ctxdoms; i++) { 943 ASSERT(hat->sfmmu_ctxs[i].cnum == INVALID_CONTEXT); 944 } 945 #endif /* DEBUG */ 946 hat->sfmmu_cext = new_cext; 947 } 948 /* 949 * sfmmu_setctx_sec() will take care of the 950 * rest of the dirty work for us. 951 */ 952 } 953 954 /* 955 * This function assumes that there are either four or six supported page 956 * sizes and at most two programmable TLBs, so we need to decide which 957 * page sizes are most important and then adjust the TLB page sizes 958 * accordingly (if supported). 959 * 960 * If these assumptions change, this function will need to be 961 * updated to support whatever the new limits are. 962 */ 963 void 964 mmu_check_page_sizes(sfmmu_t *sfmmup, uint64_t *ttecnt) 965 { 966 uint64_t sortcnt[MMU_PAGE_SIZES]; 967 uint8_t tmp_pgsz[MMU_PAGE_SIZES]; 968 uint8_t i, j, max; 969 uint16_t oldval, newval; 970 971 /* 972 * We only consider reprogramming the TLBs if one or more of 973 * the two most used page sizes changes and we're using 974 * large pages in this process. 975 */ 976 if (SFMMU_LGPGS_INUSE(sfmmup)) { 977 /* Sort page sizes. */ 978 for (i = 0; i < mmu_page_sizes; i++) { 979 sortcnt[i] = ttecnt[i]; 980 } 981 for (j = 0; j < mmu_page_sizes; j++) { 982 for (i = mmu_page_sizes - 1, max = 0; i > 0; i--) { 983 if (sortcnt[i] > sortcnt[max]) 984 max = i; 985 } 986 tmp_pgsz[j] = max; 987 sortcnt[max] = 0; 988 } 989 990 oldval = sfmmup->sfmmu_pgsz[0] << 8 | sfmmup->sfmmu_pgsz[1]; 991 992 mmu_setup_page_sizes(sfmmup, ttecnt, tmp_pgsz); 993 994 /* Check 2 largest values after the sort. */ 995 newval = tmp_pgsz[0] << 8 | tmp_pgsz[1]; 996 if (newval != oldval) { 997 sfmmu_reprog_pgsz_arr(sfmmup, tmp_pgsz); 998 } 999 } 1000 } 1001 1002 /* 1003 * Return processor specific async error structure 1004 * size used. 1005 */ 1006 int 1007 cpu_aflt_size(void) 1008 { 1009 return (sizeof (opl_async_flt_t)); 1010 } 1011 1012 /* 1013 * The cpu_sync_log_err() function is called via the [uc]e_drain() function to 1014 * post-process CPU events that are dequeued. As such, it can be invoked 1015 * from softint context, from AST processing in the trap() flow, or from the 1016 * panic flow. We decode the CPU-specific data, and take appropriate actions. 1017 * Historically this entry point was used to log the actual cmn_err(9F) text; 1018 * now with FMA it is used to prepare 'flt' to be converted into an ereport. 1019 * With FMA this function now also returns a flag which indicates to the 1020 * caller whether the ereport should be posted (1) or suppressed (0). 1021 */ 1022 /*ARGSUSED*/ 1023 static int 1024 cpu_sync_log_err(void *flt) 1025 { 1026 opl_async_flt_t *opl_flt = (opl_async_flt_t *)flt; 1027 struct async_flt *aflt = (struct async_flt *)flt; 1028 1029 /* 1030 * No extra processing of urgent error events. 1031 * Always generate ereports for these events. 1032 */ 1033 if (aflt->flt_status == OPL_ECC_URGENT_TRAP) 1034 return (1); 1035 1036 /* 1037 * Additional processing for synchronous errors. 1038 */ 1039 switch (opl_flt->flt_type) { 1040 case OPL_CPU_INV_SFSR: 1041 return (1); 1042 1043 case OPL_CPU_SYNC_UE: 1044 /* 1045 * The validity: SFSR_MK_UE bit has been checked 1046 * in opl_cpu_sync_error() 1047 * No more check is required. 1048 * 1049 * opl_flt->flt_eid_mod and flt_eid_sid have been set by H/W, 1050 * and they have been retrieved in cpu_queue_events() 1051 */ 1052 1053 if (opl_flt->flt_eid_mod == OPL_ERRID_MEM) { 1054 ASSERT(aflt->flt_in_memory); 1055 /* 1056 * We want to skip logging only if ALL the following 1057 * conditions are true: 1058 * 1059 * 1. We are not panicing already. 1060 * 2. The error is a memory error. 1061 * 3. There is only one error. 1062 * 4. The error is on a retired page. 1063 * 5. The error occurred under on_trap 1064 * protection AFLT_PROT_EC 1065 */ 1066 if (!panicstr && aflt->flt_prot == AFLT_PROT_EC && 1067 page_retire_check(aflt->flt_addr, NULL) == 0) { 1068 /* 1069 * Do not log an error from 1070 * the retired page 1071 */ 1072 softcall(ecc_page_zero, (void *)aflt->flt_addr); 1073 return (0); 1074 } 1075 if (!panicstr) 1076 cpu_page_retire(opl_flt); 1077 } 1078 return (1); 1079 1080 case OPL_CPU_SYNC_OTHERS: 1081 /* 1082 * For the following error cases, the processor HW does 1083 * not set the flt_eid_mod/flt_eid_sid. Instead, SW will attempt 1084 * to assign appropriate values here to reflect what we 1085 * think is the most likely cause of the problem w.r.t to 1086 * the particular error event. For Buserr and timeout 1087 * error event, we will assign OPL_ERRID_CHANNEL as the 1088 * most likely reason. For TLB parity or multiple hit 1089 * error events, we will assign the reason as 1090 * OPL_ERRID_CPU (cpu related problem) and set the 1091 * flt_eid_sid to point to the cpuid. 1092 */ 1093 1094 if (opl_flt->flt_bit & (SFSR_BERR|SFSR_TO)) { 1095 /* 1096 * flt_eid_sid will not be used for this case. 1097 */ 1098 opl_flt->flt_eid_mod = OPL_ERRID_CHANNEL; 1099 } 1100 if (opl_flt->flt_bit & (SFSR_TLB_MUL|SFSR_TLB_PRT)) { 1101 opl_flt->flt_eid_mod = OPL_ERRID_CPU; 1102 opl_flt->flt_eid_sid = aflt->flt_inst; 1103 } 1104 1105 /* 1106 * In case of no effective error bit 1107 */ 1108 if ((opl_flt->flt_bit & SFSR_ERRS) == 0) { 1109 opl_flt->flt_eid_mod = OPL_ERRID_CPU; 1110 opl_flt->flt_eid_sid = aflt->flt_inst; 1111 } 1112 break; 1113 1114 default: 1115 return (1); 1116 } 1117 return (1); 1118 } 1119 1120 /* 1121 * Retire the bad page that may contain the flushed error. 1122 */ 1123 void 1124 cpu_page_retire(opl_async_flt_t *opl_flt) 1125 { 1126 struct async_flt *aflt = (struct async_flt *)opl_flt; 1127 (void) page_retire(aflt->flt_addr, PR_UE); 1128 } 1129 1130 /* 1131 * Invoked by error_init() early in startup and therefore before 1132 * startup_errorq() is called to drain any error Q - 1133 * 1134 * startup() 1135 * startup_end() 1136 * error_init() 1137 * cpu_error_init() 1138 * errorq_init() 1139 * errorq_drain() 1140 * start_other_cpus() 1141 * 1142 * The purpose of this routine is to create error-related taskqs. Taskqs 1143 * are used for this purpose because cpu_lock can't be grabbed from interrupt 1144 * context. 1145 * 1146 */ 1147 /*ARGSUSED*/ 1148 void 1149 cpu_error_init(int items) 1150 { 1151 opl_err_log = (opl_errlog_t *) 1152 kmem_alloc(ERRLOG_ALLOC_SZ, KM_SLEEP); 1153 if ((uint64_t)opl_err_log & MMU_PAGEOFFSET) 1154 cmn_err(CE_PANIC, "The base address of the error log " 1155 "is not page aligned"); 1156 } 1157 1158 /* 1159 * We route all errors through a single switch statement. 1160 */ 1161 void 1162 cpu_ue_log_err(struct async_flt *aflt) 1163 { 1164 switch (aflt->flt_class) { 1165 case CPU_FAULT: 1166 if (cpu_sync_log_err(aflt)) 1167 cpu_ereport_post(aflt); 1168 break; 1169 1170 case BUS_FAULT: 1171 bus_async_log_err(aflt); 1172 break; 1173 1174 default: 1175 cmn_err(CE_WARN, "discarding async error %p with invalid " 1176 "fault class (0x%x)", (void *)aflt, aflt->flt_class); 1177 return; 1178 } 1179 } 1180 1181 /* 1182 * Routine for panic hook callback from panic_idle(). 1183 * 1184 * Nothing to do here. 1185 */ 1186 void 1187 cpu_async_panic_callb(void) 1188 { 1189 } 1190 1191 /* 1192 * Routine to return a string identifying the physical name 1193 * associated with a memory/cache error. 1194 */ 1195 /*ARGSUSED*/ 1196 int 1197 cpu_get_mem_unum(int synd_status, ushort_t flt_synd, uint64_t flt_stat, 1198 uint64_t flt_addr, int flt_bus_id, int flt_in_memory, 1199 ushort_t flt_status, char *buf, int buflen, int *lenp) 1200 { 1201 int synd_code; 1202 int ret; 1203 1204 /* 1205 * An AFSR of -1 defaults to a memory syndrome. 1206 */ 1207 synd_code = (int)flt_synd; 1208 1209 if (&plat_get_mem_unum) { 1210 if ((ret = plat_get_mem_unum(synd_code, flt_addr, flt_bus_id, 1211 flt_in_memory, flt_status, buf, buflen, lenp)) != 0) { 1212 buf[0] = '\0'; 1213 *lenp = 0; 1214 } 1215 return (ret); 1216 } 1217 buf[0] = '\0'; 1218 *lenp = 0; 1219 return (ENOTSUP); 1220 } 1221 1222 /* 1223 * Wrapper for cpu_get_mem_unum() routine that takes an 1224 * async_flt struct rather than explicit arguments. 1225 */ 1226 int 1227 cpu_get_mem_unum_aflt(int synd_status, struct async_flt *aflt, 1228 char *buf, int buflen, int *lenp) 1229 { 1230 /* 1231 * We always pass -1 so that cpu_get_mem_unum will interpret this as a 1232 * memory error. 1233 */ 1234 return (cpu_get_mem_unum(synd_status, aflt->flt_synd, 1235 (uint64_t)-1, 1236 aflt->flt_addr, aflt->flt_bus_id, aflt->flt_in_memory, 1237 aflt->flt_status, buf, buflen, lenp)); 1238 } 1239 1240 /* 1241 * This routine is a more generic interface to cpu_get_mem_unum() 1242 * that may be used by other modules (e.g. mm). 1243 */ 1244 /*ARGSUSED*/ 1245 int 1246 cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar, 1247 char *buf, int buflen, int *lenp) 1248 { 1249 int synd_status, flt_in_memory, ret; 1250 ushort_t flt_status = 0; 1251 char unum[UNUM_NAMLEN]; 1252 1253 /* 1254 * Check for an invalid address. 1255 */ 1256 if (afar == (uint64_t)-1) 1257 return (ENXIO); 1258 1259 if (synd == (uint64_t)-1) 1260 synd_status = AFLT_STAT_INVALID; 1261 else 1262 synd_status = AFLT_STAT_VALID; 1263 1264 flt_in_memory = (*afsr & SFSR_MEMORY) && 1265 pf_is_memory(afar >> MMU_PAGESHIFT); 1266 1267 ret = cpu_get_mem_unum(synd_status, (ushort_t)synd, *afsr, afar, 1268 CPU->cpu_id, flt_in_memory, flt_status, unum, UNUM_NAMLEN, lenp); 1269 if (ret != 0) 1270 return (ret); 1271 1272 if (*lenp >= buflen) 1273 return (ENAMETOOLONG); 1274 1275 (void) strncpy(buf, unum, buflen); 1276 1277 return (0); 1278 } 1279 1280 /* 1281 * Routine to return memory information associated 1282 * with a physical address and syndrome. 1283 */ 1284 /*ARGSUSED*/ 1285 int 1286 cpu_get_mem_info(uint64_t synd, uint64_t afar, 1287 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 1288 int *segsp, int *banksp, int *mcidp) 1289 { 1290 int synd_code = (int)synd; 1291 1292 if (afar == (uint64_t)-1) 1293 return (ENXIO); 1294 1295 if (p2get_mem_info != NULL) 1296 return ((p2get_mem_info)(synd_code, afar, mem_sizep, seg_sizep, 1297 bank_sizep, segsp, banksp, mcidp)); 1298 else 1299 return (ENOTSUP); 1300 } 1301 1302 /* 1303 * Routine to return a string identifying the physical 1304 * name associated with a cpuid. 1305 */ 1306 int 1307 cpu_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 1308 { 1309 int ret; 1310 char unum[UNUM_NAMLEN]; 1311 1312 if (&plat_get_cpu_unum) { 1313 if ((ret = plat_get_cpu_unum(cpuid, unum, UNUM_NAMLEN, 1314 lenp)) != 0) 1315 return (ret); 1316 } else { 1317 return (ENOTSUP); 1318 } 1319 1320 if (*lenp >= buflen) 1321 return (ENAMETOOLONG); 1322 1323 (void) strncpy(buf, unum, *lenp); 1324 1325 return (0); 1326 } 1327 1328 /* 1329 * This routine exports the name buffer size. 1330 */ 1331 size_t 1332 cpu_get_name_bufsize() 1333 { 1334 return (UNUM_NAMLEN); 1335 } 1336 1337 /* 1338 * Flush the entire ecache by ASI_L2_CNTL.U2_FLUSH 1339 */ 1340 void 1341 cpu_flush_ecache(void) 1342 { 1343 flush_ecache(ecache_flushaddr, cpunodes[CPU->cpu_id].ecache_size, 1344 cpunodes[CPU->cpu_id].ecache_linesize); 1345 } 1346 1347 static uint8_t 1348 flt_to_trap_type(struct async_flt *aflt) 1349 { 1350 if (aflt->flt_status & OPL_ECC_ISYNC_TRAP) 1351 return (TRAP_TYPE_ECC_I); 1352 if (aflt->flt_status & OPL_ECC_DSYNC_TRAP) 1353 return (TRAP_TYPE_ECC_D); 1354 if (aflt->flt_status & OPL_ECC_URGENT_TRAP) 1355 return (TRAP_TYPE_URGENT); 1356 return (TRAP_TYPE_UNKNOWN); 1357 } 1358 1359 /* 1360 * Encode the data saved in the opl_async_flt_t struct into 1361 * the FM ereport payload. 1362 */ 1363 /* ARGSUSED */ 1364 static void 1365 cpu_payload_add_aflt(struct async_flt *aflt, nvlist_t *payload, 1366 nvlist_t *resource) 1367 { 1368 opl_async_flt_t *opl_flt = (opl_async_flt_t *)aflt; 1369 char unum[UNUM_NAMLEN]; 1370 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1371 int len; 1372 1373 1374 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_SFSR) { 1375 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SFSR, 1376 DATA_TYPE_UINT64, aflt->flt_stat, NULL); 1377 } 1378 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_SFAR) { 1379 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SFAR, 1380 DATA_TYPE_UINT64, aflt->flt_addr, NULL); 1381 } 1382 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_UGESR) { 1383 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_UGESR, 1384 DATA_TYPE_UINT64, aflt->flt_stat, NULL); 1385 } 1386 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_PC) { 1387 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_PC, 1388 DATA_TYPE_UINT64, (uint64_t)aflt->flt_pc, NULL); 1389 } 1390 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_TL) { 1391 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_TL, 1392 DATA_TYPE_UINT8, (uint8_t)aflt->flt_tl, NULL); 1393 } 1394 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_TT) { 1395 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_TT, 1396 DATA_TYPE_UINT8, flt_to_trap_type(aflt), NULL); 1397 } 1398 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_PRIV) { 1399 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_PRIV, 1400 DATA_TYPE_BOOLEAN_VALUE, 1401 (aflt->flt_priv ? B_TRUE : B_FALSE), NULL); 1402 } 1403 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_FLT_STATUS) { 1404 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_FLT_STATUS, 1405 DATA_TYPE_UINT64, (uint64_t)aflt->flt_status, NULL); 1406 } 1407 1408 switch (opl_flt->flt_eid_mod) { 1409 case OPL_ERRID_CPU: 1410 (void) snprintf(sbuf, sizeof (sbuf), "%llX", 1411 (u_longlong_t)cpunodes[opl_flt->flt_eid_sid].device_id); 1412 (void) fm_fmri_cpu_set(resource, FM_CPU_SCHEME_VERSION, 1413 NULL, opl_flt->flt_eid_sid, 1414 (uint8_t *)&cpunodes[opl_flt->flt_eid_sid].version, sbuf); 1415 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RESOURCE, 1416 DATA_TYPE_NVLIST, resource, NULL); 1417 break; 1418 1419 case OPL_ERRID_CHANNEL: 1420 /* 1421 * No resource is created but the cpumem DE will find 1422 * the defective path by retreiving EID from SFSR which is 1423 * included in the payload. 1424 */ 1425 break; 1426 1427 case OPL_ERRID_MEM: 1428 (void) cpu_get_mem_unum_aflt(0, aflt, unum, UNUM_NAMLEN, &len); 1429 (void) fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, NULL, 1430 unum, NULL, (uint64_t)-1); 1431 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RESOURCE, 1432 DATA_TYPE_NVLIST, resource, NULL); 1433 break; 1434 1435 case OPL_ERRID_PATH: 1436 /* 1437 * No resource is created but the cpumem DE will find 1438 * the defective path by retreiving EID from SFSR which is 1439 * included in the payload. 1440 */ 1441 break; 1442 } 1443 } 1444 1445 /* 1446 * Returns whether fault address is valid for this error bit and 1447 * whether the address is "in memory" (i.e. pf_is_memory returns 1). 1448 */ 1449 /*ARGSUSED*/ 1450 static int 1451 cpu_flt_in_memory(opl_async_flt_t *opl_flt, uint64_t t_afsr_bit) 1452 { 1453 struct async_flt *aflt = (struct async_flt *)opl_flt; 1454 1455 if (aflt->flt_status & (OPL_ECC_SYNC_TRAP)) { 1456 return ((t_afsr_bit & SFSR_MEMORY) && 1457 pf_is_memory(aflt->flt_addr >> MMU_PAGESHIFT)); 1458 } 1459 return (0); 1460 } 1461 1462 /* 1463 * In OPL SCF does the stick synchronization. 1464 */ 1465 void 1466 sticksync_slave(void) 1467 { 1468 } 1469 1470 /* 1471 * In OPL SCF does the stick synchronization. 1472 */ 1473 void 1474 sticksync_master(void) 1475 { 1476 } 1477 1478 /* 1479 * Cpu private unitialization. OPL cpus do not use the private area. 1480 */ 1481 void 1482 cpu_uninit_private(struct cpu *cp) 1483 { 1484 cmp_delete_cpu(cp->cpu_id); 1485 } 1486 1487 /* 1488 * Always flush an entire cache. 1489 */ 1490 void 1491 cpu_error_ecache_flush(void) 1492 { 1493 cpu_flush_ecache(); 1494 } 1495 1496 void 1497 cpu_ereport_post(struct async_flt *aflt) 1498 { 1499 char *cpu_type, buf[FM_MAX_CLASS]; 1500 nv_alloc_t *nva = NULL; 1501 nvlist_t *ereport, *detector, *resource; 1502 errorq_elem_t *eqep; 1503 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1504 1505 if (aflt->flt_panic || panicstr) { 1506 eqep = errorq_reserve(ereport_errorq); 1507 if (eqep == NULL) 1508 return; 1509 ereport = errorq_elem_nvl(ereport_errorq, eqep); 1510 nva = errorq_elem_nva(ereport_errorq, eqep); 1511 } else { 1512 ereport = fm_nvlist_create(nva); 1513 } 1514 1515 /* 1516 * Create the scheme "cpu" FMRI. 1517 */ 1518 detector = fm_nvlist_create(nva); 1519 resource = fm_nvlist_create(nva); 1520 switch (cpunodes[aflt->flt_inst].implementation) { 1521 case OLYMPUS_C_IMPL: 1522 cpu_type = FM_EREPORT_CPU_SPARC64_VI; 1523 break; 1524 case JUPITER_IMPL: 1525 cpu_type = FM_EREPORT_CPU_SPARC64_VII; 1526 break; 1527 default: 1528 cpu_type = FM_EREPORT_CPU_UNSUPPORTED; 1529 break; 1530 } 1531 (void) snprintf(sbuf, sizeof (sbuf), "%llX", 1532 (u_longlong_t)cpunodes[aflt->flt_inst].device_id); 1533 (void) fm_fmri_cpu_set(detector, FM_CPU_SCHEME_VERSION, NULL, 1534 aflt->flt_inst, (uint8_t *)&cpunodes[aflt->flt_inst].version, 1535 sbuf); 1536 1537 /* 1538 * Encode all the common data into the ereport. 1539 */ 1540 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s.%s", 1541 FM_ERROR_CPU, cpu_type, aflt->flt_erpt_class); 1542 1543 fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, 1544 fm_ena_generate(aflt->flt_id, FM_ENA_FMT1), detector, NULL); 1545 1546 /* 1547 * Encode the error specific data that was saved in 1548 * the async_flt structure into the ereport. 1549 */ 1550 cpu_payload_add_aflt(aflt, ereport, resource); 1551 1552 if (aflt->flt_panic || panicstr) { 1553 errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC); 1554 } else { 1555 (void) fm_ereport_post(ereport, EVCH_TRYHARD); 1556 fm_nvlist_destroy(ereport, FM_NVA_FREE); 1557 fm_nvlist_destroy(detector, FM_NVA_FREE); 1558 fm_nvlist_destroy(resource, FM_NVA_FREE); 1559 } 1560 } 1561 1562 void 1563 cpu_run_bus_error_handlers(struct async_flt *aflt, int expected) 1564 { 1565 int status; 1566 ddi_fm_error_t de; 1567 1568 bzero(&de, sizeof (ddi_fm_error_t)); 1569 1570 de.fme_version = DDI_FME_VERSION; 1571 de.fme_ena = fm_ena_generate(aflt->flt_id, FM_ENA_FMT1); 1572 de.fme_flag = expected; 1573 de.fme_bus_specific = (void *)aflt->flt_addr; 1574 status = ndi_fm_handler_dispatch(ddi_root_node(), NULL, &de); 1575 if ((aflt->flt_prot == AFLT_PROT_NONE) && (status == DDI_FM_FATAL)) 1576 aflt->flt_panic = 1; 1577 } 1578 1579 void 1580 cpu_errorq_dispatch(char *error_class, void *payload, size_t payload_sz, 1581 errorq_t *eqp, uint_t flag) 1582 { 1583 struct async_flt *aflt = (struct async_flt *)payload; 1584 1585 aflt->flt_erpt_class = error_class; 1586 errorq_dispatch(eqp, payload, payload_sz, flag); 1587 } 1588 1589 void 1590 adjust_hw_copy_limits(int ecache_size) 1591 { 1592 /* 1593 * Set hw copy limits. 1594 * 1595 * /etc/system will be parsed later and can override one or more 1596 * of these settings. 1597 * 1598 * At this time, ecache size seems only mildly relevant. 1599 * We seem to run into issues with the d-cache and stalls 1600 * we see on misses. 1601 * 1602 * Cycle measurement indicates that 2 byte aligned copies fare 1603 * little better than doing things with VIS at around 512 bytes. 1604 * 4 byte aligned shows promise until around 1024 bytes. 8 Byte 1605 * aligned is faster whenever the source and destination data 1606 * in cache and the total size is less than 2 Kbytes. The 2K 1607 * limit seems to be driven by the 2K write cache. 1608 * When more than 2K of copies are done in non-VIS mode, stores 1609 * backup in the write cache. In VIS mode, the write cache is 1610 * bypassed, allowing faster cache-line writes aligned on cache 1611 * boundaries. 1612 * 1613 * In addition, in non-VIS mode, there is no prefetching, so 1614 * for larger copies, the advantage of prefetching to avoid even 1615 * occasional cache misses is enough to justify using the VIS code. 1616 * 1617 * During testing, it was discovered that netbench ran 3% slower 1618 * when hw_copy_limit_8 was 2K or larger. Apparently for server 1619 * applications, data is only used once (copied to the output 1620 * buffer, then copied by the network device off the system). Using 1621 * the VIS copy saves more L2 cache state. Network copies are 1622 * around 1.3K to 1.5K in size for historical reasons. 1623 * 1624 * Therefore, a limit of 1K bytes will be used for the 8 byte 1625 * aligned copy even for large caches and 8 MB ecache. The 1626 * infrastructure to allow different limits for different sized 1627 * caches is kept to allow further tuning in later releases. 1628 */ 1629 1630 if (min_ecache_size == 0 && use_hw_bcopy) { 1631 /* 1632 * First time through - should be before /etc/system 1633 * is read. 1634 * Could skip the checks for zero but this lets us 1635 * preserve any debugger rewrites. 1636 */ 1637 if (hw_copy_limit_1 == 0) { 1638 hw_copy_limit_1 = VIS_COPY_THRESHOLD; 1639 priv_hcl_1 = hw_copy_limit_1; 1640 } 1641 if (hw_copy_limit_2 == 0) { 1642 hw_copy_limit_2 = 2 * VIS_COPY_THRESHOLD; 1643 priv_hcl_2 = hw_copy_limit_2; 1644 } 1645 if (hw_copy_limit_4 == 0) { 1646 hw_copy_limit_4 = 4 * VIS_COPY_THRESHOLD; 1647 priv_hcl_4 = hw_copy_limit_4; 1648 } 1649 if (hw_copy_limit_8 == 0) { 1650 hw_copy_limit_8 = 4 * VIS_COPY_THRESHOLD; 1651 priv_hcl_8 = hw_copy_limit_8; 1652 } 1653 min_ecache_size = ecache_size; 1654 } else { 1655 /* 1656 * MP initialization. Called *after* /etc/system has 1657 * been parsed. One CPU has already been initialized. 1658 * Need to cater for /etc/system having scragged one 1659 * of our values. 1660 */ 1661 if (ecache_size == min_ecache_size) { 1662 /* 1663 * Same size ecache. We do nothing unless we 1664 * have a pessimistic ecache setting. In that 1665 * case we become more optimistic (if the cache is 1666 * large enough). 1667 */ 1668 if (hw_copy_limit_8 == 4 * VIS_COPY_THRESHOLD) { 1669 /* 1670 * Need to adjust hw_copy_limit* from our 1671 * pessimistic uniprocessor value to a more 1672 * optimistic UP value *iff* it hasn't been 1673 * reset. 1674 */ 1675 if ((ecache_size > 1048576) && 1676 (priv_hcl_8 == hw_copy_limit_8)) { 1677 if (ecache_size <= 2097152) 1678 hw_copy_limit_8 = 4 * 1679 VIS_COPY_THRESHOLD; 1680 else if (ecache_size <= 4194304) 1681 hw_copy_limit_8 = 4 * 1682 VIS_COPY_THRESHOLD; 1683 else 1684 hw_copy_limit_8 = 4 * 1685 VIS_COPY_THRESHOLD; 1686 priv_hcl_8 = hw_copy_limit_8; 1687 } 1688 } 1689 } else if (ecache_size < min_ecache_size) { 1690 /* 1691 * A different ecache size. Can this even happen? 1692 */ 1693 if (priv_hcl_8 == hw_copy_limit_8) { 1694 /* 1695 * The previous value that we set 1696 * is unchanged (i.e., it hasn't been 1697 * scragged by /etc/system). Rewrite it. 1698 */ 1699 if (ecache_size <= 1048576) 1700 hw_copy_limit_8 = 8 * 1701 VIS_COPY_THRESHOLD; 1702 else if (ecache_size <= 2097152) 1703 hw_copy_limit_8 = 8 * 1704 VIS_COPY_THRESHOLD; 1705 else if (ecache_size <= 4194304) 1706 hw_copy_limit_8 = 8 * 1707 VIS_COPY_THRESHOLD; 1708 else 1709 hw_copy_limit_8 = 10 * 1710 VIS_COPY_THRESHOLD; 1711 priv_hcl_8 = hw_copy_limit_8; 1712 min_ecache_size = ecache_size; 1713 } 1714 } 1715 } 1716 } 1717 1718 #define VIS_BLOCKSIZE 64 1719 1720 int 1721 dtrace_blksuword32_err(uintptr_t addr, uint32_t *data) 1722 { 1723 int ret, watched; 1724 1725 watched = watch_disable_addr((void *)addr, VIS_BLOCKSIZE, S_WRITE); 1726 ret = dtrace_blksuword32(addr, data, 0); 1727 if (watched) 1728 watch_enable_addr((void *)addr, VIS_BLOCKSIZE, S_WRITE); 1729 1730 return (ret); 1731 } 1732 1733 void 1734 opl_cpu_reg_init() 1735 { 1736 uint64_t this_cpu_log; 1737 1738 /* 1739 * We do not need to re-initialize cpu0 registers. 1740 */ 1741 if (cpu[getprocessorid()] == &cpu0) { 1742 /* 1743 * Support for "ta 3" 1744 */ 1745 opl_ta3(); 1746 return; 1747 } 1748 1749 /* 1750 * Initialize Error log Scratch register for error handling. 1751 */ 1752 1753 this_cpu_log = va_to_pa((void*)(((uint64_t)opl_err_log) + 1754 ERRLOG_BUFSZ * (getprocessorid()))); 1755 opl_error_setup(this_cpu_log); 1756 1757 /* 1758 * Enable MMU translating multiple page sizes for 1759 * sITLB and sDTLB. 1760 */ 1761 opl_mpg_enable(); 1762 } 1763 1764 /* 1765 * Queue one event in ue_queue based on ecc_type_to_info entry. 1766 */ 1767 static void 1768 cpu_queue_one_event(opl_async_flt_t *opl_flt, char *reason, 1769 ecc_type_to_info_t *eccp) 1770 { 1771 struct async_flt *aflt = (struct async_flt *)opl_flt; 1772 1773 if (reason && 1774 strlen(reason) + strlen(eccp->ec_reason) < MAX_REASON_STRING) { 1775 (void) strcat(reason, eccp->ec_reason); 1776 } 1777 1778 opl_flt->flt_bit = eccp->ec_afsr_bit; 1779 opl_flt->flt_type = eccp->ec_flt_type; 1780 aflt->flt_in_memory = cpu_flt_in_memory(opl_flt, opl_flt->flt_bit); 1781 aflt->flt_payload = eccp->ec_err_payload; 1782 1783 ASSERT(aflt->flt_status & (OPL_ECC_SYNC_TRAP|OPL_ECC_URGENT_TRAP)); 1784 cpu_errorq_dispatch(eccp->ec_err_class, (void *)opl_flt, 1785 sizeof (opl_async_flt_t), ue_queue, aflt->flt_panic); 1786 } 1787 1788 /* 1789 * Queue events on async event queue one event per error bit. 1790 * Return number of events queued. 1791 */ 1792 int 1793 cpu_queue_events(opl_async_flt_t *opl_flt, char *reason, uint64_t t_afsr_errs) 1794 { 1795 struct async_flt *aflt = (struct async_flt *)opl_flt; 1796 ecc_type_to_info_t *eccp; 1797 int nevents = 0; 1798 1799 /* 1800 * Queue expected errors, error bit and fault type must must match 1801 * in the ecc_type_to_info table. 1802 */ 1803 for (eccp = ecc_type_to_info; t_afsr_errs != 0 && eccp->ec_desc != NULL; 1804 eccp++) { 1805 if ((eccp->ec_afsr_bit & t_afsr_errs) != 0 && 1806 (eccp->ec_flags & aflt->flt_status) != 0) { 1807 /* 1808 * UE error event can be further 1809 * classified/breakdown into finer granularity 1810 * based on the flt_eid_mod value set by HW. We do 1811 * special handling here so that we can report UE 1812 * error in finer granularity as ue_mem, 1813 * ue_channel, ue_cpu or ue_path. 1814 */ 1815 if (eccp->ec_flt_type == OPL_CPU_SYNC_UE) { 1816 opl_flt->flt_eid_mod = (aflt->flt_stat & 1817 SFSR_EID_MOD) >> SFSR_EID_MOD_SHIFT; 1818 opl_flt->flt_eid_sid = (aflt->flt_stat & 1819 SFSR_EID_SID) >> SFSR_EID_SID_SHIFT; 1820 /* 1821 * Need to advance eccp pointer by flt_eid_mod 1822 * so that we get an appropriate ecc pointer 1823 * 1824 * EID # of advances 1825 * ---------------------------------- 1826 * OPL_ERRID_MEM 0 1827 * OPL_ERRID_CHANNEL 1 1828 * OPL_ERRID_CPU 2 1829 * OPL_ERRID_PATH 3 1830 */ 1831 eccp += opl_flt->flt_eid_mod; 1832 } 1833 cpu_queue_one_event(opl_flt, reason, eccp); 1834 t_afsr_errs &= ~eccp->ec_afsr_bit; 1835 nevents++; 1836 } 1837 } 1838 1839 return (nevents); 1840 } 1841 1842 /* 1843 * Sync. error wrapper functions. 1844 * We use these functions in order to transfer here from the 1845 * nucleus trap handler information about trap type (data or 1846 * instruction) and trap level (0 or above 0). This way we 1847 * get rid of using SFSR's reserved bits. 1848 */ 1849 1850 #define OPL_SYNC_TL0 0 1851 #define OPL_SYNC_TL1 1 1852 #define OPL_ISYNC_ERR 0 1853 #define OPL_DSYNC_ERR 1 1854 1855 void 1856 opl_cpu_isync_tl0_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1857 { 1858 uint64_t t_sfar = p_sfar; 1859 uint64_t t_sfsr = p_sfsr; 1860 1861 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1862 OPL_SYNC_TL0, OPL_ISYNC_ERR); 1863 } 1864 1865 void 1866 opl_cpu_isync_tl1_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1867 { 1868 uint64_t t_sfar = p_sfar; 1869 uint64_t t_sfsr = p_sfsr; 1870 1871 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1872 OPL_SYNC_TL1, OPL_ISYNC_ERR); 1873 } 1874 1875 void 1876 opl_cpu_dsync_tl0_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1877 { 1878 uint64_t t_sfar = p_sfar; 1879 uint64_t t_sfsr = p_sfsr; 1880 1881 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1882 OPL_SYNC_TL0, OPL_DSYNC_ERR); 1883 } 1884 1885 void 1886 opl_cpu_dsync_tl1_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1887 { 1888 uint64_t t_sfar = p_sfar; 1889 uint64_t t_sfsr = p_sfsr; 1890 1891 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1892 OPL_SYNC_TL1, OPL_DSYNC_ERR); 1893 } 1894 1895 /* 1896 * The fj sync err handler transfers control here for UE, BERR, TO, TLB_MUL 1897 * and TLB_PRT. 1898 * This function is designed based on cpu_deferred_error(). 1899 */ 1900 1901 static void 1902 opl_cpu_sync_error(struct regs *rp, ulong_t t_sfar, ulong_t t_sfsr, 1903 uint_t tl, uint_t derr) 1904 { 1905 opl_async_flt_t opl_flt; 1906 struct async_flt *aflt; 1907 int trampolined = 0; 1908 char pr_reason[MAX_REASON_STRING]; 1909 uint64_t log_sfsr; 1910 int expected = DDI_FM_ERR_UNEXPECTED; 1911 ddi_acc_hdl_t *hp; 1912 1913 /* 1914 * We need to look at p_flag to determine if the thread detected an 1915 * error while dumping core. We can't grab p_lock here, but it's ok 1916 * because we just need a consistent snapshot and we know that everyone 1917 * else will store a consistent set of bits while holding p_lock. We 1918 * don't have to worry about a race because SDOCORE is set once prior 1919 * to doing i/o from the process's address space and is never cleared. 1920 */ 1921 uint_t pflag = ttoproc(curthread)->p_flag; 1922 1923 pr_reason[0] = '\0'; 1924 1925 /* 1926 * handle the specific error 1927 */ 1928 bzero(&opl_flt, sizeof (opl_async_flt_t)); 1929 aflt = (struct async_flt *)&opl_flt; 1930 aflt->flt_id = gethrtime_waitfree(); 1931 aflt->flt_bus_id = getprocessorid(); 1932 aflt->flt_inst = CPU->cpu_id; 1933 aflt->flt_stat = t_sfsr; 1934 aflt->flt_addr = t_sfar; 1935 aflt->flt_pc = (caddr_t)rp->r_pc; 1936 aflt->flt_prot = (uchar_t)AFLT_PROT_NONE; 1937 aflt->flt_class = (uchar_t)CPU_FAULT; 1938 aflt->flt_priv = (uchar_t)(tl == 1 ? 1 : ((rp->r_tstate & 1939 TSTATE_PRIV) ? 1 : 0)); 1940 aflt->flt_tl = (uchar_t)tl; 1941 aflt->flt_panic = (uchar_t)(tl != 0 || aft_testfatal != 0 || 1942 (t_sfsr & (SFSR_TLB_MUL|SFSR_TLB_PRT)) != 0); 1943 aflt->flt_core = (pflag & SDOCORE) ? 1 : 0; 1944 aflt->flt_status = (derr) ? OPL_ECC_DSYNC_TRAP : OPL_ECC_ISYNC_TRAP; 1945 1946 /* 1947 * If SFSR.FV is not set, both SFSR and SFAR/SFPAR values are uncertain. 1948 * So, clear all error bits to avoid mis-handling and force the system 1949 * panicked. 1950 * We skip all the procedures below down to the panic message call. 1951 */ 1952 if (!(t_sfsr & SFSR_FV)) { 1953 opl_flt.flt_type = OPL_CPU_INV_SFSR; 1954 aflt->flt_panic = 1; 1955 aflt->flt_payload = FM_EREPORT_PAYLOAD_SYNC; 1956 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_SFSR, (void *)&opl_flt, 1957 sizeof (opl_async_flt_t), ue_queue, aflt->flt_panic); 1958 fm_panic("%sErrors(s)", "invalid SFSR"); 1959 } 1960 1961 /* 1962 * If either UE and MK bit is off, this is not valid UE error. 1963 * If it is not valid UE error, clear UE & MK_UE bits to prevent 1964 * mis-handling below. 1965 * aflt->flt_stat keeps the original bits as a reference. 1966 */ 1967 if ((t_sfsr & (SFSR_MK_UE|SFSR_UE)) != 1968 (SFSR_MK_UE|SFSR_UE)) { 1969 t_sfsr &= ~(SFSR_MK_UE|SFSR_UE); 1970 } 1971 1972 /* 1973 * If the trap occurred in privileged mode at TL=0, we need to check to 1974 * see if we were executing in the kernel under on_trap() or t_lofault 1975 * protection. If so, modify the saved registers so that we return 1976 * from the trap to the appropriate trampoline routine. 1977 */ 1978 if (!aflt->flt_panic && aflt->flt_priv && tl == 0) { 1979 if (curthread->t_ontrap != NULL) { 1980 on_trap_data_t *otp = curthread->t_ontrap; 1981 1982 if (otp->ot_prot & OT_DATA_EC) { 1983 aflt->flt_prot = (uchar_t)AFLT_PROT_EC; 1984 otp->ot_trap |= (ushort_t)OT_DATA_EC; 1985 rp->r_pc = otp->ot_trampoline; 1986 rp->r_npc = rp->r_pc + 4; 1987 trampolined = 1; 1988 } 1989 1990 if ((t_sfsr & (SFSR_TO | SFSR_BERR)) && 1991 (otp->ot_prot & OT_DATA_ACCESS)) { 1992 aflt->flt_prot = (uchar_t)AFLT_PROT_ACCESS; 1993 otp->ot_trap |= (ushort_t)OT_DATA_ACCESS; 1994 rp->r_pc = otp->ot_trampoline; 1995 rp->r_npc = rp->r_pc + 4; 1996 trampolined = 1; 1997 /* 1998 * for peeks and caut_gets errors are expected 1999 */ 2000 hp = (ddi_acc_hdl_t *)otp->ot_handle; 2001 if (!hp) 2002 expected = DDI_FM_ERR_PEEK; 2003 else if (hp->ah_acc.devacc_attr_access == 2004 DDI_CAUTIOUS_ACC) 2005 expected = DDI_FM_ERR_EXPECTED; 2006 } 2007 2008 } else if (curthread->t_lofault) { 2009 aflt->flt_prot = AFLT_PROT_COPY; 2010 rp->r_g1 = EFAULT; 2011 rp->r_pc = curthread->t_lofault; 2012 rp->r_npc = rp->r_pc + 4; 2013 trampolined = 1; 2014 } 2015 } 2016 2017 /* 2018 * If we're in user mode or we're doing a protected copy, we either 2019 * want the ASTON code below to send a signal to the user process 2020 * or we want to panic if aft_panic is set. 2021 * 2022 * If we're in privileged mode and we're not doing a copy, then we 2023 * need to check if we've trampolined. If we haven't trampolined, 2024 * we should panic. 2025 */ 2026 if (!aflt->flt_priv || aflt->flt_prot == AFLT_PROT_COPY) { 2027 if (t_sfsr & (SFSR_ERRS & ~(SFSR_BERR | SFSR_TO))) 2028 aflt->flt_panic |= aft_panic; 2029 } else if (!trampolined) { 2030 aflt->flt_panic = 1; 2031 } 2032 2033 /* 2034 * If we've trampolined due to a privileged TO or BERR, or if an 2035 * unprivileged TO or BERR occurred, we don't want to enqueue an 2036 * event for that TO or BERR. Queue all other events (if any) besides 2037 * the TO/BERR. 2038 */ 2039 log_sfsr = t_sfsr; 2040 if (trampolined) { 2041 log_sfsr &= ~(SFSR_TO | SFSR_BERR); 2042 } else if (!aflt->flt_priv) { 2043 /* 2044 * User mode, suppress messages if 2045 * cpu_berr_to_verbose is not set. 2046 */ 2047 if (!cpu_berr_to_verbose) 2048 log_sfsr &= ~(SFSR_TO | SFSR_BERR); 2049 } 2050 2051 if (((log_sfsr & SFSR_ERRS) && (cpu_queue_events(&opl_flt, pr_reason, 2052 t_sfsr) == 0)) || ((t_sfsr & SFSR_ERRS) == 0)) { 2053 opl_flt.flt_type = OPL_CPU_INV_SFSR; 2054 aflt->flt_payload = FM_EREPORT_PAYLOAD_SYNC; 2055 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_SFSR, (void *)&opl_flt, 2056 sizeof (opl_async_flt_t), ue_queue, aflt->flt_panic); 2057 } 2058 2059 if (t_sfsr & (SFSR_UE|SFSR_TO|SFSR_BERR)) { 2060 cpu_run_bus_error_handlers(aflt, expected); 2061 } 2062 2063 /* 2064 * Panic here if aflt->flt_panic has been set. Enqueued errors will 2065 * be logged as part of the panic flow. 2066 */ 2067 if (aflt->flt_panic) { 2068 if (pr_reason[0] == 0) 2069 strcpy(pr_reason, "invalid SFSR "); 2070 2071 fm_panic("%sErrors(s)", pr_reason); 2072 } 2073 2074 /* 2075 * If we queued an error and we are going to return from the trap and 2076 * the error was in user mode or inside of a copy routine, set AST flag 2077 * so the queue will be drained before returning to user mode. The 2078 * AST processing will also act on our failure policy. 2079 */ 2080 if (!aflt->flt_priv || aflt->flt_prot == AFLT_PROT_COPY) { 2081 int pcb_flag = 0; 2082 2083 if (t_sfsr & (SFSR_ERRS & ~(SFSR_BERR | SFSR_TO))) 2084 pcb_flag |= ASYNC_HWERR; 2085 2086 if (t_sfsr & SFSR_BERR) 2087 pcb_flag |= ASYNC_BERR; 2088 2089 if (t_sfsr & SFSR_TO) 2090 pcb_flag |= ASYNC_BTO; 2091 2092 ttolwp(curthread)->lwp_pcb.pcb_flags |= pcb_flag; 2093 aston(curthread); 2094 } 2095 } 2096 2097 /*ARGSUSED*/ 2098 void 2099 opl_cpu_urgent_error(struct regs *rp, ulong_t p_ugesr, ulong_t tl) 2100 { 2101 opl_async_flt_t opl_flt; 2102 struct async_flt *aflt; 2103 char pr_reason[MAX_REASON_STRING]; 2104 2105 /* normalize tl */ 2106 tl = (tl >= 2 ? 1 : 0); 2107 pr_reason[0] = '\0'; 2108 2109 bzero(&opl_flt, sizeof (opl_async_flt_t)); 2110 aflt = (struct async_flt *)&opl_flt; 2111 aflt->flt_id = gethrtime_waitfree(); 2112 aflt->flt_bus_id = getprocessorid(); 2113 aflt->flt_inst = CPU->cpu_id; 2114 aflt->flt_stat = p_ugesr; 2115 aflt->flt_pc = (caddr_t)rp->r_pc; 2116 aflt->flt_class = (uchar_t)CPU_FAULT; 2117 aflt->flt_tl = tl; 2118 aflt->flt_priv = (uchar_t)(tl == 1 ? 1 : ((rp->r_tstate & TSTATE_PRIV) ? 2119 1 : 0)); 2120 aflt->flt_status = OPL_ECC_URGENT_TRAP; 2121 aflt->flt_panic = 1; 2122 /* 2123 * HW does not set mod/sid in case of urgent error. 2124 * So we have to set it here. 2125 */ 2126 opl_flt.flt_eid_mod = OPL_ERRID_CPU; 2127 opl_flt.flt_eid_sid = aflt->flt_inst; 2128 2129 if (cpu_queue_events(&opl_flt, pr_reason, p_ugesr) == 0) { 2130 opl_flt.flt_type = OPL_CPU_INV_UGESR; 2131 aflt->flt_payload = FM_EREPORT_PAYLOAD_URGENT; 2132 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_URG, (void *)&opl_flt, 2133 sizeof (opl_async_flt_t), ue_queue, aflt->flt_panic); 2134 } 2135 2136 fm_panic("Urgent Error"); 2137 } 2138 2139 /* 2140 * Initialization error counters resetting. 2141 */ 2142 /* ARGSUSED */ 2143 static void 2144 opl_ras_online(void *arg, cpu_t *cp, cyc_handler_t *hdlr, cyc_time_t *when) 2145 { 2146 hdlr->cyh_func = (cyc_func_t)ras_cntr_reset; 2147 hdlr->cyh_level = CY_LOW_LEVEL; 2148 hdlr->cyh_arg = (void *)(uintptr_t)cp->cpu_id; 2149 2150 when->cyt_when = cp->cpu_id * (((hrtime_t)NANOSEC * 10)/ NCPU); 2151 when->cyt_interval = (hrtime_t)NANOSEC * opl_async_check_interval; 2152 } 2153 2154 void 2155 cpu_mp_init(void) 2156 { 2157 cyc_omni_handler_t hdlr; 2158 2159 hdlr.cyo_online = opl_ras_online; 2160 hdlr.cyo_offline = NULL; 2161 hdlr.cyo_arg = NULL; 2162 mutex_enter(&cpu_lock); 2163 (void) cyclic_add_omni(&hdlr); 2164 mutex_exit(&cpu_lock); 2165 } 2166 2167 int heaplp_use_stlb = -1; 2168 2169 void 2170 mmu_init_kernel_pgsz(struct hat *hat) 2171 { 2172 uint_t tte = page_szc(segkmem_lpsize); 2173 uchar_t new_cext_primary, new_cext_nucleus; 2174 2175 if (heaplp_use_stlb == 0) { 2176 /* do not reprogram stlb */ 2177 tte = TTE8K; 2178 } else if (!plat_prom_preserve_kctx_is_supported()) { 2179 /* OBP does not support non-zero primary context */ 2180 tte = TTE8K; 2181 heaplp_use_stlb = 0; 2182 } 2183 2184 new_cext_nucleus = TAGACCEXT_MKSZPAIR(tte, TTE8K); 2185 new_cext_primary = TAGACCEXT_MKSZPAIR(TTE8K, tte); 2186 2187 hat->sfmmu_cext = new_cext_primary; 2188 kcontextreg = ((uint64_t)new_cext_nucleus << CTXREG_NEXT_SHIFT) | 2189 ((uint64_t)new_cext_primary << CTXREG_EXT_SHIFT); 2190 } 2191 2192 size_t 2193 mmu_get_kernel_lpsize(size_t lpsize) 2194 { 2195 uint_t tte; 2196 2197 if (lpsize == 0) { 2198 /* no setting for segkmem_lpsize in /etc/system: use default */ 2199 return (MMU_PAGESIZE4M); 2200 } 2201 2202 for (tte = TTE8K; tte <= TTE4M; tte++) { 2203 if (lpsize == TTEBYTES(tte)) 2204 return (lpsize); 2205 } 2206 2207 return (TTEBYTES(TTE8K)); 2208 } 2209 2210 /* 2211 * Support for ta 3. 2212 * We allocate here a buffer for each cpu 2213 * for saving the current register window. 2214 */ 2215 typedef struct win_regs { 2216 uint64_t l[8]; 2217 uint64_t i[8]; 2218 } win_regs_t; 2219 static void 2220 opl_ta3(void) 2221 { 2222 opl_ta3_save = (char *)kmem_alloc(NCPU * sizeof (win_regs_t), KM_SLEEP); 2223 } 2224 2225 /* 2226 * The following are functions that are unused in 2227 * OPL cpu module. They are defined here to resolve 2228 * dependencies in the "unix" module. 2229 * Unused functions that should never be called in 2230 * OPL are coded with ASSERT(0). 2231 */ 2232 2233 void 2234 cpu_disable_errors(void) 2235 {} 2236 2237 void 2238 cpu_enable_errors(void) 2239 { ASSERT(0); } 2240 2241 /*ARGSUSED*/ 2242 void 2243 cpu_ce_scrub_mem_err(struct async_flt *ecc, boolean_t t) 2244 { ASSERT(0); } 2245 2246 /*ARGSUSED*/ 2247 void 2248 cpu_faulted_enter(struct cpu *cp) 2249 {} 2250 2251 /*ARGSUSED*/ 2252 void 2253 cpu_faulted_exit(struct cpu *cp) 2254 {} 2255 2256 /*ARGSUSED*/ 2257 void 2258 cpu_check_allcpus(struct async_flt *aflt) 2259 {} 2260 2261 /*ARGSUSED*/ 2262 void 2263 cpu_ce_log_err(struct async_flt *aflt, errorq_elem_t *t) 2264 { ASSERT(0); } 2265 2266 /*ARGSUSED*/ 2267 void 2268 cpu_check_ce(int flag, uint64_t pa, caddr_t va, uint_t psz) 2269 { ASSERT(0); } 2270 2271 /*ARGSUSED*/ 2272 void 2273 cpu_ce_count_unum(struct async_flt *ecc, int len, char *unum) 2274 { ASSERT(0); } 2275 2276 /*ARGSUSED*/ 2277 void 2278 cpu_busy_ecache_scrub(struct cpu *cp) 2279 {} 2280 2281 /*ARGSUSED*/ 2282 void 2283 cpu_idle_ecache_scrub(struct cpu *cp) 2284 {} 2285 2286 /* ARGSUSED */ 2287 void 2288 cpu_change_speed(uint64_t divisor, uint64_t arg2) 2289 { ASSERT(0); } 2290 2291 void 2292 cpu_init_cache_scrub(void) 2293 {} 2294 2295 /* ARGSUSED */ 2296 int 2297 cpu_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 2298 { 2299 if (&plat_get_mem_sid) { 2300 return (plat_get_mem_sid(unum, buf, buflen, lenp)); 2301 } else { 2302 return (ENOTSUP); 2303 } 2304 } 2305 2306 /* ARGSUSED */ 2307 int 2308 cpu_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp) 2309 { 2310 if (&plat_get_mem_addr) { 2311 return (plat_get_mem_addr(unum, sid, offset, addrp)); 2312 } else { 2313 return (ENOTSUP); 2314 } 2315 } 2316 2317 /* ARGSUSED */ 2318 int 2319 cpu_get_mem_offset(uint64_t flt_addr, uint64_t *offp) 2320 { 2321 if (&plat_get_mem_offset) { 2322 return (plat_get_mem_offset(flt_addr, offp)); 2323 } else { 2324 return (ENOTSUP); 2325 } 2326 } 2327 2328 /*ARGSUSED*/ 2329 void 2330 itlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag) 2331 { ASSERT(0); } 2332 2333 /*ARGSUSED*/ 2334 void 2335 dtlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag) 2336 { ASSERT(0); } 2337 2338 /*ARGSUSED*/ 2339 void 2340 read_ecc_data(struct async_flt *aflt, short verbose, short ce_err) 2341 { ASSERT(0); } 2342 2343 /*ARGSUSED*/ 2344 int 2345 ce_scrub_xdiag_recirc(struct async_flt *aflt, errorq_t *eqp, 2346 errorq_elem_t *eqep, size_t afltoffset) 2347 { 2348 ASSERT(0); 2349 return (0); 2350 } 2351 2352 /*ARGSUSED*/ 2353 char * 2354 flt_to_error_type(struct async_flt *aflt) 2355 { 2356 ASSERT(0); 2357 return (NULL); 2358 } 2359 2360 #define PROM_SPARC64VII_MODE_PROPNAME "SPARC64-VII-mode" 2361 2362 /* 2363 * Check for existence of OPL OBP property that indicates 2364 * SPARC64-VII support. By default, only enable Jupiter 2365 * features if the property is present. It will be 2366 * present in all-Jupiter domains by OBP if the domain has 2367 * been selected by the user on the system controller to 2368 * run in Jupiter mode. Basically, this OBP property must 2369 * be present to turn on the cpu_alljupiter flag. 2370 */ 2371 static int 2372 prom_SPARC64VII_support_enabled(void) 2373 { 2374 int val; 2375 2376 return ((prom_getprop(prom_rootnode(), PROM_SPARC64VII_MODE_PROPNAME, 2377 (caddr_t)&val) == 0) ? 1 : 0); 2378 } 2379 2380 #define PROM_KCTX_PRESERVED_PROPNAME "context0-page-size-preserved" 2381 2382 /* 2383 * Check for existence of OPL OBP property that indicates support for 2384 * preserving Solaris kernel page sizes when entering OBP. We need to 2385 * check the prom tree since the ddi tree is not yet built when the 2386 * platform startup sequence is called. 2387 */ 2388 static int 2389 plat_prom_preserve_kctx_is_supported(void) 2390 { 2391 pnode_t pnode; 2392 int val; 2393 2394 /* 2395 * Check for existence of context0-page-size-preserved property 2396 * in virtual-memory prom node. 2397 */ 2398 pnode = (pnode_t)prom_getphandle(prom_mmu_ihandle()); 2399 return ((prom_getprop(pnode, PROM_KCTX_PRESERVED_PROPNAME, 2400 (caddr_t)&val) == 0) ? 1 : 0); 2401 } 2402