1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/systm.h> 30 #include <sys/ddi.h> 31 #include <sys/sysmacros.h> 32 #include <sys/archsystm.h> 33 #include <sys/vmsystm.h> 34 #include <sys/machparam.h> 35 #include <sys/machsystm.h> 36 #include <sys/machthread.h> 37 #include <sys/cpu.h> 38 #include <sys/cmp.h> 39 #include <sys/elf_SPARC.h> 40 #include <vm/vm_dep.h> 41 #include <vm/hat_sfmmu.h> 42 #include <vm/seg_kpm.h> 43 #include <sys/cpuvar.h> 44 #include <sys/opl_olympus_regs.h> 45 #include <sys/opl_module.h> 46 #include <sys/async.h> 47 #include <sys/cmn_err.h> 48 #include <sys/debug.h> 49 #include <sys/dditypes.h> 50 #include <sys/cpu_module.h> 51 #include <sys/sysmacros.h> 52 #include <sys/intreg.h> 53 #include <sys/clock.h> 54 #include <sys/platform_module.h> 55 #include <sys/ontrap.h> 56 #include <sys/panic.h> 57 #include <sys/memlist.h> 58 #include <sys/ndifm.h> 59 #include <sys/ddifm.h> 60 #include <sys/fm/protocol.h> 61 #include <sys/fm/util.h> 62 #include <sys/fm/cpu/SPARC64-VI.h> 63 #include <sys/dtrace.h> 64 #include <sys/watchpoint.h> 65 #include <sys/promif.h> 66 67 /* 68 * Internal functions. 69 */ 70 static int cpu_sync_log_err(void *flt); 71 static void cpu_payload_add_aflt(struct async_flt *, nvlist_t *, nvlist_t *); 72 static void opl_cpu_sync_error(struct regs *, ulong_t, ulong_t, uint_t, uint_t); 73 static int cpu_flt_in_memory(opl_async_flt_t *, uint64_t); 74 75 /* 76 * Error counters resetting interval. 77 */ 78 static int opl_async_check_interval = 60; /* 1 min */ 79 80 uint_t cpu_impl_dual_pgsz = 1; 81 82 /* 83 * PA[22:0] represent Displacement in Jupiter 84 * configuration space. 85 */ 86 uint_t root_phys_addr_lo_mask = 0x7fffffu; 87 88 /* 89 * set in /etc/system to control logging of user BERR/TO's 90 */ 91 int cpu_berr_to_verbose = 0; 92 93 static int min_ecache_size; 94 static uint_t priv_hcl_1; 95 static uint_t priv_hcl_2; 96 static uint_t priv_hcl_4; 97 static uint_t priv_hcl_8; 98 99 /* 100 * Olympus error log 101 */ 102 static opl_errlog_t *opl_err_log; 103 104 /* 105 * UE is classified into four classes (MEM, CHANNEL, CPU, PATH). 106 * No any other ecc_type_info insertion is allowed in between the following 107 * four UE classess. 108 */ 109 ecc_type_to_info_t ecc_type_to_info[] = { 110 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 111 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 112 FM_EREPORT_CPU_UE_MEM, 113 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 114 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 115 FM_EREPORT_CPU_UE_CHANNEL, 116 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 117 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 118 FM_EREPORT_CPU_UE_CPU, 119 SFSR_UE, "UE ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_UE, 120 "Uncorrectable ECC", FM_EREPORT_PAYLOAD_SYNC, 121 FM_EREPORT_CPU_UE_PATH, 122 SFSR_BERR, "BERR ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 123 "Bus Error", FM_EREPORT_PAYLOAD_SYNC, 124 FM_EREPORT_CPU_BERR, 125 SFSR_TO, "TO ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 126 "Bus Timeout", FM_EREPORT_PAYLOAD_SYNC, 127 FM_EREPORT_CPU_BTO, 128 SFSR_TLB_MUL, "TLB_MUL ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 129 "TLB MultiHit", FM_EREPORT_PAYLOAD_SYNC, 130 FM_EREPORT_CPU_MTLB, 131 SFSR_TLB_PRT, "TLB_PRT ", (OPL_ECC_SYNC_TRAP), OPL_CPU_SYNC_OTHERS, 132 "TLB Parity", FM_EREPORT_PAYLOAD_SYNC, 133 FM_EREPORT_CPU_TLBP, 134 135 UGESR_IAUG_CRE, "IAUG_CRE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 136 "IAUG CRE", FM_EREPORT_PAYLOAD_URGENT, 137 FM_EREPORT_CPU_CRE, 138 UGESR_IAUG_TSBCTXT, "IAUG_TSBCTXT", 139 OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 140 "IAUG TSBCTXT", FM_EREPORT_PAYLOAD_URGENT, 141 FM_EREPORT_CPU_TSBCTX, 142 UGESR_IUG_TSBP, "IUG_TSBP", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 143 "IUG TSBP", FM_EREPORT_PAYLOAD_URGENT, 144 FM_EREPORT_CPU_TSBP, 145 UGESR_IUG_PSTATE, "IUG_PSTATE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 146 "IUG PSTATE", FM_EREPORT_PAYLOAD_URGENT, 147 FM_EREPORT_CPU_PSTATE, 148 UGESR_IUG_TSTATE, "IUG_TSTATE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 149 "IUG TSTATE", FM_EREPORT_PAYLOAD_URGENT, 150 FM_EREPORT_CPU_TSTATE, 151 UGESR_IUG_F, "IUG_F", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 152 "IUG FREG", FM_EREPORT_PAYLOAD_URGENT, 153 FM_EREPORT_CPU_IUG_F, 154 UGESR_IUG_R, "IUG_R", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 155 "IUG RREG", FM_EREPORT_PAYLOAD_URGENT, 156 FM_EREPORT_CPU_IUG_R, 157 UGESR_AUG_SDC, "AUG_SDC", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 158 "AUG SDC", FM_EREPORT_PAYLOAD_URGENT, 159 FM_EREPORT_CPU_SDC, 160 UGESR_IUG_WDT, "IUG_WDT", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 161 "IUG WDT", FM_EREPORT_PAYLOAD_URGENT, 162 FM_EREPORT_CPU_WDT, 163 UGESR_IUG_DTLB, "IUG_DTLB", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 164 "IUG DTLB", FM_EREPORT_PAYLOAD_URGENT, 165 FM_EREPORT_CPU_DTLB, 166 UGESR_IUG_ITLB, "IUG_ITLB", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 167 "IUG ITLB", FM_EREPORT_PAYLOAD_URGENT, 168 FM_EREPORT_CPU_ITLB, 169 UGESR_IUG_COREERR, "IUG_COREERR", 170 OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 171 "IUG COREERR", FM_EREPORT_PAYLOAD_URGENT, 172 FM_EREPORT_CPU_CORE, 173 UGESR_MULTI_DAE, "MULTI_DAE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 174 "MULTI DAE", FM_EREPORT_PAYLOAD_URGENT, 175 FM_EREPORT_CPU_DAE, 176 UGESR_MULTI_IAE, "MULTI_IAE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 177 "MULTI IAE", FM_EREPORT_PAYLOAD_URGENT, 178 FM_EREPORT_CPU_IAE, 179 UGESR_MULTI_UGE, "MULTI_UGE", OPL_ECC_URGENT_TRAP, OPL_CPU_URGENT, 180 "MULTI UGE", FM_EREPORT_PAYLOAD_URGENT, 181 FM_EREPORT_CPU_UGE, 182 0, NULL, 0, 0, 183 NULL, 0, 0, 184 }; 185 186 int (*p2get_mem_info)(int synd_code, uint64_t paddr, 187 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 188 int *segsp, int *banksp, int *mcidp); 189 190 191 /* 192 * Setup trap handlers for 0xA, 0x32, 0x40 trap types. 193 */ 194 void 195 cpu_init_trap(void) 196 { 197 OPL_SET_TRAP(tt0_iae, opl_serr_instr); 198 OPL_SET_TRAP(tt1_iae, opl_serr_instr); 199 OPL_SET_TRAP(tt0_dae, opl_serr_instr); 200 OPL_SET_TRAP(tt1_dae, opl_serr_instr); 201 OPL_SET_TRAP(tt0_asdat, opl_ugerr_instr); 202 OPL_SET_TRAP(tt1_asdat, opl_ugerr_instr); 203 } 204 205 static int 206 getintprop(pnode_t node, char *name, int deflt) 207 { 208 int value; 209 210 switch (prom_getproplen(node, name)) { 211 case sizeof (int): 212 (void) prom_getprop(node, name, (caddr_t)&value); 213 break; 214 215 default: 216 value = deflt; 217 break; 218 } 219 220 return (value); 221 } 222 223 /* 224 * Set the magic constants of the implementation. 225 */ 226 /*ARGSUSED*/ 227 void 228 cpu_fiximp(pnode_t dnode) 229 { 230 int i, a; 231 extern int vac_size, vac_shift; 232 extern uint_t vac_mask; 233 234 static struct { 235 char *name; 236 int *var; 237 int defval; 238 } prop[] = { 239 "l1-dcache-size", &dcache_size, OPL_DCACHE_SIZE, 240 "l1-dcache-line-size", &dcache_linesize, OPL_DCACHE_LSIZE, 241 "l1-icache-size", &icache_size, OPL_ICACHE_SIZE, 242 "l1-icache-line-size", &icache_linesize, OPL_ICACHE_LSIZE, 243 "l2-cache-size", &ecache_size, OPL_ECACHE_SIZE, 244 "l2-cache-line-size", &ecache_alignsize, OPL_ECACHE_LSIZE, 245 "l2-cache-associativity", &ecache_associativity, OPL_ECACHE_NWAY 246 }; 247 248 for (i = 0; i < sizeof (prop) / sizeof (prop[0]); i++) 249 *prop[i].var = getintprop(dnode, prop[i].name, prop[i].defval); 250 251 ecache_setsize = ecache_size / ecache_associativity; 252 253 vac_size = OPL_VAC_SIZE; 254 vac_mask = MMU_PAGEMASK & (vac_size - 1); 255 i = 0; a = vac_size; 256 while (a >>= 1) 257 ++i; 258 vac_shift = i; 259 shm_alignment = vac_size; 260 vac = 1; 261 } 262 263 #ifdef OLYMPUS_C_REV_B_ERRATA_XCALL 264 /* 265 * Quick and dirty way to redefine locally in 266 * OPL the value of IDSR_BN_SETS to 31 instead 267 * of the standard 32 value. This is to workaround 268 * REV_B of Olympus_c processor's problem in handling 269 * more than 31 xcall broadcast. 270 */ 271 #undef IDSR_BN_SETS 272 #define IDSR_BN_SETS 31 273 #endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */ 274 275 void 276 send_mondo_set(cpuset_t set) 277 { 278 int lo, busy, nack, shipped = 0; 279 uint16_t i, cpuids[IDSR_BN_SETS]; 280 uint64_t idsr, nackmask = 0, busymask, curnack, curbusy; 281 uint64_t starttick, endtick, tick, lasttick; 282 #if (NCPU > IDSR_BN_SETS) 283 int index = 0; 284 int ncpuids = 0; 285 #endif 286 #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 287 int bn_sets = IDSR_BN_SETS; 288 uint64_t ver; 289 290 ASSERT(NCPU > bn_sets); 291 #endif 292 293 ASSERT(!CPUSET_ISNULL(set)); 294 starttick = lasttick = gettick(); 295 296 #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 297 ver = ultra_getver(); 298 if (((ULTRA_VER_IMPL(ver)) == OLYMPUS_C_IMPL) && 299 ((OLYMPUS_REV_MASK(ver)) == OLYMPUS_C_A)) 300 bn_sets = 1; 301 #endif 302 303 #if (NCPU <= IDSR_BN_SETS) 304 for (i = 0; i < NCPU; i++) 305 if (CPU_IN_SET(set, i)) { 306 shipit(i, shipped); 307 nackmask |= IDSR_NACK_BIT(shipped); 308 cpuids[shipped++] = i; 309 CPUSET_DEL(set, i); 310 if (CPUSET_ISNULL(set)) 311 break; 312 } 313 CPU_STATS_ADDQ(CPU, sys, xcalls, shipped); 314 #else 315 for (i = 0; i < NCPU; i++) 316 if (CPU_IN_SET(set, i)) { 317 ncpuids++; 318 319 /* 320 * Ship only to the first (IDSR_BN_SETS) CPUs. If we 321 * find we have shipped to more than (IDSR_BN_SETS) 322 * CPUs, set "index" to the highest numbered CPU in 323 * the set so we can ship to other CPUs a bit later on. 324 */ 325 #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 326 if (shipped < bn_sets) { 327 #else 328 if (shipped < IDSR_BN_SETS) { 329 #endif 330 shipit(i, shipped); 331 nackmask |= IDSR_NACK_BIT(shipped); 332 cpuids[shipped++] = i; 333 CPUSET_DEL(set, i); 334 if (CPUSET_ISNULL(set)) 335 break; 336 } else 337 index = (int)i; 338 } 339 340 CPU_STATS_ADDQ(CPU, sys, xcalls, ncpuids); 341 #endif 342 343 busymask = IDSR_NACK_TO_BUSY(nackmask); 344 busy = nack = 0; 345 endtick = starttick + xc_tick_limit; 346 for (;;) { 347 idsr = getidsr(); 348 #if (NCPU <= IDSR_BN_SETS) 349 if (idsr == 0) 350 break; 351 #else 352 if (idsr == 0 && shipped == ncpuids) 353 break; 354 #endif 355 tick = gettick(); 356 /* 357 * If there is a big jump between the current tick 358 * count and lasttick, we have probably hit a break 359 * point. Adjust endtick accordingly to avoid panic. 360 */ 361 if (tick > (lasttick + xc_tick_jump_limit)) 362 endtick += (tick - lasttick); 363 lasttick = tick; 364 if (tick > endtick) { 365 if (panic_quiesce) 366 return; 367 cmn_err(CE_CONT, "send mondo timeout " 368 "[%d NACK %d BUSY]\nIDSR 0x%" 369 "" PRIx64 " cpuids:", nack, busy, idsr); 370 #ifdef OLYMPUS_C_REV_A_ERRATA_XCALL 371 for (i = 0; i < bn_sets; i++) { 372 #else 373 for (i = 0; i < IDSR_BN_SETS; i++) { 374 #endif 375 if (idsr & (IDSR_NACK_BIT(i) | 376 IDSR_BUSY_BIT(i))) { 377 cmn_err(CE_CONT, " 0x%x", 378 cpuids[i]); 379 } 380 } 381 cmn_err(CE_CONT, "\n"); 382 cmn_err(CE_PANIC, "send_mondo_set: timeout"); 383 } 384 curnack = idsr & nackmask; 385 curbusy = idsr & busymask; 386 387 #ifdef OLYMPUS_C_REV_B_ERRATA_XCALL 388 /* 389 * Only proceed to send more xcalls if all the 390 * cpus in the previous IDSR_BN_SETS were completed. 391 */ 392 if (curbusy) { 393 busy++; 394 continue; 395 } 396 #endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */ 397 398 #if (NCPU > IDSR_BN_SETS) 399 if (shipped < ncpuids) { 400 uint64_t cpus_left; 401 uint16_t next = (uint16_t)index; 402 403 cpus_left = ~(IDSR_NACK_TO_BUSY(curnack) | curbusy) & 404 busymask; 405 406 if (cpus_left) { 407 do { 408 /* 409 * Sequence through and ship to the 410 * remainder of the CPUs in the system 411 * (e.g. other than the first 412 * (IDSR_BN_SETS)) in reverse order. 413 */ 414 lo = lowbit(cpus_left) - 1; 415 i = IDSR_BUSY_IDX(lo); 416 shipit(next, i); 417 shipped++; 418 cpuids[i] = next; 419 420 /* 421 * If we've processed all the CPUs, 422 * exit the loop now and save 423 * instructions. 424 */ 425 if (shipped == ncpuids) 426 break; 427 428 for ((index = ((int)next - 1)); 429 index >= 0; index--) 430 if (CPU_IN_SET(set, index)) { 431 next = (uint16_t)index; 432 break; 433 } 434 435 cpus_left &= ~(1ull << lo); 436 } while (cpus_left); 437 continue; 438 } 439 } 440 #endif 441 #ifndef OLYMPUS_C_REV_B_ERRATA_XCALL 442 if (curbusy) { 443 busy++; 444 continue; 445 } 446 #endif /* OLYMPUS_C_REV_B_ERRATA_XCALL */ 447 #ifdef SEND_MONDO_STATS 448 { 449 int n = gettick() - starttick; 450 if (n < 8192) 451 x_nack_stimes[n >> 7]++; 452 } 453 #endif 454 while (gettick() < (tick + sys_clock_mhz)) 455 ; 456 do { 457 lo = lowbit(curnack) - 1; 458 i = IDSR_NACK_IDX(lo); 459 shipit(cpuids[i], i); 460 curnack &= ~(1ull << lo); 461 } while (curnack); 462 nack++; 463 busy = 0; 464 } 465 #ifdef SEND_MONDO_STATS 466 { 467 int n = gettick() - starttick; 468 if (n < 8192) 469 x_set_stimes[n >> 7]++; 470 else 471 x_set_ltimes[(n >> 13) & 0xf]++; 472 } 473 x_set_cpus[shipped]++; 474 #endif 475 } 476 477 /* 478 * Cpu private initialization. 479 */ 480 void 481 cpu_init_private(struct cpu *cp) 482 { 483 if (!(IS_OLYMPUS_C(cpunodes[cp->cpu_id].implementation))) { 484 cmn_err(CE_PANIC, "CPU%d Impl %d: Only SPARC64-VI is supported", 485 cp->cpu_id, cpunodes[cp->cpu_id].implementation); 486 } 487 488 adjust_hw_copy_limits(cpunodes[cp->cpu_id].ecache_size); 489 } 490 491 void 492 cpu_setup(void) 493 { 494 extern int at_flags; 495 extern int disable_delay_tlb_flush, delay_tlb_flush; 496 extern int cpc_has_overflow_intr; 497 uint64_t cpu0_log; 498 extern uint64_t opl_cpu0_err_log; 499 500 /* 501 * Initialize Error log Scratch register for error handling. 502 */ 503 504 cpu0_log = va_to_pa(&opl_cpu0_err_log); 505 opl_error_setup(cpu0_log); 506 507 /* 508 * Enable MMU translating multiple page sizes for 509 * sITLB and sDTLB. 510 */ 511 opl_mpg_enable(); 512 513 /* 514 * Setup chip-specific trap handlers. 515 */ 516 cpu_init_trap(); 517 518 cache |= (CACHE_VAC | CACHE_PTAG | CACHE_IOCOHERENT); 519 520 at_flags = EF_SPARC_32PLUS | EF_SPARC_SUN_US1 | EF_SPARC_SUN_US3; 521 522 /* 523 * Due to the number of entries in the fully-associative tlb 524 * this may have to be tuned lower than in spitfire. 525 */ 526 pp_slots = MIN(8, MAXPP_SLOTS); 527 528 /* 529 * Block stores do not invalidate all pages of the d$, pagecopy 530 * et. al. need virtual translations with virtual coloring taken 531 * into consideration. prefetch/ldd will pollute the d$ on the 532 * load side. 533 */ 534 pp_consistent_coloring = PPAGE_STORE_VCOLORING | PPAGE_LOADS_POLLUTE; 535 536 if (use_page_coloring) { 537 do_pg_coloring = 1; 538 if (use_virtual_coloring) 539 do_virtual_coloring = 1; 540 } 541 542 isa_list = 543 "sparcv9+vis2 sparcv9+vis sparcv9 " 544 "sparcv8plus+vis2 sparcv8plus+vis sparcv8plus " 545 "sparcv8 sparcv8-fsmuld sparcv7 sparc"; 546 547 cpu_hwcap_flags = AV_SPARC_VIS | AV_SPARC_VIS2 | 548 AV_SPARC_POPC | AV_SPARC_FMAF; 549 550 /* 551 * On SPARC64-VI, there's no hole in the virtual address space 552 */ 553 hole_start = hole_end = 0; 554 555 /* 556 * The kpm mapping window. 557 * kpm_size: 558 * The size of a single kpm range. 559 * The overall size will be: kpm_size * vac_colors. 560 * kpm_vbase: 561 * The virtual start address of the kpm range within the kernel 562 * virtual address space. kpm_vbase has to be kpm_size aligned. 563 */ 564 kpm_size = (size_t)(128ull * 1024 * 1024 * 1024 * 1024); /* 128TB */ 565 kpm_size_shift = 47; 566 kpm_vbase = (caddr_t)0x8000000000000000ull; /* 8EB */ 567 kpm_smallpages = 1; 568 569 /* 570 * The traptrace code uses either %tick or %stick for 571 * timestamping. We have %stick so we can use it. 572 */ 573 traptrace_use_stick = 1; 574 575 /* 576 * SPARC64-VI has a performance counter overflow interrupt 577 */ 578 cpc_has_overflow_intr = 1; 579 580 /* 581 * Use SPARC64-VI flush-all support 582 */ 583 if (!disable_delay_tlb_flush) 584 delay_tlb_flush = 1; 585 586 /* 587 * Declare that this architecture/cpu combination does not support 588 * fpRAS. 589 */ 590 fpras_implemented = 0; 591 } 592 593 /* 594 * Called by setcpudelay 595 */ 596 void 597 cpu_init_tick_freq(void) 598 { 599 /* 600 * For SPARC64-VI we want to use the system clock rate as 601 * the basis for low level timing, due to support of mixed 602 * speed CPUs and power managment. 603 */ 604 if (system_clock_freq == 0) 605 cmn_err(CE_PANIC, "setcpudelay: invalid system_clock_freq"); 606 607 sys_tick_freq = system_clock_freq; 608 } 609 610 #ifdef SEND_MONDO_STATS 611 uint32_t x_one_stimes[64]; 612 uint32_t x_one_ltimes[16]; 613 uint32_t x_set_stimes[64]; 614 uint32_t x_set_ltimes[16]; 615 uint32_t x_set_cpus[NCPU]; 616 uint32_t x_nack_stimes[64]; 617 #endif 618 619 /* 620 * Note: A version of this function is used by the debugger via the KDI, 621 * and must be kept in sync with this version. Any changes made to this 622 * function to support new chips or to accomodate errata must also be included 623 * in the KDI-specific version. See us3_kdi.c. 624 */ 625 void 626 send_one_mondo(int cpuid) 627 { 628 int busy, nack; 629 uint64_t idsr, starttick, endtick, tick, lasttick; 630 uint64_t busymask; 631 632 CPU_STATS_ADDQ(CPU, sys, xcalls, 1); 633 starttick = lasttick = gettick(); 634 shipit(cpuid, 0); 635 endtick = starttick + xc_tick_limit; 636 busy = nack = 0; 637 busymask = IDSR_BUSY; 638 for (;;) { 639 idsr = getidsr(); 640 if (idsr == 0) 641 break; 642 643 tick = gettick(); 644 /* 645 * If there is a big jump between the current tick 646 * count and lasttick, we have probably hit a break 647 * point. Adjust endtick accordingly to avoid panic. 648 */ 649 if (tick > (lasttick + xc_tick_jump_limit)) 650 endtick += (tick - lasttick); 651 lasttick = tick; 652 if (tick > endtick) { 653 if (panic_quiesce) 654 return; 655 cmn_err(CE_PANIC, "send mondo timeout " 656 "(target 0x%x) [%d NACK %d BUSY]", 657 cpuid, nack, busy); 658 } 659 660 if (idsr & busymask) { 661 busy++; 662 continue; 663 } 664 drv_usecwait(1); 665 shipit(cpuid, 0); 666 nack++; 667 busy = 0; 668 } 669 #ifdef SEND_MONDO_STATS 670 { 671 int n = gettick() - starttick; 672 if (n < 8192) 673 x_one_stimes[n >> 7]++; 674 else 675 x_one_ltimes[(n >> 13) & 0xf]++; 676 } 677 #endif 678 } 679 680 /* 681 * init_mmu_page_sizes is set to one after the bootup time initialization 682 * via mmu_init_mmu_page_sizes, to indicate that mmu_page_sizes has a 683 * valid value. 684 * 685 * mmu_disable_ism_large_pages and mmu_disable_large_pages are the mmu-specific 686 * versions of disable_ism_large_pages and disable_large_pages, and feed back 687 * into those two hat variables at hat initialization time. 688 * 689 */ 690 int init_mmu_page_sizes = 0; 691 692 static uint_t mmu_disable_large_pages = 0; 693 static uint_t mmu_disable_ism_large_pages = ((1 << TTE64K) | 694 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 695 static uint_t mmu_disable_auto_data_large_pages = ((1 << TTE64K) | 696 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 697 static uint_t mmu_disable_auto_text_large_pages = ((1 << TTE64K) | 698 (1 << TTE512K)); 699 700 /* 701 * Re-initialize mmu_page_sizes and friends, for SPARC64-VI mmu support. 702 * Called during very early bootup from check_cpus_set(). 703 * Can be called to verify that mmu_page_sizes are set up correctly. 704 * 705 * Set Olympus defaults. We do not use the function parameter. 706 */ 707 /*ARGSUSED*/ 708 int 709 mmu_init_mmu_page_sizes(int32_t not_used) 710 { 711 if (!init_mmu_page_sizes) { 712 mmu_page_sizes = MMU_PAGE_SIZES; 713 mmu_hashcnt = MAX_HASHCNT; 714 mmu_ism_pagesize = DEFAULT_ISM_PAGESIZE; 715 mmu_exported_pagesize_mask = (1 << TTE8K) | 716 (1 << TTE64K) | (1 << TTE512K) | (1 << TTE4M) | 717 (1 << TTE32M) | (1 << TTE256M); 718 init_mmu_page_sizes = 1; 719 return (0); 720 } 721 return (1); 722 } 723 724 /* SPARC64-VI worst case DTLB parameters */ 725 #ifndef LOCKED_DTLB_ENTRIES 726 #define LOCKED_DTLB_ENTRIES 5 /* 2 user TSBs, 2 nucleus, + OBP */ 727 #endif 728 #define TOTAL_DTLB_ENTRIES 32 729 #define AVAIL_32M_ENTRIES 0 730 #define AVAIL_256M_ENTRIES 0 731 #define AVAIL_DTLB_ENTRIES (TOTAL_DTLB_ENTRIES - LOCKED_DTLB_ENTRIES) 732 static uint64_t ttecnt_threshold[MMU_PAGE_SIZES] = { 733 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES, 734 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES, 735 AVAIL_DTLB_ENTRIES, AVAIL_DTLB_ENTRIES}; 736 737 /* 738 * The function returns the mmu-specific values for the 739 * hat's disable_large_pages, disable_ism_large_pages, and 740 * disable_auto_data_large_pages and 741 * disable_text_data_large_pages variables. 742 */ 743 uint_t 744 mmu_large_pages_disabled(uint_t flag) 745 { 746 uint_t pages_disable = 0; 747 extern int use_text_pgsz64K; 748 extern int use_text_pgsz512K; 749 750 if (flag == HAT_LOAD) { 751 pages_disable = mmu_disable_large_pages; 752 } else if (flag == HAT_LOAD_SHARE) { 753 pages_disable = mmu_disable_ism_large_pages; 754 } else if (flag == HAT_AUTO_DATA) { 755 pages_disable = mmu_disable_auto_data_large_pages; 756 } else if (flag == HAT_AUTO_TEXT) { 757 pages_disable = mmu_disable_auto_text_large_pages; 758 if (use_text_pgsz512K) { 759 pages_disable &= ~(1 << TTE512K); 760 } 761 if (use_text_pgsz64K) { 762 pages_disable &= ~(1 << TTE64K); 763 } 764 } 765 return (pages_disable); 766 } 767 768 /* 769 * mmu_init_large_pages is called with the desired ism_pagesize parameter. 770 * It may be called from set_platform_defaults, if some value other than 32M 771 * is desired. mmu_ism_pagesize is the tunable. If it has a bad value, 772 * then only warn, since it would be bad form to panic due to a user typo. 773 * 774 * The function re-initializes the mmu_disable_ism_large_pages variable. 775 */ 776 void 777 mmu_init_large_pages(size_t ism_pagesize) 778 { 779 switch (ism_pagesize) { 780 case MMU_PAGESIZE4M: 781 mmu_disable_ism_large_pages = ((1 << TTE64K) | 782 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 783 mmu_disable_auto_data_large_pages = ((1 << TTE64K) | 784 (1 << TTE512K) | (1 << TTE32M) | (1 << TTE256M)); 785 break; 786 case MMU_PAGESIZE32M: 787 mmu_disable_ism_large_pages = ((1 << TTE64K) | 788 (1 << TTE512K) | (1 << TTE256M)); 789 mmu_disable_auto_data_large_pages = ((1 << TTE64K) | 790 (1 << TTE512K) | (1 << TTE4M) | (1 << TTE256M)); 791 adjust_data_maxlpsize(ism_pagesize); 792 break; 793 case MMU_PAGESIZE256M: 794 mmu_disable_ism_large_pages = ((1 << TTE64K) | 795 (1 << TTE512K) | (1 << TTE32M)); 796 mmu_disable_auto_data_large_pages = ((1 << TTE64K) | 797 (1 << TTE512K) | (1 << TTE4M) | (1 << TTE32M)); 798 adjust_data_maxlpsize(ism_pagesize); 799 break; 800 default: 801 cmn_err(CE_WARN, "Unrecognized mmu_ism_pagesize value 0x%lx", 802 ism_pagesize); 803 break; 804 } 805 } 806 807 /* 808 * Function to reprogram the TLBs when page sizes used 809 * by a process change significantly. 810 */ 811 void 812 mmu_setup_page_sizes(struct hat *hat, uint64_t *ttecnt, uint8_t *tmp_pgsz) 813 { 814 uint8_t pgsz0, pgsz1; 815 816 /* 817 * Don't program 2nd dtlb for kernel and ism hat 818 */ 819 ASSERT(hat->sfmmu_ismhat == NULL); 820 ASSERT(hat != ksfmmup); 821 822 /* 823 * hat->sfmmu_pgsz[] is an array whose elements 824 * contain a sorted order of page sizes. Element 825 * 0 is the most commonly used page size, followed 826 * by element 1, and so on. 827 * 828 * ttecnt[] is an array of per-page-size page counts 829 * mapped into the process. 830 * 831 * If the HAT's choice for page sizes is unsuitable, 832 * we can override it here. The new values written 833 * to the array will be handed back to us later to 834 * do the actual programming of the TLB hardware. 835 * 836 */ 837 pgsz0 = (uint8_t)MIN(tmp_pgsz[0], tmp_pgsz[1]); 838 pgsz1 = (uint8_t)MAX(tmp_pgsz[0], tmp_pgsz[1]); 839 840 /* 841 * This implements PAGESIZE programming of the sTLB 842 * if large TTE counts don't exceed the thresholds. 843 */ 844 if (ttecnt[pgsz0] < ttecnt_threshold[pgsz0]) 845 pgsz0 = page_szc(MMU_PAGESIZE); 846 if (ttecnt[pgsz1] < ttecnt_threshold[pgsz1]) 847 pgsz1 = page_szc(MMU_PAGESIZE); 848 tmp_pgsz[0] = pgsz0; 849 tmp_pgsz[1] = pgsz1; 850 /* otherwise, accept what the HAT chose for us */ 851 } 852 853 /* 854 * The HAT calls this function when an MMU context is allocated so that we 855 * can reprogram the large TLBs appropriately for the new process using 856 * the context. 857 * 858 * The caller must hold the HAT lock. 859 */ 860 void 861 mmu_set_ctx_page_sizes(struct hat *hat) 862 { 863 uint8_t pgsz0, pgsz1; 864 uint8_t new_cext; 865 866 ASSERT(sfmmu_hat_lock_held(hat)); 867 /* 868 * Don't program 2nd dtlb for kernel and ism hat 869 */ 870 if (hat->sfmmu_ismhat || hat == ksfmmup) 871 return; 872 873 /* 874 * If supported, reprogram the TLBs to a larger pagesize. 875 */ 876 pgsz0 = hat->sfmmu_pgsz[0]; 877 pgsz1 = hat->sfmmu_pgsz[1]; 878 ASSERT(pgsz0 < mmu_page_sizes); 879 ASSERT(pgsz1 < mmu_page_sizes); 880 new_cext = TAGACCEXT_MKSZPAIR(pgsz1, pgsz0); 881 if (hat->sfmmu_cext != new_cext) { 882 #ifdef DEBUG 883 int i; 884 /* 885 * assert cnum should be invalid, this is because pagesize 886 * can only be changed after a proc's ctxs are invalidated. 887 */ 888 for (i = 0; i < max_mmu_ctxdoms; i++) { 889 ASSERT(hat->sfmmu_ctxs[i].cnum == INVALID_CONTEXT); 890 } 891 #endif /* DEBUG */ 892 hat->sfmmu_cext = new_cext; 893 } 894 /* 895 * sfmmu_setctx_sec() will take care of the 896 * rest of the dirty work for us. 897 */ 898 } 899 900 /* 901 * This function assumes that there are either four or six supported page 902 * sizes and at most two programmable TLBs, so we need to decide which 903 * page sizes are most important and then adjust the TLB page sizes 904 * accordingly (if supported). 905 * 906 * If these assumptions change, this function will need to be 907 * updated to support whatever the new limits are. 908 */ 909 void 910 mmu_check_page_sizes(sfmmu_t *sfmmup, uint64_t *ttecnt) 911 { 912 uint64_t sortcnt[MMU_PAGE_SIZES]; 913 uint8_t tmp_pgsz[MMU_PAGE_SIZES]; 914 uint8_t i, j, max; 915 uint16_t oldval, newval; 916 917 /* 918 * We only consider reprogramming the TLBs if one or more of 919 * the two most used page sizes changes and we're using 920 * large pages in this process. 921 */ 922 if (sfmmup->sfmmu_flags & HAT_LGPG_FLAGS) { 923 /* Sort page sizes. */ 924 for (i = 0; i < mmu_page_sizes; i++) { 925 sortcnt[i] = ttecnt[i]; 926 } 927 for (j = 0; j < mmu_page_sizes; j++) { 928 for (i = mmu_page_sizes - 1, max = 0; i > 0; i--) { 929 if (sortcnt[i] > sortcnt[max]) 930 max = i; 931 } 932 tmp_pgsz[j] = max; 933 sortcnt[max] = 0; 934 } 935 936 oldval = sfmmup->sfmmu_pgsz[0] << 8 | sfmmup->sfmmu_pgsz[1]; 937 938 mmu_setup_page_sizes(sfmmup, ttecnt, tmp_pgsz); 939 940 /* Check 2 largest values after the sort. */ 941 newval = tmp_pgsz[0] << 8 | tmp_pgsz[1]; 942 if (newval != oldval) { 943 sfmmu_reprog_pgsz_arr(sfmmup, tmp_pgsz); 944 } 945 } 946 } 947 948 /* 949 * Return processor specific async error structure 950 * size used. 951 */ 952 int 953 cpu_aflt_size(void) 954 { 955 return (sizeof (opl_async_flt_t)); 956 } 957 958 /* 959 * The cpu_sync_log_err() function is called via the [uc]e_drain() function to 960 * post-process CPU events that are dequeued. As such, it can be invoked 961 * from softint context, from AST processing in the trap() flow, or from the 962 * panic flow. We decode the CPU-specific data, and take appropriate actions. 963 * Historically this entry point was used to log the actual cmn_err(9F) text; 964 * now with FMA it is used to prepare 'flt' to be converted into an ereport. 965 * With FMA this function now also returns a flag which indicates to the 966 * caller whether the ereport should be posted (1) or suppressed (0). 967 */ 968 /*ARGSUSED*/ 969 static int 970 cpu_sync_log_err(void *flt) 971 { 972 opl_async_flt_t *opl_flt = (opl_async_flt_t *)flt; 973 struct async_flt *aflt = (struct async_flt *)flt; 974 975 /* 976 * No extra processing of urgent error events. 977 * Always generate ereports for these events. 978 */ 979 if (aflt->flt_status == OPL_ECC_URGENT_TRAP) 980 return (1); 981 982 /* 983 * Additional processing for synchronous errors. 984 */ 985 switch (opl_flt->flt_type) { 986 case OPL_CPU_INV_SFSR: 987 return (1); 988 989 case OPL_CPU_SYNC_UE: 990 /* 991 * The validity: SFSR_MK_UE bit has been checked 992 * in opl_cpu_sync_error() 993 * No more check is required. 994 * 995 * opl_flt->flt_eid_mod and flt_eid_sid have been set by H/W, 996 * and they have been retrieved in cpu_queue_events() 997 */ 998 999 if (opl_flt->flt_eid_mod == OPL_ERRID_MEM) { 1000 ASSERT(aflt->flt_in_memory); 1001 /* 1002 * We want to skip logging only if ALL the following 1003 * conditions are true: 1004 * 1005 * 1. We are not panicing already. 1006 * 2. The error is a memory error. 1007 * 3. There is only one error. 1008 * 4. The error is on a retired page. 1009 * 5. The error occurred under on_trap 1010 * protection AFLT_PROT_EC 1011 */ 1012 if (!panicstr && aflt->flt_prot == AFLT_PROT_EC && 1013 page_retire_check(aflt->flt_addr, NULL) == 0) { 1014 /* 1015 * Do not log an error from 1016 * the retired page 1017 */ 1018 softcall(ecc_page_zero, (void *)aflt->flt_addr); 1019 return (0); 1020 } 1021 if (!panicstr) 1022 cpu_page_retire(opl_flt); 1023 } 1024 return (1); 1025 1026 case OPL_CPU_SYNC_OTHERS: 1027 /* 1028 * For the following error cases, the processor HW does 1029 * not set the flt_eid_mod/flt_eid_sid. Instead, SW will attempt 1030 * to assign appropriate values here to reflect what we 1031 * think is the most likely cause of the problem w.r.t to 1032 * the particular error event. For Buserr and timeout 1033 * error event, we will assign OPL_ERRID_CHANNEL as the 1034 * most likely reason. For TLB parity or multiple hit 1035 * error events, we will assign the reason as 1036 * OPL_ERRID_CPU (cpu related problem) and set the 1037 * flt_eid_sid to point to the cpuid. 1038 */ 1039 1040 if (opl_flt->flt_bit & (SFSR_BERR|SFSR_TO)) { 1041 /* 1042 * flt_eid_sid will not be used for this case. 1043 */ 1044 opl_flt->flt_eid_mod = OPL_ERRID_CHANNEL; 1045 } 1046 if (opl_flt->flt_bit & (SFSR_TLB_MUL|SFSR_TLB_PRT)) { 1047 opl_flt->flt_eid_mod = OPL_ERRID_CPU; 1048 opl_flt->flt_eid_sid = aflt->flt_inst; 1049 } 1050 1051 /* 1052 * In case of no effective error bit 1053 */ 1054 if ((opl_flt->flt_bit & SFSR_ERRS) == 0) { 1055 opl_flt->flt_eid_mod = OPL_ERRID_CPU; 1056 opl_flt->flt_eid_sid = aflt->flt_inst; 1057 } 1058 break; 1059 1060 default: 1061 return (1); 1062 } 1063 return (1); 1064 } 1065 1066 /* 1067 * Retire the bad page that may contain the flushed error. 1068 */ 1069 void 1070 cpu_page_retire(opl_async_flt_t *opl_flt) 1071 { 1072 struct async_flt *aflt = (struct async_flt *)opl_flt; 1073 (void) page_retire(aflt->flt_addr, PR_UE); 1074 } 1075 1076 /* 1077 * Invoked by error_init() early in startup and therefore before 1078 * startup_errorq() is called to drain any error Q - 1079 * 1080 * startup() 1081 * startup_end() 1082 * error_init() 1083 * cpu_error_init() 1084 * errorq_init() 1085 * errorq_drain() 1086 * start_other_cpus() 1087 * 1088 * The purpose of this routine is to create error-related taskqs. Taskqs 1089 * are used for this purpose because cpu_lock can't be grabbed from interrupt 1090 * context. 1091 * 1092 */ 1093 /*ARGSUSED*/ 1094 void 1095 cpu_error_init(int items) 1096 { 1097 opl_err_log = (opl_errlog_t *) 1098 kmem_alloc(ERRLOG_ALLOC_SZ, KM_SLEEP); 1099 if ((uint64_t)opl_err_log & MMU_PAGEOFFSET) 1100 cmn_err(CE_PANIC, "The base address of the error log " 1101 "is not page aligned"); 1102 } 1103 1104 /* 1105 * We route all errors through a single switch statement. 1106 */ 1107 void 1108 cpu_ue_log_err(struct async_flt *aflt) 1109 { 1110 switch (aflt->flt_class) { 1111 case CPU_FAULT: 1112 if (cpu_sync_log_err(aflt)) 1113 cpu_ereport_post(aflt); 1114 break; 1115 1116 case BUS_FAULT: 1117 bus_async_log_err(aflt); 1118 break; 1119 1120 default: 1121 cmn_err(CE_WARN, "discarding async error %p with invalid " 1122 "fault class (0x%x)", (void *)aflt, aflt->flt_class); 1123 return; 1124 } 1125 } 1126 1127 /* 1128 * Routine for panic hook callback from panic_idle(). 1129 * 1130 * Nothing to do here. 1131 */ 1132 void 1133 cpu_async_panic_callb(void) 1134 { 1135 } 1136 1137 /* 1138 * Routine to return a string identifying the physical name 1139 * associated with a memory/cache error. 1140 */ 1141 /*ARGSUSED*/ 1142 int 1143 cpu_get_mem_unum(int synd_status, ushort_t flt_synd, uint64_t flt_stat, 1144 uint64_t flt_addr, int flt_bus_id, int flt_in_memory, 1145 ushort_t flt_status, char *buf, int buflen, int *lenp) 1146 { 1147 int synd_code; 1148 int ret; 1149 1150 /* 1151 * An AFSR of -1 defaults to a memory syndrome. 1152 */ 1153 synd_code = (int)flt_synd; 1154 1155 if (&plat_get_mem_unum) { 1156 if ((ret = plat_get_mem_unum(synd_code, flt_addr, flt_bus_id, 1157 flt_in_memory, flt_status, buf, buflen, lenp)) != 0) { 1158 buf[0] = '\0'; 1159 *lenp = 0; 1160 } 1161 return (ret); 1162 } 1163 buf[0] = '\0'; 1164 *lenp = 0; 1165 return (ENOTSUP); 1166 } 1167 1168 /* 1169 * Wrapper for cpu_get_mem_unum() routine that takes an 1170 * async_flt struct rather than explicit arguments. 1171 */ 1172 int 1173 cpu_get_mem_unum_aflt(int synd_status, struct async_flt *aflt, 1174 char *buf, int buflen, int *lenp) 1175 { 1176 /* 1177 * We always pass -1 so that cpu_get_mem_unum will interpret this as a 1178 * memory error. 1179 */ 1180 return (cpu_get_mem_unum(synd_status, aflt->flt_synd, 1181 (uint64_t)-1, 1182 aflt->flt_addr, aflt->flt_bus_id, aflt->flt_in_memory, 1183 aflt->flt_status, buf, buflen, lenp)); 1184 } 1185 1186 /* 1187 * This routine is a more generic interface to cpu_get_mem_unum() 1188 * that may be used by other modules (e.g. mm). 1189 */ 1190 /*ARGSUSED*/ 1191 int 1192 cpu_get_mem_name(uint64_t synd, uint64_t *afsr, uint64_t afar, 1193 char *buf, int buflen, int *lenp) 1194 { 1195 int synd_status, flt_in_memory, ret; 1196 ushort_t flt_status = 0; 1197 char unum[UNUM_NAMLEN]; 1198 1199 /* 1200 * Check for an invalid address. 1201 */ 1202 if (afar == (uint64_t)-1) 1203 return (ENXIO); 1204 1205 if (synd == (uint64_t)-1) 1206 synd_status = AFLT_STAT_INVALID; 1207 else 1208 synd_status = AFLT_STAT_VALID; 1209 1210 flt_in_memory = (*afsr & SFSR_MEMORY) && 1211 pf_is_memory(afar >> MMU_PAGESHIFT); 1212 1213 ret = cpu_get_mem_unum(synd_status, (ushort_t)synd, *afsr, afar, 1214 CPU->cpu_id, flt_in_memory, flt_status, unum, 1215 UNUM_NAMLEN, lenp); 1216 if (ret != 0) 1217 return (ret); 1218 1219 if (*lenp >= buflen) 1220 return (ENAMETOOLONG); 1221 1222 (void) strncpy(buf, unum, buflen); 1223 1224 return (0); 1225 } 1226 1227 /* 1228 * Routine to return memory information associated 1229 * with a physical address and syndrome. 1230 */ 1231 /*ARGSUSED*/ 1232 int 1233 cpu_get_mem_info(uint64_t synd, uint64_t afar, 1234 uint64_t *mem_sizep, uint64_t *seg_sizep, uint64_t *bank_sizep, 1235 int *segsp, int *banksp, int *mcidp) 1236 { 1237 int synd_code = (int)synd; 1238 1239 if (afar == (uint64_t)-1) 1240 return (ENXIO); 1241 1242 if (p2get_mem_info != NULL) 1243 return ((p2get_mem_info)(synd_code, afar, 1244 mem_sizep, seg_sizep, bank_sizep, 1245 segsp, banksp, mcidp)); 1246 else 1247 return (ENOTSUP); 1248 } 1249 1250 /* 1251 * Routine to return a string identifying the physical 1252 * name associated with a cpuid. 1253 */ 1254 int 1255 cpu_get_cpu_unum(int cpuid, char *buf, int buflen, int *lenp) 1256 { 1257 int ret; 1258 char unum[UNUM_NAMLEN]; 1259 1260 if (&plat_get_cpu_unum) { 1261 if ((ret = plat_get_cpu_unum(cpuid, unum, UNUM_NAMLEN, lenp)) 1262 != 0) 1263 return (ret); 1264 } else { 1265 return (ENOTSUP); 1266 } 1267 1268 if (*lenp >= buflen) 1269 return (ENAMETOOLONG); 1270 1271 (void) strncpy(buf, unum, *lenp); 1272 1273 return (0); 1274 } 1275 1276 /* 1277 * This routine exports the name buffer size. 1278 */ 1279 size_t 1280 cpu_get_name_bufsize() 1281 { 1282 return (UNUM_NAMLEN); 1283 } 1284 1285 /* 1286 * Flush the entire ecache by ASI_L2_CNTL.U2_FLUSH 1287 */ 1288 void 1289 cpu_flush_ecache(void) 1290 { 1291 flush_ecache(ecache_flushaddr, cpunodes[CPU->cpu_id].ecache_size, 1292 cpunodes[CPU->cpu_id].ecache_linesize); 1293 } 1294 1295 static uint8_t 1296 flt_to_trap_type(struct async_flt *aflt) 1297 { 1298 if (aflt->flt_status & OPL_ECC_ISYNC_TRAP) 1299 return (TRAP_TYPE_ECC_I); 1300 if (aflt->flt_status & OPL_ECC_DSYNC_TRAP) 1301 return (TRAP_TYPE_ECC_D); 1302 if (aflt->flt_status & OPL_ECC_URGENT_TRAP) 1303 return (TRAP_TYPE_URGENT); 1304 return (-1); 1305 } 1306 1307 /* 1308 * Encode the data saved in the opl_async_flt_t struct into 1309 * the FM ereport payload. 1310 */ 1311 /* ARGSUSED */ 1312 static void 1313 cpu_payload_add_aflt(struct async_flt *aflt, nvlist_t *payload, 1314 nvlist_t *resource) 1315 { 1316 opl_async_flt_t *opl_flt = (opl_async_flt_t *)aflt; 1317 char unum[UNUM_NAMLEN]; 1318 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1319 int len; 1320 1321 1322 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_SFSR) { 1323 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SFSR, 1324 DATA_TYPE_UINT64, aflt->flt_stat, NULL); 1325 } 1326 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_SFAR) { 1327 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_SFAR, 1328 DATA_TYPE_UINT64, aflt->flt_addr, NULL); 1329 } 1330 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_UGESR) { 1331 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_UGESR, 1332 DATA_TYPE_UINT64, aflt->flt_stat, NULL); 1333 } 1334 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_PC) { 1335 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_PC, 1336 DATA_TYPE_UINT64, (uint64_t)aflt->flt_pc, NULL); 1337 } 1338 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_TL) { 1339 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_TL, 1340 DATA_TYPE_UINT8, (uint8_t)aflt->flt_tl, NULL); 1341 } 1342 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_TT) { 1343 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_TT, 1344 DATA_TYPE_UINT8, flt_to_trap_type(aflt), NULL); 1345 } 1346 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_PRIV) { 1347 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_PRIV, 1348 DATA_TYPE_BOOLEAN_VALUE, 1349 (aflt->flt_priv ? B_TRUE : B_FALSE), NULL); 1350 } 1351 if (aflt->flt_payload & FM_EREPORT_PAYLOAD_FLAG_FLT_STATUS) { 1352 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_FLT_STATUS, 1353 DATA_TYPE_UINT64, (uint64_t)aflt->flt_status, NULL); 1354 } 1355 1356 switch (opl_flt->flt_eid_mod) { 1357 case OPL_ERRID_CPU: 1358 (void) snprintf(sbuf, sizeof (sbuf), "%llX", 1359 (u_longlong_t)cpunodes[opl_flt->flt_eid_sid].device_id); 1360 (void) fm_fmri_cpu_set(resource, FM_CPU_SCHEME_VERSION, 1361 NULL, opl_flt->flt_eid_sid, 1362 (uint8_t *)&cpunodes[opl_flt->flt_eid_sid].version, 1363 sbuf); 1364 fm_payload_set(payload, 1365 FM_EREPORT_PAYLOAD_NAME_RESOURCE, 1366 DATA_TYPE_NVLIST, resource, NULL); 1367 break; 1368 1369 case OPL_ERRID_CHANNEL: 1370 /* 1371 * No resource is created but the cpumem DE will find 1372 * the defective path by retreiving EID from SFSR which is 1373 * included in the payload. 1374 */ 1375 break; 1376 1377 case OPL_ERRID_MEM: 1378 (void) cpu_get_mem_unum_aflt(0, aflt, unum, UNUM_NAMLEN, &len); 1379 (void) fm_fmri_mem_set(resource, FM_MEM_SCHEME_VERSION, 1380 NULL, unum, NULL, (uint64_t)-1); 1381 fm_payload_set(payload, FM_EREPORT_PAYLOAD_NAME_RESOURCE, 1382 DATA_TYPE_NVLIST, resource, NULL); 1383 break; 1384 1385 case OPL_ERRID_PATH: 1386 /* 1387 * No resource is created but the cpumem DE will find 1388 * the defective path by retreiving EID from SFSR which is 1389 * included in the payload. 1390 */ 1391 break; 1392 } 1393 } 1394 1395 /* 1396 * Returns whether fault address is valid for this error bit and 1397 * whether the address is "in memory" (i.e. pf_is_memory returns 1). 1398 */ 1399 /*ARGSUSED*/ 1400 static int 1401 cpu_flt_in_memory(opl_async_flt_t *opl_flt, uint64_t t_afsr_bit) 1402 { 1403 struct async_flt *aflt = (struct async_flt *)opl_flt; 1404 1405 if (aflt->flt_status & (OPL_ECC_SYNC_TRAP)) { 1406 return ((t_afsr_bit & SFSR_MEMORY) && 1407 pf_is_memory(aflt->flt_addr >> MMU_PAGESHIFT)); 1408 } 1409 return (0); 1410 } 1411 1412 /* 1413 * In OPL SCF does the stick synchronization. 1414 */ 1415 void 1416 sticksync_slave(void) 1417 { 1418 } 1419 1420 /* 1421 * In OPL SCF does the stick synchronization. 1422 */ 1423 void 1424 sticksync_master(void) 1425 { 1426 } 1427 1428 /* 1429 * Cpu private unitialization. OPL cpus do not use the private area. 1430 */ 1431 void 1432 cpu_uninit_private(struct cpu *cp) 1433 { 1434 cmp_delete_cpu(cp->cpu_id); 1435 } 1436 1437 /* 1438 * Always flush an entire cache. 1439 */ 1440 void 1441 cpu_error_ecache_flush(void) 1442 { 1443 cpu_flush_ecache(); 1444 } 1445 1446 void 1447 cpu_ereport_post(struct async_flt *aflt) 1448 { 1449 char *cpu_type, buf[FM_MAX_CLASS]; 1450 nv_alloc_t *nva = NULL; 1451 nvlist_t *ereport, *detector, *resource; 1452 errorq_elem_t *eqep; 1453 char sbuf[21]; /* sizeof (UINT64_MAX) + '\0' */ 1454 1455 if (aflt->flt_panic || panicstr) { 1456 eqep = errorq_reserve(ereport_errorq); 1457 if (eqep == NULL) 1458 return; 1459 ereport = errorq_elem_nvl(ereport_errorq, eqep); 1460 nva = errorq_elem_nva(ereport_errorq, eqep); 1461 } else { 1462 ereport = fm_nvlist_create(nva); 1463 } 1464 1465 /* 1466 * Create the scheme "cpu" FMRI. 1467 */ 1468 detector = fm_nvlist_create(nva); 1469 resource = fm_nvlist_create(nva); 1470 switch (cpunodes[aflt->flt_inst].implementation) { 1471 case OLYMPUS_C_IMPL: 1472 cpu_type = FM_EREPORT_CPU_SPARC64_VI; 1473 break; 1474 default: 1475 cpu_type = FM_EREPORT_CPU_UNSUPPORTED; 1476 break; 1477 } 1478 (void) snprintf(sbuf, sizeof (sbuf), "%llX", 1479 (u_longlong_t)cpunodes[aflt->flt_inst].device_id); 1480 (void) fm_fmri_cpu_set(detector, FM_CPU_SCHEME_VERSION, NULL, 1481 aflt->flt_inst, (uint8_t *)&cpunodes[aflt->flt_inst].version, 1482 sbuf); 1483 1484 /* 1485 * Encode all the common data into the ereport. 1486 */ 1487 (void) snprintf(buf, FM_MAX_CLASS, "%s.%s.%s", 1488 FM_ERROR_CPU, cpu_type, aflt->flt_erpt_class); 1489 1490 fm_ereport_set(ereport, FM_EREPORT_VERSION, buf, 1491 fm_ena_generate(aflt->flt_id, FM_ENA_FMT1), detector, NULL); 1492 1493 /* 1494 * Encode the error specific data that was saved in 1495 * the async_flt structure into the ereport. 1496 */ 1497 cpu_payload_add_aflt(aflt, ereport, resource); 1498 1499 if (aflt->flt_panic || panicstr) { 1500 errorq_commit(ereport_errorq, eqep, ERRORQ_SYNC); 1501 } else { 1502 (void) fm_ereport_post(ereport, EVCH_TRYHARD); 1503 fm_nvlist_destroy(ereport, FM_NVA_FREE); 1504 fm_nvlist_destroy(detector, FM_NVA_FREE); 1505 fm_nvlist_destroy(resource, FM_NVA_FREE); 1506 } 1507 } 1508 1509 void 1510 cpu_run_bus_error_handlers(struct async_flt *aflt, int expected) 1511 { 1512 int status; 1513 ddi_fm_error_t de; 1514 1515 bzero(&de, sizeof (ddi_fm_error_t)); 1516 1517 de.fme_version = DDI_FME_VERSION; 1518 de.fme_ena = fm_ena_generate(aflt->flt_id, FM_ENA_FMT1); 1519 de.fme_flag = expected; 1520 de.fme_bus_specific = (void *)aflt->flt_addr; 1521 status = ndi_fm_handler_dispatch(ddi_root_node(), NULL, &de); 1522 if ((aflt->flt_prot == AFLT_PROT_NONE) && (status == DDI_FM_FATAL)) 1523 aflt->flt_panic = 1; 1524 } 1525 1526 void 1527 cpu_errorq_dispatch(char *error_class, void *payload, size_t payload_sz, 1528 errorq_t *eqp, uint_t flag) 1529 { 1530 struct async_flt *aflt = (struct async_flt *)payload; 1531 1532 aflt->flt_erpt_class = error_class; 1533 errorq_dispatch(eqp, payload, payload_sz, flag); 1534 } 1535 1536 void 1537 adjust_hw_copy_limits(int ecache_size) 1538 { 1539 /* 1540 * Set hw copy limits. 1541 * 1542 * /etc/system will be parsed later and can override one or more 1543 * of these settings. 1544 * 1545 * At this time, ecache size seems only mildly relevant. 1546 * We seem to run into issues with the d-cache and stalls 1547 * we see on misses. 1548 * 1549 * Cycle measurement indicates that 2 byte aligned copies fare 1550 * little better than doing things with VIS at around 512 bytes. 1551 * 4 byte aligned shows promise until around 1024 bytes. 8 Byte 1552 * aligned is faster whenever the source and destination data 1553 * in cache and the total size is less than 2 Kbytes. The 2K 1554 * limit seems to be driven by the 2K write cache. 1555 * When more than 2K of copies are done in non-VIS mode, stores 1556 * backup in the write cache. In VIS mode, the write cache is 1557 * bypassed, allowing faster cache-line writes aligned on cache 1558 * boundaries. 1559 * 1560 * In addition, in non-VIS mode, there is no prefetching, so 1561 * for larger copies, the advantage of prefetching to avoid even 1562 * occasional cache misses is enough to justify using the VIS code. 1563 * 1564 * During testing, it was discovered that netbench ran 3% slower 1565 * when hw_copy_limit_8 was 2K or larger. Apparently for server 1566 * applications, data is only used once (copied to the output 1567 * buffer, then copied by the network device off the system). Using 1568 * the VIS copy saves more L2 cache state. Network copies are 1569 * around 1.3K to 1.5K in size for historical reasons. 1570 * 1571 * Therefore, a limit of 1K bytes will be used for the 8 byte 1572 * aligned copy even for large caches and 8 MB ecache. The 1573 * infrastructure to allow different limits for different sized 1574 * caches is kept to allow further tuning in later releases. 1575 */ 1576 1577 if (min_ecache_size == 0 && use_hw_bcopy) { 1578 /* 1579 * First time through - should be before /etc/system 1580 * is read. 1581 * Could skip the checks for zero but this lets us 1582 * preserve any debugger rewrites. 1583 */ 1584 if (hw_copy_limit_1 == 0) { 1585 hw_copy_limit_1 = VIS_COPY_THRESHOLD; 1586 priv_hcl_1 = hw_copy_limit_1; 1587 } 1588 if (hw_copy_limit_2 == 0) { 1589 hw_copy_limit_2 = 2 * VIS_COPY_THRESHOLD; 1590 priv_hcl_2 = hw_copy_limit_2; 1591 } 1592 if (hw_copy_limit_4 == 0) { 1593 hw_copy_limit_4 = 4 * VIS_COPY_THRESHOLD; 1594 priv_hcl_4 = hw_copy_limit_4; 1595 } 1596 if (hw_copy_limit_8 == 0) { 1597 hw_copy_limit_8 = 4 * VIS_COPY_THRESHOLD; 1598 priv_hcl_8 = hw_copy_limit_8; 1599 } 1600 min_ecache_size = ecache_size; 1601 } else { 1602 /* 1603 * MP initialization. Called *after* /etc/system has 1604 * been parsed. One CPU has already been initialized. 1605 * Need to cater for /etc/system having scragged one 1606 * of our values. 1607 */ 1608 if (ecache_size == min_ecache_size) { 1609 /* 1610 * Same size ecache. We do nothing unless we 1611 * have a pessimistic ecache setting. In that 1612 * case we become more optimistic (if the cache is 1613 * large enough). 1614 */ 1615 if (hw_copy_limit_8 == 4 * VIS_COPY_THRESHOLD) { 1616 /* 1617 * Need to adjust hw_copy_limit* from our 1618 * pessimistic uniprocessor value to a more 1619 * optimistic UP value *iff* it hasn't been 1620 * reset. 1621 */ 1622 if ((ecache_size > 1048576) && 1623 (priv_hcl_8 == hw_copy_limit_8)) { 1624 if (ecache_size <= 2097152) 1625 hw_copy_limit_8 = 4 * 1626 VIS_COPY_THRESHOLD; 1627 else if (ecache_size <= 4194304) 1628 hw_copy_limit_8 = 4 * 1629 VIS_COPY_THRESHOLD; 1630 else 1631 hw_copy_limit_8 = 4 * 1632 VIS_COPY_THRESHOLD; 1633 priv_hcl_8 = hw_copy_limit_8; 1634 } 1635 } 1636 } else if (ecache_size < min_ecache_size) { 1637 /* 1638 * A different ecache size. Can this even happen? 1639 */ 1640 if (priv_hcl_8 == hw_copy_limit_8) { 1641 /* 1642 * The previous value that we set 1643 * is unchanged (i.e., it hasn't been 1644 * scragged by /etc/system). Rewrite it. 1645 */ 1646 if (ecache_size <= 1048576) 1647 hw_copy_limit_8 = 8 * 1648 VIS_COPY_THRESHOLD; 1649 else if (ecache_size <= 2097152) 1650 hw_copy_limit_8 = 8 * 1651 VIS_COPY_THRESHOLD; 1652 else if (ecache_size <= 4194304) 1653 hw_copy_limit_8 = 8 * 1654 VIS_COPY_THRESHOLD; 1655 else 1656 hw_copy_limit_8 = 10 * 1657 VIS_COPY_THRESHOLD; 1658 priv_hcl_8 = hw_copy_limit_8; 1659 min_ecache_size = ecache_size; 1660 } 1661 } 1662 } 1663 } 1664 1665 #define VIS_BLOCKSIZE 64 1666 1667 int 1668 dtrace_blksuword32_err(uintptr_t addr, uint32_t *data) 1669 { 1670 int ret, watched; 1671 1672 watched = watch_disable_addr((void *)addr, VIS_BLOCKSIZE, S_WRITE); 1673 ret = dtrace_blksuword32(addr, data, 0); 1674 if (watched) 1675 watch_enable_addr((void *)addr, VIS_BLOCKSIZE, S_WRITE); 1676 1677 return (ret); 1678 } 1679 1680 void 1681 opl_cpu_reg_init() 1682 { 1683 uint64_t this_cpu_log; 1684 1685 /* 1686 * We do not need to re-initialize cpu0 registers. 1687 */ 1688 if (cpu[getprocessorid()] == &cpu0) 1689 return; 1690 1691 /* 1692 * Initialize Error log Scratch register for error handling. 1693 */ 1694 1695 this_cpu_log = va_to_pa((void*)(((uint64_t)opl_err_log) + 1696 ERRLOG_BUFSZ * (getprocessorid()))); 1697 opl_error_setup(this_cpu_log); 1698 1699 /* 1700 * Enable MMU translating multiple page sizes for 1701 * sITLB and sDTLB. 1702 */ 1703 opl_mpg_enable(); 1704 } 1705 1706 /* 1707 * Queue one event in ue_queue based on ecc_type_to_info entry. 1708 */ 1709 static void 1710 cpu_queue_one_event(opl_async_flt_t *opl_flt, char *reason, 1711 ecc_type_to_info_t *eccp) 1712 { 1713 struct async_flt *aflt = (struct async_flt *)opl_flt; 1714 1715 if (reason && 1716 strlen(reason) + strlen(eccp->ec_reason) < MAX_REASON_STRING) { 1717 (void) strcat(reason, eccp->ec_reason); 1718 } 1719 1720 opl_flt->flt_bit = eccp->ec_afsr_bit; 1721 opl_flt->flt_type = eccp->ec_flt_type; 1722 aflt->flt_in_memory = cpu_flt_in_memory(opl_flt, opl_flt->flt_bit); 1723 aflt->flt_payload = eccp->ec_err_payload; 1724 1725 ASSERT(aflt->flt_status & (OPL_ECC_SYNC_TRAP|OPL_ECC_URGENT_TRAP)); 1726 cpu_errorq_dispatch(eccp->ec_err_class, 1727 (void *)opl_flt, sizeof (opl_async_flt_t), 1728 ue_queue, 1729 aflt->flt_panic); 1730 } 1731 1732 /* 1733 * Queue events on async event queue one event per error bit. 1734 * Return number of events queued. 1735 */ 1736 int 1737 cpu_queue_events(opl_async_flt_t *opl_flt, char *reason, uint64_t t_afsr_errs) 1738 { 1739 struct async_flt *aflt = (struct async_flt *)opl_flt; 1740 ecc_type_to_info_t *eccp; 1741 int nevents = 0; 1742 1743 /* 1744 * Queue expected errors, error bit and fault type must must match 1745 * in the ecc_type_to_info table. 1746 */ 1747 for (eccp = ecc_type_to_info; t_afsr_errs != 0 && eccp->ec_desc != NULL; 1748 eccp++) { 1749 if ((eccp->ec_afsr_bit & t_afsr_errs) != 0 && 1750 (eccp->ec_flags & aflt->flt_status) != 0) { 1751 /* 1752 * UE error event can be further 1753 * classified/breakdown into finer granularity 1754 * based on the flt_eid_mod value set by HW. We do 1755 * special handling here so that we can report UE 1756 * error in finer granularity as ue_mem, 1757 * ue_channel, ue_cpu or ue_path. 1758 */ 1759 if (eccp->ec_flt_type == OPL_CPU_SYNC_UE) { 1760 opl_flt->flt_eid_mod = 1761 (aflt->flt_stat & SFSR_EID_MOD) 1762 >> SFSR_EID_MOD_SHIFT; 1763 opl_flt->flt_eid_sid = 1764 (aflt->flt_stat & SFSR_EID_SID) 1765 >> SFSR_EID_SID_SHIFT; 1766 /* 1767 * Need to advance eccp pointer by flt_eid_mod 1768 * so that we get an appropriate ecc pointer 1769 * 1770 * EID # of advances 1771 * ---------------------------------- 1772 * OPL_ERRID_MEM 0 1773 * OPL_ERRID_CHANNEL 1 1774 * OPL_ERRID_CPU 2 1775 * OPL_ERRID_PATH 3 1776 */ 1777 eccp += opl_flt->flt_eid_mod; 1778 } 1779 cpu_queue_one_event(opl_flt, reason, eccp); 1780 t_afsr_errs &= ~eccp->ec_afsr_bit; 1781 nevents++; 1782 } 1783 } 1784 1785 return (nevents); 1786 } 1787 1788 /* 1789 * Sync. error wrapper functions. 1790 * We use these functions in order to transfer here from the 1791 * nucleus trap handler information about trap type (data or 1792 * instruction) and trap level (0 or above 0). This way we 1793 * get rid of using SFSR's reserved bits. 1794 */ 1795 1796 #define OPL_SYNC_TL0 0 1797 #define OPL_SYNC_TL1 1 1798 #define OPL_ISYNC_ERR 0 1799 #define OPL_DSYNC_ERR 1 1800 1801 void 1802 opl_cpu_isync_tl0_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1803 { 1804 uint64_t t_sfar = p_sfar; 1805 uint64_t t_sfsr = p_sfsr; 1806 1807 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1808 OPL_SYNC_TL0, OPL_ISYNC_ERR); 1809 } 1810 1811 void 1812 opl_cpu_isync_tl1_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1813 { 1814 uint64_t t_sfar = p_sfar; 1815 uint64_t t_sfsr = p_sfsr; 1816 1817 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1818 OPL_SYNC_TL1, OPL_ISYNC_ERR); 1819 } 1820 1821 void 1822 opl_cpu_dsync_tl0_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1823 { 1824 uint64_t t_sfar = p_sfar; 1825 uint64_t t_sfsr = p_sfsr; 1826 1827 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1828 OPL_SYNC_TL0, OPL_DSYNC_ERR); 1829 } 1830 1831 void 1832 opl_cpu_dsync_tl1_error(struct regs *rp, ulong_t p_sfar, ulong_t p_sfsr) 1833 { 1834 uint64_t t_sfar = p_sfar; 1835 uint64_t t_sfsr = p_sfsr; 1836 1837 opl_cpu_sync_error(rp, t_sfar, t_sfsr, 1838 OPL_SYNC_TL1, OPL_DSYNC_ERR); 1839 } 1840 1841 /* 1842 * The fj sync err handler transfers control here for UE, BERR, TO, TLB_MUL 1843 * and TLB_PRT. 1844 * This function is designed based on cpu_deferred_error(). 1845 */ 1846 1847 static void 1848 opl_cpu_sync_error(struct regs *rp, ulong_t t_sfar, ulong_t t_sfsr, 1849 uint_t tl, uint_t derr) 1850 { 1851 opl_async_flt_t opl_flt; 1852 struct async_flt *aflt; 1853 int trampolined = 0; 1854 char pr_reason[MAX_REASON_STRING]; 1855 uint64_t log_sfsr; 1856 int expected = DDI_FM_ERR_UNEXPECTED; 1857 ddi_acc_hdl_t *hp; 1858 1859 /* 1860 * We need to look at p_flag to determine if the thread detected an 1861 * error while dumping core. We can't grab p_lock here, but it's ok 1862 * because we just need a consistent snapshot and we know that everyone 1863 * else will store a consistent set of bits while holding p_lock. We 1864 * don't have to worry about a race because SDOCORE is set once prior 1865 * to doing i/o from the process's address space and is never cleared. 1866 */ 1867 uint_t pflag = ttoproc(curthread)->p_flag; 1868 1869 pr_reason[0] = '\0'; 1870 1871 /* 1872 * handle the specific error 1873 */ 1874 bzero(&opl_flt, sizeof (opl_async_flt_t)); 1875 aflt = (struct async_flt *)&opl_flt; 1876 aflt->flt_id = gethrtime_waitfree(); 1877 aflt->flt_bus_id = getprocessorid(); 1878 aflt->flt_inst = CPU->cpu_id; 1879 aflt->flt_stat = t_sfsr; 1880 aflt->flt_addr = t_sfar; 1881 aflt->flt_pc = (caddr_t)rp->r_pc; 1882 aflt->flt_prot = (uchar_t)AFLT_PROT_NONE; 1883 aflt->flt_class = (uchar_t)CPU_FAULT; 1884 aflt->flt_priv = (uchar_t) 1885 (tl == 1 ? 1 : ((rp->r_tstate & TSTATE_PRIV) ? 1 : 0)); 1886 aflt->flt_tl = (uchar_t)tl; 1887 aflt->flt_panic = (uchar_t)(tl != 0 || aft_testfatal != 0 || 1888 (t_sfsr & (SFSR_TLB_MUL|SFSR_TLB_PRT)) != 0); 1889 aflt->flt_core = (pflag & SDOCORE) ? 1 : 0; 1890 aflt->flt_status = (derr) ? OPL_ECC_DSYNC_TRAP : OPL_ECC_ISYNC_TRAP; 1891 1892 /* 1893 * If SFSR.FV is not set, both SFSR and SFAR/SFPAR values are uncertain. 1894 * So, clear all error bits to avoid mis-handling and force the system 1895 * panicked. 1896 * We skip all the procedures below down to the panic message call. 1897 */ 1898 if (!(t_sfsr & SFSR_FV)) { 1899 opl_flt.flt_type = OPL_CPU_INV_SFSR; 1900 aflt->flt_panic = 1; 1901 aflt->flt_payload = FM_EREPORT_PAYLOAD_SYNC; 1902 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_SFSR, 1903 (void *)&opl_flt, sizeof (opl_async_flt_t), ue_queue, 1904 aflt->flt_panic); 1905 fm_panic("%sErrors(s)", "invalid SFSR"); 1906 } 1907 1908 /* 1909 * If either UE and MK bit is off, this is not valid UE error. 1910 * If it is not valid UE error, clear UE & MK_UE bits to prevent 1911 * mis-handling below. 1912 * aflt->flt_stat keeps the original bits as a reference. 1913 */ 1914 if ((t_sfsr & (SFSR_MK_UE|SFSR_UE)) != 1915 (SFSR_MK_UE|SFSR_UE)) { 1916 t_sfsr &= ~(SFSR_MK_UE|SFSR_UE); 1917 } 1918 1919 /* 1920 * If the trap occurred in privileged mode at TL=0, we need to check to 1921 * see if we were executing in the kernel under on_trap() or t_lofault 1922 * protection. If so, modify the saved registers so that we return 1923 * from the trap to the appropriate trampoline routine. 1924 */ 1925 if (!aflt->flt_panic && aflt->flt_priv && tl == 0) { 1926 if (curthread->t_ontrap != NULL) { 1927 on_trap_data_t *otp = curthread->t_ontrap; 1928 1929 if (otp->ot_prot & OT_DATA_EC) { 1930 aflt->flt_prot = (uchar_t)AFLT_PROT_EC; 1931 otp->ot_trap |= (ushort_t)OT_DATA_EC; 1932 rp->r_pc = otp->ot_trampoline; 1933 rp->r_npc = rp->r_pc + 4; 1934 trampolined = 1; 1935 } 1936 1937 if ((t_sfsr & (SFSR_TO | SFSR_BERR)) && 1938 (otp->ot_prot & OT_DATA_ACCESS)) { 1939 aflt->flt_prot = (uchar_t)AFLT_PROT_ACCESS; 1940 otp->ot_trap |= (ushort_t)OT_DATA_ACCESS; 1941 rp->r_pc = otp->ot_trampoline; 1942 rp->r_npc = rp->r_pc + 4; 1943 trampolined = 1; 1944 /* 1945 * for peeks and caut_gets errors are expected 1946 */ 1947 hp = (ddi_acc_hdl_t *)otp->ot_handle; 1948 if (!hp) 1949 expected = DDI_FM_ERR_PEEK; 1950 else if (hp->ah_acc.devacc_attr_access == 1951 DDI_CAUTIOUS_ACC) 1952 expected = DDI_FM_ERR_EXPECTED; 1953 } 1954 1955 } else if (curthread->t_lofault) { 1956 aflt->flt_prot = AFLT_PROT_COPY; 1957 rp->r_g1 = EFAULT; 1958 rp->r_pc = curthread->t_lofault; 1959 rp->r_npc = rp->r_pc + 4; 1960 trampolined = 1; 1961 } 1962 } 1963 1964 /* 1965 * If we're in user mode or we're doing a protected copy, we either 1966 * want the ASTON code below to send a signal to the user process 1967 * or we want to panic if aft_panic is set. 1968 * 1969 * If we're in privileged mode and we're not doing a copy, then we 1970 * need to check if we've trampolined. If we haven't trampolined, 1971 * we should panic. 1972 */ 1973 if (!aflt->flt_priv || aflt->flt_prot == AFLT_PROT_COPY) { 1974 if (t_sfsr & (SFSR_ERRS & ~(SFSR_BERR | SFSR_TO))) 1975 aflt->flt_panic |= aft_panic; 1976 } else if (!trampolined) { 1977 aflt->flt_panic = 1; 1978 } 1979 1980 /* 1981 * If we've trampolined due to a privileged TO or BERR, or if an 1982 * unprivileged TO or BERR occurred, we don't want to enqueue an 1983 * event for that TO or BERR. Queue all other events (if any) besides 1984 * the TO/BERR. 1985 */ 1986 log_sfsr = t_sfsr; 1987 if (trampolined) { 1988 log_sfsr &= ~(SFSR_TO | SFSR_BERR); 1989 } else if (!aflt->flt_priv) { 1990 /* 1991 * User mode, suppress messages if 1992 * cpu_berr_to_verbose is not set. 1993 */ 1994 if (!cpu_berr_to_verbose) 1995 log_sfsr &= ~(SFSR_TO | SFSR_BERR); 1996 } 1997 1998 if (((log_sfsr & SFSR_ERRS) && 1999 (cpu_queue_events(&opl_flt, pr_reason, t_sfsr) == 0)) || 2000 ((t_sfsr & SFSR_ERRS) == 0)) { 2001 opl_flt.flt_type = OPL_CPU_INV_SFSR; 2002 aflt->flt_payload = FM_EREPORT_PAYLOAD_SYNC; 2003 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_SFSR, 2004 (void *)&opl_flt, sizeof (opl_async_flt_t), ue_queue, 2005 aflt->flt_panic); 2006 } 2007 2008 if (t_sfsr & (SFSR_UE|SFSR_TO|SFSR_BERR)) { 2009 cpu_run_bus_error_handlers(aflt, expected); 2010 } 2011 2012 /* 2013 * Panic here if aflt->flt_panic has been set. Enqueued errors will 2014 * be logged as part of the panic flow. 2015 */ 2016 if (aflt->flt_panic) { 2017 if (pr_reason[0] == 0) 2018 strcpy(pr_reason, "invalid SFSR "); 2019 2020 fm_panic("%sErrors(s)", pr_reason); 2021 } 2022 2023 /* 2024 * If we queued an error and we are going to return from the trap and 2025 * the error was in user mode or inside of a copy routine, set AST flag 2026 * so the queue will be drained before returning to user mode. The 2027 * AST processing will also act on our failure policy. 2028 */ 2029 if (!aflt->flt_priv || aflt->flt_prot == AFLT_PROT_COPY) { 2030 int pcb_flag = 0; 2031 2032 if (t_sfsr & (SFSR_ERRS & 2033 ~(SFSR_BERR | SFSR_TO))) 2034 pcb_flag |= ASYNC_HWERR; 2035 2036 if (t_sfsr & SFSR_BERR) 2037 pcb_flag |= ASYNC_BERR; 2038 2039 if (t_sfsr & SFSR_TO) 2040 pcb_flag |= ASYNC_BTO; 2041 2042 ttolwp(curthread)->lwp_pcb.pcb_flags |= pcb_flag; 2043 aston(curthread); 2044 } 2045 } 2046 2047 /*ARGSUSED*/ 2048 void 2049 opl_cpu_urgent_error(struct regs *rp, ulong_t p_ugesr, ulong_t tl) 2050 { 2051 opl_async_flt_t opl_flt; 2052 struct async_flt *aflt; 2053 char pr_reason[MAX_REASON_STRING]; 2054 2055 /* normalize tl */ 2056 tl = (tl >= 2 ? 1 : 0); 2057 pr_reason[0] = '\0'; 2058 2059 bzero(&opl_flt, sizeof (opl_async_flt_t)); 2060 aflt = (struct async_flt *)&opl_flt; 2061 aflt->flt_id = gethrtime_waitfree(); 2062 aflt->flt_bus_id = getprocessorid(); 2063 aflt->flt_inst = CPU->cpu_id; 2064 aflt->flt_stat = p_ugesr; 2065 aflt->flt_pc = (caddr_t)rp->r_pc; 2066 aflt->flt_class = (uchar_t)CPU_FAULT; 2067 aflt->flt_tl = tl; 2068 aflt->flt_priv = (uchar_t) 2069 (tl == 1 ? 1 : ((rp->r_tstate & TSTATE_PRIV) ? 1 : 0)); 2070 aflt->flt_status = OPL_ECC_URGENT_TRAP; 2071 aflt->flt_panic = 1; 2072 /* 2073 * HW does not set mod/sid in case of urgent error. 2074 * So we have to set it here. 2075 */ 2076 opl_flt.flt_eid_mod = OPL_ERRID_CPU; 2077 opl_flt.flt_eid_sid = aflt->flt_inst; 2078 2079 if (cpu_queue_events(&opl_flt, pr_reason, p_ugesr) == 0) { 2080 opl_flt.flt_type = OPL_CPU_INV_UGESR; 2081 aflt->flt_payload = FM_EREPORT_PAYLOAD_URGENT; 2082 cpu_errorq_dispatch(FM_EREPORT_CPU_INV_URG, 2083 (void *)&opl_flt, sizeof (opl_async_flt_t), 2084 ue_queue, aflt->flt_panic); 2085 } 2086 2087 fm_panic("Urgent Error"); 2088 } 2089 2090 /* 2091 * Initialization error counters resetting. 2092 */ 2093 /* ARGSUSED */ 2094 static void 2095 opl_ras_online(void *arg, cpu_t *cp, cyc_handler_t *hdlr, cyc_time_t *when) 2096 { 2097 hdlr->cyh_func = (cyc_func_t)ras_cntr_reset; 2098 hdlr->cyh_level = CY_LOW_LEVEL; 2099 hdlr->cyh_arg = (void *)(uintptr_t)cp->cpu_id; 2100 2101 when->cyt_when = cp->cpu_id * (((hrtime_t)NANOSEC * 10)/ NCPU); 2102 when->cyt_interval = (hrtime_t)NANOSEC * opl_async_check_interval; 2103 } 2104 2105 void 2106 cpu_mp_init(void) 2107 { 2108 cyc_omni_handler_t hdlr; 2109 2110 hdlr.cyo_online = opl_ras_online; 2111 hdlr.cyo_offline = NULL; 2112 hdlr.cyo_arg = NULL; 2113 mutex_enter(&cpu_lock); 2114 (void) cyclic_add_omni(&hdlr); 2115 mutex_exit(&cpu_lock); 2116 } 2117 2118 /*ARGSUSED*/ 2119 void 2120 mmu_init_kernel_pgsz(struct hat *hat) 2121 { 2122 } 2123 2124 size_t 2125 mmu_get_kernel_lpsize(size_t lpsize) 2126 { 2127 uint_t tte; 2128 2129 if (lpsize == 0) { 2130 /* no setting for segkmem_lpsize in /etc/system: use default */ 2131 return (MMU_PAGESIZE4M); 2132 } 2133 2134 for (tte = TTE8K; tte <= TTE4M; tte++) { 2135 if (lpsize == TTEBYTES(tte)) 2136 return (lpsize); 2137 } 2138 2139 return (TTEBYTES(TTE8K)); 2140 } 2141 2142 /* 2143 * The following are functions that are unused in 2144 * OPL cpu module. They are defined here to resolve 2145 * dependencies in the "unix" module. 2146 * Unused functions that should never be called in 2147 * OPL are coded with ASSERT(0). 2148 */ 2149 2150 void 2151 cpu_disable_errors(void) 2152 {} 2153 2154 void 2155 cpu_enable_errors(void) 2156 { ASSERT(0); } 2157 2158 /*ARGSUSED*/ 2159 void 2160 cpu_ce_scrub_mem_err(struct async_flt *ecc, boolean_t t) 2161 { ASSERT(0); } 2162 2163 /*ARGSUSED*/ 2164 void 2165 cpu_faulted_enter(struct cpu *cp) 2166 {} 2167 2168 /*ARGSUSED*/ 2169 void 2170 cpu_faulted_exit(struct cpu *cp) 2171 {} 2172 2173 /*ARGSUSED*/ 2174 void 2175 cpu_check_allcpus(struct async_flt *aflt) 2176 {} 2177 2178 /*ARGSUSED*/ 2179 void 2180 cpu_ce_log_err(struct async_flt *aflt, errorq_elem_t *t) 2181 { ASSERT(0); } 2182 2183 /*ARGSUSED*/ 2184 void 2185 cpu_check_ce(int flag, uint64_t pa, caddr_t va, uint_t psz) 2186 { ASSERT(0); } 2187 2188 /*ARGSUSED*/ 2189 void 2190 cpu_ce_count_unum(struct async_flt *ecc, int len, char *unum) 2191 { ASSERT(0); } 2192 2193 /*ARGSUSED*/ 2194 void 2195 cpu_busy_ecache_scrub(struct cpu *cp) 2196 {} 2197 2198 /*ARGSUSED*/ 2199 void 2200 cpu_idle_ecache_scrub(struct cpu *cp) 2201 {} 2202 2203 /* ARGSUSED */ 2204 void 2205 cpu_change_speed(uint64_t divisor, uint64_t arg2) 2206 { ASSERT(0); } 2207 2208 void 2209 cpu_init_cache_scrub(void) 2210 {} 2211 2212 /* ARGSUSED */ 2213 int 2214 cpu_get_mem_sid(char *unum, char *buf, int buflen, int *lenp) 2215 { 2216 if (&plat_get_mem_sid) { 2217 return (plat_get_mem_sid(unum, buf, buflen, lenp)); 2218 } else { 2219 return (ENOTSUP); 2220 } 2221 } 2222 2223 /* ARGSUSED */ 2224 int 2225 cpu_get_mem_addr(char *unum, char *sid, uint64_t offset, uint64_t *addrp) 2226 { 2227 if (&plat_get_mem_addr) { 2228 return (plat_get_mem_addr(unum, sid, offset, addrp)); 2229 } else { 2230 return (ENOTSUP); 2231 } 2232 } 2233 2234 /* ARGSUSED */ 2235 int 2236 cpu_get_mem_offset(uint64_t flt_addr, uint64_t *offp) 2237 { 2238 if (&plat_get_mem_offset) { 2239 return (plat_get_mem_offset(flt_addr, offp)); 2240 } else { 2241 return (ENOTSUP); 2242 } 2243 } 2244 2245 /*ARGSUSED*/ 2246 void 2247 itlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag) 2248 { ASSERT(0); } 2249 2250 /*ARGSUSED*/ 2251 void 2252 dtlb_rd_entry(uint_t entry, tte_t *tte, uint64_t *va_tag) 2253 { ASSERT(0); } 2254 2255 /*ARGSUSED*/ 2256 void 2257 read_ecc_data(struct async_flt *aflt, short verbose, short ce_err) 2258 { ASSERT(0); } 2259 2260 /*ARGSUSED*/ 2261 int 2262 ce_scrub_xdiag_recirc(struct async_flt *aflt, errorq_t *eqp, 2263 errorq_elem_t *eqep, size_t afltoffset) 2264 { 2265 ASSERT(0); 2266 return (0); 2267 } 2268 2269 /*ARGSUSED*/ 2270 char * 2271 flt_to_error_type(struct async_flt *aflt) 2272 { 2273 ASSERT(0); 2274 return (NULL); 2275 } 2276