xref: /titanic_44/usr/src/uts/sun4u/chicago/io/ppm.conf (revision ecdc41fa5c89c9485ac54228fdd4aa5133e98742)
17c478bd9Sstevel@tonic-gate#
27c478bd9Sstevel@tonic-gate# CDDL HEADER START
37c478bd9Sstevel@tonic-gate#
47c478bd9Sstevel@tonic-gate# The contents of this file are subject to the terms of the
57c478bd9Sstevel@tonic-gate# Common Development and Distribution License, Version 1.0 only
67c478bd9Sstevel@tonic-gate# (the "License").  You may not use this file except in compliance
77c478bd9Sstevel@tonic-gate# with the License.
87c478bd9Sstevel@tonic-gate#
97c478bd9Sstevel@tonic-gate# You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
107c478bd9Sstevel@tonic-gate# or http://www.opensolaris.org/os/licensing.
117c478bd9Sstevel@tonic-gate# See the License for the specific language governing permissions
127c478bd9Sstevel@tonic-gate# and limitations under the License.
137c478bd9Sstevel@tonic-gate#
147c478bd9Sstevel@tonic-gate# When distributing Covered Code, include this CDDL HEADER in each
157c478bd9Sstevel@tonic-gate# file and include the License file at usr/src/OPENSOLARIS.LICENSE.
167c478bd9Sstevel@tonic-gate# If applicable, add the following below this CDDL HEADER, with the
177c478bd9Sstevel@tonic-gate# fields enclosed by brackets "[]" replaced with your own identifying
187c478bd9Sstevel@tonic-gate# information: Portions Copyright [yyyy] [name of copyright owner]
197c478bd9Sstevel@tonic-gate#
207c478bd9Sstevel@tonic-gate# CDDL HEADER END
217c478bd9Sstevel@tonic-gate#
227c478bd9Sstevel@tonic-gate#
237c478bd9Sstevel@tonic-gate# Copyright 2005 Sun Microsystems, Inc.  All rights reserved.
247c478bd9Sstevel@tonic-gate# Use is subject to license terms.
257c478bd9Sstevel@tonic-gate#
267c478bd9Sstevel@tonic-gate#pragma ident	"%Z%%M%	%I%	%E% SMI"
277c478bd9Sstevel@tonic-gate#
287c478bd9Sstevel@tonic-gate
297c478bd9Sstevel@tonic-gatename="ppm" parent="pseudo" instance=0;
307c478bd9Sstevel@tonic-gate
317c478bd9Sstevel@tonic-gate#
327c478bd9Sstevel@tonic-gate# ppm configuration format
337c478bd9Sstevel@tonic-gate#
347c478bd9Sstevel@tonic-gate# "ppm-domains" - in form of "domain_xxx" where "xxx" string highlights
357c478bd9Sstevel@tonic-gate# the nature of the domain;
367c478bd9Sstevel@tonic-gate#
377c478bd9Sstevel@tonic-gate# "domain_xxx-model" - PM model: CPU, PCI, PCI_PROP, PCIE, FET or LED.
387c478bd9Sstevel@tonic-gate#
397c478bd9Sstevel@tonic-gate# "domain_xxx-propname" - a property name that is exported by device in
407c478bd9Sstevel@tonic-gate# a domain.  Currently, it is used by PCI_PROP model to identify devices
417c478bd9Sstevel@tonic-gate# that are to have their clocks stopped when all power-manageable devices
427c478bd9Sstevel@tonic-gate# in the domain are at D3 power level.
437c478bd9Sstevel@tonic-gate#
447c478bd9Sstevel@tonic-gate# "domain-xxx-devices" - a list of prom path match patterns to match devices
457c478bd9Sstevel@tonic-gate# that fall into "domain_xxx", where wildcard '*' is allowed by observing
467c478bd9Sstevel@tonic-gate# the following expectations:
477c478bd9Sstevel@tonic-gate#	. a single wildcard with exact match up to (but exclude) the wildcard
487c478bd9Sstevel@tonic-gate#	  which then terminates the match pattern;
497c478bd9Sstevel@tonic-gate#	. a single wildcard that does not terminate a match pattern must
507c478bd9Sstevel@tonic-gate#	  match driver name (followed by '@');
517c478bd9Sstevel@tonic-gate#	. with two wildcard occurences, the first is to match driver name,
527c478bd9Sstevel@tonic-gate#	  the second function id, as well as the last character of the match
537c478bd9Sstevel@tonic-gate#	  pattern.
547c478bd9Sstevel@tonic-gate#
557c478bd9Sstevel@tonic-gate# "domain-xxx-ctrl" - blank space separated definitions in the form of
567c478bd9Sstevel@tonic-gate# keyword=definition [keyword=definition...]
577c478bd9Sstevel@tonic-gate#    The keywords are as follows, where 'method' must come before mask as it
587c478bd9Sstevel@tonic-gate#       tells how to store 'mask' and 'val'.  Missing 'val' defaults to 0.
597c478bd9Sstevel@tonic-gate#
607c478bd9Sstevel@tonic-gate#    which keywords apply depends on cmd.  There are two sets as shown below.
617c478bd9Sstevel@tonic-gate#    Here is the first:
627c478bd9Sstevel@tonic-gate#	cmd=[CPU_GO | LED_ON | LED_OFF | FET_ON | FET_OFF | CLK_ON | CLK_OFF]
637c478bd9Sstevel@tonic-gate# 	path=<prompath>	- control device's prom pathname (includes minor)
647c478bd9Sstevel@tonic-gate# 	method=[KIO|I2CKIO]	This selects a method which may be
657c478bd9Sstevel@tonic-gate#		an ioctl that sets a single value or an i2c ioctl that
667c478bd9Sstevel@tonic-gate#		takes a value and a mask to access gpio register
677c478bd9Sstevel@tonic-gate#	iord=<integer> - value of ioctl command for reading
687c478bd9Sstevel@tonic-gate#	iowr=<integer> - value of ioctl command for writing
697c478bd9Sstevel@tonic-gate# 	val=<integer>	- a single integer value, generally the value to which
707c478bd9Sstevel@tonic-gate#			  the relevant bits of a register will be set
717c478bd9Sstevel@tonic-gate#	mask=<integer>	- which bits of val are relevant (if method is I2CKIO)
727c478bd9Sstevel@tonic-gate#
737c478bd9Sstevel@tonic-gate#    Here is the second:
747c478bd9Sstevel@tonic-gate#	cmd=[CPU_NEXT | PRE_CHNG | POST_CHNG]
757c478bd9Sstevel@tonic-gate# 	path=<prompath>	   - control device's prom pathname, including minor
767c478bd9Sstevel@tonic-gate# 	method=[CPUSPEEDKIO | VCORE]  This selects a method that uses
777c478bd9Sstevel@tonic-gate#			     information like cpu speed index, value for
787c478bd9Sstevel@tonic-gate#			     adjust cpu core voltage, delays, etc.
797c478bd9Sstevel@tonic-gate#	iowr=<integer>     - value of ioctl write command
807c478bd9Sstevel@tonic-gate#	speeds=<integer>   - indicates the number of cpu speeds that are
817c478bd9Sstevel@tonic-gate#			     supported
827c478bd9Sstevel@tonic-gate
83795870e3Sosaeedppm-domains="domain_cpu", "domain_diskfet", "domain_led", "domain_pciegfx";
847c478bd9Sstevel@tonic-gate
857c478bd9Sstevel@tonic-gate#
867c478bd9Sstevel@tonic-gate# 0x6a02 is JBPPMIOC_NEXT	(('j' << 8) | 2)
877c478bd9Sstevel@tonic-gate# 0x6a03 is JBPPMIOC_GO		(('j' << 8) | 3)
887c478bd9Sstevel@tonic-gate#
89e7147e44Szx151605domain_cpu-devices="/SUNW,UltraSPARC-IIIi@*", "/SUNW,UltraSPARC-IIIi+@*";
907c478bd9Sstevel@tonic-gatedomain_cpu-model="CPU";
917c478bd9Sstevel@tonic-gatedomain_cpu-control=
927c478bd9Sstevel@tonic-gate    "cmd=CPU_NEXT path=/ppm@1f,0:jbus-ppm method=CPUSPEEDKIO iowr=0x6a02 speeds=3",
937c478bd9Sstevel@tonic-gate    "cmd=CPU_GO path=/ppm@1f,0:jbus-ppm method=KIO iowr=0x6a03 val=0";
947c478bd9Sstevel@tonic-gate
957c478bd9Sstevel@tonic-gate#
967c478bd9Sstevel@tonic-gate# iowr -- 0x4D82 is GPIO_SET_OUTPUT per sys/i2c/clients/i2c_gpio.h file
977c478bd9Sstevel@tonic-gate# iord -- 0x4D80 is GPIO_GET_INPUT per sys/i2c/clients/i2c_gpio.h file
987c478bd9Sstevel@tonic-gate# mask -- bit mask for control pin
997c478bd9Sstevel@tonic-gate# val  -- pin value to set on/off
1007c478bd9Sstevel@tonic-gate# delay -- minimum delay between FET off and FET on
1017c478bd9Sstevel@tonic-gate# post_delay -- delay after turning on/off the FET
1027c478bd9Sstevel@tonic-gate#
1030952347cSosaeeddomain_diskfet-devices = "/pci@1e,600000/pci@0/pci@9/pci@0/scsi@1";
104795870e3Sosaeeddomain_diskfet-model = "FET";
105795870e3Sosaeeddomain_diskfet-control =
106795870e3Sosaeed    "cmd=FET_ON path=/ebus@1f,464000/i2c@3,80/gpio@0,30:pca9556_0 method=I2CKIO iowr=0x4D82 iord=0x4D80 mask=0x0f val=0x0f post_delay=1500000",
107795870e3Sosaeed    "cmd=FET_OFF path=/ebus@1f,464000/i2c@3,80/gpio@0,30:pca9556_0 method=I2CKIO iowr=0x4D82 iord=0x4D80 mask=0x0f val=0";
1087c478bd9Sstevel@tonic-gate
1097c478bd9Sstevel@tonic-gate#
1107c478bd9Sstevel@tonic-gate# Manipulate the front-panel LED.  This platform uses ACTIVE low.
1117c478bd9Sstevel@tonic-gate#
1127c478bd9Sstevel@tonic-gate# Note: no devices to claim in this domain
1137c478bd9Sstevel@tonic-gate#
1147c478bd9Sstevel@tonic-gatedomain_led-devices = "";
1157c478bd9Sstevel@tonic-gatedomain_led-model = "LED";
1167c478bd9Sstevel@tonic-gatedomain_led-control =
117*ecdc41faSosaeed    "cmd=LED_ON path=/i2c@1f,530000/gpio@0,30:pca9556_1 method=I2CKIO iowr=0x4D82 iord=0x0 mask=0x01 val=0x01",
118*ecdc41faSosaeed    "cmd=LED_OFF path=/i2c@1f,530000/gpio@0,30:pca9556_1 method=I2CKIO iowr=0x4D82 iord=0x0 mask=0x01 val=0x00";
1197c478bd9Sstevel@tonic-gate
1207c478bd9Sstevel@tonic-gate#
1217c478bd9Sstevel@tonic-gate# PCI Express Primary Graphics Slot (directly attached to root complex(Fire))
1227c478bd9Sstevel@tonic-gate#
1237c478bd9Sstevel@tonic-gatedomain_pciegfx-devices = "/pci@1f,700000/*";
1247c478bd9Sstevel@tonic-gatedomain_pciegfx-model = "PCIE";
1257c478bd9Sstevel@tonic-gatedomain_pciegfx-control =
126e7147e44Szx151605    "cmd=PRE_PWR_OFF path=/pci@1f,700000:devctl method=KIO iowr=0x504D0001 val=0x00",
127e7147e44Szx151605    "cmd=PRE_PWR_ON path=/pci@1f,700000:devctl method=KIO iowr=0x504D0002 val=0x00",
128e7147e44Szx151605    "cmd=POST_PWR_ON path=/pci@1f,700000:devctl method=KIO iowr=0x504D0003 val=0x00 post_delay=100000",
129e7147e44Szx151605    "cmd=CLK_OFF path=/i2c@1f,530000/gpio@0,30:pca9556_1 method=I2CKIO iowr=0x4D82 iord=0x0 mask=0x10 val=0x00",
130e7147e44Szx151605    "cmd=CLK_ON path=/i2c@1f,530000/gpio@0,30:pca9556_1 method=I2CKIO iowr=0x4D82 iord=0x0 mask=0x10 val=0x10",
131e7147e44Szx151605    "cmd=PWR_OFF path=/i2c@1f,530000/gpio@0,30:pca9556_1 method=I2CKIO iowr=0x4D82 iord=0x0 mask=0x08 val=0x00",
132e7147e44Szx151605    "cmd=PWR_ON path=/i2c@1f,530000/gpio@0,30:pca9556_1 method=I2CKIO iowr=0x4D82 iord=0x0 mask=0x08 val=0x08",
133fd3af1c7Sosaeed    "cmd=RESET_OFF path=/i2c@1f,530000/gpio@0,30:pca9556_1 method=I2CKIO iowr=0x4D82 iord=0x0 mask=0x04 val=0x04 delay=120000",
134e7147e44Szx151605    "cmd=RESET_ON path=/i2c@1f,530000/gpio@0,30:pca9556_1 method=I2CKIO iowr=0x4D82 iord=0x0 mask=0x04 val=0x00";
135