1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_EBUS_H 28 #define _SYS_EBUS_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* 37 * driver state type: 38 */ 39 typedef enum { NEW = 0, ATTACHED, RESUMED, DETACHED, 40 SUSPENDED, PM_SUSPENDED } driver_state_t; 41 42 /* 43 * The i86pc specific code fragments are to support the debug of "honeynut" 44 * and "multigrain" prototypes on i86pc platform. Most of the fragments 45 * deal with differences in the interrupt dispatching between the prototypes 46 * and the cheerio ebus. On the prototype boards, all interrupt lines are 47 * tied together. For this case, the nexus driver uses a common interrupt 48 * handler to poll all of its children. 49 */ 50 #if defined(i86pc) 51 #define MAX_EBUS_DEVS 6 52 53 /* 54 * ebus device interrupt info; 55 */ 56 typedef struct { 57 char *name; 58 uint_t inuse; 59 uint_t (*handler)(); 60 caddr_t arg; 61 } ebus_intr_slot_t; 62 #endif 63 64 struct ebus_intr_map { 65 uint32_t ebus_phys_hi; 66 uint32_t ebus_phys_low; 67 uint32_t ebus_intr; 68 uint32_t intr_ctlr_nodeid; 69 uint32_t ino; 70 }; 71 72 struct ebus_intr_map_mask { 73 uint32_t ebus_phys_hi; 74 uint32_t ebus_phys_low; 75 uint32_t ebus_intr; 76 }; 77 78 /* 79 * driver soft state structure: 80 */ 81 typedef struct { 82 dev_info_t *dip; 83 driver_state_t state; 84 pci_regspec_t *reg; 85 int nreg; 86 87 union { 88 struct ebus_pci_rangespec *rangep; 89 struct febus_rangespec *ferangep; 90 } rangespec; 91 92 int range_cnt; 93 kmutex_t ebus_mutex; 94 uint_t ebus_soft_state; 95 #define EBUS_SOFT_STATE_CLOSED 0x00 96 #define EBUS_SOFT_STATE_OPEN 0x01 97 #define EBUS_SOFT_STATE_OPEN_EXCL 0x02 98 99 #if defined(i86pc) 100 ddi_iblock_cookie_t iblock; 101 ddi_idevice_cookie_t idevice; 102 ebus_intr_slot_t intr_slot[MAX_EBUS_DEVS]; 103 #endif 104 #if defined(__sparc) 105 /* Interrupt support */ 106 int intr_map_size; 107 struct ebus_intr_map *intr_map; 108 struct ebus_intr_map_mask *intr_map_mask; 109 #endif 110 111 uint_t type; 112 #define EBUS_TYPE 0x00 113 #define FEBUS_TYPE 0x01 114 } ebus_devstate_t; 115 116 /* 117 * definition of ebus reg spec entry: 118 */ 119 typedef struct { 120 uint32_t addr_hi; 121 uint32_t addr_low; 122 uint32_t size; 123 } ebus_regspec_t; 124 125 /* EBUS range entry */ 126 struct ebus_pci_rangespec { 127 uint32_t ebus_phys_hi; /* Child hi range address */ 128 uint32_t ebus_phys_low; /* Child low range address */ 129 uint32_t pci_phys_hi; /* Parent hi rng addr */ 130 uint32_t pci_phys_mid; /* Parent mid rng addr */ 131 uint32_t pci_phys_low; /* Parent low rng addr */ 132 uint32_t rng_size; /* Range size */ 133 }; 134 135 /* FEBUS range entry */ 136 struct febus_rangespec { 137 uint32_t febus_phys_hi; /* Child hi range address */ 138 uint32_t febus_phys_low; /* Child low range address */ 139 uint32_t parent_phys_hi; /* Parent hi rng addr */ 140 uint32_t parent_phys_low; /* Parent low rng addr */ 141 uint32_t rng_size; /* Range size */ 142 }; 143 144 /* 145 * use macros for soft state and driver properties: 146 */ 147 #define get_ebus_soft_state(i) \ 148 ((ebus_devstate_t *)ddi_get_soft_state(per_ebus_state, (i))) 149 150 #define alloc_ebus_soft_state(i) \ 151 ddi_soft_state_zalloc(per_ebus_state, (i)) 152 153 #define free_ebus_soft_state(i) \ 154 ddi_soft_state_free(per_ebus_state, (i)) 155 156 157 #define getprop(dip, name, addr, intp) \ 158 ddi_getlongprop(DDI_DEV_T_ANY, (dip), DDI_PROP_DONTPASS, \ 159 (name), (caddr_t)(addr), (intp)) 160 161 #define IS_RIO(dip) \ 162 ((ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, \ 163 "device-id", -1) == 0x1100) && \ 164 (ddi_prop_get_int(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, \ 165 "vendor-id", -1) == 0x108e)) 166 167 #define EBUS_4MHZ 4000 168 169 /* 170 * register offsets and lengths: 171 */ 172 #define TCR_OFFSET 0x710000 173 #define TCR_LENGTH 12 174 175 /* 176 * timing control register settings: 177 */ 178 #define TCR1 0x08101008 179 #define TCR2 0x08100020 180 #define TCR3 0x00000020 181 182 #if defined(DEBUG) 183 #define D_IDENTIFY 0x00000001 184 #define D_ATTACH 0x00000002 185 #define D_DETACH 0x00000004 186 #define D_MAP 0x00000008 187 #define D_CTLOPS 0x00000010 188 #define D_INTR 0x00000100 189 190 #define DBG(flag, psp, fmt) \ 191 ebus_debug(flag, psp, fmt, 0, 0, 0, 0, 0); 192 #define DBG1(flag, psp, fmt, a1) \ 193 ebus_debug(flag, psp, fmt, (uintptr_t)(a1), 0, 0, 0, 0); 194 #define DBG2(flag, psp, fmt, a1, a2) \ 195 ebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0); 196 #define DBG3(flag, psp, fmt, a1, a2, a3) \ 197 ebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \ 198 (uintptr_t)(a3), 0, 0); 199 #define DBG4(flag, psp, fmt, a1, a2, a3, a4) \ 200 ebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \ 201 (uintptr_t)(a3), \ 202 (uintptr_t)(a4), 0); 203 #define DBG5(flag, psp, fmt, a1, a2, a3, a4, a5) \ 204 ebus_debug(flag, psp, fmt, (uintptr_t)(a1), (uintptr_t)(a2), \ 205 (uintptr_t)(a3), \ 206 (uintptr_t)(a4), (uintptr_t)(a5)); 207 static void 208 ebus_debug(uint_t, ebus_devstate_t *, char *, uintptr_t, uintptr_t, uintptr_t, 209 uintptr_t, uintptr_t); 210 #else 211 #define DBG(flag, psp, fmt) 212 #define DBG1(flag, psp, fmt, a1) 213 #define DBG2(flag, psp, fmt, a1, a2) 214 #define DBG3(flag, psp, fmt, a1, a2, a3) 215 #define DBG4(flag, psp, fmt, a1, a2, a3, a4) 216 #define DBG5(flag, psp, fmt, a1, a2, a3, a4, a5) 217 #endif 218 219 #ifdef __cplusplus 220 } 221 #endif 222 223 #endif /* _SYS_EBUS_H */ 224