1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_PX_VAR_H 28 #define _SYS_PX_VAR_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #include <sys/callb.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* 39 * offsets of PCI address spaces from base address: 40 */ 41 #define PX_CONFIG 0x001000000ull 42 #define PX_A_IO 0x002000000ull 43 #define PX_B_IO 0x002010000ull 44 #define PX_A_MEMORY 0x100000000ull 45 #define PX_B_MEMORY 0x180000000ull 46 #define PX_IO_SIZE 0x000010000ull 47 #define PX_MEM_SIZE 0x080000000ull 48 49 /* 50 * The following typedef is used to represent a 51 * 1275 "bus-range" property of a PCI Bus node. 52 */ 53 typedef struct px_bus_range { 54 uint32_t lo; 55 uint32_t hi; 56 } px_bus_range_t; 57 58 /* 59 * The following typedef is used to represent an entry in the "ranges" 60 * property of a device node. 61 */ 62 typedef struct px_ranges { 63 uint32_t child_high; 64 uint32_t child_mid; 65 uint32_t child_low; 66 uint32_t parent_high; 67 uint32_t parent_low; 68 uint32_t size_high; 69 uint32_t size_low; 70 } px_ranges_t; 71 72 /* 73 * The following typedef is used to represent a 74 * 1275 "reg" property of a PCI nexus. 75 */ 76 typedef struct px_nexus_regspec { 77 uint64_t phys_addr; 78 uint64_t size; 79 } px_nexus_regspec_t; 80 81 typedef enum { PX_NEW, PX_ATTACHED, PX_DETACHED, PX_SUSPENDED } px_state_t; 82 enum { PX_INTR_XBC, PX_INTR_PEC }; 83 84 #define PX_ATTACH_RETCODE(obj, op, err) \ 85 ((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS) 86 87 /* 88 * px soft state structure: 89 * 90 * Each px node has a px soft state structure. 91 */ 92 struct px { 93 /* 94 * State flags and mutex: 95 */ 96 px_state_t px_state; 97 uint_t px_soft_state; 98 uint_t px_open_count; 99 kmutex_t px_mutex; 100 101 /* 102 * Links to other state structures: 103 */ 104 dev_info_t *px_dip; /* devinfo structure */ 105 devhandle_t px_dev_hdl; /* device handle */ 106 px_cb_t *px_cb_p; /* XBC block */ 107 px_ib_t *px_ib_p; /* interrupt block */ 108 px_pec_t *px_pec_p; /* PEC block */ 109 px_mmu_t *px_mmu_p; /* IOMMU block */ 110 111 /* 112 * px device node properties: 113 */ 114 px_bus_range_t px_bus_range; /* "bus-range" */ 115 px_ranges_t *px_ranges_p; /* "ranges" data & length */ 116 int px_ranges_length; 117 devino_t *px_inos; /* inos from "interrupts" prop */ 118 int px_inos_len; /* "interrupts" length */ 119 int pci_numproxy; /* upa interrupt proxies */ 120 int px_thermal_interrupt; /* node has thermal interrupt */ 121 122 /* Interrupt support */ 123 int intr_map_size; 124 struct intr_map *intr_map; 125 struct intr_map_mask *intr_map_mask; 126 127 /* Error handling */ 128 px_fault_t px_fault; 129 px_fault_t px_cb_fault; 130 131 /* FMA */ 132 int px_fm_cap; 133 ddi_iblock_cookie_t px_fm_ibc; 134 135 /* Platform specific information */ 136 void *px_plat_p; 137 138 /* Power Management fields */ 139 kmutex_t px_l23ready_lock; /* used in PME_To_ACK interrupt */ 140 kcondvar_t px_l23ready_cv; /* used in PME_TO_ACK timeout */ 141 142 /* Fields below deal with link up interrupt */ 143 kmutex_t px_lup_lock; 144 kcondvar_t px_lup_cv; /* used in LUP event timeout */ 145 kmutex_t px_lupsoft_lock; 146 ddi_softintr_t px_lupsoft_id; 147 int px_lupsoft_pending; 148 int px_pm_flags; 149 msiqid_t px_pm_msiq_id; /* EQ id for PCIE_PME_ACK_MSG Message */ 150 uint32_t px_pmetoack_ignored; /* count of PME_To_ACKs ignored */ 151 uint32_t px_pme_ignored; /* count of PME ignored */ 152 uint32_t px_lup_ignored; /* count of link up events ignored */ 153 154 /* CPR callback id */ 155 callb_id_t px_cprcb_id; 156 }; 157 158 /* px soft state flag */ 159 #define PX_SOFT_STATE_OPEN 0x01 160 #define PX_SOFT_STATE_OPEN_EXCL 0x02 161 #define PX_SOFT_STATE_CLOSED 0x04 162 #define PX_BYPASS_DMA_ALLOWED 0x10 163 164 /* px_pm_flags definitions used with interrupts and FMA code */ 165 #define PX_PMETOACK_RECVD 0x01 /* With PME_To_ACK interrupt */ 166 #define PX_PME_TURNOFF_PENDING 0x02 /* With PME_To_ACK interrupt */ 167 #define PX_LINKUP_RECVD 0x04 /* With link up soft interrupt */ 168 #define PX_LINKUP_PENDING 0x08 /* With link up soft interrupt */ 169 #define PX_LUP_EXPECTED 0x10 /* With FMA code */ 170 #define PX_LDN_EXPECTED 0x20 /* With FMA code */ 171 172 #define DIP_TO_INST(dip) ddi_get_instance(dip) 173 #define INST_TO_STATE(inst) ddi_get_soft_state(px_state_p, inst) 174 #define DIP_TO_STATE(dip) INST_TO_STATE(DIP_TO_INST(dip)) 175 176 #define DEV_TO_SOFTSTATE(dev) ((px_t *)ddi_get_soft_state( \ 177 px_state_p, PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor(dev)))) 178 179 extern void *px_state_p; 180 181 /* 182 * function prototypes for bus ops routines: 183 */ 184 extern int 185 px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 186 off_t offset, off_t len, caddr_t *addrp); 187 extern int 188 px_dma_setup(dev_info_t *dip, dev_info_t *rdip, 189 ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep); 190 extern int 191 px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 192 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep); 193 extern int 194 px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 195 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 196 ddi_dma_cookie_t *cookiep, uint_t *ccountp); 197 extern int 198 px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 199 ddi_dma_handle_t handle); 200 extern int 201 px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 202 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 203 uint_t cache_flags); 204 extern int 205 px_ctlops(dev_info_t *dip, dev_info_t *rdip, 206 ddi_ctl_enum_t op, void *arg, void *result); 207 extern int 208 px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 209 ddi_intr_handle_impl_t *handle, void *result); 210 211 #ifdef __cplusplus 212 } 213 #endif 214 215 #endif /* _SYS_PX_VAR_H */ 216