1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_VAR_H 27 #define _SYS_PX_VAR_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/callb.h> 32 33 #ifdef __cplusplus 34 extern "C" { 35 #endif 36 37 /* 38 * offsets of PCI address spaces from base address: 39 */ 40 #define PX_CONFIG 0x001000000ull 41 #define PX_A_IO 0x002000000ull 42 #define PX_B_IO 0x002010000ull 43 #define PX_A_MEMORY 0x100000000ull 44 #define PX_B_MEMORY 0x180000000ull 45 #define PX_IO_SIZE 0x000010000ull 46 #define PX_MEM_SIZE 0x080000000ull 47 48 /* 49 * The following typedef is used to represent a 50 * 1275 "bus-range" property of a PCI Bus node. 51 */ 52 typedef struct px_bus_range { 53 uint32_t lo; 54 uint32_t hi; 55 } px_bus_range_t; 56 57 /* 58 * The following typedef is used to represent an entry in the "ranges" 59 * property of a device node. 60 */ 61 typedef struct px_ranges { 62 uint32_t child_high; 63 uint32_t child_mid; 64 uint32_t child_low; 65 uint32_t parent_high; 66 uint32_t parent_low; 67 uint32_t size_high; 68 uint32_t size_low; 69 } px_ranges_t; 70 71 /* 72 * The following typedef is used to represent a 73 * 1275 "reg" property of a PCI nexus. 74 */ 75 typedef struct px_nexus_regspec { 76 uint64_t phys_addr; 77 uint64_t size; 78 } px_nexus_regspec_t; 79 80 typedef enum { PX_NEW, PX_ATTACHED, PX_DETACHED, PX_SUSPENDED } px_state_t; 81 enum { PX_INTR_XBC, PX_INTR_PEC }; 82 83 #define PX_ATTACH_RETCODE(obj, op, err) \ 84 ((err) ? (obj) << 8 | (op) << 4 | (err) & 0xf : DDI_SUCCESS) 85 86 /* 87 * px soft state structure: 88 * 89 * Each px node has a px soft state structure. 90 */ 91 struct px { 92 /* 93 * State flags and mutex: 94 */ 95 px_state_t px_state; 96 uint_t px_soft_state; 97 uint_t px_open_count; 98 kmutex_t px_mutex; 99 100 /* 101 * Links to other state structures: 102 */ 103 dev_info_t *px_dip; /* devinfo structure */ 104 devhandle_t px_dev_hdl; /* device handle */ 105 px_cb_t *px_cb_p; /* XBC block */ 106 px_ib_t *px_ib_p; /* interrupt block */ 107 px_pec_t *px_pec_p; /* PEC block */ 108 px_mmu_t *px_mmu_p; /* IOMMU block */ 109 110 /* 111 * px device node properties: 112 */ 113 px_bus_range_t px_bus_range; /* "bus-range" */ 114 px_ranges_t *px_ranges_p; /* "ranges" data & length */ 115 int px_ranges_length; 116 devino_t *px_inos; /* inos from "interrupts" prop */ 117 int px_inos_len; /* "interrupts" length */ 118 119 /* Error handling */ 120 px_fault_t px_fault; 121 px_fault_t px_cb_fault; 122 123 /* FMA */ 124 int px_fm_cap; 125 ddi_iblock_cookie_t px_fm_ibc; 126 127 uint32_t px_dev_caps; 128 129 /* Platform specific information */ 130 void *px_plat_p; 131 132 /* Power Management fields */ 133 kmutex_t px_l23ready_lock; /* used in PME_To_ACK interrupt */ 134 kcondvar_t px_l23ready_cv; /* used in PME_TO_ACK timeout */ 135 volatile uint32_t px_lup_pending; 136 int px_pm_flags; 137 msiqid_t px_pm_msiq_id; /* EQ id for PCIE_PME_ACK_MSG Message */ 138 uint32_t px_pmetoack_ignored; /* count of PME_To_ACKs ignored */ 139 uint32_t px_pme_ignored; /* count of PME ignored */ 140 141 /* CPR callback id */ 142 callb_id_t px_cprcb_id; 143 }; 144 145 /* px soft state flag */ 146 #define PX_SOFT_STATE_OPEN 0x01 147 #define PX_SOFT_STATE_OPEN_EXCL 0x02 148 #define PX_SOFT_STATE_CLOSED 0x04 149 150 /* px_dev_caps definition */ 151 #define PX_BYPASS_DMA_ALLOWED 0x00000001 152 #define PX_HOTPLUG_CAPABLE 0x00000002 153 154 /* px_pm_flags definitions used with interrupts and FMA code */ 155 #define PX_PMETOACK_RECVD 0x01 /* With PME_To_ACK interrupt */ 156 #define PX_PME_TURNOFF_PENDING 0x02 /* With PME_To_ACK interrupt */ 157 #define PX_LDN_EXPECTED 0x04 /* With FMA code */ 158 159 #define DIP_TO_INST(dip) ddi_get_instance(dip) 160 #define INST_TO_STATE(inst) ddi_get_soft_state(px_state_p, inst) 161 #define DIP_TO_STATE(dip) INST_TO_STATE(DIP_TO_INST(dip)) 162 163 #define PX_DEV_TO_SOFTSTATE(dev) ((px_t *)ddi_get_soft_state( \ 164 px_state_p, PCIHP_AP_MINOR_NUM_TO_INSTANCE(getminor(dev)))) 165 166 extern void *px_state_p; 167 168 /* 169 * function prototypes for bus ops routines: 170 */ 171 extern int 172 px_map(dev_info_t *dip, dev_info_t *rdip, ddi_map_req_t *mp, 173 off_t offset, off_t len, caddr_t *addrp); 174 extern int 175 px_dma_setup(dev_info_t *dip, dev_info_t *rdip, 176 ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep); 177 extern int 178 px_dma_allochdl(dev_info_t *dip, dev_info_t *rdip, ddi_dma_attr_t *attrp, 179 int (*waitfp)(caddr_t), caddr_t arg, ddi_dma_handle_t *handlep); 180 extern int 181 px_dma_bindhdl(dev_info_t *dip, dev_info_t *rdip, 182 ddi_dma_handle_t handle, ddi_dma_req_t *dmareq, 183 ddi_dma_cookie_t *cookiep, uint_t *ccountp); 184 extern int 185 px_dma_unbindhdl(dev_info_t *dip, dev_info_t *rdip, 186 ddi_dma_handle_t handle); 187 extern int 188 px_dma_ctlops(dev_info_t *dip, dev_info_t *rdip, ddi_dma_handle_t handle, 189 enum ddi_dma_ctlops cmd, off_t *offp, size_t *lenp, caddr_t *objp, 190 uint_t cache_flags); 191 extern int 192 px_ctlops(dev_info_t *dip, dev_info_t *rdip, 193 ddi_ctl_enum_t op, void *arg, void *result); 194 extern int 195 px_intr_ops(dev_info_t *dip, dev_info_t *rdip, ddi_intr_op_t intr_op, 196 ddi_intr_handle_impl_t *handle, void *result); 197 198 #ifdef __cplusplus 199 } 200 #endif 201 202 #endif /* _SYS_PX_VAR_H */ 203