1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 /* 30 * PCI Express nexus driver tunables 31 */ 32 33 #include <sys/types.h> 34 #include <sys/cmn_err.h> 35 #include <sys/time.h> 36 #include <sys/pci.h> 37 #include "px_space.h" 38 39 /*LINTLIBRARY*/ 40 41 uint32_t px_spurintr_duration = 60000000; /* One minute */ 42 uint64_t px_spurintr_msgs = PX_SPURINTR_MSG_DEFAULT; 43 44 /* 45 * The following variable enables a workaround for the following obp bug: 46 * 47 * 1234181 - obp should set latency timer registers in pci 48 * configuration header 49 * 50 * Until this bug gets fixed in the obp, the following workaround should 51 * be enabled. 52 */ 53 uint_t px_set_latency_timer_register = 1; 54 55 /* 56 * The following driver parameters are defined as variables to allow 57 * patching for debugging and tuning. Flags that can be set on a per 58 * PBM basis are bit fields where the PBM device instance number maps 59 * to the bit position. 60 */ 61 uint_t px_mmu_error_intr_enable = (uint_t)-1; 62 uint_t px_rerun_disable = 0; 63 64 uint_t px_error_intr_enable = (uint_t)-1; 65 uint_t px_dwsync_disable = 0; 66 uint_t px_intsync_disable = 0; 67 68 uint_t px_intr_retry_intv = 5; /* for interrupt retry reg */ 69 uint8_t px_latency_timer = 0x40; /* for pci latency timer reg */ 70 uint_t px_panic_on_fatal_errors = 1; /* should be 1 at beta */ 71 uint_t px_thermal_intr_fatal = 1; /* thermal interrupts fatal */ 72 uint_t px_buserr_interrupt = 1; /* safari buserr interrupt */ 73 uint_t px_ctx_no_active_flush = 0; /* cannot handle active ctx flush */ 74 uint_t px_use_contexts = 1; 75 76 hrtime_t px_intrpend_timeout = 5ull * NANOSEC; /* 5 seconds in nanoseconds */ 77 78 uint64_t px_perr_fatal = -1ull; 79 uint64_t px_serr_fatal = -1ull; 80 uint64_t px_errtrig_pa = 0x0; 81 82 /* 83 * The following flag controls behavior of the ino handler routine 84 * when multiple interrupts are attached to a single ino. Typically 85 * this case would occur for the ino's assigned to the PCI bus slots 86 * with multi-function devices or bus bridges. 87 * 88 * Setting the flag to zero causes the ino handler routine to return 89 * after finding the first interrupt handler to claim the interrupt. 90 * 91 * Setting the flag to non-zero causes the ino handler routine to 92 * return after making one complete pass through the interrupt 93 * handlers. 94 */ 95 uint_t px_check_all_handlers = 1; 96 97 /* 98 * The following value is the number of consecutive unclaimed interrupts that 99 * will be tolerated for a particular ino_p before the interrupt is deemed to 100 * be jabbering and is blocked. 101 */ 102 uint_t px_unclaimed_intr_max = 20; 103 104 /* 105 * The following value will cause the nexus driver to block an ino after 106 * px_unclaimed_intr_max unclaimed interrupts have been seen. Setting this 107 * value to 0 will cause interrupts to never be blocked, no matter how many 108 * unclaimed interrupts are seen on a particular ino. 109 */ 110 uint_t px_unclaimed_intr_block = 1; 111 112 uint_t px_lock_tlb = 0; 113 114 uint64_t px_dvma_debug_on = 0; 115 uint64_t px_dvma_debug_off = 0; 116 uint32_t px_dvma_debug_rec = 512; 117 118 /* 119 * dvma address space allocation cache variables 120 */ 121 uint_t px_dvma_page_cache_entries = 0x200; /* # of chunks (1 << bits) */ 122 uint_t px_dvma_page_cache_clustsz = 0x8; /* # of pages per chunk */ 123 #ifdef PX_DMA_PROF 124 uint_t px_dvmaft_npages = 0; /* FT fail due npages */ 125 uint_t px_dvmaft_limit = 0; /* FT fail due limits */ 126 uint_t px_dvmaft_free = 0; /* FT free */ 127 uint_t px_dvmaft_success = 0; /* FT success */ 128 uint_t px_dvmaft_exhaust = 0; /* FT vmem fallback */ 129 uint_t px_dvma_vmem_alloc = 0; /* vmem alloc */ 130 uint_t px_dvma_vmem_xalloc = 0; /* vmem xalloc */ 131 uint_t px_dvma_vmem_xfree = 0; /* vmem xfree */ 132 uint_t px_dvma_vmem_free = 0; /* vmem free */ 133 #endif 134 uint_t px_disable_fdvma = 0; 135 uint_t px_mmu_ctx_lock_failure = 0; 136 137 /* 138 * This flag preserves prom MMU settings by copying prom TSB entries 139 * to corresponding kernel TSB entry locations. It should be removed 140 * after the interface properties from obp have become default. 141 */ 142 uint_t px_preserve_mmu_tsb = 1; 143 144 /* 145 * memory callback list id callback list for kmem_alloc failure clients 146 */ 147 uintptr_t px_kmem_clid = 0; 148 149 uint_t px_err_log_all = 0; 150 151 uint64_t px_tlu_ue_intr_mask = PX_ERR_EN_ALL; 152 uint64_t px_tlu_ue_log_mask = PX_ERR_EN_ALL; 153 uint64_t px_tlu_ue_count_mask = PX_ERR_EN_ALL; 154 155 uint64_t px_tlu_ce_intr_mask = PX_ERR_MASK_NONE; 156 uint64_t px_tlu_ce_log_mask = PX_ERR_MASK_NONE; 157 uint64_t px_tlu_ce_count_mask = PX_ERR_MASK_NONE; 158 159 /* 160 * Do not enable Link Interrupts 161 */ 162 uint64_t px_tlu_oe_intr_mask = PX_ERR_EN_ALL & ~0x80000000800; 163 uint64_t px_tlu_oe_log_mask = PX_ERR_EN_ALL; 164 uint64_t px_tlu_oe_count_mask = PX_ERR_EN_ALL; 165 166 uint64_t px_mmu_intr_mask = PX_ERR_EN_ALL; 167 uint64_t px_mmu_log_mask = PX_ERR_EN_ALL; 168 uint64_t px_mmu_count_mask = PX_ERR_EN_ALL; 169 170 uint64_t px_imu_intr_mask = PX_ERR_EN_ALL; 171 uint64_t px_imu_log_mask = PX_ERR_EN_ALL; 172 uint64_t px_imu_count_mask = PX_ERR_EN_ALL; 173 174 /* 175 * (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_S) | 176 * (1ull << ILU_INTERRUPT_ENABLE_IHB_PE_P); 177 */ 178 uint64_t px_ilu_intr_mask = (((uint64_t)0x10 << 32) | 0x10); 179 uint64_t px_ilu_log_mask = 0x10; /* ILU_ERROR_LOG_ENABLE_IHB_PE */ 180 uint64_t px_ilu_count_mask = PX_ERR_EN_ALL; 181 182 uint64_t px_cb_intr_mask = PX_ERR_EN_ALL; 183 uint64_t px_cb_log_mask = PX_ERR_EN_ALL; 184 uint64_t px_cb_count_mask = PX_ERR_EN_ALL; 185 186 /* 187 * LPU Intr Registers are reverse encoding from the registers above. 188 * 1 = disable 189 * 0 = enable 190 * 191 * Log and Count are however still the same. 192 */ 193 uint64_t px_lpul_intr_mask = LPU_INTR_DISABLE; 194 uint64_t px_lpul_log_mask = PX_ERR_EN_ALL; 195 uint64_t px_lpul_count_mask = PX_ERR_EN_ALL; 196 197 uint64_t px_lpup_intr_mask = LPU_INTR_DISABLE; 198 uint64_t px_lpup_log_mask = PX_ERR_EN_ALL; 199 uint64_t px_lpup_count_mask = PX_ERR_EN_ALL; 200 201 uint64_t px_lpur_intr_mask = LPU_INTR_DISABLE; 202 uint64_t px_lpur_log_mask = PX_ERR_EN_ALL; 203 uint64_t px_lpur_count_mask = PX_ERR_EN_ALL; 204 205 uint64_t px_lpux_intr_mask = LPU_INTR_DISABLE; 206 uint64_t px_lpux_log_mask = PX_ERR_EN_ALL; 207 uint64_t px_lpux_count_mask = PX_ERR_EN_ALL; 208 209 uint64_t px_lpus_intr_mask = LPU_INTR_DISABLE; 210 uint64_t px_lpus_log_mask = PX_ERR_EN_ALL; 211 uint64_t px_lpus_count_mask = PX_ERR_EN_ALL; 212 213 uint64_t px_lpug_intr_mask = LPU_INTR_DISABLE; 214 uint64_t px_lpug_log_mask = PX_ERR_EN_ALL; 215 uint64_t px_lpug_count_mask = PX_ERR_EN_ALL; 216 217 /* timeout in micro seconds for receiving PME_To_ACK */ 218 uint64_t px_pme_to_ack_timeout = PX_PME_TO_ACK_TIMEOUT; 219 220 /* timeout in micro seconds for receiving link up interrupt */ 221 uint64_t px_linkup_timeout = PX_LINKUP_TIMEOUT; 222 223 /* PIL at which PME_To_ACK message interrupt is handled */ 224 uint32_t px_pwr_pil = PX_PWR_PIL; 225 226 uint32_t px_max_l1_tries = PX_MAX_L1_TRIES; 227