1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * PCI Express nexus driver tunables 30 */ 31 32 #include <sys/types.h> 33 #include <sys/ddi.h> 34 #include <sys/sunddi.h> 35 #include <sys/cmn_err.h> 36 #include <sys/time.h> 37 #include <sys/pcie.h> 38 #include "px_obj.h" 39 40 /*LINTLIBRARY*/ 41 42 uint32_t px_spurintr_duration = 60000000; /* One minute */ 43 uint64_t px_spurintr_msgs = PX_SPURINTR_MSG_DEFAULT; 44 45 /* 46 * The following variable enables a workaround for the following obp bug: 47 * 48 * 1234181 - obp should set latency timer registers in pci 49 * configuration header 50 * 51 * Until this bug gets fixed in the obp, the following workaround should 52 * be enabled. 53 */ 54 uint_t px_set_latency_timer_register = 1; 55 56 /* 57 * The following driver parameters are defined as variables to allow 58 * patching for debugging and tuning. Flags that can be set on a per 59 * PBM basis are bit fields where the PBM device instance number maps 60 * to the bit position. 61 */ 62 uint_t px_mmu_error_intr_enable = (uint_t)-1; 63 uint_t px_rerun_disable = 0; 64 65 uint_t px_error_intr_enable = (uint_t)-1; 66 uint_t px_dwsync_disable = 0; 67 uint_t px_intsync_disable = 0; 68 69 uint_t px_intr_retry_intv = 5; /* for interrupt retry reg */ 70 uint8_t px_latency_timer = 0x40; /* for pci latency timer reg */ 71 uint_t px_panic_on_fatal_errors = 1; /* should be 1 at beta */ 72 uint_t px_thermal_intr_fatal = 1; /* thermal interrupts fatal */ 73 uint_t px_buserr_interrupt = 1; /* safari buserr interrupt */ 74 uint_t px_ctx_no_active_flush = 0; /* cannot handle active ctx flush */ 75 uint_t px_use_contexts = 1; 76 77 hrtime_t px_intrpend_timeout = 5ull * NANOSEC; /* 5 seconds in nanoseconds */ 78 79 uint64_t px_perr_fatal = -1ull; 80 uint64_t px_serr_fatal = -1ull; 81 uint64_t px_errtrig_pa = 0x0; 82 83 char px_panic_hb_msg[] = " System bus"; 84 char px_panic_rc_msg[] = " PCIe root complex"; 85 char px_panic_rp_msg[] = " PCIe root port"; 86 char px_panic_fab_msg[] = " PCIe fabric"; 87 88 /* 89 * The following flag controls behavior of the ino handler routine 90 * when multiple interrupts are attached to a single ino. Typically 91 * this case would occur for the ino's assigned to the PCI bus slots 92 * with multi-function devices or bus bridges. 93 * 94 * Setting the flag to zero causes the ino handler routine to return 95 * after finding the first interrupt handler to claim the interrupt. 96 * 97 * Setting the flag to non-zero causes the ino handler routine to 98 * return after making one complete pass through the interrupt 99 * handlers. 100 */ 101 uint_t px_check_all_handlers = 1; 102 103 /* 104 * The following value is the number of consecutive unclaimed interrupts that 105 * will be tolerated for a particular ino_p before the interrupt is deemed to 106 * be jabbering and is blocked. 107 */ 108 uint_t px_unclaimed_intr_max = 20; 109 110 /* 111 * The following value will cause the nexus driver to block an ino after 112 * px_unclaimed_intr_max unclaimed interrupts have been seen. Setting this 113 * value to 0 will cause interrupts to never be blocked, no matter how many 114 * unclaimed interrupts are seen on a particular ino. 115 */ 116 uint_t px_unclaimed_intr_block = 1; 117 118 uint_t px_lock_tlb = 0; 119 120 uint64_t px_dvma_debug_on = 0; 121 uint64_t px_dvma_debug_off = 0; 122 uint32_t px_dvma_debug_rec = 512; 123 124 /* 125 * dvma address space allocation cache variables 126 */ 127 uint_t px_dvma_page_cache_entries = 0x200; /* # of chunks (1 << bits) */ 128 uint_t px_dvma_page_cache_clustsz = 0x8; /* # of pages per chunk */ 129 #ifdef PX_DMA_PROF 130 uint_t px_dvmaft_npages = 0; /* FT fail due npages */ 131 uint_t px_dvmaft_limit = 0; /* FT fail due limits */ 132 uint_t px_dvmaft_free = 0; /* FT free */ 133 uint_t px_dvmaft_success = 0; /* FT success */ 134 uint_t px_dvmaft_exhaust = 0; /* FT vmem fallback */ 135 uint_t px_dvma_vmem_alloc = 0; /* vmem alloc */ 136 uint_t px_dvma_vmem_xalloc = 0; /* vmem xalloc */ 137 uint_t px_dvma_vmem_xfree = 0; /* vmem xfree */ 138 uint_t px_dvma_vmem_free = 0; /* vmem free */ 139 #endif 140 uint_t px_disable_fdvma = 0; 141 uint_t px_mmu_ctx_lock_failure = 0; 142 143 /* 144 * This flag preserves prom MMU settings by copying prom TSB entries 145 * to corresponding kernel TSB entry locations. It should be removed 146 * after the interface properties from obp have become default. 147 */ 148 uint_t px_preserve_mmu_tsb = 1; 149 150 /* 151 * memory callback list id callback list for kmem_alloc failure clients 152 */ 153 uintptr_t px_kmem_clid = 0; 154 155 /* timeout in micro seconds for receiving PME_To_ACK */ 156 uint64_t px_pme_to_ack_timeout = PX_PME_TO_ACK_TIMEOUT; 157 158 /* timeout in micro seconds for receiving link up interrupt */ 159 uint64_t px_lup_poll_to = PX_LUP_POLL_TO; 160 uint64_t px_lup_poll_interval = PX_LUP_POLL_INTERVAL; 161 162 /* PIL at which PME_To_ACK message interrupt is handled */ 163 uint32_t px_pwr_pil = PX_PWR_PIL; 164 165 uint32_t px_max_l1_tries = PX_MAX_L1_TRIES; 166 167 /* Print and Log tunables. The following variables are booleans */ 168 #ifdef DEBUG 169 uint32_t px_log = PX_PANIC | PX_NO_PANIC | PX_PROTECTED | PX_HW_RESET; 170 #else 171 uint32_t px_log = PX_PANIC; 172 #endif 173 uint32_t px_die = PX_PANIC | PX_PROTECTED | PX_HW_RESET; 174 175 /* Fire PCIe Error that should cause panics */ 176 boolean_t px_fabric_die = B_TRUE; 177 178 /* Root Complex PCIe Error bit flags that should cause panics */ 179 uint32_t px_fabric_die_rc_ce = 0; 180 uint32_t px_fabric_die_rc_ue = 0; 181 182 /* Root Complex PCIe Error bit flags that should cause forgiven */ 183 uint32_t px_fabric_forgive_rc_ce = 0; 184 uint32_t px_fabric_forgive_rc_ue = 0; 185 186 /* Fabric Error that should cause panics */ 187 uint32_t px_fabric_die_ce = 0; 188 uint32_t px_fabric_die_ue = PCIE_AER_UCE_UR | 189 PCIE_AER_UCE_UC | 190 PCIE_AER_UCE_TO | 191 PCIE_AER_UCE_RO | 192 PCIE_AER_UCE_FCP | 193 PCIE_AER_UCE_DLP | 194 PCIE_AER_UCE_TRAINING; 195 196 /* Fabric Error that should cause panics even under protected access */ 197 uint32_t px_fabric_die_ce_gos = 0; 198 uint32_t px_fabric_die_ue_gos = PCIE_AER_UCE_UC | 199 PCIE_AER_UCE_TO | 200 PCIE_AER_UCE_RO | 201 PCIE_AER_UCE_FCP | 202 PCIE_AER_UCE_DLP | 203 PCIE_AER_UCE_TRAINING; 204 205 /* Fabric Bridge Sec. Error that should cause panics */ 206 uint16_t px_fabric_die_bdg_sts = PCI_STAT_S_PERROR | 207 PCI_STAT_R_TARG_AB | 208 PCI_STAT_R_MAST_AB | 209 PCI_STAT_S_SYSERR | 210 PCI_STAT_PERROR; 211 212 /* 213 * Fabric Bridge Sec. Error that should cause panics even under 214 * protected access 215 */ 216 uint16_t px_fabric_die_bdg_sts_gos = PCI_STAT_S_PERROR | 217 PCI_STAT_PERROR; 218 219 /* Fabric Switch Sec. Error that should cause panics */ 220 uint16_t px_fabric_die_sw_sts = PCI_STAT_R_TARG_AB | 221 PCI_STAT_R_MAST_AB; 222 223 /* 224 * Fabric Switch Sec. Error that should cause panics even under 225 * protected access 226 */ 227 uint16_t px_fabric_die_sw_sts_gos = 0; 228 229 uint32_t px_fabric_die_sue = PCIE_AER_SUCE_TA_ON_SC | 230 PCIE_AER_SUCE_MA_ON_SC | 231 PCIE_AER_SUCE_RCVD_TA | 232 PCIE_AER_SUCE_RCVD_MA | 233 PCIE_AER_SUCE_USC_ERR | 234 PCIE_AER_SUCE_USC_MSG_DATA_ERR | 235 PCIE_AER_SUCE_UC_DATA_ERR | 236 PCIE_AER_SUCE_UC_ATTR_ERR | 237 PCIE_AER_SUCE_UC_ADDR_ERR | 238 PCIE_AER_SUCE_TIMER_EXPIRED | 239 PCIE_AER_SUCE_PERR_ASSERT | 240 PCIE_AER_SUCE_SERR_ASSERT | 241 PCIE_AER_SUCE_INTERNAL_ERR; 242 243 uint32_t px_fabric_die_sue_gos = PCIE_AER_SUCE_TA_ON_SC | 244 PCIE_AER_SUCE_MA_ON_SC | 245 PCIE_AER_SUCE_USC_ERR | 246 PCIE_AER_SUCE_USC_MSG_DATA_ERR | 247 PCIE_AER_SUCE_UC_DATA_ERR | 248 PCIE_AER_SUCE_UC_ATTR_ERR | 249 PCIE_AER_SUCE_UC_ADDR_ERR | 250 PCIE_AER_SUCE_TIMER_EXPIRED | 251 PCIE_AER_SUCE_PERR_ASSERT | 252 PCIE_AER_SUCE_SERR_ASSERT | 253 PCIE_AER_SUCE_INTERNAL_ERR; 254