1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PX_IOAPI_H 27 #define _SYS_PX_IOAPI_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #ifdef __cplusplus 32 extern "C" { 33 #endif 34 35 #ifndef _ASM 36 37 /* 38 * SUN4V IO Data Definitions 39 * 40 * cpuid - A unique opaque value which represents a target cpu. 41 * 42 * devhandle - Device handle. The device handle uniquely 43 * identifies a SUN4V device. It consists of the 44 * the lower 28-bits of the hi-cell of the first 45 * entry of the SUN4V device's "reg" property as defined 46 * by the SUN4V Bus Binding to Open Firmware. 47 * 48 * devino - Device Interrupt Number. An unsigned integer representing 49 * an interrupt within a specific device. 50 * 51 * sysino - System Interrupt Number. A 64-bit unsigned integer 52 * representing a unique interrupt within a "system". 53 * 54 * intr_state - A flag representing the interrupt state for a 55 * a given sysino. The state values are defined as: 56 * 57 * INTR_IDLE 0 58 * INTR_RECEIVED 1 59 * INTR_DELIVERED 2 60 * 61 * intr_valid_state - A flag representing the 'valid' state for 62 * a given sysino. The state values are defined as: 63 * 64 * INTR_NOTVALID 0 sysino not enabled 65 * INTR_VALID 1 sysino enabled 66 */ 67 68 typedef uint64_t devhandle_t; 69 70 typedef uint32_t cpuid_t; 71 typedef uint32_t devino_t; 72 typedef uint64_t sysino_t; 73 74 typedef enum intr_state { 75 INTR_IDLE_STATE = (uint32_t)0, 76 INTR_RECEIVED_STATE = (uint32_t)1, 77 INTR_DELIVERED_STATE = (uint32_t)2 78 } intr_state_t; 79 80 typedef enum intr_valid_state { 81 INTR_NOTVALID = (uint32_t)0, 82 INTR_VALID = (uint32_t)1 83 } intr_valid_state_t; 84 85 /* 86 * PCI IO Data Definitions 87 * 88 * tsbnum - TSB Number. Identifies which io-tsb is used. 89 * For this version of the spec, tsbnum must be zero. 90 * 91 * tsbindex - TSB Index. Identifies which entry in the tsb is 92 * is used. The first entry is zero. 93 * 94 * tsbid - A 64-bit aligned data structure which contains 95 * a tsbnum and a tsbindex. 96 * bits 63:32 contain the tsbnum. 97 * bits 31:00 contain the tsbindex. 98 * 99 * io_attributes - IO Attributes for iommu mappings. 100 * Attributes for iommu mappings. One or more of the 101 * following attribute bits stored in a 64-bit unsigned int. 102 * 103 * 6 3 0 104 * 3 1 0 105 * 00000000 00000000 00000000 00000000 BBBBBBBB DDDDDFFF 00000000 00PP0LWR 106 * 107 * R: DMA data is transferred from main memory to device. 108 * W: DMA data is transferred from device to main memory. 109 * L: Requested DMA transaction can be relaxed ordered within RC. 110 * P: Value of PCI Express and PCI-X phantom function 111 * configuration. Its encoding is identical to the 112 * "Phantom Function Supported" field of the 113 * "Device Capabilities Register (offset 0x4)" 114 * in the "PCI Express Capability Structure". 115 * The structure is part of a device's config space. 116 * BDF: Bus, device and function number of the device 117 * that is going to issue DMA transactions. 118 * The BDF values are used to guarantee the mapping 119 * only be accessed by the specified device. 120 * If the BDF is set to all 0, RID based protection 121 * will be turned off. 122 * 123 * Relaxed Ordering (L) is advisory. Not all hardware implements a 124 * relaxed ordering attribute. If L attribute is not implemented in 125 * hardware, the implementation is permitted to ignore the L bit. 126 * 127 * Bits 3, 15:6 and 63:32 are unused and must be set to zero for 128 * this version of the specification. 129 * 130 * Note: For compatibility with future versions of this 131 * specification, the caller must set bits 3, 15:6 and 63:32 to 132 * zero. The implementation shall ignore these bits. 133 * 134 * r_addr - 64-bit Real Address. 135 * 136 * io_addr - 64-bit IO Address. 137 * 138 * pci_device - PCI device address. A PCI device address 139 * identifies a specific device on a specific PCI 140 * bus segment. A PCI device address is a 32-bit unsigned 141 * integer with the following format: 142 * 143 * 00000000.bbbbbbbb.dddddfff.00000000 144 * 145 * Where: 146 * 147 * bbbbbbbb is the 8-bit pci bus number 148 * ddddd is the 5-bit pci device number 149 * fff is the 3-bit pci function number 150 * 151 * 00000000 is the 8-bit literal zero. 152 * 153 * pci_config_offset - PCI Configuration Space offset. 154 * 155 * For conventional PCI, an unsigned integer in the range 156 * 0 .. 255 representing the offset of the field in pci config 157 * space. 158 * 159 * For PCI implementations with extended configuration space, 160 * an unsigned integer in the range 0 .. 4095, representing 161 * the offset of the field in configuration space. Conventional 162 * PCI config space is offset 0 .. 255. Extended config space 163 * is offset 256 .. 4095 164 * 165 * Note: For pci config space accesses, the offset must be 'size' 166 * aligned. 167 * 168 * error_flag - Error flag 169 * 170 * A return value specifies if the action succeeded 171 * or failed, where: 172 * 173 * 0 - No error occurred while performing the service. 174 * non-zero - Error occurred while performing the service. 175 * 176 * io_sync_direction - "direction" definition for pci_dma_sync 177 * 178 * A value specifying the direction for a memory/io sync 179 * operation, The direction value is a flag, one or both 180 * directions may be specified by the caller. 181 * 182 * 0x01 - For device (device read from memory) 183 * 0x02 - For cpu (device write to memory) 184 * 185 * io_page_list - A list of io_page_addresses. An io_page_address 186 * is an r_addr. 187 * 188 * io_page_list_p - A pointer to an io_page_list. 189 */ 190 typedef uint32_t tsbnum_t; 191 typedef uint32_t tsbindex_t; 192 typedef uint64_t tsbid_t; 193 typedef uint64_t r_addr_t; 194 typedef uint64_t io_addr_t; 195 typedef uint64_t io_page_list_t; 196 typedef uint32_t pages_t; 197 typedef uint32_t error_flag_t; 198 199 typedef uint32_t pci_config_offset_t; 200 typedef uint64_t pci_device_t; 201 202 #define PCI_TSB_INDEX 0 203 #define PCI_TSB_INDEX_MASK 0xFFFFFFFF 204 #define PCI_TSB_NUM 32 205 #define PCI_TSB_NUM_MASK 0xFFFFFFFF 206 207 #define PCI_TSBID(tsbnum, tsbindex) \ 208 ((((tsbid_t)tsbnum & PCI_TSB_NUM_MASK) << PCI_TSB_NUM) | \ 209 (((tsbid_t)tsbindex & PCI_TSB_INDEX_MASK) << PCI_TSB_INDEX)) 210 211 #define PCI_TSBID_TO_TSBNUM(tsbid) \ 212 ((tsbid >> PCI_TSB_NUM) & PCI_TSB_NUM_MASK) 213 214 #define PCI_TSBID_TO_TSBINDEX(tsbid) \ 215 ((tsbid >> PCI_TSB_INDEX) & PCI_TSB_INDEX_MASK) 216 217 typedef enum io_attributes { 218 PCI_MAP_ATTR_READ = 0x1ull, 219 PCI_MAP_ATTR_WRITE = 0x2ull, 220 PCI_MAP_ATTR_RO = 0x4ull 221 } io_attributes_t; 222 223 #define PCI_MAP_ATTR_PHFUN 4 224 #define PCI_MAP_ATTR_BDF 16 225 226 #define PX_ADD_ATTR_EXTNS(attr, bdf) \ 227 (attr | (bdf << PCI_MAP_ATTR_BDF)) 228 229 typedef enum io_sync_direction { 230 IO_SYNC_DEVICE = (uint32_t)0x01, 231 IO_SYNC_CPU = (uint32_t)0x02 232 } io_sync_direction_t; 233 234 typedef enum pci_config_size { 235 PCI_CFG_SIZE_BYTE = 0, 236 PCI_CFG_SIZE_WORD, 237 PCI_CFG_SIZE_DWORD 238 } pci_config_size_t; 239 240 typedef union pci_cfg_data { 241 uint8_t b; 242 uint16_t w; 243 uint32_t dw; 244 uint64_t qw; 245 } pci_cfg_data_t; 246 247 /* 248 * MSI Definitions 249 * 250 * MSI - Message Signaled Interrupt 251 * 252 * Message Signaled Interrupt as defined in the PCI Local Bus 253 * Specification and the PCI Express Base Specification. 254 * A device signals an interrupt via MSI using a posted 255 * write cycle to an address specified by system software 256 * using a data value specified by system software. 257 * The MSI capability data structure contains fields for 258 * the PCI address and data values the device uses when 259 * sending an MSI message on the bus. MSI-X is an extended 260 * form of MSI, but uses the same mechanism for signaling 261 * the interrupt as MSI. For the purposes of this document, 262 * the term "MSI" refers to MSI or MSI-X. 263 * 264 * Root complexes that support MSI define an address range 265 * and set of data values that can be used to signal MSIs. 266 * 267 * SUN4V/pci requirements for MSI: 268 * 269 * The root complex defines two address ranges. One in 270 * the 32-bit pci memory space and one in the 64-bit 271 * pci memory address space used as the target of a posted 272 * write to signal an MSI. 273 * 274 * The root complex treats any write to these address 275 * ranges as signaling an MSI, however, only the data 276 * value used in the posted write signals the MSI. 277 * 278 * 279 * MSI EQ - MSI Event Queue 280 * 281 * The MSI Event Queue is a page-aligned main memory data 282 * structure used to store MSI data records. 283 * 284 * Each root port supports several MSI EQs, and each EQ has a 285 * system interrupt associated with it, and can be targeted 286 * (individually) to any cpu. The number of MSI EQs supported 287 * by a root complex is described by a property defined in [3]. 288 * Each MSI EQ must be large enough to contain all possible MSI 289 * data records generated by any one PCI root port. The number 290 * of entries in each MSI EQ is described by a property defined 291 * in [3]. 292 * 293 * Each MSI EQ is compliant with the definition of interrupt 294 * queues described in [5], however, instead of accessing the 295 * queue head/tail registers via ASI-based registers, an API 296 * is provided to access the head/tail registers. 297 * 298 * The SUN4V/pci compliant root complex has the ability to 299 * generate a system interrupt when the MSI EQ is non-empty. 300 * 301 * MSI/Message/INTx Data Record format 302 * 303 * Each data record consists of 64 bytes of data, aligned 304 * on a 64-byte boundary. 305 * 306 * The data record is defined as follows: 307 * 308 * 309 * 6666555555555544444444443333333333222222222211111111110000000000 310 * 3210987654321098765432109876543210987654321098765432109876543210 311 * 312 * 0x00: VVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVVxxxxxxxxxxxxxxxxxxxxxxxxTTTTTTTT 313 * 0x08: IIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIIII 314 * 0x10: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 315 * 0x18: SSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSSS 316 * 0x20: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxRRRRRRRRRRRRRRRR 317 * 0x28: AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA 318 * 0x30: DDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDDD 319 * 0x38: xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx 320 * 321 * Where, 322 * 323 * xx..xx are unused bits and must be ignored by sw. 324 * 325 * VV..VV is the version number of this data record 326 * 327 * For this release of the spec, the version number 328 * field must be zero. 329 * 330 * TTTTTTTT is the data record type: 331 * 332 * Upper 4 bits are reserved, and must be zero 333 * 334 * 0000 - Not an MSI data record - reserved for sw use. 335 * 0001 - MSG 336 * 0010 - MSI32 337 * 0011 - MSI64 338 * 0010 - Reserved 339 * ... 340 * 0111 - Reserved 341 * 1000 - INTx 342 * 1001 - Reserved 343 * ... 344 * 1110 - Reserved 345 * 1111 - Not an MSI data record - reserved for sw use. 346 * 347 * All other encodings are reserved. 348 * 349 * II..II is the sysino for INTx (sw defined value), 350 * otherwise zero. 351 * 352 * SS..SS is the message timestamp if available. 353 * If supported by the implementation, a non-zero 354 * value in this field is a copy of the %stick register 355 * at the time the message is created. 356 * 357 * If unsupported, this field will contain zero. 358 * 359 * RR..RR is the requester ID of the device that initiated the MSI/MSG 360 * and has the following format: 361 * 362 * bbbbbbbb.dddddfff 363 * 364 * Where bb..bb is the bus number, 365 * dd..dd is the device number 366 * and fff is the function number. 367 * 368 * Note that for PCI devices or any message where 369 * the requester is unknown, this may be zero, 370 * or the device-id of an intermediate bridge. 371 * 372 * For intx messages, this field should be ignored. 373 * 374 * AA..AA is the MSI address. For MSI32, the upper 32-bits must be zero. 375 * (for data record type MSG or INTx, this field is ignored) 376 * 377 * DD..DD is the MSI/MSG data or INTx number 378 * 379 * For MSI-X, bits 31..0 contain the data from the MSI packet 380 * which is the msi-number. bits 63..32 shall be zero. 381 * 382 * For MSI, bits 15..0 contain the data from the MSI message 383 * which is the msi-number. bits 63..16 shall be zero 384 * 385 * For MSG data, the message code and message routing code 386 * are encoded as follows: 387 * 388 * 63:32 - 0000.0000.0000.0000.0000.0000.GGGG.GGGG 389 * 32:00 - 0000.0000.0000.0CCC.0000.0000.MMMM.MMMM 390 * 391 * Where, 392 * 393 * GG..GG is the target-id of the message in the 394 * following form: 395 * 396 * bbbbbbbb.dddddfff 397 * 398 * where bb..bb is the target bus number. 399 * ddddd is the target deviceid 400 * fff is the target function number. 401 * 402 * CCC is the message routing code as defined by [4] 403 * 404 * MM..MM is the message code as defined by [4] 405 * 406 * For INTx data, bits 63:2 must be zero and 407 * the low order 2 bits are defined as follows: 408 * 409 * 00 - INTA 410 * 01 - INTB 411 * 10 - INTC 412 * 11 - INTD 413 * 414 * cpuid - A unique opaque value which represents a target cpu. 415 * 416 * devhandle - Device handle. The device handle uniquely identifies a 417 * SUN4V device. It consists of the the lower 28-bits of the hi-cell 418 * of the first entry of the SUN4V device's "reg" property as defined 419 * by the SUN4V Bus Binding to Open Firmware. 420 * 421 * msinum - A value defining which MSI is being used. 422 * 423 * msiqhead - The index value of the current head index for a given 424 * MSI-EQ. 425 * 426 * msiqtail - The index value of the current tail index for a given 427 * MSI-EQ. 428 * 429 * msitype - Type specifier for MSI32 or MSI64 430 * 0 - type is MSI32 431 * 1 - type is MSI64 432 * 433 * msiqid - A number from 0 .. 'number of MSI-EQs - 1', defining 434 * which MSI EQ within the device is being used. 435 * 436 * msiqstate - An unsigned integer containing one of the 437 * following values: 438 * 439 * PCI_MSIQSTATE_IDLE 0 # idle (non-error) state 440 * PCI_MSIQSTATE_ERROR 1 # error state 441 * 442 * msiqvalid - An unsigned integer containing one of the 443 * following values: 444 * 445 * PCI_MSIQ_INVALID 0 # disabled/invalid 446 * PCI_MSIQ_VALID 1 # enabled/valid 447 * 448 * msistate - An unsigned integer containing one of the following 449 * values: 450 * 451 * PCI_MSISTATE_IDLE 0 # idle/not enabled 452 * PCI_MSISTATE_DELIVERED 1 # MSI Delivered 453 * 454 * msivalid - An unsigned integer containing one of the 455 * following values: 456 * 457 * PCI_MSI_INVALID 0 # disabled/invalid 458 * PCI_MSI_VALID 1 # enabled/valid 459 * 460 * msgtype - A value defining which MSG type is being used. An unsigned 461 * integer containing one of the following values: 462 * (as per PCIe spec 1.0a) 463 * 464 * PCIE_PME_MSG 0x18 PME message 465 * PCIE_PME_ACK_MSG 0x1b PME ACK message 466 * PCIE_CORR_MSG 0x30 Correctable message 467 * PCIE_NONFATAL_MSG 0x31 Non fatal message 468 * PCIE_FATAL_MSG 0x33 Fatal message 469 */ 470 471 typedef uint32_t msinum_t; 472 typedef uint32_t msiqid_t; 473 typedef uint32_t msgcode_t; 474 typedef uint64_t msiqhead_t; 475 typedef uint64_t msiqtail_t; 476 477 /* MSIQ state */ 478 typedef enum pci_msiq_state { 479 PCI_MSIQ_STATE_IDLE = (uint32_t)0, /* idle (non-error) state */ 480 PCI_MSIQ_STATE_ERROR = (uint32_t)1 /* error state */ 481 } pci_msiq_state_t; 482 483 /* MSIQ valid */ 484 typedef enum pci_msiq_valid_state { 485 PCI_MSIQ_INVALID = (uint32_t)0, /* disabled/invalid */ 486 PCI_MSIQ_VALID = (uint32_t)1 /* enabled/valid */ 487 } pci_msiq_valid_state_t; 488 489 /* MSIQ Record data structure */ 490 typedef struct msiq_rec { 491 uint64_t msiq_rec_version : 32, /* DW 0 - 63:32 */ 492 msiq_rec_rsvd0 : 24, /* DW 0 - 31:09 */ 493 msiq_rec_type : 8; /* DW 0 - 07:00 */ 494 uint64_t msiq_rec_intx; /* DW 1 */ 495 uint64_t msiq_rec_rsvd1; /* DW 2 */ 496 uint64_t msiq_rec_timestamp; /* DW 3 */ 497 uint64_t msiq_rec_rsvd2 : 48, /* DW 4 - 63:16 */ 498 msiq_rec_rid : 16; /* DW 4 - 15:00 */ 499 uint64_t msiq_rec_msi_addr; /* DW 5 - 63:00 */ 500 union { 501 struct { 502 uint64_t msix_rsvd0 : 32, /* DW 6 - 63:32 */ 503 msix_data : 32; /* DW 6 - 31:00 */ 504 } msix; 505 struct { 506 uint64_t msi_rsvd0 : 48, /* DW 6 - 63:16 */ 507 msi_data: 16; /* DW 6 - 15:00 */ 508 } msi; 509 struct { 510 uint64_t msg_rsvd0: 24, /* DW 6 - 63:40 */ 511 msg_targ: 8, /* DW 6 - 39:32 */ 512 msg_rsvd1: 13, /* DW 6 - 31:19 */ 513 msg_route: 3, /* DW 6 - 18:16 */ 514 msg_rsvd2: 8, /* DW 6 - 15:08 */ 515 msg_code: 8; /* DW 6 - 07:00 */ 516 } msg; 517 } msiq_rec_data; 518 uint64_t msiq_rec_rsvd3; /* DW 7 */ 519 } msiq_rec_t; 520 521 /* MSIQ Record type */ 522 typedef enum msiq_rec_type { 523 MSG_REC = (uint32_t)1, /* PCIe message record */ 524 MSI32_REC = (uint32_t)2, /* MSI32 record */ 525 MSI64_REC = (uint32_t)3, /* MSI64 record */ 526 INTX_REC = (uint32_t)8 /* INTx record */ 527 } msiq_rec_type_t; 528 529 /* MSIQ Record type */ 530 typedef enum msi_type { 531 MSI32_TYPE = (uint32_t)0, /* MSI32 type */ 532 MSI64_TYPE = (uint32_t)1 /* MSI64 type */ 533 } msi_type_t; 534 535 /* MSI state */ 536 typedef enum pci_msi_state { 537 PCI_MSI_STATE_IDLE = (uint32_t)0, /* idle/not enabled */ 538 PCI_MSI_STATE_DELIVERED = (uint32_t)1 /* MSI delivered */ 539 } pci_msi_state_t; 540 541 /* MSI valid */ 542 typedef enum pci_msi_valid_state { 543 PCI_MSI_INVALID = (uint32_t)0, /* disabled/invalid */ 544 PCI_MSI_VALID = (uint32_t)1 /* enabled/valid */ 545 } pci_msi_valid_state_t; 546 547 /* MSG valid */ 548 typedef enum pcie_msg_valid_state { 549 PCIE_MSG_INVALID = (uint32_t)0, /* disabled/invalid */ 550 PCIE_MSG_VALID = (uint32_t)1 /* enabled/valid */ 551 } pcie_msg_valid_state_t; 552 553 /* PCIe MSG types */ 554 typedef enum pcie_msg_type { 555 PCIE_PME_MSG = (uint64_t)0x18, /* PME message */ 556 PCIE_PME_ACK_MSG = (uint64_t)0x1b, /* PME ACK message */ 557 PCIE_CORR_MSG = (uint64_t)0x30, /* Correctable message */ 558 PCIE_NONFATAL_MSG = (uint64_t)0x31, /* Non fatal message */ 559 PCIE_FATAL_MSG = (uint64_t)0x33 /* Fatal message */ 560 } pcie_msg_type_t; 561 562 #endif /* _ASM */ 563 564 #ifdef __cplusplus 565 } 566 #endif 567 568 #endif /* _SYS_PX_IOAPI_H */ 569