1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Internal PCI Fast DVMA implementation 30 */ 31 #include <sys/types.h> 32 #include <sys/kmem.h> 33 #include <sys/async.h> 34 #include <sys/sysmacros.h> 35 #include <sys/sunddi.h> 36 #include <sys/ddi_impldefs.h> 37 #include <sys/dvma.h> 38 #include "px_obj.h" 39 40 /*LINTLIBRARY*/ 41 42 static struct dvma_ops fdvma_ops; 43 typedef struct fast_dvma fdvma_t; 44 45 /* 46 * The following routines are used to implement the sun4u fast dvma 47 * routines on this bus. 48 */ 49 50 /*ARGSUSED*/ 51 static void 52 px_fdvma_load(ddi_dma_handle_t h, caddr_t a, uint_t len, uint_t index, 53 ddi_dma_cookie_t *cp) 54 { 55 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)h; 56 fdvma_t *fdvma_p = (fdvma_t *)mp->dmai_fdvma; 57 px_t *px_p = (px_t *)fdvma_p->softsp; 58 px_mmu_t *mmu_p = px_p->px_mmu_p; 59 dev_info_t *dip = px_p->px_dip; 60 px_dvma_addr_t dvma_addr, dvma_pg; 61 uint32_t offset; 62 size_t npages, pg_index; 63 uint64_t attr; 64 65 offset = (uint32_t)(uintptr_t)a & MMU_PAGE_OFFSET; 66 npages = MMU_BTOPR(len + offset); 67 if (!npages) 68 return; 69 70 /* make sure we don't exceed reserved boundary */ 71 DBG(DBG_FAST_DVMA, dip, "load index=%x: %p+%x ", index, a, len); 72 if (index + npages > mp->dmai_ndvmapages) { 73 cmn_err(px_panic_on_fatal_errors ? CE_PANIC : CE_WARN, 74 "%s%d: kaddr_load index(%x)+pgs(%lx) exceeds limit\n", 75 ddi_driver_name(dip), ddi_get_instance(dip), 76 index, npages); 77 return; 78 } 79 fdvma_p->pagecnt[index] = npages; 80 81 dvma_addr = mp->dmai_mapping + MMU_PTOB(index); 82 dvma_pg = MMU_BTOP(dvma_addr); 83 pg_index = dvma_pg - mmu_p->dvma_base_pg; 84 85 /* construct the dma cookie to be returned */ 86 MAKE_DMA_COOKIE(cp, dvma_addr | offset, len); 87 DBG(DBG_FAST_DVMA | DBG_CONT, dip, "cookie: %x+%x\n", 88 cp->dmac_address, cp->dmac_size); 89 90 attr = PX_GET_TTE_ATTR(mp->dmai_rflags, mp->dmai_attr.dma_attr_flags); 91 92 if (px_lib_iommu_map(dip, PCI_TSBID(0, pg_index), npages, attr, 93 (void *)a, 0, MMU_MAP_BUF) != DDI_SUCCESS) { 94 cmn_err(CE_WARN, "%s%d: kaddr_load can't get " 95 "page frame for vaddr %lx", ddi_driver_name(dip), 96 ddi_get_instance(dip), (uintptr_t)a); 97 } 98 } 99 100 /*ARGSUSED*/ 101 static void 102 px_fdvma_unload(ddi_dma_handle_t h, uint_t index, uint_t sync_flag) 103 { 104 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)h; 105 fdvma_t *fdvma_p = (fdvma_t *)mp->dmai_fdvma; 106 px_t *px_p = (px_t *)fdvma_p->softsp; 107 size_t npages = fdvma_p->pagecnt[index]; 108 px_dvma_addr_t dvma_pg = MMU_BTOP(mp->dmai_mapping + MMU_PTOB(index)); 109 110 DBG(DBG_FAST_DVMA, px_p->px_dip, 111 "unload index=%x sync_flag=%x %x+%x+%x\n", index, sync_flag, 112 mp->dmai_mapping, MMU_PTOB(index), MMU_PTOB(npages)); 113 114 px_mmu_unmap_pages(px_p->px_mmu_p, mp, dvma_pg, npages); 115 fdvma_p->pagecnt[index] = 0; 116 } 117 118 /*ARGSUSED*/ 119 static void 120 px_fdvma_sync(ddi_dma_handle_t h, uint_t index, uint_t sync_flag) 121 { 122 ddi_dma_impl_t *mp = (ddi_dma_impl_t *)h; 123 fdvma_t *fdvma_p = (fdvma_t *)mp->dmai_fdvma; 124 px_t *px_p = (px_t *)fdvma_p->softsp; 125 size_t npg = fdvma_p->pagecnt[index]; 126 127 DBG(DBG_FAST_DVMA, px_p->px_dip, 128 "sync index=%x sync_flag=%x %x+%x+%x\n", index, sync_flag, 129 mp->dmai_mapping, MMU_PTOB(index), MMU_PTOB(npg)); 130 } 131 132 int 133 px_fdvma_reserve(dev_info_t *dip, dev_info_t *rdip, px_t *px_p, 134 ddi_dma_req_t *dmareq, ddi_dma_handle_t *handlep) 135 { 136 fdvma_t *fdvma_p; 137 px_dvma_addr_t dvma_pg; 138 px_mmu_t *mmu_p = px_p->px_mmu_p; 139 size_t npages; 140 ddi_dma_impl_t *mp; 141 ddi_dma_lim_t *lim_p = dmareq->dmar_limits; 142 ulong_t hi = lim_p->dlim_addr_hi; 143 ulong_t lo = lim_p->dlim_addr_lo; 144 size_t counter_max = (lim_p->dlim_cntr_max + 1) & MMU_PAGE_MASK; 145 146 if (px_disable_fdvma) 147 return (DDI_FAILURE); 148 149 DBG(DBG_DMA_CTL, dip, "DDI_DMA_RESERVE: rdip=%s%d\n", 150 ddi_driver_name(rdip), ddi_get_instance(rdip)); 151 152 /* 153 * Check the limit structure. 154 */ 155 if ((lo >= hi) || (hi < mmu_p->mmu_dvma_base)) 156 return (DDI_DMA_BADLIMITS); 157 158 /* 159 * Check the size of the request. 160 */ 161 npages = dmareq->dmar_object.dmao_size; 162 if (npages > mmu_p->mmu_dvma_reserve) 163 return (DDI_DMA_NORESOURCES); 164 165 /* 166 * Allocate the dma handle. 167 */ 168 mp = kmem_zalloc(sizeof (px_dma_hdl_t), KM_SLEEP); 169 170 /* 171 * Get entries from dvma space map. 172 * (vmem_t *vmp, 173 * size_t size, size_t align, size_t phase, 174 * size_t nocross, void *minaddr, void *maxaddr, int vmflag) 175 */ 176 dvma_pg = MMU_BTOP((ulong_t)vmem_xalloc(mmu_p->mmu_dvma_map, 177 MMU_PTOB(npages), MMU_PAGE_SIZE, 0, 178 counter_max, (void *)lo, (void *)(hi + 1), 179 dmareq->dmar_fp == DDI_DMA_SLEEP ? VM_SLEEP : VM_NOSLEEP)); 180 if (dvma_pg == 0) { 181 kmem_free(mp, sizeof (px_dma_hdl_t)); 182 return (DDI_DMA_NOMAPPING); 183 } 184 mmu_p->mmu_dvma_reserve -= npages; 185 186 /* 187 * Create the fast dvma request structure. 188 */ 189 fdvma_p = kmem_alloc(sizeof (fdvma_t), KM_SLEEP); 190 fdvma_p->pagecnt = kmem_alloc(npages * sizeof (uint_t), KM_SLEEP); 191 fdvma_p->ops = &fdvma_ops; 192 fdvma_p->softsp = (caddr_t)px_p; 193 fdvma_p->sync_flag = NULL; 194 195 /* 196 * Initialize the handle. 197 */ 198 mp->dmai_rdip = rdip; 199 mp->dmai_rflags = DMP_BYPASSNEXUS | DDI_DMA_READ | DMP_NOSYNC; 200 mp->dmai_minxfer = dmareq->dmar_limits->dlim_minxfer; 201 mp->dmai_burstsizes = dmareq->dmar_limits->dlim_burstsizes; 202 mp->dmai_mapping = MMU_PTOB(dvma_pg); 203 mp->dmai_ndvmapages = npages; 204 mp->dmai_size = npages * MMU_PAGE_SIZE; 205 mp->dmai_nwin = 0; 206 mp->dmai_fdvma = (caddr_t)fdvma_p; 207 DBG(DBG_DMA_CTL, dip, 208 "DDI_DMA_RESERVE: mp=%p dvma=%x npages=%x private=%p\n", 209 mp, mp->dmai_mapping, npages, fdvma_p); 210 *handlep = (ddi_dma_handle_t)mp; 211 return (DDI_SUCCESS); 212 } 213 214 int 215 px_fdvma_release(dev_info_t *dip, px_t *px_p, ddi_dma_impl_t *mp) 216 { 217 px_mmu_t *mmu_p = px_p->px_mmu_p; 218 size_t npages; 219 fdvma_t *fdvma_p = (fdvma_t *)mp->dmai_fdvma; 220 221 if (px_disable_fdvma) 222 return (DDI_FAILURE); 223 224 /* validate fdvma handle */ 225 if (!(mp->dmai_rflags & DMP_BYPASSNEXUS)) { 226 DBG(DBG_DMA_CTL, dip, "DDI_DMA_RELEASE: not fast dma\n"); 227 return (DDI_FAILURE); 228 } 229 230 /* flush all reserved dvma addresses from mmu */ 231 px_mmu_unmap_window(mmu_p, mp); 232 233 npages = mp->dmai_ndvmapages; 234 vmem_xfree(mmu_p->mmu_dvma_map, (void *)mp->dmai_mapping, 235 MMU_PTOB(npages)); 236 237 mmu_p->mmu_dvma_reserve += npages; 238 mp->dmai_ndvmapages = 0; 239 240 /* see if there is anyone waiting for dvma space */ 241 if (mmu_p->mmu_dvma_clid != 0) { 242 DBG(DBG_DMA_CTL, dip, "run dvma callback\n"); 243 ddi_run_callback(&mmu_p->mmu_dvma_clid); 244 } 245 246 /* free data structures */ 247 kmem_free(fdvma_p->pagecnt, npages * sizeof (uint_t)); 248 kmem_free(fdvma_p, sizeof (fdvma_t)); 249 kmem_free(mp, sizeof (px_dma_hdl_t)); 250 251 /* see if there is anyone waiting for kmem */ 252 if (px_kmem_clid != 0) { 253 DBG(DBG_DMA_CTL, dip, "run handle callback\n"); 254 ddi_run_callback(&px_kmem_clid); 255 } 256 return (DDI_SUCCESS); 257 } 258 259 static struct dvma_ops fdvma_ops = { 260 DVMAO_REV, 261 px_fdvma_load, 262 px_fdvma_unload, 263 px_fdvma_sync 264 }; 265