1 /* 2 * Copyright (c) 1995,1997-1998 by Sun Microsystems, Inc. 3 * All rights reserved. 4 */ 5 6 #ifndef _SYS_SOCALREG_H 7 #define _SYS_SOCALREG_H 8 9 #pragma ident "%Z%%M% %I% %E% SMI" 10 11 #ifdef __cplusplus 12 extern "C" { 13 #endif 14 15 /* 16 * socalreg.h: 17 * 18 * SOC+ Register Definitions, Interface Adaptor to Fiber Channel 19 */ 20 21 #define N_SOCAL_NPORTS 2 22 23 /* 24 * Define the SOC+ configuration register bits. 25 */ 26 typedef union socal_cr_register { 27 struct cr { 28 uint_t aaa:5; 29 uint_t ramsel:3; /* Ram bank select. */ 30 uint_t bbb:6; 31 uint_t eepromsel:2; /* Eeprom bank select. */ 32 uint_t ccc:5; 33 uint_t burst64:3; /* Sbus Burst size, 64 bit mode. */ 34 uint_t ddd:2; 35 uint_t parenable:1; /* Partity test enable. */ 36 uint_t parsbus:1; /* Sbus Parity checking. */ 37 uint_t sbusmode:1; /* Enhanced Sbus mode. */ 38 uint_t sbusburst:3; /* Sbus burst size. */ 39 } reg; 40 uint32_t w; 41 } socal_cr_reg_t; 42 43 /* 44 * Define Configuration register bits. 45 */ 46 47 #define SOCAL_CR_SBUS_BURST_SIZE_MASK 0x007 48 #define SOCAL_CR_SBUS_BURST_SIZE_64BIT_MASK 0x700 49 #define SOCAL_CR_SBUS_BURST_SIZE_64BIT(a) \ 50 (((a) & SOCAL_CR_SBUS_BURST_SIZE_64BIT_MASK) >> 8) 51 52 #define SOCAL_CR_BURST_4 0x0 53 #define SOCAL_CR_BURST_8 0x3 54 #define SOCAL_CR_BURST_16 0x4 55 #define SOCAL_CR_BURST_32 0x5 56 #define SOCAL_CR_BURST_64 0x6 57 #define SOCAL_CR_BURST_128 0x7 58 59 #define SOCAL_CR_SBUS_ENHANCED 0x08 60 #define SOCAL_CR_SBUS_PARITY_CHK 0x10 61 #define SOCAL_CR_SBUS_PARITY_TEST 0x20 62 63 #define SOCAL_CR_EEPROM_BANK_MASK 0x30000 64 #define SOCAL_CR_EEPROM_BANK(a) (((a) & SOCAL_CR_EEPROM_BANK_MASK) >> 16) 65 66 #define SOCAL_CR_EXTERNAL_RAM_BANK_MASK 0x7000000 67 #define SOCAL_CR_EXTERNAL_RAM_BANK(a) \ 68 (((a) & SOCAL_CR_EXTERNAL_RAM_BANK_MASK) >> 24) 69 70 /* 71 * Define SOC+ Slave Access Register. 72 */ 73 typedef union socal_sae_register { 74 struct sae { 75 uint_t aaa:29; /* Reserved. */ 76 uint_t alignment_err:1; /* Soc Alignment Error. */ 77 uint_t bad_size_err:1; /* Bad Size error. */ 78 uint_t parity_err:1; /* Parity Error. */ 79 } reg; 80 uint32_t w; 81 } socal_sae_reg_t; 82 83 /* 84 * Define the Slave Access Regsiter Bits. 85 */ 86 87 #define SOCAL_SAE_PARITY_ERROR 0x01 88 #define SOCAL_SAE_UNSUPPORTED_TRANSFER 0x02 89 #define SOCAL_SAE_ALIGNMENT_ERROR 0x04 90 91 /* 92 * Define SOC+ Command and Status Register. 93 */ 94 typedef union socal_csr_register { 95 struct csr { 96 uint_t comm_param:8; /* Communication Parameters. */ 97 uint_t aaa:4; 98 uint_t socal_to_host:4; /* Soc to host attention. */ 99 uint_t bbb:4; 100 uint_t host_to_socal:4; /* Host to soc+ attention. */ 101 uint_t sae:1; /* Slave access error indicator. */ 102 uint_t ccc:3; 103 uint_t int_pending:1; /* Interrupt Pending. */ 104 uint_t nqcmd:1; /* Non queued command */ 105 uint_t idle:1; /* SOC+ idle indicator. */ 106 uint_t reset:1; /* Software Reset. */ 107 } reg; 108 uint32_t w; 109 } socal_csr_reg_t; 110 111 112 /* 113 * Define SOC+ CSR Register Macros. 114 */ 115 #define SOCAL_CSR_ZEROS 0x00000070 116 #define SOCAL_CSR_SOCAL_TO_HOST 0x000f0000 117 #define SOCAL_CSR_HOST_TO_SOCAL 0x00000f00 118 #define SOCAL_CSR_SLV_ACC_ERR 0x00000080 119 #define SOCAL_CSR_INT_PENDING 0x00000008 120 #define SOCAL_CSR_NON_Q_CMD 0x00000004 121 #define SOCAL_CSR_IDLE 0x00000002 122 #define SOCAL_CSR_SOFT_RESET 0x00000001 123 124 #define SOCAL_CSR_1ST_S_TO_H 0x00010000 125 #define SOCAL_CSR_1ST_H_TO_S 0x00000100 126 127 #define SOCAL_CSR_RSP_QUE_0 SOCAL_CSR_1ST_S_TO_H 128 #define SOCAL_CSR_RSP_QUE_1 0x00020000 129 #define SOCAL_CSR_RSP_QUE_2 0x00040000 130 #define SOCAL_CSR_RSP_QUE_3 0x00080000 131 132 #define SOCAL_CSR_REQ_QUE_0 SOCAL_CSR_1ST_H_TO_S 133 #define SOCAL_CSR_REQ_QUE_1 0x00000200 134 #define SOCAL_CSR_REQ_QUE_2 0x00000400 135 #define SOCAL_CSR_REQ_QUE_3 0x00000800 136 137 /* 138 * Define SOC Interrupt Mask Register Bits. 139 */ 140 141 #define SOCAL_IMR_NON_QUEUED_STATE 0x04 142 #define SOCAL_IMR_SLAVE_ACCESS_ERROR 0x80 143 144 #define SOCAL_IMR_REQUEST_QUEUE_0 0x100 145 #define SOCAL_IMR_REQUEST_QUEUE_1 0x200 146 #define SOCAL_IMR_REQUEST_QUEUE_2 0x400 147 #define SOCAL_IMR_REQUEST_QUEUE_3 0x800 148 149 #define SOCAL_IMR_RESPONSE_QUEUE_0 0x10000 150 #define SOCAL_IMR_RESPONSE_QUEUE_1 0x20000 151 #define SOCAL_IMR_RESPONSE_QUEUE_2 0x40000 152 #define SOCAL_IMR_RESPONSE_QUEUE_3 0x80000 153 154 /* 155 * Define SOC+ Request Queue Index Register 156 */ 157 typedef union socal_reqp_register { 158 struct reqp { 159 uint_t reqq0_index:8; 160 uint_t reqq1_index:8; 161 uint_t reqq2_index:8; 162 uint_t reqq3_index:8; 163 } reg; 164 uint32_t w; 165 } socal_reqp_reg_t; 166 167 #define SOCAL_REQUESTQ0_MASK 0xff000000 168 #define SOCAL_REQUESTQ1_MASK 0x00ff0000 169 #define SOCAL_REQUESTQ2_MASK 0x0000ff00 170 #define SOCAL_REQUESTQ3_MASK 0x000000ff 171 172 #define SOCAL_REQUESTQ0_INDEX(a) (((a) & SOCAL_REQUESTQ0_MASK) >> 24) 173 #define SOCAL_REQUESTQ1_INDEX(a) (((a) & SOCAL_REQUESTQ1_MASK) >> 16) 174 #define SOCAL_REQUESTQ2_INDEX(a) (((a) & SOCAL_REQUESTQ2_MASK) >> 8) 175 #define SOCAL_REQUESTQ3_INDEX(a) ((a) & SOCAL_REQUESTQ3_MASK) 176 177 #define SOCAL_REQUESTQ_INDEX(a, b) ((b)>>((3-(a))<<3) & 0xff) 178 179 /* 180 * Define SOC+ Response Queue Index Register 181 */ 182 typedef union socal_rspp_register { 183 struct rspp { 184 uint_t rspq0_index:8; 185 uint_t rspq1_index:8; 186 uint_t rspq2_index:8; 187 uint_t rspq3_index:8; 188 } reg; 189 uint32_t w; 190 } socal_rspp_reg_t; 191 192 #define SOCAL_RESPONSEQ0_MASK 0xff000000 193 #define SOCAL_RESPONSEQ1_MASK 0x00ff0000 194 #define SOCAL_RESPONSEQ2_MASK 0x0000ff00 195 #define SOCAL_RESPONSEQ3_MASK 0x000000ff 196 197 #define SOCAL_RESPONSEQ0_INDEX(a) (((a) & SOCAL_RESPONSEQ0_MASK) >> 24) 198 #define SOCAL_RESPONSEQ1_INDEX(a) (((a) & SOCAL_RESPONSEQ1_MASK) >> 16) 199 #define SOCAL_RESPONSEQ2_INDEX(a) (((a) & SOCAL_RESPONSEQ2_MASK) >> 8) 200 #define SOCAL_RESPONSEQ3_INDEX(a) ((a) & SOCAL_RESPONSEQ3_MASK) 201 202 #define SOCAL_RESPONSEQ_INDEX(a, b) ((b)>>((3-(a))<<3) & 0xff) 203 204 typedef struct _socalreg_ { 205 socal_cr_reg_t socal_cr; /* Configuration reg */ 206 socal_sae_reg_t socal_sae; /* Slave access error reg */ 207 socal_csr_reg_t socal_csr; /* Command Status reg */ 208 uint32_t socal_imr; /* Interrupt Mask reg */ 209 socal_reqp_reg_t socal_reqp; /* request queue index reg */ 210 socal_rspp_reg_t socal_rspp; /* response queue index reg */ 211 } socal_reg_t; 212 213 /* 214 * Device Address Space Offsets. 215 */ 216 217 #define SOCAL_XRAM_OFFSET 0x10000 218 #define SOCAL_XRAM_SIZE 0x10000 219 220 #define SOCAL_MAX_XCHG 1024 221 222 #define SOCAL_REG_OFFSET (SOCAL_XRAM_OFFSET + SOCAL_XRAM_SIZE) 223 224 #define SOCAL_CQ_REQUEST_OFFSET (SOCAL_XRAM_OFFSET + 0x200) 225 #define SOCAL_CQ_RESPONSE_OFFSET (SOCAL_XRAM_OFFSET + 0x220) 226 227 228 #define SOCAL_INTR_CAUSE(socalp, csr) \ 229 (((csr) & SOCAL_CSR_SOCAL_TO_HOST) | \ 230 ((~csr) & (SOCAL_CSR_HOST_TO_SOCAL))) & socalp->socal_k_imr 231 232 /* 233 * Bus dma burst sizes 234 */ 235 #ifndef BURSTSIZE 236 #define BURSTSIZE 237 #define BURST1 0x01 238 #define BURST2 0x02 239 #define BURST4 0x04 240 #define BURST8 0x08 241 #define BURST16 0x10 242 #define BURST32 0x20 243 #define BURST64 0x40 244 #define BURST128 0x80 245 #define BURSTSIZE_MASK 0xff 246 #define DEFAULT_BURSTSIZE BURST16|BURST8|BURST4|BURST2|BURST1 247 #endif /* BURSTSIZE */ 248 249 #ifdef __cplusplus 250 } 251 #endif 252 253 #endif /* !_SYS_SOCALREG_H */ 254