1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_PRIVREGS_H 27 #define _SYS_PRIVREGS_H 28 29 #ifdef __cplusplus 30 extern "C" { 31 #endif 32 33 /* 34 * This file is kernel isa dependent. 35 */ 36 37 #include <sys/fsr.h> 38 #include <v9/sys/asi.h> 39 40 /* 41 * This file describes the cpu's privileged register set, and 42 * how the machine state is saved on the stack when a trap occurs. 43 */ 44 45 #ifndef _ASM 46 47 struct regs { 48 long long r_tstate; 49 long long r_g1; /* user global regs */ 50 long long r_g2; 51 long long r_g3; 52 long long r_g4; 53 long long r_g5; 54 long long r_g6; 55 long long r_g7; 56 long long r_o0; 57 long long r_o1; 58 long long r_o2; 59 long long r_o3; 60 long long r_o4; 61 long long r_o5; 62 long long r_o6; 63 long long r_o7; 64 /* 65 * These are still 32b in 4u's v8/v9 hybrid 66 */ 67 long r_pc; /* program counter */ 68 long r_npc; /* next program counter */ 69 int r_y; /* the y register */ 70 }; 71 72 #define r_ps r_tstate 73 #define r_sp r_o6 74 75 #endif /* _ASM */ 76 77 #ifdef _KERNEL 78 79 #define lwptoregs(lwp) ((struct regs *)((lwp)->lwp_regs)) 80 #define lwptofpu(lwp) ((kfpu_t *)((lwp)->lwp_fpu)) 81 82 /* 83 * Macros for saving/restoring registers. 84 */ 85 86 #define SAVE_GLOBALS(RP) \ 87 stx %g1, [RP + G1_OFF]; \ 88 stx %g2, [RP + G2_OFF]; \ 89 stx %g3, [RP + G3_OFF]; \ 90 stx %g4, [RP + G4_OFF]; \ 91 stx %g5, [RP + G5_OFF]; \ 92 stx %g6, [RP + G6_OFF]; \ 93 stx %g7, [RP + G7_OFF]; \ 94 mov %y, %g1; \ 95 st %g1, [RP + Y_OFF]; 96 97 #define RESTORE_GLOBALS(RP) \ 98 ld [RP + Y_OFF], %g1; \ 99 mov %g1, %y; \ 100 ldx [RP + G1_OFF], %g1; \ 101 ldx [RP + G2_OFF], %g2; \ 102 ldx [RP + G3_OFF], %g3; \ 103 ldx [RP + G4_OFF], %g4; \ 104 ldx [RP + G5_OFF], %g5; \ 105 ldx [RP + G6_OFF], %g6; \ 106 ldx [RP + G7_OFF], %g7; 107 108 #define SAVE_OUTS(RP) \ 109 stx %i0, [RP + O0_OFF]; \ 110 stx %i1, [RP + O1_OFF]; \ 111 stx %i2, [RP + O2_OFF]; \ 112 stx %i3, [RP + O3_OFF]; \ 113 stx %i4, [RP + O4_OFF]; \ 114 stx %i5, [RP + O5_OFF]; \ 115 stx %i6, [RP + O6_OFF]; \ 116 stx %i7, [RP + O7_OFF]; 117 118 #define RESTORE_OUTS(RP) \ 119 ldx [RP + O0_OFF], %i0; \ 120 ldx [RP + O1_OFF], %i1; \ 121 ldx [RP + O2_OFF], %i2; \ 122 ldx [RP + O3_OFF], %i3; \ 123 ldx [RP + O4_OFF], %i4; \ 124 ldx [RP + O5_OFF], %i5; \ 125 ldx [RP + O6_OFF], %i6; \ 126 ldx [RP + O7_OFF], %i7; 127 128 #define SAVE_V8WINDOW(SBP) \ 129 st %l0, [SBP + (0*4)]; \ 130 st %l1, [SBP + (1*4)]; \ 131 st %l2, [SBP + (2*4)]; \ 132 st %l3, [SBP + (3*4)]; \ 133 st %l4, [SBP + (4*4)]; \ 134 st %l5, [SBP + (5*4)]; \ 135 st %l6, [SBP + (6*4)]; \ 136 st %l7, [SBP + (7*4)]; \ 137 st %i0, [SBP + (8*4)]; \ 138 st %i1, [SBP + (9*4)]; \ 139 st %i2, [SBP + (10*4)]; \ 140 st %i3, [SBP + (11*4)]; \ 141 st %i4, [SBP + (12*4)]; \ 142 st %i5, [SBP + (13*4)]; \ 143 st %i6, [SBP + (14*4)]; \ 144 st %i7, [SBP + (15*4)]; 145 146 #define SAVE_V8WINDOW_ASI(SBP) \ 147 sta %l0, [SBP + (0*4)]%asi; \ 148 sta %l1, [SBP + (1*4)]%asi; \ 149 sta %l2, [SBP + (2*4)]%asi; \ 150 sta %l3, [SBP + (3*4)]%asi; \ 151 sta %l4, [SBP + (4*4)]%asi; \ 152 sta %l5, [SBP + (5*4)]%asi; \ 153 sta %l6, [SBP + (6*4)]%asi; \ 154 sta %l7, [SBP + (7*4)]%asi; \ 155 sta %i0, [SBP + (8*4)]%asi; \ 156 sta %i1, [SBP + (9*4)]%asi; \ 157 sta %i2, [SBP + (10*4)]%asi; \ 158 sta %i3, [SBP + (11*4)]%asi; \ 159 sta %i4, [SBP + (12*4)]%asi; \ 160 sta %i5, [SBP + (13*4)]%asi; \ 161 sta %i6, [SBP + (14*4)]%asi; \ 162 sta %i7, [SBP + (15*4)]%asi; 163 164 #define RESTORE_V8WINDOW(SBP) \ 165 ld [SBP + (0*4)], %l0; \ 166 ld [SBP + (1*4)], %l1; \ 167 ld [SBP + (2*4)], %l2; \ 168 ld [SBP + (3*4)], %l3; \ 169 ld [SBP + (4*4)], %l4; \ 170 ld [SBP + (5*4)], %l5; \ 171 ld [SBP + (6*4)], %l6; \ 172 ld [SBP + (7*4)], %l7; \ 173 ld [SBP + (8*4)], %i0; \ 174 ld [SBP + (9*4)], %i1; \ 175 ld [SBP + (10*4)], %i2; \ 176 ld [SBP + (11*4)], %i3; \ 177 ld [SBP + (12*4)], %i4; \ 178 ld [SBP + (13*4)], %i5; \ 179 ld [SBP + (14*4)], %i6; \ 180 ld [SBP + (15*4)], %i7; 181 182 #define SAVE_V9WINDOW(SBP) \ 183 stx %l0, [SBP + (0*8)]; \ 184 stx %l1, [SBP + (1*8)]; \ 185 stx %l2, [SBP + (2*8)]; \ 186 stx %l3, [SBP + (3*8)]; \ 187 stx %l4, [SBP + (4*8)]; \ 188 stx %l5, [SBP + (5*8)]; \ 189 stx %l6, [SBP + (6*8)]; \ 190 stx %l7, [SBP + (7*8)]; \ 191 stx %i0, [SBP + (8*8)]; \ 192 stx %i1, [SBP + (9*8)]; \ 193 stx %i2, [SBP + (10*8)]; \ 194 stx %i3, [SBP + (11*8)]; \ 195 stx %i4, [SBP + (12*8)]; \ 196 stx %i5, [SBP + (13*8)]; \ 197 stx %i6, [SBP + (14*8)]; \ 198 stx %i7, [SBP + (15*8)]; 199 200 #define SAVE_V9WINDOW_ASI(SBP) \ 201 stxa %l0, [SBP + (0*8)]%asi; \ 202 stxa %l1, [SBP + (1*8)]%asi; \ 203 stxa %l2, [SBP + (2*8)]%asi; \ 204 stxa %l3, [SBP + (3*8)]%asi; \ 205 stxa %l4, [SBP + (4*8)]%asi; \ 206 stxa %l5, [SBP + (5*8)]%asi; \ 207 stxa %l6, [SBP + (6*8)]%asi; \ 208 stxa %l7, [SBP + (7*8)]%asi; \ 209 stxa %i0, [SBP + (8*8)]%asi; \ 210 stxa %i1, [SBP + (9*8)]%asi; \ 211 stxa %i2, [SBP + (10*8)]%asi; \ 212 stxa %i3, [SBP + (11*8)]%asi; \ 213 stxa %i4, [SBP + (12*8)]%asi; \ 214 stxa %i5, [SBP + (13*8)]%asi; \ 215 stxa %i6, [SBP + (14*8)]%asi; \ 216 stxa %i7, [SBP + (15*8)]%asi; 217 218 #define RESTORE_V9WINDOW(SBP) \ 219 ldx [SBP + (0*8)], %l0; \ 220 ldx [SBP + (1*8)], %l1; \ 221 ldx [SBP + (2*8)], %l2; \ 222 ldx [SBP + (3*8)], %l3; \ 223 ldx [SBP + (4*8)], %l4; \ 224 ldx [SBP + (5*8)], %l5; \ 225 ldx [SBP + (6*8)], %l6; \ 226 ldx [SBP + (7*8)], %l7; \ 227 ldx [SBP + (8*8)], %i0; \ 228 ldx [SBP + (9*8)], %i1; \ 229 ldx [SBP + (10*8)], %i2; \ 230 ldx [SBP + (11*8)], %i3; \ 231 ldx [SBP + (12*8)], %i4; \ 232 ldx [SBP + (13*8)], %i5; \ 233 ldx [SBP + (14*8)], %i6; \ 234 ldx [SBP + (15*8)], %i7; 235 236 #define STORE_FPREGS(FP) \ 237 std %f0, [FP]; \ 238 std %f2, [FP + 8]; \ 239 std %f4, [FP + 16]; \ 240 std %f6, [FP + 24]; \ 241 std %f8, [FP + 32]; \ 242 std %f10, [FP + 40]; \ 243 std %f12, [FP + 48]; \ 244 std %f14, [FP + 56]; \ 245 std %f16, [FP + 64]; \ 246 std %f18, [FP + 72]; \ 247 std %f20, [FP + 80]; \ 248 std %f22, [FP + 88]; \ 249 std %f24, [FP + 96]; \ 250 std %f26, [FP + 104]; \ 251 std %f28, [FP + 112]; \ 252 std %f30, [FP + 120]; \ 253 std %d32, [FP + 128]; \ 254 std %d34, [FP + 136]; \ 255 std %d36, [FP + 144]; \ 256 std %d38, [FP + 152]; \ 257 std %d40, [FP + 160]; \ 258 std %d42, [FP + 168]; \ 259 std %d44, [FP + 176]; \ 260 std %d46, [FP + 184]; \ 261 std %d48, [FP + 192]; \ 262 std %d50, [FP + 200]; \ 263 std %d52, [FP + 208]; \ 264 std %d54, [FP + 216]; \ 265 std %d56, [FP + 224]; \ 266 std %d58, [FP + 232]; \ 267 std %d60, [FP + 240]; \ 268 std %d62, [FP + 248]; 269 270 #define LOAD_FPREGS(FP) \ 271 ldd [FP], %f0; \ 272 ldd [FP + 8], %f2; \ 273 ldd [FP + 16], %f4; \ 274 ldd [FP + 24], %f6; \ 275 ldd [FP + 32], %f8; \ 276 ldd [FP + 40], %f10; \ 277 ldd [FP + 48], %f12; \ 278 ldd [FP + 56], %f14; \ 279 ldd [FP + 64], %f16; \ 280 ldd [FP + 72], %f18; \ 281 ldd [FP + 80], %f20; \ 282 ldd [FP + 88], %f22; \ 283 ldd [FP + 96], %f24; \ 284 ldd [FP + 104], %f26; \ 285 ldd [FP + 112], %f28; \ 286 ldd [FP + 120], %f30; \ 287 ldd [FP + 128], %d32; \ 288 ldd [FP + 136], %d34; \ 289 ldd [FP + 144], %d36; \ 290 ldd [FP + 152], %d38; \ 291 ldd [FP + 160], %d40; \ 292 ldd [FP + 168], %d42; \ 293 ldd [FP + 176], %d44; \ 294 ldd [FP + 184], %d46; \ 295 ldd [FP + 192], %d48; \ 296 ldd [FP + 200], %d50; \ 297 ldd [FP + 208], %d52; \ 298 ldd [FP + 216], %d54; \ 299 ldd [FP + 224], %d56; \ 300 ldd [FP + 232], %d58; \ 301 ldd [FP + 240], %d60; \ 302 ldd [FP + 248], %d62; 303 304 #define STORE_DL_FPREGS(FP) \ 305 std %f0, [FP]; \ 306 std %f2, [FP + 8]; \ 307 std %f4, [FP + 16]; \ 308 std %f6, [FP + 24]; \ 309 std %f8, [FP + 32]; \ 310 std %f10, [FP + 40]; \ 311 std %f12, [FP + 48]; \ 312 std %f14, [FP + 56]; \ 313 std %f16, [FP + 64]; \ 314 std %f18, [FP + 72]; \ 315 std %f20, [FP + 80]; \ 316 std %f22, [FP + 88]; \ 317 std %f24, [FP + 96]; \ 318 std %f26, [FP + 104]; \ 319 std %f28, [FP + 112]; \ 320 std %f30, [FP + 120]; 321 322 #define STORE_DU_FPREGS(FP) \ 323 std %d32, [FP + 128]; \ 324 std %d34, [FP + 136]; \ 325 std %d36, [FP + 144]; \ 326 std %d38, [FP + 152]; \ 327 std %d40, [FP + 160]; \ 328 std %d42, [FP + 168]; \ 329 std %d44, [FP + 176]; \ 330 std %d46, [FP + 184]; \ 331 std %d48, [FP + 192]; \ 332 std %d50, [FP + 200]; \ 333 std %d52, [FP + 208]; \ 334 std %d54, [FP + 216]; \ 335 std %d56, [FP + 224]; \ 336 std %d58, [FP + 232]; \ 337 std %d60, [FP + 240]; \ 338 std %d62, [FP + 248]; 339 340 #define LOAD_DL_FPREGS(FP) \ 341 ldd [FP], %f0; \ 342 ldd [FP + 8], %f2; \ 343 ldd [FP + 16], %f4; \ 344 ldd [FP + 24], %f6; \ 345 ldd [FP + 32], %f8; \ 346 ldd [FP + 40], %f10; \ 347 ldd [FP + 48], %f12; \ 348 ldd [FP + 56], %f14; \ 349 ldd [FP + 64], %f16; \ 350 ldd [FP + 72], %f18; \ 351 ldd [FP + 80], %f20; \ 352 ldd [FP + 88], %f22; \ 353 ldd [FP + 96], %f24; \ 354 ldd [FP + 104], %f26; \ 355 ldd [FP + 112], %f28; \ 356 ldd [FP + 120], %f30; 357 358 #define LOAD_DU_FPREGS(FP) \ 359 ldd [FP + 128], %d32; \ 360 ldd [FP + 136], %d34; \ 361 ldd [FP + 144], %d36; \ 362 ldd [FP + 152], %d38; \ 363 ldd [FP + 160], %d40; \ 364 ldd [FP + 168], %d42; \ 365 ldd [FP + 176], %d44; \ 366 ldd [FP + 184], %d46; \ 367 ldd [FP + 192], %d48; \ 368 ldd [FP + 200], %d50; \ 369 ldd [FP + 208], %d52; \ 370 ldd [FP + 216], %d54; \ 371 ldd [FP + 224], %d56; \ 372 ldd [FP + 232], %d58; \ 373 ldd [FP + 240], %d60; \ 374 ldd [FP + 248], %d62; 375 376 #endif /* _KERNEL */ 377 378 /* 379 * V9 privileged registers 380 */ 381 382 /* 383 * Condition Codes Register (CCR) 384 * 385 * |-------------------------------| 386 * | XCC | ICC | 387 * | N | Z | V | C | N | Z | V | C | 388 * |---|---|---|---|---|---|---|---| 389 * 7 6 5 4 3 2 1 0 390 */ 391 #define CCR_IC 0x01 /* 32b carry */ 392 #define CCR_IV 0x02 /* 32b overflow */ 393 #define CCR_IZ 0x04 /* 32b zero */ 394 #define CCR_IN 0x08 /* 32b negative */ 395 #define CCR_XC 0x10 /* 64b carry */ 396 #define CCR_XV 0x20 /* 64b overflow */ 397 #define CCR_XZ 0x40 /* 64b zero */ 398 #define CCR_XN 0x80 /* 64b negative */ 399 #define CCR_ICC 0x0F 400 #define CCR_XCC 0xF0 401 402 403 /* 404 * Processor State Register (PSTATE) 405 * 406 * |-------------------------------------------------------------| 407 * | IG | MG | CLE | TLE | MM | RED | PEF | AM | PRIV | IE | AG | 408 * |-----|----|-----|-----|----|-----|-----|----|------|----|----| 409 * 11 10 9 8 7 6 5 4 3 2 1 0 410 * 411 * Note that the IG, MG, RED and AG fields are not applicable to sun4v 412 * compliant processors. 413 */ 414 #ifndef GLREG 415 #define PSTATE_AG 0x001 /* alternate globals */ 416 #endif /* GLREG */ 417 418 #define PSTATE_IE 0x002 /* interrupt enable */ 419 #define PSTATE_PRIV 0x004 /* privileged mode */ 420 #define PSTATE_AM 0x008 /* use 32b address mask */ 421 #define PSTATE_PEF 0x010 /* fp enable */ 422 423 #ifndef GLREG 424 #define PSTATE_RED 0x020 /* red mode */ 425 #endif /* GLREG */ 426 427 #define PSTATE_MM 0x0C0 /* memory model */ 428 #define PSTATE_TLE 0x100 /* trap little endian */ 429 #define PSTATE_CLE 0x200 /* current little endian */ 430 431 #ifndef GLREG 432 #define PSTATE_MG 0x400 /* MMU globals */ 433 #define PSTATE_IG 0x800 /* interrupt globals */ 434 #endif /* GLREG */ 435 436 #define PSTATE_BITS \ 437 "\020\014IG\013MG\012CLE\011TLE\010MM-RMO\ 438 \07MM-PSO\06RED\05PEF\04AM\03PRIV\02IE\01AG" 439 440 /* 441 * Definition of MM (Memory Mode) bit field of pstate. 442 */ 443 #define PSTATE_MM_TSO 0x00 /* total store ordering */ 444 #define PSTATE_MM_PSO 0x40 /* partial store ordering */ 445 #define PSTATE_MM_RMO 0x80 /* relaxed memory ordering */ 446 #define PSTATE_MM_WC 0xC0 /* weak consistency */ 447 448 449 /* 450 * Trap State Register (TSTATE) 451 * 452 * |------------------------------------------| 453 * | GL | CCR | ASI | --- | PSTATE | -- | CWP | 454 * |----|-----|-----|-----|--------|----|-----| 455 * 42 40 39 32 31 24 23 20 19 8 7 5 4 0 456 * 457 * Note that the GL field is applicable to sun4v compliant processors only. 458 */ 459 #define TSTATE_CWP_MASK 0x01F 460 #define TSTATE_CWP_SHIFT 0 461 #define TSTATE_PSTATE_MASK 0xFFF 462 #define TSTATE_PSTATE_SHIFT 8 463 #define TSTATE_ASI_MASK 0x0FF 464 #define TSTATE_ASI_SHIFT 24 465 #define TSTATE_CCR_MASK 0x0FF 466 #define TSTATE_CCR_SHIFT 32 467 468 #ifdef GLREG 469 #define TSTATE_GL_MASK 0x7 470 #define TSTATE_GL_SHIFT 40 471 #endif /* GLREG */ 472 473 /* 474 * Some handy tstate macros 475 */ 476 #define TSTATE_AG (PSTATE_AG << TSTATE_PSTATE_SHIFT) 477 #define TSTATE_IE (PSTATE_IE << TSTATE_PSTATE_SHIFT) 478 #define TSTATE_PRIV (PSTATE_PRIV << TSTATE_PSTATE_SHIFT) 479 #define TSTATE_AM (PSTATE_AM << TSTATE_PSTATE_SHIFT) 480 #define TSTATE_PEF (PSTATE_PEF << TSTATE_PSTATE_SHIFT) 481 #define TSTATE_MM (PSTATE_MM << TSTATE_PSTATE_SHIFT) 482 #define TSTATE_MM_TSO (PSTATE_MM_TSO << TSTATE_PSTATE_SHIFT) 483 #define TSTATE_MM_WC (PSTATE_MM_WC << TSTATE_PSTATE_SHIFT) 484 #define TSTATE_MG (PSTATE_MG << TSTATE_PSTATE_SHIFT) 485 #define TSTATE_IG (PSTATE_IG << TSTATE_PSTATE_SHIFT) 486 #define TSTATE_CWP TSTATE_CWP_MASK 487 488 /* 489 * as is 64b, but cc is 32b, so we need this hack. 490 */ 491 #ifndef _ASM 492 #define TSTATE_ICC ((long long)CCR_ICC << TSTATE_CCR_SHIFT) 493 #define TSTATE_XCC ((long long)CCR_XCC << TSTATE_CCR_SHIFT) 494 #define TSTATE_IC ((long long)CCR_IC << TSTATE_CCR_SHIFT) 495 #define TSTATE_IV ((long long)CCR_IV << TSTATE_CCR_SHIFT) 496 #define TSTATE_IN ((long long)CCR_IN << TSTATE_CCR_SHIFT) 497 #define TSTATE_XV ((long long)CCR_XV << TSTATE_CCR_SHIFT) 498 #define TSTATE_XZ ((long long)CCR_XZ << TSTATE_CCR_SHIFT) 499 #else 500 #define TSTATE_ICC (CCR_ICC << TSTATE_CCR_SHIFT) 501 #define TSTATE_XCC (CCR_XCC << TSTATE_CCR_SHIFT) 502 #define TSTATE_IC (CCR_IC << TSTATE_CCR_SHIFT) 503 #define TSTATE_IV (CCR_IV << TSTATE_CCR_SHIFT) 504 #define TSTATE_IN (CCR_IN << TSTATE_CCR_SHIFT) 505 #define TSTATE_XV (CCR_XV << TSTATE_CCR_SHIFT) 506 #define TSTATE_XZ (CCR_XZ << TSTATE_CCR_SHIFT) 507 #endif 508 #define TSTATE_V8_UBITS (TSTATE_ICC | TSTATE_PEF) 509 510 /* 511 * Initial kernel and user %tstate. 512 */ 513 #define PTSTATE_KERN_COMMON \ 514 (PSTATE_PRIV | PSTATE_PEF | PSTATE_MM_TSO) 515 516 #define TSTATE_KERN \ 517 (PTSTATE_KERN_COMMON << TSTATE_PSTATE_SHIFT) 518 519 #define PSTATE_KERN \ 520 (PTSTATE_KERN_COMMON | PSTATE_PRIV | PSTATE_IE) 521 522 #define TSTATE_USER32 \ 523 (((PSTATE_IE | PSTATE_PEF | PSTATE_AM) << TSTATE_PSTATE_SHIFT) | \ 524 ((long long)ASI_PNF << TSTATE_ASI_SHIFT)) 525 526 #define TSTATE_USER64 \ 527 (((PSTATE_IE | PSTATE_PEF) << TSTATE_PSTATE_SHIFT) | \ 528 ((long long)ASI_PNF << TSTATE_ASI_SHIFT)) 529 530 #define USERMODE(x) (!((x) & TSTATE_PRIV)) 531 532 /* 533 * Window State Register (WSTATE) 534 * 535 * |------------| 536 * |OTHER|NORMAL| 537 * |-----|------| 538 * 5 3 2 0 539 */ 540 #define WSTATE_BAD 0 /* unused */ 541 #define WSTATE_U32 1 /* 32b stack */ 542 #define WSTATE_U64 2 /* 64b stack */ 543 #define WSTATE_CLEAN32 3 /* cleanwin workaround, 32b stack */ 544 #define WSTATE_CLEAN64 4 /* cleanwin workaround, 64b stack */ 545 #define WSTATE_K32 5 /* priv 32b stack */ 546 #define WSTATE_K64 6 /* priv 64b stack */ 547 #define WSTATE_KMIX 7 /* priv mixed stack */ 548 549 #define WSTATE_CLEAN_OFFSET 2 550 #define WSTATE_SHIFT 3 /* normal-to-other shift */ 551 #define WSTATE_MASK 7 /* mask for each set */ 552 #define WSTATE(o, n) (((o) << WSTATE_SHIFT) | (n)) 553 554 #define WSTATE_USER32 WSTATE(WSTATE_BAD, WSTATE_U32) 555 #define WSTATE_USER64 WSTATE(WSTATE_BAD, WSTATE_U64) 556 #define WSTATE_KERN WSTATE(WSTATE_U32, WSTATE_K64) 557 558 /* 559 * Processor Interrupt Level Register (PIL) 560 * 561 * |-----| 562 * | PIL | 563 * |-----| 564 * 3 0 565 */ 566 567 /* 568 * Version Register (VER) 569 * 570 * |-------------------------------------------------| 571 * | manuf | impl | mask | ---- | maxtl | - | maxwin | 572 * |-------|------|------|------|-------|---|--------| 573 * 63 48 47 32 31 24 23 16 15 8 7 5 4 0 574 */ 575 #define VER_MANUF 0xFFFF000000000000 576 #define VER_IMPL 0x0000FFFF00000000 577 #define VER_MASK 0x00000000FF000000 578 #define VER_MAXTL 0x000000000000FF00 579 #define VER_MAXWIN 0x000000000000001F 580 #define VER_MAXTL_SHIFT 8 581 #define VER_MAXTL_MASK (VER_MAXTL >> VER_MAXTL_SHIFT) 582 583 /* 584 * Tick Register (TICK) 585 * 586 * |---------------| 587 * | npt | counter | 588 * |-----|---------| 589 * 63 62 0 590 * 591 * Note: UltraSparc III Stick register has the same layout. When 592 * present, we clear it too. 593 */ 594 595 #define TICK_NPT 0x8000000000000000 596 #define TICK_COUNTER 0x7FFFFFFFFFFFFFFF 597 598 #ifdef __cplusplus 599 } 600 #endif 601 602 #endif /* _SYS_PRIVREGS_H */ 603