1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22 /* 23 * Copyright 1991-1998,2003 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_SIMULATE_H 28 #define _SYS_SIMULATE_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 #ifdef __cplusplus 33 extern "C" { 34 #endif 35 36 /* SPARC instruction simulator return codes. */ 37 38 #define SIMU_SUCCESS 1 /* simulation worked */ 39 #define SIMU_ILLEGAL 2 /* tried to simulate an illegal instuction */ 40 #define SIMU_FAULT 3 /* simulation generated an illegal access */ 41 #define SIMU_DZERO 4 /* simulation generated divide by zero */ 42 #define SIMU_UNALIGN 5 /* simulation generated an unaligned access */ 43 #define SIMU_RETRY 6 /* fixed up instruction, now retry it */ 44 45 46 /* 47 * Opcode types. 48 */ 49 #define OP_V8_BRANCH 0 50 #define OP_V8_CALL 1 51 #define OP_V8_ARITH 2 /* includes control xfer (e.g. JMPL) */ 52 #define OP_V8_LDSTR 3 53 54 /* 55 * Relevant instruction opcodes. 56 */ 57 58 /* OP_V8_LDSTR */ 59 #define IOP_V8_LD 0x00 60 #define IOP_V8_LDA 0x10 61 #define IOP_V8_LDUBA 0x11 62 #define IOP_V8_LDUHA 0x12 63 #define IOP_V8_LDDA 0x13 64 #define IOP_V8_STA 0x14 65 #define IOP_V8_STBA 0x15 66 #define IOP_V8_STHA 0x16 67 #define IOP_V8_STDA 0x17 68 #define IOP_V8_LDSBA 0x19 69 #define IOP_V8_LDSHA 0x1a 70 #define IOP_V8_LDSTUBA 0x1d 71 #define IOP_V8_SWAPA 0x1f 72 #define IOP_V8_LDFSR 0x21 73 #define IOP_V8_LDQF 0x22 74 #define IOP_V8_STFSR 0x25 75 #define IOP_V8_STQF 0x26 76 #define IOP_V8_LDQFA 0x32 77 #define IOP_V8_LDDFA 0x33 78 #define IOP_V8_STQFA 0x36 79 #define IOP_V8_STDFA 0x37 80 81 /* OP_V8_ARITH */ 82 #define IOP_V8_ADD 0x00 83 #define IOP_V8_AND 0x01 84 #define IOP_V8_OR 0x02 85 #define IOP_V8_XOR 0x03 86 #define IOP_V8_SUB 0x04 87 #define IOP_V8_ANDN 0x05 88 #define IOP_V8_ORN 0x06 89 #define IOP_V8_XNOR 0x07 90 #define IOP_V8_ADDC 0x08 91 #define IOP_V8_UMUL 0x0a 92 #define IOP_V8_SMUL 0x0b 93 #define IOP_V8_SUBC 0x0c 94 #define IOP_V8_UDIV 0x0e 95 #define IOP_V8_SDIV 0x0f 96 #define IOP_V8_ADDcc 0x10 97 #define IOP_V8_ANDcc 0x11 98 #define IOP_V8_ORcc 0x12 99 #define IOP_V8_XORcc 0x13 100 #define IOP_V8_SUBcc 0x14 101 #define IOP_V8_ANDNcc 0x15 102 #define IOP_V8_ORNcc 0x16 103 #define IOP_V8_XNORcc 0x17 104 #define IOP_V8_ADDCcc 0x18 105 #define IOP_V8_UMULcc 0x1a 106 #define IOP_V8_SMULcc 0x1b 107 #define IOP_V8_SUBCcc 0x1c 108 #define IOP_V8_UDIVcc 0x1e 109 #define IOP_V8_SDIVcc 0x1f 110 #define IOP_V8_TADDcc 0x20 111 #define IOP_V8_TSUBcc 0x21 112 #define IOP_V8_TADDccTV 0x22 113 #define IOP_V8_TSUBccTV 0x23 114 #define IOP_V8_MULScc 0x24 115 #define IOP_V8_SLL 0x25 116 #define IOP_V8_SRL 0x26 117 #define IOP_V8_SRA 0x27 118 #define IOP_V8_RDASR 0x28 119 #define IOP_V8_POPC 0x2e 120 #define IOP_V8_WRASR 0x30 121 #define IOP_V8_FCMP 0x35 122 #define IOP_V8_JMPL 0x38 123 #define IOP_V8_RETT 0x39 124 #define IOP_V8_TCC 0x3a 125 #define IOP_V8_FLUSH 0x3b 126 #define IOP_V8_SAVE 0x3c 127 #define IOP_V8_RESTORE 0x3d 128 129 /* 130 * Check for a load/store to alternate space. All other ld/st 131 * instructions should have bits 12-5 clear, if the i-bit is 0. 132 */ 133 #define IS_LDST_ALT(x) \ 134 (((x) == IOP_V8_LDA || (x) == IOP_V8_LDDA || \ 135 (x) == IOP_V8_LDSBA || (x) == IOP_V8_LDSHA || \ 136 (x) == IOP_V8_LDSTUBA || (x) == IOP_V8_LDUBA || \ 137 (x) == IOP_V8_LDUHA || (x) == IOP_V8_STA || \ 138 (x) == IOP_V8_STBA || (x) == IOP_V8_STDA || \ 139 (x) == IOP_V8_STHA || (x) == IOP_V8_SWAPA) ? 1 : 0) 140 141 142 #ifndef _ASM 143 144 #include <vm/seg_enum.h> 145 146 extern int32_t fetch_user_instr(caddr_t); 147 extern int simulate_unimp(struct regs *, caddr_t *); 148 extern int do_unaligned(struct regs *, caddr_t *); 149 extern int calc_memaddr(struct regs *, caddr_t *); 150 extern int is_atomic(struct regs *); 151 extern int instr_size(struct regs *, caddr_t *, enum seg_rw); 152 extern int getreg(struct regs *, uint_t, uint64_t *, caddr_t *); 153 extern int putreg(uint64_t *, struct regs *, uint_t, caddr_t *); 154 extern int extended_asi_size(int asi); 155 156 #endif /* _ASM */ 157 158 #ifdef __cplusplus 159 } 160 #endif 161 162 #endif /* _SYS_SIMULATE_H */ 163