xref: /titanic_44/usr/src/uts/sparc/sys/cpu.h (revision 6dfee4834394825da35b977ca71cdc965bc7b6a4)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License, Version 1.0 only
6  * (the "License").  You may not use this file except in compliance
7  * with the License.
8  *
9  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
10  * or http://www.opensolaris.org/os/licensing.
11  * See the License for the specific language governing permissions
12  * and limitations under the License.
13  *
14  * When distributing Covered Code, include this CDDL HEADER in each
15  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
16  * If applicable, add the following below this CDDL HEADER, with the
17  * fields enclosed by brackets "[]" replaced with your own identifying
18  * information: Portions Copyright [yyyy] [name of copyright owner]
19  *
20  * CDDL HEADER END
21  */
22 /*
23  * Copyright 2004 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 #ifndef _SYS_CPU_H
28 #define	_SYS_CPU_H
29 
30 #pragma ident	"%Z%%M%	%I%	%E% SMI"
31 
32 /*
33  * Include generic bustype cookies.
34  */
35 #include <sys/bustypes.h>
36 
37 #ifdef	__cplusplus
38 extern "C" {
39 #endif
40 
41 /*
42  * Global kernel variables of interest
43  */
44 
45 #if defined(_KERNEL) && !defined(_ASM)
46 
47 extern int dvmasize;			/* usable dvma size in pages */
48 
49 /*
50  * Cache defines
51  *
52  * Each bit represents an attribute of the system's caches that
53  * the OS must handle.  For example, VAC caches must have virtual
54  * alias detection, VTAG caches must be flushed on every demap, etc.
55  */
56 #define	CACHE_NONE		0	/* No caches of any type */
57 #define	CACHE_VAC		0x01	/* Virtual addressed cache */
58 #define	CACHE_VTAG		0x02	/* Virtual tagged cache */
59 #define	CACHE_PAC		0x04	/* Physical addressed cache */
60 #define	CACHE_PTAG		0x08	/* Physical tagged cache */
61 #define	CACHE_WRITEBACK		0x10	/* Writeback cache */
62 #define	CACHE_IOCOHERENT	0x20	/* I/O coherent cache */
63 
64 extern int cache;
65 
66 /* set this to zero if no vac */
67 extern int vac;
68 
69 /*
70  * Use to insert cpu-dependent instructions into spin loops
71  */
72 #define	SMT_PAUSE()		/* none */
73 
74 #endif /* defined(_KERNEL) && !defined(_ASM) */
75 
76 #ifdef	__cplusplus
77 }
78 #endif
79 
80 #endif	/* _SYS_CPU_H */
81