1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 1995, 2010, Oracle and/or its affiliates. All rights reserved. 23 */ 24 /* 25 * Copyright (c) 2010, Intel Corporation. 26 * All rights reserved. 27 */ 28 29 #ifndef _SYS_X86_ARCHEXT_H 30 #define _SYS_X86_ARCHEXT_H 31 32 #if !defined(_ASM) 33 #include <sys/regset.h> 34 #include <sys/processor.h> 35 #include <vm/seg_enum.h> 36 #include <vm/page.h> 37 #endif /* _ASM */ 38 39 #ifdef __cplusplus 40 extern "C" { 41 #endif 42 43 /* 44 * cpuid instruction feature flags in %edx (standard function 1) 45 */ 46 47 #define CPUID_INTC_EDX_FPU 0x00000001 /* x87 fpu present */ 48 #define CPUID_INTC_EDX_VME 0x00000002 /* virtual-8086 extension */ 49 #define CPUID_INTC_EDX_DE 0x00000004 /* debugging extensions */ 50 #define CPUID_INTC_EDX_PSE 0x00000008 /* page size extension */ 51 #define CPUID_INTC_EDX_TSC 0x00000010 /* time stamp counter */ 52 #define CPUID_INTC_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 53 #define CPUID_INTC_EDX_PAE 0x00000040 /* physical addr extension */ 54 #define CPUID_INTC_EDX_MCE 0x00000080 /* machine check exception */ 55 #define CPUID_INTC_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 56 #define CPUID_INTC_EDX_APIC 0x00000200 /* local APIC */ 57 /* 0x400 - reserved */ 58 #define CPUID_INTC_EDX_SEP 0x00000800 /* sysenter and sysexit */ 59 #define CPUID_INTC_EDX_MTRR 0x00001000 /* memory type range reg */ 60 #define CPUID_INTC_EDX_PGE 0x00002000 /* page global enable */ 61 #define CPUID_INTC_EDX_MCA 0x00004000 /* machine check arch */ 62 #define CPUID_INTC_EDX_CMOV 0x00008000 /* conditional move insns */ 63 #define CPUID_INTC_EDX_PAT 0x00010000 /* page attribute table */ 64 #define CPUID_INTC_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 65 #define CPUID_INTC_EDX_PSN 0x00040000 /* processor serial number */ 66 #define CPUID_INTC_EDX_CLFSH 0x00080000 /* clflush instruction */ 67 /* 0x100000 - reserved */ 68 #define CPUID_INTC_EDX_DS 0x00200000 /* debug store exists */ 69 #define CPUID_INTC_EDX_ACPI 0x00400000 /* monitoring + clock ctrl */ 70 #define CPUID_INTC_EDX_MMX 0x00800000 /* MMX instructions */ 71 #define CPUID_INTC_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 72 #define CPUID_INTC_EDX_SSE 0x02000000 /* streaming SIMD extensions */ 73 #define CPUID_INTC_EDX_SSE2 0x04000000 /* SSE extensions */ 74 #define CPUID_INTC_EDX_SS 0x08000000 /* self-snoop */ 75 #define CPUID_INTC_EDX_HTT 0x10000000 /* Hyper Thread Technology */ 76 #define CPUID_INTC_EDX_TM 0x20000000 /* thermal monitoring */ 77 #define CPUID_INTC_EDX_IA64 0x40000000 /* Itanium emulating IA32 */ 78 #define CPUID_INTC_EDX_PBE 0x80000000 /* Pending Break Enable */ 79 80 #define FMT_CPUID_INTC_EDX \ 81 "\20" \ 82 "\40pbe\37ia64\36tm\35htt\34ss\33sse2\32sse\31fxsr" \ 83 "\30mmx\27acpi\26ds\24clfsh\23psn\22pse36\21pat" \ 84 "\20cmov\17mca\16pge\15mtrr\14sep\12apic\11cx8" \ 85 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 86 87 /* 88 * cpuid instruction feature flags in %ecx (standard function 1) 89 */ 90 91 #define CPUID_INTC_ECX_SSE3 0x00000001 /* Yet more SSE extensions */ 92 #define CPUID_INTC_ECX_PCLMULQDQ 0x00000002 /* PCLMULQDQ insn */ 93 /* 0x00000004 - reserved */ 94 #define CPUID_INTC_ECX_MON 0x00000008 /* MONITOR/MWAIT */ 95 #define CPUID_INTC_ECX_DSCPL 0x00000010 /* CPL-qualified debug store */ 96 #define CPUID_INTC_ECX_VMX 0x00000020 /* Hardware VM extensions */ 97 #define CPUID_INTC_ECX_SMX 0x00000040 /* Secure mode extensions */ 98 #define CPUID_INTC_ECX_EST 0x00000080 /* enhanced SpeedStep */ 99 #define CPUID_INTC_ECX_TM2 0x00000100 /* thermal monitoring */ 100 #define CPUID_INTC_ECX_SSSE3 0x00000200 /* Supplemental SSE3 insns */ 101 #define CPUID_INTC_ECX_CID 0x00000400 /* L1 context ID */ 102 /* 0x00000800 - reserved */ 103 /* 0x00001000 - reserved */ 104 #define CPUID_INTC_ECX_CX16 0x00002000 /* cmpxchg16 */ 105 #define CPUID_INTC_ECX_ETPRD 0x00004000 /* extended task pri messages */ 106 /* 0x00008000 - reserved */ 107 /* 0x00010000 - reserved */ 108 /* 0x00020000 - reserved */ 109 #define CPUID_INTC_ECX_DCA 0x00040000 /* direct cache access */ 110 #define CPUID_INTC_ECX_SSE4_1 0x00080000 /* SSE4.1 insns */ 111 #define CPUID_INTC_ECX_SSE4_2 0x00100000 /* SSE4.2 insns */ 112 #define CPUID_INTC_ECX_MOVBE 0x00400000 /* MOVBE insn */ 113 #define CPUID_INTC_ECX_POPCNT 0x00800000 /* POPCNT insn */ 114 #define CPUID_INTC_ECX_AES 0x02000000 /* AES insns */ 115 116 #define FMT_CPUID_INTC_ECX \ 117 "\20" \ 118 "\32aes" \ 119 "\30popcnt\27movbe\25sse4.2\24sse4.1\23dca" \ 120 "\20\17etprd\16cx16\13cid\12ssse3\11tm2" \ 121 "\10est\7smx\6vmx\5dscpl\4mon\2pclmulqdq\1sse3" 122 123 /* 124 * cpuid instruction feature flags in %edx (extended function 0x80000001) 125 */ 126 127 #define CPUID_AMD_EDX_FPU 0x00000001 /* x87 fpu present */ 128 #define CPUID_AMD_EDX_VME 0x00000002 /* virtual-8086 extension */ 129 #define CPUID_AMD_EDX_DE 0x00000004 /* debugging extensions */ 130 #define CPUID_AMD_EDX_PSE 0x00000008 /* page size extensions */ 131 #define CPUID_AMD_EDX_TSC 0x00000010 /* time stamp counter */ 132 #define CPUID_AMD_EDX_MSR 0x00000020 /* rdmsr and wrmsr */ 133 #define CPUID_AMD_EDX_PAE 0x00000040 /* physical addr extension */ 134 #define CPUID_AMD_EDX_MCE 0x00000080 /* machine check exception */ 135 #define CPUID_AMD_EDX_CX8 0x00000100 /* cmpxchg8b instruction */ 136 #define CPUID_AMD_EDX_APIC 0x00000200 /* local APIC */ 137 /* 0x00000400 - sysc on K6m6 */ 138 #define CPUID_AMD_EDX_SYSC 0x00000800 /* AMD: syscall and sysret */ 139 #define CPUID_AMD_EDX_MTRR 0x00001000 /* memory type and range reg */ 140 #define CPUID_AMD_EDX_PGE 0x00002000 /* page global enable */ 141 #define CPUID_AMD_EDX_MCA 0x00004000 /* machine check arch */ 142 #define CPUID_AMD_EDX_CMOV 0x00008000 /* conditional move insns */ 143 #define CPUID_AMD_EDX_PAT 0x00010000 /* K7: page attribute table */ 144 #define CPUID_AMD_EDX_FCMOV 0x00010000 /* FCMOVcc etc. */ 145 #define CPUID_AMD_EDX_PSE36 0x00020000 /* 36-bit pagesize extension */ 146 /* 0x00040000 - reserved */ 147 /* 0x00080000 - reserved */ 148 #define CPUID_AMD_EDX_NX 0x00100000 /* AMD: no-execute page prot */ 149 /* 0x00200000 - reserved */ 150 #define CPUID_AMD_EDX_MMXamd 0x00400000 /* AMD: MMX extensions */ 151 #define CPUID_AMD_EDX_MMX 0x00800000 /* MMX instructions */ 152 #define CPUID_AMD_EDX_FXSR 0x01000000 /* fxsave and fxrstor */ 153 #define CPUID_AMD_EDX_FFXSR 0x02000000 /* fast fxsave/fxrstor */ 154 #define CPUID_AMD_EDX_1GPG 0x04000000 /* 1GB page */ 155 #define CPUID_AMD_EDX_TSCP 0x08000000 /* rdtscp instruction */ 156 /* 0x10000000 - reserved */ 157 #define CPUID_AMD_EDX_LM 0x20000000 /* AMD: long mode */ 158 #define CPUID_AMD_EDX_3DNowx 0x40000000 /* AMD: extensions to 3DNow! */ 159 #define CPUID_AMD_EDX_3DNow 0x80000000 /* AMD: 3DNow! instructions */ 160 161 #define FMT_CPUID_AMD_EDX \ 162 "\20" \ 163 "\40a3d\37a3d+\36lm\34tscp\32ffxsr\31fxsr" \ 164 "\30mmx\27mmxext\25nx\22pse\21pat" \ 165 "\20cmov\17mca\16pge\15mtrr\14syscall\12apic\11cx8" \ 166 "\10mce\7pae\6msr\5tsc\4pse\3de\2vme\1fpu" 167 168 #define CPUID_AMD_ECX_AHF64 0x00000001 /* LAHF and SAHF in long mode */ 169 #define CPUID_AMD_ECX_CMP_LGCY 0x00000002 /* AMD: multicore chip */ 170 #define CPUID_AMD_ECX_SVM 0x00000004 /* AMD: secure VM */ 171 #define CPUID_AMD_ECX_EAS 0x00000008 /* extended apic space */ 172 #define CPUID_AMD_ECX_CR8D 0x00000010 /* AMD: 32-bit mov %cr8 */ 173 #define CPUID_AMD_ECX_LZCNT 0x00000020 /* AMD: LZCNT insn */ 174 #define CPUID_AMD_ECX_SSE4A 0x00000040 /* AMD: SSE4A insns */ 175 #define CPUID_AMD_ECX_MAS 0x00000080 /* AMD: MisAlignSse mnode */ 176 #define CPUID_AMD_ECX_3DNP 0x00000100 /* AMD: 3DNowPrefectch */ 177 #define CPUID_AMD_ECX_OSVW 0x00000200 /* AMD: OSVW */ 178 #define CPUID_AMD_ECX_IBS 0x00000400 /* AMD: IBS */ 179 #define CPUID_AMD_ECX_SSE5 0x00000800 /* AMD: SSE5 */ 180 #define CPUID_AMD_ECX_SKINIT 0x00001000 /* AMD: SKINIT */ 181 #define CPUID_AMD_ECX_WDT 0x00002000 /* AMD: WDT */ 182 183 #define FMT_CPUID_AMD_ECX \ 184 "\20" \ 185 "\14wdt\13skinit\12sse5\11ibs\10osvw\93dnp\8mas" \ 186 "\7sse4a\6lzcnt\5cr8d\3svm\2lcmplgcy\1ahf64" 187 188 /* 189 * Intel now seems to have claimed part of the "extended" function 190 * space that we previously for non-Intel implementors to use. 191 * More excitingly still, they've claimed bit 20 to mean LAHF/SAHF 192 * is available in long mode i.e. what AMD indicate using bit 0. 193 * On the other hand, everything else is labelled as reserved. 194 */ 195 #define CPUID_INTC_ECX_AHF64 0x00100000 /* LAHF and SAHF in long mode */ 196 197 198 #define P5_MCHADDR 0x0 199 #define P5_CESR 0x11 200 #define P5_CTR0 0x12 201 #define P5_CTR1 0x13 202 203 #define K5_MCHADDR 0x0 204 #define K5_MCHTYPE 0x01 205 #define K5_TSC 0x10 206 #define K5_TR12 0x12 207 208 #define REG_PAT 0x277 209 210 #define REG_MC0_CTL 0x400 211 #define REG_MC5_MISC 0x417 212 #define REG_PERFCTR0 0xc1 213 #define REG_PERFCTR1 0xc2 214 215 #define REG_PERFEVNT0 0x186 216 #define REG_PERFEVNT1 0x187 217 218 #define REG_TSC 0x10 /* timestamp counter */ 219 #define REG_APIC_BASE_MSR 0x1b 220 #define REG_X2APIC_BASE_MSR 0x800 /* The MSR address offset of x2APIC */ 221 222 #if !defined(__xpv) 223 /* 224 * AMD C1E 225 */ 226 #define MSR_AMD_INT_PENDING_CMP_HALT 0xC0010055 227 #define AMD_ACTONCMPHALT_SHIFT 27 228 #define AMD_ACTONCMPHALT_MASK 3 229 #endif 230 231 #define MSR_DEBUGCTL 0x1d9 232 233 #define DEBUGCTL_LBR 0x01 234 #define DEBUGCTL_BTF 0x02 235 236 /* Intel P6, AMD */ 237 #define MSR_LBR_FROM 0x1db 238 #define MSR_LBR_TO 0x1dc 239 #define MSR_LEX_FROM 0x1dd 240 #define MSR_LEX_TO 0x1de 241 242 /* Intel P4 (pre-Prescott, non P4 M) */ 243 #define MSR_P4_LBSTK_TOS 0x1da 244 #define MSR_P4_LBSTK_0 0x1db 245 #define MSR_P4_LBSTK_1 0x1dc 246 #define MSR_P4_LBSTK_2 0x1dd 247 #define MSR_P4_LBSTK_3 0x1de 248 249 /* Intel Pentium M */ 250 #define MSR_P6M_LBSTK_TOS 0x1c9 251 #define MSR_P6M_LBSTK_0 0x040 252 #define MSR_P6M_LBSTK_1 0x041 253 #define MSR_P6M_LBSTK_2 0x042 254 #define MSR_P6M_LBSTK_3 0x043 255 #define MSR_P6M_LBSTK_4 0x044 256 #define MSR_P6M_LBSTK_5 0x045 257 #define MSR_P6M_LBSTK_6 0x046 258 #define MSR_P6M_LBSTK_7 0x047 259 260 /* Intel P4 (Prescott) */ 261 #define MSR_PRP4_LBSTK_TOS 0x1da 262 #define MSR_PRP4_LBSTK_FROM_0 0x680 263 #define MSR_PRP4_LBSTK_FROM_1 0x681 264 #define MSR_PRP4_LBSTK_FROM_2 0x682 265 #define MSR_PRP4_LBSTK_FROM_3 0x683 266 #define MSR_PRP4_LBSTK_FROM_4 0x684 267 #define MSR_PRP4_LBSTK_FROM_5 0x685 268 #define MSR_PRP4_LBSTK_FROM_6 0x686 269 #define MSR_PRP4_LBSTK_FROM_7 0x687 270 #define MSR_PRP4_LBSTK_FROM_8 0x688 271 #define MSR_PRP4_LBSTK_FROM_9 0x689 272 #define MSR_PRP4_LBSTK_FROM_10 0x68a 273 #define MSR_PRP4_LBSTK_FROM_11 0x68b 274 #define MSR_PRP4_LBSTK_FROM_12 0x68c 275 #define MSR_PRP4_LBSTK_FROM_13 0x68d 276 #define MSR_PRP4_LBSTK_FROM_14 0x68e 277 #define MSR_PRP4_LBSTK_FROM_15 0x68f 278 #define MSR_PRP4_LBSTK_TO_0 0x6c0 279 #define MSR_PRP4_LBSTK_TO_1 0x6c1 280 #define MSR_PRP4_LBSTK_TO_2 0x6c2 281 #define MSR_PRP4_LBSTK_TO_3 0x6c3 282 #define MSR_PRP4_LBSTK_TO_4 0x6c4 283 #define MSR_PRP4_LBSTK_TO_5 0x6c5 284 #define MSR_PRP4_LBSTK_TO_6 0x6c6 285 #define MSR_PRP4_LBSTK_TO_7 0x6c7 286 #define MSR_PRP4_LBSTK_TO_8 0x6c8 287 #define MSR_PRP4_LBSTK_TO_9 0x6c9 288 #define MSR_PRP4_LBSTK_TO_10 0x6ca 289 #define MSR_PRP4_LBSTK_TO_11 0x6cb 290 #define MSR_PRP4_LBSTK_TO_12 0x6cc 291 #define MSR_PRP4_LBSTK_TO_13 0x6cd 292 #define MSR_PRP4_LBSTK_TO_14 0x6ce 293 #define MSR_PRP4_LBSTK_TO_15 0x6cf 294 295 #define MCI_CTL_VALUE 0xffffffff 296 297 #define MTRR_TYPE_UC 0 298 #define MTRR_TYPE_WC 1 299 #define MTRR_TYPE_WT 4 300 #define MTRR_TYPE_WP 5 301 #define MTRR_TYPE_WB 6 302 #define MTRR_TYPE_UC_ 7 303 304 /* 305 * For Solaris we set up the page attritubute table in the following way: 306 * PAT0 Write-Back 307 * PAT1 Write-Through 308 * PAT2 Unchacheable- 309 * PAT3 Uncacheable 310 * PAT4 Write-Back 311 * PAT5 Write-Through 312 * PAT6 Write-Combine 313 * PAT7 Uncacheable 314 * The only difference from h/w default is entry 6. 315 */ 316 #define PAT_DEFAULT_ATTRIBUTE \ 317 ((uint64_t)MTRR_TYPE_WB | \ 318 ((uint64_t)MTRR_TYPE_WT << 8) | \ 319 ((uint64_t)MTRR_TYPE_UC_ << 16) | \ 320 ((uint64_t)MTRR_TYPE_UC << 24) | \ 321 ((uint64_t)MTRR_TYPE_WB << 32) | \ 322 ((uint64_t)MTRR_TYPE_WT << 40) | \ 323 ((uint64_t)MTRR_TYPE_WC << 48) | \ 324 ((uint64_t)MTRR_TYPE_UC << 56)) 325 326 #define X86FSET_LARGEPAGE 0 327 #define X86FSET_TSC 1 328 #define X86FSET_MSR 2 329 #define X86FSET_MTRR 3 330 #define X86FSET_PGE 4 331 #define X86FSET_DE 5 332 #define X86FSET_CMOV 6 333 #define X86FSET_MMX 7 334 #define X86FSET_MCA 8 335 #define X86FSET_PAE 9 336 #define X86FSET_CX8 10 337 #define X86FSET_PAT 11 338 #define X86FSET_SEP 12 339 #define X86FSET_SSE 13 340 #define X86FSET_SSE2 14 341 #define X86FSET_HTT 15 342 #define X86FSET_ASYSC 16 343 #define X86FSET_NX 17 344 #define X86FSET_SSE3 18 345 #define X86FSET_CX16 19 346 #define X86FSET_CMP 20 347 #define X86FSET_TSCP 21 348 #define X86FSET_MWAIT 22 349 #define X86FSET_SSE4A 23 350 #define X86FSET_CPUID 24 351 #define X86FSET_SSSE3 25 352 #define X86FSET_SSE4_1 26 353 #define X86FSET_SSE4_2 27 354 #define X86FSET_1GPG 28 355 #define X86FSET_CLFSH 29 356 #define X86FSET_64 30 357 #define X86FSET_AES 31 358 #define X86FSET_PCLMULQDQ 32 359 360 /* 361 * flags to patch tsc_read routine. 362 */ 363 #define X86_NO_TSC 0x0 364 #define X86_HAVE_TSCP 0x1 365 #define X86_TSC_MFENCE 0x2 366 #define X86_TSC_LFENCE 0x4 367 368 /* 369 * Intel Deep C-State invariant TSC in leaf 0x80000007. 370 */ 371 #define CPUID_TSC_CSTATE_INVARIANCE (0x100) 372 373 /* 374 * Intel Deep C-state always-running local APIC timer 375 */ 376 #define CPUID_CSTATE_ARAT (0x4) 377 378 /* 379 * Intel ENERGY_PERF_BIAS MSR indicated by feature bit CPUID.6.ECX[3]. 380 */ 381 #define CPUID_EPB_SUPPORT (1 << 3) 382 383 /* 384 * Intel TSC deadline timer 385 */ 386 #define CPUID_DEADLINE_TSC (1 << 24) 387 388 /* 389 * x86_type is a legacy concept; this is supplanted 390 * for most purposes by x86_featureset; modern CPUs 391 * should be X86_TYPE_OTHER 392 */ 393 #define X86_TYPE_OTHER 0 394 #define X86_TYPE_486 1 395 #define X86_TYPE_P5 2 396 #define X86_TYPE_P6 3 397 #define X86_TYPE_CYRIX_486 4 398 #define X86_TYPE_CYRIX_6x86L 5 399 #define X86_TYPE_CYRIX_6x86 6 400 #define X86_TYPE_CYRIX_GXm 7 401 #define X86_TYPE_CYRIX_6x86MX 8 402 #define X86_TYPE_CYRIX_MediaGX 9 403 #define X86_TYPE_CYRIX_MII 10 404 #define X86_TYPE_VIA_CYRIX_III 11 405 #define X86_TYPE_P4 12 406 407 /* 408 * x86_vendor allows us to select between 409 * implementation features and helps guide 410 * the interpretation of the cpuid instruction. 411 */ 412 #define X86_VENDOR_Intel 0 413 #define X86_VENDORSTR_Intel "GenuineIntel" 414 415 #define X86_VENDOR_IntelClone 1 416 417 #define X86_VENDOR_AMD 2 418 #define X86_VENDORSTR_AMD "AuthenticAMD" 419 420 #define X86_VENDOR_Cyrix 3 421 #define X86_VENDORSTR_CYRIX "CyrixInstead" 422 423 #define X86_VENDOR_UMC 4 424 #define X86_VENDORSTR_UMC "UMC UMC UMC " 425 426 #define X86_VENDOR_NexGen 5 427 #define X86_VENDORSTR_NexGen "NexGenDriven" 428 429 #define X86_VENDOR_Centaur 6 430 #define X86_VENDORSTR_Centaur "CentaurHauls" 431 432 #define X86_VENDOR_Rise 7 433 #define X86_VENDORSTR_Rise "RiseRiseRise" 434 435 #define X86_VENDOR_SiS 8 436 #define X86_VENDORSTR_SiS "SiS SiS SiS " 437 438 #define X86_VENDOR_TM 9 439 #define X86_VENDORSTR_TM "GenuineTMx86" 440 441 #define X86_VENDOR_NSC 10 442 #define X86_VENDORSTR_NSC "Geode by NSC" 443 444 /* 445 * Vendor string max len + \0 446 */ 447 #define X86_VENDOR_STRLEN 13 448 449 /* 450 * Some vendor/family/model/stepping ranges are commonly grouped under 451 * a single identifying banner by the vendor. The following encode 452 * that "revision" in a uint32_t with the 8 most significant bits 453 * identifying the vendor with X86_VENDOR_*, the next 8 identifying the 454 * family, and the remaining 16 typically forming a bitmask of revisions 455 * within that family with more significant bits indicating "later" revisions. 456 */ 457 458 #define _X86_CHIPREV_VENDOR_MASK 0xff000000u 459 #define _X86_CHIPREV_VENDOR_SHIFT 24 460 #define _X86_CHIPREV_FAMILY_MASK 0x00ff0000u 461 #define _X86_CHIPREV_FAMILY_SHIFT 16 462 #define _X86_CHIPREV_REV_MASK 0x0000ffffu 463 464 #define _X86_CHIPREV_VENDOR(x) \ 465 (((x) & _X86_CHIPREV_VENDOR_MASK) >> _X86_CHIPREV_VENDOR_SHIFT) 466 #define _X86_CHIPREV_FAMILY(x) \ 467 (((x) & _X86_CHIPREV_FAMILY_MASK) >> _X86_CHIPREV_FAMILY_SHIFT) 468 #define _X86_CHIPREV_REV(x) \ 469 ((x) & _X86_CHIPREV_REV_MASK) 470 471 /* True if x matches in vendor and family and if x matches the given rev mask */ 472 #define X86_CHIPREV_MATCH(x, mask) \ 473 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(mask) && \ 474 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(mask) && \ 475 ((_X86_CHIPREV_REV(x) & _X86_CHIPREV_REV(mask)) != 0)) 476 477 /* True if x matches in vendor and family, and rev is at least minx */ 478 #define X86_CHIPREV_ATLEAST(x, minx) \ 479 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 480 _X86_CHIPREV_FAMILY(x) == _X86_CHIPREV_FAMILY(minx) && \ 481 _X86_CHIPREV_REV(x) >= _X86_CHIPREV_REV(minx)) 482 483 #define _X86_CHIPREV_MKREV(vendor, family, rev) \ 484 ((uint32_t)(vendor) << _X86_CHIPREV_VENDOR_SHIFT | \ 485 (family) << _X86_CHIPREV_FAMILY_SHIFT | (rev)) 486 487 /* True if x matches in vendor, and family is at least minx */ 488 #define X86_CHIPFAM_ATLEAST(x, minx) \ 489 (_X86_CHIPREV_VENDOR(x) == _X86_CHIPREV_VENDOR(minx) && \ 490 _X86_CHIPREV_FAMILY(x) >= _X86_CHIPREV_FAMILY(minx)) 491 492 /* Revision default */ 493 #define X86_CHIPREV_UNKNOWN 0x0 494 495 /* 496 * Definitions for AMD Family 0xf. Minor revisions C0 and CG are 497 * sufficiently different that we will distinguish them; in all other 498 * case we will identify the major revision. 499 */ 500 #define X86_CHIPREV_AMD_F_REV_B _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0001) 501 #define X86_CHIPREV_AMD_F_REV_C0 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0002) 502 #define X86_CHIPREV_AMD_F_REV_CG _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0004) 503 #define X86_CHIPREV_AMD_F_REV_D _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0008) 504 #define X86_CHIPREV_AMD_F_REV_E _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0010) 505 #define X86_CHIPREV_AMD_F_REV_F _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0020) 506 #define X86_CHIPREV_AMD_F_REV_G _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0xf, 0x0040) 507 508 /* 509 * Definitions for AMD Family 0x10. Rev A was Engineering Samples only. 510 */ 511 #define X86_CHIPREV_AMD_10_REV_A \ 512 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0001) 513 #define X86_CHIPREV_AMD_10_REV_B \ 514 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0002) 515 #define X86_CHIPREV_AMD_10_REV_C \ 516 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0004) 517 #define X86_CHIPREV_AMD_10_REV_D \ 518 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x10, 0x0008) 519 520 /* 521 * Definitions for AMD Family 0x11. 522 */ 523 #define X86_CHIPREV_AMD_11 \ 524 _X86_CHIPREV_MKREV(X86_VENDOR_AMD, 0x11, 0x0001) 525 526 527 /* 528 * Various socket/package types, extended as the need to distinguish 529 * a new type arises. The top 8 byte identfies the vendor and the 530 * remaining 24 bits describe 24 socket types. 531 */ 532 533 #define _X86_SOCKET_VENDOR_SHIFT 24 534 #define _X86_SOCKET_VENDOR(x) ((x) >> _X86_SOCKET_VENDOR_SHIFT) 535 #define _X86_SOCKET_TYPE_MASK 0x00ffffff 536 #define _X86_SOCKET_TYPE(x) ((x) & _X86_SOCKET_TYPE_MASK) 537 538 #define _X86_SOCKET_MKVAL(vendor, bitval) \ 539 ((uint32_t)(vendor) << _X86_SOCKET_VENDOR_SHIFT | (bitval)) 540 541 #define X86_SOCKET_MATCH(s, mask) \ 542 (_X86_SOCKET_VENDOR(s) == _X86_SOCKET_VENDOR(mask) && \ 543 (_X86_SOCKET_TYPE(s) & _X86_SOCKET_TYPE(mask)) != 0) 544 545 #define X86_SOCKET_UNKNOWN 0x0 546 /* 547 * AMD socket types 548 */ 549 #define X86_SOCKET_754 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000001) 550 #define X86_SOCKET_939 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000002) 551 #define X86_SOCKET_940 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000004) 552 #define X86_SOCKET_S1g1 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000008) 553 #define X86_SOCKET_AM2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000010) 554 #define X86_SOCKET_F1207 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000020) 555 #define X86_SOCKET_S1g2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000040) 556 #define X86_SOCKET_S1g3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000080) 557 #define X86_SOCKET_AM _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000100) 558 #define X86_SOCKET_AM2R2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000200) 559 #define X86_SOCKET_AM3 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000400) 560 #define X86_SOCKET_G34 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x000800) 561 #define X86_SOCKET_ASB2 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x001000) 562 #define X86_SOCKET_C32 _X86_SOCKET_MKVAL(X86_VENDOR_AMD, 0x002000) 563 564 #if !defined(_ASM) 565 566 #if defined(_KERNEL) || defined(_KMEMUSER) 567 568 extern void *x86_featureset; 569 570 extern void free_x86_featureset(void *featureset); 571 extern boolean_t is_x86_feature(void *featureset, uint_t feature); 572 extern void add_x86_feature(void *featureset, uint_t feature); 573 extern void remove_x86_feature(void *featureset, uint_t feature); 574 extern boolean_t compare_x86_featureset(void *setA, void *setB); 575 extern void print_x86_featureset(void *featureset); 576 577 578 extern uint_t x86_type; 579 extern uint_t x86_vendor; 580 extern uint_t x86_clflush_size; 581 582 extern uint_t pentiumpro_bug4046376; 583 extern uint_t pentiumpro_bug4064495; 584 585 extern uint_t enable486; 586 587 extern const char CyrixInstead[]; 588 589 #endif 590 591 #if defined(_KERNEL) 592 593 /* 594 * This structure is used to pass arguments and get return values back 595 * from the CPUID instruction in __cpuid_insn() routine. 596 */ 597 struct cpuid_regs { 598 uint32_t cp_eax; 599 uint32_t cp_ebx; 600 uint32_t cp_ecx; 601 uint32_t cp_edx; 602 }; 603 604 extern uint64_t rdmsr(uint_t); 605 extern void wrmsr(uint_t, const uint64_t); 606 extern uint64_t xrdmsr(uint_t); 607 extern void xwrmsr(uint_t, const uint64_t); 608 extern int checked_rdmsr(uint_t, uint64_t *); 609 extern int checked_wrmsr(uint_t, uint64_t); 610 611 extern void invalidate_cache(void); 612 extern ulong_t getcr4(void); 613 extern void setcr4(ulong_t); 614 615 extern void mtrr_sync(void); 616 617 extern void cpu_fast_syscall_enable(void *); 618 extern void cpu_fast_syscall_disable(void *); 619 620 struct cpu; 621 622 extern int cpuid_checkpass(struct cpu *, int); 623 extern uint32_t cpuid_insn(struct cpu *, struct cpuid_regs *); 624 extern uint32_t __cpuid_insn(struct cpuid_regs *); 625 extern int cpuid_getbrandstr(struct cpu *, char *, size_t); 626 extern int cpuid_getidstr(struct cpu *, char *, size_t); 627 extern const char *cpuid_getvendorstr(struct cpu *); 628 extern uint_t cpuid_getvendor(struct cpu *); 629 extern uint_t cpuid_getfamily(struct cpu *); 630 extern uint_t cpuid_getmodel(struct cpu *); 631 extern uint_t cpuid_getstep(struct cpu *); 632 extern uint_t cpuid_getsig(struct cpu *); 633 extern uint_t cpuid_get_ncpu_per_chip(struct cpu *); 634 extern uint_t cpuid_get_ncore_per_chip(struct cpu *); 635 extern uint_t cpuid_get_ncpu_sharing_last_cache(struct cpu *); 636 extern id_t cpuid_get_last_lvl_cacheid(struct cpu *); 637 extern int cpuid_get_chipid(struct cpu *); 638 extern id_t cpuid_get_coreid(struct cpu *); 639 extern int cpuid_get_pkgcoreid(struct cpu *); 640 extern int cpuid_get_clogid(struct cpu *); 641 extern int cpuid_get_cacheid(struct cpu *); 642 extern uint32_t cpuid_get_apicid(struct cpu *); 643 extern uint_t cpuid_get_procnodeid(struct cpu *cpu); 644 extern uint_t cpuid_get_procnodes_per_pkg(struct cpu *cpu); 645 extern int cpuid_is_cmt(struct cpu *); 646 extern int cpuid_syscall32_insn(struct cpu *); 647 extern int getl2cacheinfo(struct cpu *, int *, int *, int *); 648 649 extern uint32_t cpuid_getchiprev(struct cpu *); 650 extern const char *cpuid_getchiprevstr(struct cpu *); 651 extern uint32_t cpuid_getsockettype(struct cpu *); 652 extern const char *cpuid_getsocketstr(struct cpu *); 653 654 extern int cpuid_have_cr8access(struct cpu *); 655 656 extern int cpuid_opteron_erratum(struct cpu *, uint_t); 657 658 struct cpuid_info; 659 660 extern void setx86isalist(void); 661 extern void cpuid_alloc_space(struct cpu *); 662 extern void cpuid_free_space(struct cpu *); 663 extern void *cpuid_pass1(struct cpu *); 664 extern void cpuid_pass2(struct cpu *); 665 extern void cpuid_pass3(struct cpu *); 666 extern uint_t cpuid_pass4(struct cpu *); 667 extern void cpuid_set_cpu_properties(void *, processorid_t, 668 struct cpuid_info *); 669 670 extern void cpuid_get_addrsize(struct cpu *, uint_t *, uint_t *); 671 extern uint_t cpuid_get_dtlb_nent(struct cpu *, size_t); 672 673 #if !defined(__xpv) 674 extern uint32_t *cpuid_mwait_alloc(struct cpu *); 675 extern void cpuid_mwait_free(struct cpu *); 676 extern int cpuid_deep_cstates_supported(void); 677 extern int cpuid_arat_supported(void); 678 extern int cpuid_iepb_supported(struct cpu *); 679 extern int cpuid_deadline_tsc_supported(void); 680 extern int vmware_platform(void); 681 #endif 682 683 struct cpu_ucode_info; 684 685 extern void ucode_alloc_space(struct cpu *); 686 extern void ucode_free_space(struct cpu *); 687 extern void ucode_check(struct cpu *); 688 extern void ucode_cleanup(); 689 690 #if !defined(__xpv) 691 extern char _tsc_mfence_start; 692 extern char _tsc_mfence_end; 693 extern char _tscp_start; 694 extern char _tscp_end; 695 extern char _no_rdtsc_start; 696 extern char _no_rdtsc_end; 697 extern char _tsc_lfence_start; 698 extern char _tsc_lfence_end; 699 #endif 700 701 #if !defined(__xpv) 702 extern char bcopy_patch_start; 703 extern char bcopy_patch_end; 704 extern char bcopy_ck_size; 705 #endif 706 707 extern void post_startup_cpu_fixups(void); 708 709 extern uint_t workaround_errata(struct cpu *); 710 711 #if defined(OPTERON_ERRATUM_93) 712 extern int opteron_erratum_93; 713 #endif 714 715 #if defined(OPTERON_ERRATUM_91) 716 extern int opteron_erratum_91; 717 #endif 718 719 #if defined(OPTERON_ERRATUM_100) 720 extern int opteron_erratum_100; 721 #endif 722 723 #if defined(OPTERON_ERRATUM_121) 724 extern int opteron_erratum_121; 725 #endif 726 727 #if defined(OPTERON_WORKAROUND_6323525) 728 extern int opteron_workaround_6323525; 729 extern void patch_workaround_6323525(void); 730 #endif 731 732 extern int get_hwenv(void); 733 extern int is_controldom(void); 734 735 /* 736 * Defined hardware environments 737 */ 738 #define HW_NATIVE 0x00 /* Running on bare metal */ 739 #define HW_XEN_PV 0x01 /* Running on Xen Hypervisor paravirutualized */ 740 #define HW_XEN_HVM 0x02 /* Running on Xen hypervisor HVM */ 741 #define HW_VMWARE 0x03 /* Running on VMware hypervisor */ 742 743 #endif /* _KERNEL */ 744 745 #endif 746 747 #ifdef __cplusplus 748 } 749 #endif 750 751 #endif /* _SYS_X86_ARCHEXT_H */ 752