1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #ifndef _SYS_MCA_AMD_H 28 #define _SYS_MCA_AMD_H 29 30 #pragma ident "%Z%%M% %I% %E% SMI" 31 32 /* 33 * Constants the Memory Check Architecture as implemented on AMD CPUs. 34 */ 35 36 #ifdef __cplusplus 37 extern "C" { 38 #endif 39 40 #define AMD_MSR_MCG_CAP 0x179 41 #define AMD_MSR_MCG_STATUS 0x17a 42 #define AMD_MSR_MCG_CTL 0x17b 43 44 #define AMD_MCA_BANK_DC 0 /* Data Cache */ 45 #define AMD_MCA_BANK_IC 1 /* Instruction Cache */ 46 #define AMD_MCA_BANK_BU 2 /* Bus Unit */ 47 #define AMD_MCA_BANK_LS 3 /* Load/Store Unit */ 48 #define AMD_MCA_BANK_NB 4 /* Northbridge */ 49 #define AMD_MCA_BANK_COUNT 5 50 51 #define AMD_MSR_DC_CTL 0x400 52 #define AMD_MSR_DC_MASK 0xc0010044 53 #define AMD_MSR_DC_STATUS 0x401 54 #define AMD_MSR_DC_ADDR 0x402 55 #define AMD_MSR_DC_MISC 0x403 56 57 #define AMD_MSR_IC_CTL 0x404 58 #define AMD_MSR_IC_MASK 0xc0010045 59 #define AMD_MSR_IC_STATUS 0x405 60 #define AMD_MSR_IC_ADDR 0x406 61 #define AMD_MSR_IC_MISC 0x407 62 63 #define AMD_MSR_BU_CTL 0x408 64 #define AMD_MSR_BU_MASK 0xc0010046 65 #define AMD_MSR_BU_STATUS 0x409 66 #define AMD_MSR_BU_ADDR 0x40a 67 #define AMD_MSR_BU_MISC 0x40b 68 69 #define AMD_MSR_LS_CTL 0x40c 70 #define AMD_MSR_LS_MASK 0xc0010047 71 #define AMD_MSR_LS_STATUS 0x40d 72 #define AMD_MSR_LS_ADDR 0x40e 73 #define AMD_MSR_LS_MISC 0x40f 74 75 #define AMD_MSR_NB_CTL 0x410 76 #define AMD_MSR_NB_MASK 0xc0010048 77 #define AMD_MSR_NB_STATUS 0x411 78 #define AMD_MSR_NB_ADDR 0x412 79 #define AMD_MSR_NB_MISC 0x413 80 81 #define AMD_MCG_EN_DC 0x01 82 #define AMD_MCG_EN_IC 0x02 83 #define AMD_MCG_EN_BU 0x04 84 #define AMD_MCG_EN_LS 0x08 85 #define AMD_MCG_EN_NB 0x10 86 #define AMD_MCG_EN_ALL \ 87 (AMD_MCG_EN_DC | AMD_MCG_EN_IC | AMD_MCG_EN_BU | AMD_MCG_EN_LS | \ 88 AMD_MCG_EN_NB) 89 90 /* 91 * Data Cache (DC) bank error-detection enabling bits and CTL register 92 * initializer value. 93 */ 94 95 #define AMD_DC_EN_ECCI 0x00000001ULL 96 #define AMD_DC_EN_ECCM 0x00000002ULL 97 #define AMD_DC_EN_DECC 0x00000004ULL 98 #define AMD_DC_EN_DMTP 0x00000008ULL 99 #define AMD_DC_EN_DSTP 0x00000010ULL 100 #define AMD_DC_EN_L1TP 0x00000020ULL 101 #define AMD_DC_EN_L2TP 0x00000040ULL 102 103 #define AMD_DC_CTL_INIT_CMN \ 104 (AMD_DC_EN_ECCI | AMD_DC_EN_ECCM | AMD_DC_EN_DECC | AMD_DC_EN_DMTP | \ 105 AMD_DC_EN_DSTP | AMD_DC_EN_L1TP | AMD_DC_EN_L2TP) 106 107 /* 108 * Instruction Cache (IC) bank error-detection enabling bits and CTL register 109 * initializer value. 110 * 111 * The Northbridge will handle Read Data errors. Our initializer will enable 112 * all but the RDDE detector. 113 */ 114 115 #define AMD_IC_EN_ECCI 0x00000001ULL 116 #define AMD_IC_EN_ECCM 0x00000002ULL 117 #define AMD_IC_EN_IDP 0x00000004ULL 118 #define AMD_IC_EN_IMTP 0x00000008ULL 119 #define AMD_IC_EN_ISTP 0x00000010ULL 120 #define AMD_IC_EN_L1TP 0x00000020ULL 121 #define AMD_IC_EN_L2TP 0x00000040ULL 122 #define AMD_IC_EN_RDDE 0x00000200ULL 123 124 #define AMD_IC_CTL_INIT_CMN \ 125 (AMD_IC_EN_ECCI | AMD_IC_EN_ECCM | AMD_IC_EN_IDP | AMD_IC_EN_IMTP | \ 126 AMD_IC_EN_ISTP | AMD_IC_EN_L1TP | AMD_IC_EN_L2TP) 127 128 /* 129 * Bus Unit (BU) bank error-detection enabling bits and CTL register 130 * initializer value. 131 * 132 * The Northbridge will handle Read Data errors. Our initializer will enable 133 * all but the S_RDE_* detectors. 134 */ 135 136 #define AMD_BU_EN_S_RDE_HP 0x00000001ULL 137 #define AMD_BU_EN_S_RDE_TLB 0x00000002ULL 138 #define AMD_BU_EN_S_RDE_ALL 0x00000004ULL 139 #define AMD_BU_EN_S_ECC1_TLB 0x00000008ULL 140 #define AMD_BU_EN_S_ECC1_HP 0x00000010ULL 141 #define AMD_BU_EN_S_ECCM_TLB 0x00000020ULL 142 #define AMD_BU_EN_S_ECCM_HP 0x00000040ULL 143 #define AMD_BU_EN_L2T_PAR_ICDC 0x00000080ULL 144 #define AMD_BU_EN_L2T_PAR_TLB 0x00000100ULL 145 #define AMD_BU_EN_L2T_PAR_SNP 0x00000200ULL 146 #define AMD_BU_EN_L2T_PAR_CPB 0x00000400ULL 147 #define AMD_BU_EN_L2T_PAR_SCR 0x00000800ULL 148 #define AMD_BU_EN_L2D_ECC1_TLB 0x00001000ULL 149 #define AMD_BU_EN_L2D_ECC1_SNP 0x00002000ULL 150 #define AMD_BU_EN_L2D_ECC1_CPB 0x00004000ULL 151 #define AMD_BU_EN_L2D_ECCM_TLB 0x00008000ULL 152 #define AMD_BU_EN_L2D_ECCM_SNP 0x00010000ULL 153 #define AMD_BU_EN_L2D_ECCM_CPB 0x00020000ULL 154 #define AMD_BU_EN_L2T_ECC1_SCR 0x00040000ULL 155 #define AMD_BU_EN_L2T_ECCM_SCR 0x00080000ULL 156 157 #define AMD_BU_CTL_INIT_CMN \ 158 (AMD_BU_EN_S_ECC1_TLB | AMD_BU_EN_S_ECC1_HP | \ 159 AMD_BU_EN_S_ECCM_TLB | AMD_BU_EN_S_ECCM_HP | \ 160 AMD_BU_EN_L2T_PAR_ICDC | AMD_BU_EN_L2T_PAR_TLB | \ 161 AMD_BU_EN_L2T_PAR_SNP | AMD_BU_EN_L2T_PAR_CPB | \ 162 AMD_BU_EN_L2T_PAR_SCR | AMD_BU_EN_L2D_ECC1_TLB | \ 163 AMD_BU_EN_L2D_ECC1_SNP | AMD_BU_EN_L2D_ECC1_CPB | \ 164 AMD_BU_EN_L2D_ECCM_TLB | AMD_BU_EN_L2D_ECCM_SNP | \ 165 AMD_BU_EN_L2D_ECCM_CPB | AMD_BU_EN_L2T_ECC1_SCR | \ 166 AMD_BU_EN_L2T_ECCM_SCR) 167 168 /* 169 * Load/Store (LS) bank error-detection enabling bits and CTL register 170 * initializer value. 171 * 172 * The Northbridge will handle Read Data errors. That's the only type of 173 * error the LS unit can detect at present, so we won't be enabling any 174 * LS detectors. 175 */ 176 177 #define AMD_LS_EN_S_RDE_S 0x00000001ULL 178 #define AMD_LS_EN_S_RDE_L 0x00000002ULL 179 180 #define AMD_LS_CTL_INIT_CMN 0ULL 181 182 /* 183 * NorthBridge (NB) MCi_MISC - DRAM Errors Threshold Register. 184 */ 185 #define AMD_NB_MISC_VALID (0x1ULL << 63) 186 #define AMD_NB_MISC_CTRP (0x1ULL << 62) 187 #define AMD_NB_MISC_LOCKED (0x1ULL << 61) 188 #define AMD_NB_MISC_CNTEN (0x1ULL << 51) 189 #define AMD_NB_MISC_INTTYPE (0x1ULL << 49) 190 #define AMD_NB_MISC_INTTYPE_MASK (0x3ULL << 49) 191 #define AMD_NB_MISC_OVRFLW (0x1ULL << 48) 192 #define AMD_NB_MISC_ERRCOUNT_MASK (0xfffULL << 32) 193 194 /* 195 * The Northbridge (NB) is configured using both the standard MCA CTL register 196 * and a NB-specific configuration register (NB CFG). The AMD_NB_EN_* macros 197 * are the detector enabling bits for the NB MCA CTL register. The 198 * AMD_NB_CFG_* bits are for the NB CFG register. 199 * 200 * The CTL register can be initialized statically, but portions of the NB CFG 201 * register must be initialized based on the current machine's configuration. 202 * 203 * The MCA NB Control Register maps to MC4_CTL[31:0], but we initialize it 204 * via and MSR write of 64 bits so define all as ULL. 205 * 206 */ 207 #define AMD_NB_EN_CORRECC 0x00000001ULL 208 #define AMD_NB_EN_UNCORRECC 0x00000002ULL 209 #define AMD_NB_EN_CRCERR0 0x00000004ULL 210 #define AMD_NB_EN_CRCERR1 0x00000008ULL 211 #define AMD_NB_EN_CRCERR2 0x00000010ULL 212 #define AMD_NB_EN_SYNCPKT0 0x00000020ULL 213 #define AMD_NB_EN_SYNCPKT1 0x00000040ULL 214 #define AMD_NB_EN_SYNCPKT2 0x00000080ULL 215 #define AMD_NB_EN_MSTRABRT 0x00000100ULL 216 #define AMD_NB_EN_TGTABRT 0x00000200ULL 217 #define AMD_NB_EN_GARTTBLWK 0x00000400ULL 218 #define AMD_NB_EN_ATOMICRMW 0x00000800ULL 219 #define AMD_NB_EN_WCHDOGTMR 0x00001000ULL 220 #define AMD_NB_EN_DRAMPAR 0x00040000ULL /* revs F and G */ 221 222 #define AMD_NB_CTL_INIT_CMN /* Revs B to G; All but GARTTBLWK */ \ 223 (AMD_NB_EN_CORRECC | AMD_NB_EN_UNCORRECC | \ 224 AMD_NB_EN_CRCERR0 | AMD_NB_EN_CRCERR1 | AMD_NB_EN_CRCERR2 | \ 225 AMD_NB_EN_SYNCPKT0 | AMD_NB_EN_SYNCPKT1 | AMD_NB_EN_SYNCPKT2 | \ 226 AMD_NB_EN_MSTRABRT | AMD_NB_EN_TGTABRT | \ 227 AMD_NB_EN_ATOMICRMW | AMD_NB_EN_WCHDOGTMR) 228 229 #define AMD_NB_CTL_INIT_REV_FG /* Additional bits for revs F and G */ \ 230 AMD_NB_EN_DRAMPAR 231 232 /* 233 * NB MCA Configuration register 234 */ 235 #define AMD_NB_CFG_CPUECCERREN 0x00000001 236 #define AMD_NB_CFG_CPURDDATERREN 0x00000002 237 #define AMD_NB_CFG_SYNCONUCECCEN 0x00000004 238 #define AMD_NB_CFG_SYNCPKTGENDIS 0x00000008 239 #define AMD_NB_CFG_SYNCPKTPROPDIS 0x00000010 240 #define AMD_NB_CFG_IOMSTABORTDIS 0x00000020 241 #define AMD_NB_CFG_CPUERRDIS 0x00000040 242 #define AMD_NB_CFG_IOERRDIS 0x00000080 243 #define AMD_NB_CFG_WDOGTMRDIS 0x00000100 244 #define AMD_NB_CFG_SYNCONWDOGEN 0x00100000 245 #define AMD_NB_CFG_SYNCONANYERREN 0x00200000 246 #define AMD_NB_CFG_ECCEN 0x00400000 247 #define AMD_NB_CFG_CHIPKILLECCEN 0x00800000 248 #define AMD_NB_CFG_IORDDATERREN 0x01000000 249 #define AMD_NB_CFG_DISPCICFGCPUERRRSP 0x02000000 250 #define AMD_NB_CFG_NBMCATOMSTCPUEN 0x08000000 251 #define AMD_NB_CFG_DISTGTABTCPUERRRSP 0x10000000 252 #define AMD_NB_CFG_DISMSTABTCPUERRRSP 0x20000000 253 #define AMD_NB_CFG_SYNCONDRAMADRPARERREN 0x40000000 /* Revs F & G */ 254 255 /* 256 * We do not initialize the NB config with an absolute value; instead we 257 * selectively add some bits and remove others. Note that 258 * AMD_NB_CFG_{ADD,REMOVE}_{CMN,REV_FG} below are not the whole 259 * story here - additional config is performed regarding the watchdog (see 260 * ao_mca.c for details). 261 */ 262 #define AMD_NB_CFG_ADD_CMN /* Revs B to G */ \ 263 (AMD_NB_CFG_DISPCICFGCPUERRRSP | AMD_NB_CFG_SYNCONUCECCEN | \ 264 AMD_NB_CFG_CPUECCERREN) 265 266 #define AMD_NB_CFG_REMOVE_CMN /* Revs B to G */ \ 267 (AMD_NB_CFG_NBMCATOMSTCPUEN | \ 268 AMD_NB_CFG_IORDDATERREN | AMD_NB_CFG_SYNCONANYERREN | \ 269 AMD_NB_CFG_SYNCONWDOGEN | AMD_NB_CFG_IOERRDIS | \ 270 AMD_NB_CFG_IOMSTABORTDIS | AMD_NB_CFG_SYNCPKTPROPDIS | \ 271 AMD_NB_CFG_SYNCPKTGENDIS) 272 273 #define AMD_NB_CFG_ADD_REV_FG /* Revs F and G */ \ 274 AMD_NB_CFG_SYNCONDRAMADRPARERREN 275 276 #define AMD_NB_CFG_REMOVE_REV_FG 0x0 /* Revs F and G */ 277 278 #define AMD_NB_CFG_WDOGTMRCNTSEL_4095 0x00000000 279 #define AMD_NB_CFG_WDOGTMRCNTSEL_2047 0x00000200 280 #define AMD_NB_CFG_WDOGTMRCNTSEL_1023 0x00000400 281 #define AMD_NB_CFG_WDOGTMRCNTSEL_511 0x00000600 282 #define AMD_NB_CFG_WDOGTMRCNTSEL_255 0x00000800 283 #define AMD_NB_CFG_WDOGTMRCNTSEL_127 0x00000a00 284 #define AMD_NB_CFG_WDOGTMRCNTSEL_63 0x00000c00 285 #define AMD_NB_CFG_WDOGTMRCNTSEL_31 0x00000e00 286 #define AMD_NB_CFG_WDOGTMRCNTSEL_MASK 0x00000e00 287 #define AMD_NB_CFG_WDOGTMRCNTSEL_SHIFT 9 288 289 #define AMD_NB_CFG_WDOGTMRBASESEL_1MS 0x00000000 290 #define AMD_NB_CFG_WDOGTMRBASESEL_1US 0x00001000 291 #define AMD_NB_CFG_WDOGTMRBASESEL_5NS 0x00002000 292 #define AMD_NB_CFG_WDOGTMRBASESEL_MASK 0x00003000 293 #define AMD_NB_CFG_WDOGTMRBASESEL_SHIFT 12 294 295 #define AMD_NB_CFG_LDTLINKSEL_MASK 0x0000c000 296 #define AMD_NB_CFG_LDTLINKSEL_SHIFT 14 297 298 #define AMD_NB_CFG_GENCRCERRBYTE0 0x00010000 299 #define AMD_NB_CFG_GENCRCERRBYTE1 0x00020000 300 301 /* Generic bank status register bits */ 302 #define AMD_BANK_STAT_VALID 0x8000000000000000ULL 303 #define AMD_BANK_STAT_OVER 0x4000000000000000ULL 304 #define AMD_BANK_STAT_UC 0x2000000000000000ULL 305 #define AMD_BANK_STAT_EN 0x1000000000000000ULL 306 #define AMD_BANK_STAT_MISCV 0x0800000000000000ULL 307 #define AMD_BANK_STAT_ADDRV 0x0400000000000000ULL 308 #define AMD_BANK_STAT_PCC 0x0200000000000000ULL 309 310 #define AMD_BANK_STAT_CECC 0x0000400000000000ULL 311 #define AMD_BANK_STAT_UECC 0x0000200000000000ULL 312 #define AMD_BANK_STAT_SCRUB 0x0000010000000000ULL 313 314 /* syndrome[7:0] */ 315 #define AMD_BANK_STAT_SYND_MASK 0x007f800000000000ULL 316 #define AMD_BANK_STAT_SYND_SHIFT 47 317 318 #define AMD_BANK_SYND(stat) \ 319 (((stat) & AMD_BANK_STAT_SYND_MASK) >> AMD_BANK_STAT_SYND_SHIFT) 320 #define AMD_BANK_MKSYND(synd) \ 321 (((uint64_t)(synd) << AMD_BANK_STAT_SYND_SHIFT) & \ 322 AMD_BANK_STAT_SYND_MASK) 323 324 #define AMD_NB_STAT_DRAMCHANNEL 0x0000020000000000ULL 325 #define AMD_NB_STAT_LDTLINK_MASK 0x0000007000000000ULL 326 #define AMD_NB_STAT_LDTLINK_SHIFT 4 327 #define AMD_NB_STAT_ERRCPU1 0x0000000200000000ULL 328 #define AMD_NB_STAT_ERRCPU0 0x0000000100000000ULL 329 330 #define AMD_NB_STAT_CKSYND_MASK 0x00000000ff000000 /* syndrome[15:8] */ 331 #define AMD_NB_STAT_CKSYND_SHIFT (24 - 8) /* shift [31:24] to [15:8] */ 332 333 #define AMD_NB_STAT_CKSYND(stat) \ 334 ((((stat) & AMD_NB_STAT_CKSYND_MASK) >> AMD_NB_STAT_CKSYND_SHIFT) | \ 335 AMD_BANK_SYND((stat))) 336 337 #define AMD_NB_STAT_MKCKSYND(synd) \ 338 ((((uint64_t)(synd) << AMD_NB_STAT_CKSYND_SHIFT) & \ 339 AMD_NB_STAT_CKSYND_MASK) | AMD_BANK_MKSYND(synd)) 340 341 #define AMD_ERRCODE_MASK 0x000000000000ffffULL 342 #define AMD_ERREXT_MASK 0x00000000000f0000ULL 343 #define AMD_ERREXT_SHIFT 16 344 345 #define AMD_ERRCODE_TT_MASK 0x000c 346 #define AMD_ERRCODE_TT_SHIFT 2 347 #define AMD_ERRCODE_TT_INSTR 0x0 348 #define AMD_ERRCODE_TT_DATA 0x1 349 #define AMD_ERRCODE_TT_GEN 0x2 350 351 #define AMD_ERRCODE_LL_MASK 0x0003 352 #define AMD_ERRCODE_LL_L0 0x0 353 #define AMD_ERRCODE_LL_L1 0x1 354 #define AMD_ERRCODE_LL_L2 0x2 355 #define AMD_ERRCODE_LL_LG 0x3 356 357 #define AMD_ERRCODE_R4_MASK 0x00f0 358 #define AMD_ERRCODE_R4_SHIFT 4 359 #define AMD_ERRCODE_R4_GEN 0x0 360 #define AMD_ERRCODE_R4_RD 0x1 361 #define AMD_ERRCODE_R4_WR 0x2 362 #define AMD_ERRCODE_R4_DRD 0x3 363 #define AMD_ERRCODE_R4_DWR 0x4 364 #define AMD_ERRCODE_R4_IRD 0x5 365 #define AMD_ERRCODE_R4_PREFETCH 0x6 366 #define AMD_ERRCODE_R4_EVICT 0x7 367 #define AMD_ERRCODE_R4_SNOOP 0x8 368 369 #define AMD_ERRCODE_PP_MASK 0x0600 370 #define AMD_ERRCODE_PP_SHIFT 9 371 #define AMD_ERRCODE_PP_SRC 0x0 372 #define AMD_ERRCODE_PP_RSP 0x1 373 #define AMD_ERRCODE_PP_OBS 0x2 374 #define AMD_ERRCODE_PP_GEN 0x3 375 376 #define AMD_ERRCODE_T_MASK 0x0100 377 #define AMD_ERRCODE_T_SHIFT 8 378 #define AMD_ERRCODE_T_NONE 0x0 379 #define AMD_ERRCODE_T_TIMEOUT 0x1 380 381 #define AMD_ERRCODE_II_MASK 0x000c 382 #define AMD_ERRCODE_II_SHIFT 2 383 #define AMD_ERRCODE_II_MEM 0x0 384 #define AMD_ERRCODE_II_IO 0x2 385 #define AMD_ERRCODE_II_GEN 0x3 386 387 #define AMD_ERRCODE_TLB_BIT 4 388 #define AMD_ERRCODE_MEM_BIT 8 389 #define AMD_ERRCODE_BUS_BIT 11 390 391 #define AMD_ERRCODE_TLB_MASK 0xfff0 392 #define AMD_ERRCODE_TLB_VAL 0x0010 393 #define AMD_ERRCODE_MEM_MASK 0xff00 394 #define AMD_ERRCODE_MEM_VAL 0x0100 395 #define AMD_ERRCODE_BUS_MASK 0xf800 396 #define AMD_ERRCODE_BUS_VAL 0x0800 397 398 #define AMD_ERRCODE_MKTLB(tt, ll) \ 399 (AMD_ERRCODE_TLB_VAL | \ 400 (((tt) << AMD_ERRCODE_TT_SHIFT) & AMD_ERRCODE_TT_MASK) | \ 401 ((ll) & AMD_ERRCODE_LL_MASK)) 402 #define AMD_ERRCODE_ISTLB(code) \ 403 (((code) & AMD_ERRCODE_TLB_MASK) == AMD_ERRCODE_TLB_VAL) 404 405 #define AMD_ERRCODE_MKMEM(r4, tt, ll) \ 406 (AMD_ERRCODE_MEM_VAL | \ 407 (((r4) << AMD_ERRCODE_R4_SHIFT) & AMD_ERRCODE_R4_MASK) | \ 408 (((tt) << AMD_ERRCODE_TT_SHIFT) & AMD_ERRCODE_TT_MASK) | \ 409 ((ll) & AMD_ERRCODE_LL_MASK)) 410 #define AMD_ERRCODE_ISMEM(code) \ 411 (((code) & AMD_ERRCODE_MEM_MASK) == AMD_ERRCODE_MEM_VAL) 412 413 #define AMD_ERRCODE_MKBUS(pp, t, r4, ii, ll) \ 414 (AMD_ERRCODE_BUS_VAL | \ 415 (((pp) << AMD_ERRCODE_PP_SHIFT) & AMD_ERRCODE_PP_MASK) | \ 416 (((t) << AMD_ERRCODE_T_SHIFT) & AMD_ERRCODE_T_MASK) | \ 417 (((r4) << AMD_ERRCODE_R4_SHIFT) & AMD_ERRCODE_R4_MASK) | \ 418 (((ii) << AMD_ERRCODE_II_SHIFT) & AMD_ERRCODE_II_MASK) | \ 419 ((ll) & AMD_ERRCODE_LL_MASK)) 420 #define AMD_ERRCODE_ISBUS(code) \ 421 (((code) & AMD_ERRCODE_BUS_MASK) == AMD_ERRCODE_BUS_VAL) 422 423 #define AMD_NB_ADDRLO_MASK 0xfffffff8 424 #define AMD_NB_ADDRHI_MASK 0x000000ff 425 426 #define AMD_SYNDTYPE_ECC 0 427 #define AMD_SYNDTYPE_CHIPKILL 1 428 429 #define AMD_NB_SCRUBCTL_DRAM_MASK 0x0000001f 430 #define AMD_NB_SCRUBCTL_DRAM_SHIFT 0 431 #define AMD_NB_SCRUBCTL_L2_MASK 0x00001f00 432 #define AMD_NB_SCRUBCTL_L2_SHIFT 8 433 #define AMD_NB_SCRUBCTL_DC_MASK 0x001f0000 434 #define AMD_NB_SCRUBCTL_DC_SHIFT 16 435 436 #define AMD_NB_SCRUBCTL_RATE_NONE 0 437 #define AMD_NB_SCRUBCTL_RATE_MAX 0x16 438 439 #define AMD_NB_SCRUBADDR_LO_MASK 0xffffffc0 440 #define AMD_NB_SCRUBADDR_LO_SCRUBREDIREN 0x1 441 #define AMD_NB_SCRUBADDR_HI_MASK 0x000000ff 442 443 #define AMD_NB_SCRUBADDR_MKLO(addr) \ 444 ((addr) & AMD_NB_SCRUBADDR_LO_MASK) 445 446 #define AMD_NB_SCRUBADDR_MKHI(addr) \ 447 (((addr) >> 32) & AMD_NB_SCRUBADDR_HI_MASK) 448 449 #define AMD_NB_MKSCRUBCTL(dc, l2, dr) ( \ 450 (((dc) << AMD_NB_SCRUBCTL_DC_SHIFT) & AMD_NB_SCRUBCTL_DC_MASK) | \ 451 (((l2) << AMD_NB_SCRUBCTL_L2_SHIFT) & AMD_NB_SCRUBCTL_L2_MASK) | \ 452 (((dr) << AMD_NB_SCRUBCTL_DRAM_SHIFT) & AMD_NB_SCRUBCTL_DRAM_MASK)) 453 454 #ifdef __cplusplus 455 } 456 #endif 457 458 #endif /* _SYS_MCA_AMD_H */ 459