xref: /titanic_44/usr/src/uts/intel/sys/mc_intel.h (revision 491f61a1e1c1fc54a47bbcf53dbbbe1293b93b27)
120c794b3Sgavinm /*
220c794b3Sgavinm  * CDDL HEADER START
320c794b3Sgavinm  *
420c794b3Sgavinm  * The contents of this file are subject to the terms of the
520c794b3Sgavinm  * Common Development and Distribution License (the "License").
620c794b3Sgavinm  * You may not use this file except in compliance with the License.
720c794b3Sgavinm  *
820c794b3Sgavinm  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
920c794b3Sgavinm  * or http://www.opensolaris.org/os/licensing.
1020c794b3Sgavinm  * See the License for the specific language governing permissions
1120c794b3Sgavinm  * and limitations under the License.
1220c794b3Sgavinm  *
1320c794b3Sgavinm  * When distributing Covered Code, include this CDDL HEADER in each
1420c794b3Sgavinm  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
1520c794b3Sgavinm  * If applicable, add the following below this CDDL HEADER, with the
1620c794b3Sgavinm  * fields enclosed by brackets "[]" replaced with your own identifying
1720c794b3Sgavinm  * information: Portions Copyright [yyyy] [name of copyright owner]
1820c794b3Sgavinm  *
1920c794b3Sgavinm  * CDDL HEADER END
2020c794b3Sgavinm  */
2120c794b3Sgavinm 
2220c794b3Sgavinm /*
23ee9ef9e5SAdrian Frost  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
2420c794b3Sgavinm  * Use is subject to license terms.
2520c794b3Sgavinm  */
2620c794b3Sgavinm 
2720c794b3Sgavinm #ifndef _MC_INTEL_H
2820c794b3Sgavinm #define	_MC_INTEL_H
2920c794b3Sgavinm 
3020c794b3Sgavinm #ifdef __cplusplus
3120c794b3Sgavinm extern "C" {
3220c794b3Sgavinm #endif
3320c794b3Sgavinm 
3420c794b3Sgavinm #define	FM_EREPORT_CPU_INTEL	"intel"
3520c794b3Sgavinm 
3620c794b3Sgavinm #define	MCINTEL_NVLIST_VERSTR	"mcintel-nvlist-version"
3720c794b3Sgavinm #define	MCINTEL_NVLIST_VERS0	0
3820c794b3Sgavinm 
3920c794b3Sgavinm #define	MCINTEL_NVLIST_VERS	MCINTEL_NVLIST_VERS0
4020c794b3Sgavinm 
41e3d60c9bSAdrian Frost #define	MCINTEL_NVLIST_MEM	"memory-controller"
42e3d60c9bSAdrian Frost #define	MCINTEL_NVLIST_NMEM	"memory-controllers"
4320c794b3Sgavinm #define	MCINTEL_NVLIST_MC	"memory-channels"
4420c794b3Sgavinm #define	MCINTEL_NVLIST_DIMMS	"memory-dimms"
4520c794b3Sgavinm #define	MCINTEL_NVLIST_DIMMSZ	"memory-dimm-size"
46e3d60c9bSAdrian Frost #define	MCINTEL_NVLIST_NRANKS	"dimm-max-ranks"
47*491f61a1SYanmin Sun #define	MCINTEL_NVLIST_NDIMMS	"dimm-max-dimms"
4820c794b3Sgavinm #define	MCINTEL_NVLIST_RANKS	"dimm-ranks"
4985738508SVuong Nguyen #define	MCINTEL_NVLIST_1ST_RANK	"dimm-start-rank"
50*491f61a1SYanmin Sun #define	MCINTEL_NVLIST_DIMM_NUM	"dimm-number"
5120c794b3Sgavinm #define	MCINTEL_NVLIST_ROWS	"dimm-rows"
5220c794b3Sgavinm #define	MCINTEL_NVLIST_COL	"dimm-column"
5320c794b3Sgavinm #define	MCINTEL_NVLIST_BANK	"dimm-banks"
5420c794b3Sgavinm #define	MCINTEL_NVLIST_WIDTH	"dimm-width"
5520c794b3Sgavinm #define	MCINTEL_NVLIST_MID	"dimm-manufacture-id"
5620c794b3Sgavinm #define	MCINTEL_NVLIST_MLOC	"dimm-manufacture-location"
5720c794b3Sgavinm #define	MCINTEL_NVLIST_MWEEK	"dimm-manufacture-week"
5820c794b3Sgavinm #define	MCINTEL_NVLIST_MYEAR	"dimm-manufacture-year"
5920c794b3Sgavinm #define	MCINTEL_NVLIST_SERIALNO	"dimm-serial-number"
6020c794b3Sgavinm #define	MCINTEL_NVLIST_PARTNO	"dimm-part-number"
6120c794b3Sgavinm #define	MCINTEL_NVLIST_REV	"dimm-part-rev"
6220c794b3Sgavinm 
6320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_GLOBAL		"ferr_global"
6420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_GLOBAL		"nerr_global"
6520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FSB			"fsb"
6620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_FSB		"ferr_fat_fsb"
6720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_FSB		"nerr_fat_fsb"
6820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_FSB		"ferr_nf_fsb"
6920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_FSB		"nerr_nf_fsb"
7020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFSB			"nrecfsb"
7120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFSB_ADDR		"nrecfsb_addr"
7220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFSB			"recfsb"
7320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEX			"pex"
7420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEX_FAT_FERR		"pex_fat_ferr"
7520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEX_FAT_NERR		"pex_fat_nerr"
7620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEX_NF_CORR_FERR	"pex_nf_corr_ferr"
7720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEX_NF_CORR_NERR	"pex_nf_corr_nerr"
7820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_UNCERRSEV		"uncerrsev"
7920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RPERRSTS		"rperrsts"
8020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RPERRSID		"rperrsid"
8120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_UNCERRSTS		"uncerrsts"
8220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_AERRCAPCTRL		"aerrcapctrl"
8320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_CORERRSTS		"corerrsts"
8420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEXDEVSTS		"pexdevsts"
8520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_INT		"ferr_fat_int"
8620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_INT		"ferr_nf_int"
8720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_INT		"nerr_fat_int"
8820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_INT		"nerr_nf_int"
8920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECINT			"nrecint"
9020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECINT			"recint"
9120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECSF			"nrecsf"
9220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECSF			"recsf"
9320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RANK			"rank"
9420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BANK			"bank"
9520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_CAS			"cas"
9620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RAS			"ras"
9720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_FBD		"ferr_fat_fbd"
9820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_FBD		"nerr_fat_fbd"
9985738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_VALIDLOG		"validlog"
10020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECMEMA		"nrecmema"
10120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECMEMB		"nrecmemb"
10220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFGLOG		"nrecfglog"
10320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDA		"nrecfbda"
10420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDB		"nrecfbdb"
10520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDC		"nrecfbdc"
10620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDD		"nrecfbdd"
10720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDE		"nrecfbde"
1085de8e333Saf #define	FM_EREPORT_PAYLOAD_NAME_NRECFBDF		"nrecfbdf"
10920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_SPCPC			"spcpc"
11020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_SPCPS			"spcps"
11120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_UERRCNT			"uerrcnt"
11220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_UERRCNT_LAST		"uerrcnt_last"
11385738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_BADRAM			"badram"
11420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BADRAMA			"badrama"
11520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BADRAMB			"badramb"
11620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BADCNT			"badcnt"
11720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_MC			"mc"
11820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_MCA			"mca"
11920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_TOLM			"tolm"
12020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_MIR			"mir"
12120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_MTR			"mtr"
12220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_DMIR			"dmir"
12320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_FBD		"ferr_nf_fbd"
12420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_FBD		"nerr_nf_fbd"
12585738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_MEM		"ferr_nf_mem"
12685738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_MEM		"nerr_nf_mem"
12720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECMEMA			"recmema"
12820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECMEMB			"recmemb"
12985738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_REDMEMA			"redmema"
13085738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_REDMEMB			"redmemb"
13120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFGLOG		"recfglog"
13220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFBDA			"recfbda"
13320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFBDB			"recfbdb"
13420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFBDC			"recfbdc"
13520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFBDD			"recfbdd"
13620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_RECFBDE			"recfbde"
1375de8e333Saf #define	FM_EREPORT_PAYLOAD_NAME_RECFBDF			"recfbdf"
13820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT			"cerrcnt"
13920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_LAST		"cerrcnt_last"
14085738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_EXT		"cerrcnt_ext"
14185738508SVuong Nguyen #define	FM_EREPORT_PAYLOAD_NAME_CERRCNT_EXT_LAST	"cerrcnt_ext_last"
1425f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTA		"cerrcnta"
1435f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTB		"cerrcntb"
1445f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTC		"cerrcntc"
1455f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTD		"cerrcntd"
1465f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTA_LAST		"cerrcnta_last"
1475f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTB_LAST		"cerrcntb_last"
1485f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTC_LAST		"cerrcntc_last"
1495f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CERRCNTD_LAST		"cerrcntd_last"
15020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PCISTS			"pcists"
15120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_PEXDEVSTS		"pexdevsts"
15220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_ERROR_NO		"intel-error-list"
15320c794b3Sgavinm 
1545f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_CTSTS			"ctsts"
1555f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_THRTSTS			"thrtsts"
1565f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_FERR_FAT_THR		"ferr_fat_thr"
1575f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_NERR_FAT_THR		"nerr_fat_thr"
1585f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_FERR_NF_THR		"ferr_nf_thr"
1595f28a827Saf #define	FM_EREPORT_PAYLOAD_NAME_NERR_NF_THR		"nerr_nf_thr"
1605f28a827Saf 
16120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_ADDR			"addr"
16220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BANK_NUM		"bank-number"
16320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BANK_MISC		"bank-misc"
16420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BANK_STAT		"bank-status"
16520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_BANK_OFFSET		"bank-offset"
16620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_NAME_MC_TYPE			"mc-type"
16720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_CPUID			"cpuid"
16820c794b3Sgavinm 
16920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_BQR				"Bus-queue-request"
17020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_BQET				"Bus-queue-error-type"
17120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_FRC				"FRC-error"
17220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_BERR				"BERR"
17320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_INT_BINT			"Internal-BINT"
17420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_EXT_BINT			"External-BINT"
17520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_BUS_BINT			"Bus-BINT"
17620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_TO_BINT			"Timeout-BINT"
17720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_HARD				"Hard-error"
17820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_IERR				"IERR"
17920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_AERR				"AERR"
18020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_UERR				"UERR"
18120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_CECC				"CECC"
18220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_UECC				"UECC"
18320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_ECC_SYND			"ECC-syndrome"
18420c794b3Sgavinm 
18520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_FSB_PARITY			"fsb-address-parity"
18620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_RESP_HF			"response-hard-fail"
18720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_RESP_PARITY			"response-parity"
18820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_DATA_PARITY			"bus-data-parity"
18920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_INV_PIC			"invalid-pic-request"
19020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_PAD_SM			"pad-state-machine"
19120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_PAD_SG			"pad-strobe-glitch"
19220c794b3Sgavinm 
19320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_TAG				"tag-error"
19420c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_TAG_CLEAN			"clean"
19520c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_TAG_HIT			"hit"
19620c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_TAG_MISS			"miss"
19720c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_DATA				"data-error"
19820c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_DATA_SINGLE			"single-bit"
19920c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_DATA_DBL_CLEAN		"double-bit-clean"
20020c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_DATA_DBL_MOD			"double-bit-modified"
20120c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_L3				"l3-cache"
20220c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_INV_PIC			"invalid-pic-request"
20320c794b3Sgavinm #define	FM_EREPORT_PAYLOAD_CACHE_NERRORS		"cache-error-count"
20420c794b3Sgavinm 
205e3d60c9bSAdrian Frost #define	FM_EREPORT_PAYLOAD_NAME_RESOURCE		"resource"
206e3d60c9bSAdrian Frost #define	FM_EREPORT_PAYLOAD_MEM_ECC_COUNTER_THIS	"mem_cor_ecc_counter"
207e3d60c9bSAdrian Frost #define	FM_EREPORT_PAYLOAD_MEM_ECC_COUNTER_LAST	"mem_cor_ecc_counter_last"
208e3d60c9bSAdrian Frost 
20920c794b3Sgavinm #define	INTEL_NB_5000P	0x25d88086
21020c794b3Sgavinm #define	INTEL_NB_5000V	0x25d48086
21120c794b3Sgavinm #define	INTEL_NB_5000X	0x25c08086
21220c794b3Sgavinm #define	INTEL_NB_5000Z	0x25d08086
21385738508SVuong Nguyen #define	INTEL_NB_5100	0x65c08086
2145f28a827Saf #define	INTEL_NB_5400	0x40008086
2155f28a827Saf #define	INTEL_NB_5400A	0x40018086
2165f28a827Saf #define	INTEL_NB_5400B	0x40038086
21720c794b3Sgavinm #define	INTEL_NB_7300	0x36008086
21820c794b3Sgavinm 
219e3d60c9bSAdrian Frost #define	INTEL_NHM	0x2c408086
220e3d60c9bSAdrian Frost #define	INTEL_QP_IO	0x34008086
221e3d60c9bSAdrian Frost #define	INTEL_QP_36D	0x34068086
222e3d60c9bSAdrian Frost #define	INTEL_QP_24D	0x34038086
223ee9ef9e5SAdrian Frost #define	INTEL_QP_WP	0x34058086
224ee9ef9e5SAdrian Frost #define	INTEL_QP_U1	0x34018086
225ee9ef9e5SAdrian Frost #define	INTEL_QP_U2	0x34028086
226ee9ef9e5SAdrian Frost #define	INTEL_QP_U3	0x34048086
227ee9ef9e5SAdrian Frost #define	INTEL_QP_U4	0x34078086
22835366b93SAdrian Frost #define	INTEL_QP_JF	0x37208086
22935366b93SAdrian Frost #define	INTEL_QP_JF0	0x37008086
23035366b93SAdrian Frost #define	INTEL_QP_JF1	0x37018086
23135366b93SAdrian Frost #define	INTEL_QP_JF2	0x37028086
23235366b93SAdrian Frost #define	INTEL_QP_JF3	0x37038086
23335366b93SAdrian Frost #define	INTEL_QP_JF4	0x37048086
23435366b93SAdrian Frost #define	INTEL_QP_JF5	0x37058086
23535366b93SAdrian Frost #define	INTEL_QP_JF6	0x37068086
23635366b93SAdrian Frost #define	INTEL_QP_JF7	0x37078086
23735366b93SAdrian Frost #define	INTEL_QP_JF8	0x37088086
23835366b93SAdrian Frost #define	INTEL_QP_JF9	0x37098086
23935366b93SAdrian Frost #define	INTEL_QP_JFa	0x370a8086
24035366b93SAdrian Frost #define	INTEL_QP_JFb	0x370b8086
24135366b93SAdrian Frost #define	INTEL_QP_JFc	0x370c8086
24235366b93SAdrian Frost #define	INTEL_QP_JFd	0x370d8086
24335366b93SAdrian Frost #define	INTEL_QP_JFe	0x370e8086
24435366b93SAdrian Frost #define	INTEL_QP_JFf	0x370f8086
245e3d60c9bSAdrian Frost 
246e3d60c9bSAdrian Frost /* Intel QuickPath Bus Interconnect Errors */
247e3d60c9bSAdrian Frost 
248e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_HEADER_PARITY		(1 << 16)
249e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_DATA_PARITY		(1 << 17)
250e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_RETRIES_EXCEEDED	(1 << 18)
251e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_POISON		(1 << 19)
252e3d60c9bSAdrian Frost 
253e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_UNSUPPORTED_MSG	(1 << 22)
254e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_UNSUPPORTED_CREDIT	(1 << 23)
255e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_FLIT_BUF_OVER		(1 << 24)
256e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_FAILED_RESPONSE	(1 << 25)
257e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_QP_CLOCK_JITTER		(1 << 26)
258e3d60c9bSAdrian Frost 
259e3d60c9bSAdrian Frost #define	MSR_MC_MISC_QP_CLASS		0x000000ff
260e3d60c9bSAdrian Frost #define	MSR_MC_MISC_QP_RTID		0x00003f00
261e3d60c9bSAdrian Frost #define	MSR_MC_MISC_QP_RHNID		0x00070000
262e3d60c9bSAdrian Frost #define	MSR_MC_MISC_QP_IIB		0x01000000
263e3d60c9bSAdrian Frost 
264e3d60c9bSAdrian Frost /* Intel QuickPath Memory Errors */
265e3d60c9bSAdrian Frost 
266e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY		0x0080
267e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY_MASK		0xff80
268e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY_TRANSACTION	0x0070
269e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY_READ		0x0010
270e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY_WRITE	0x0020
271e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY_CMD		0x0030
272e3d60c9bSAdrian Frost #define	MCAX86_COMPOUND_BUS_MEMORY_CHANNEL	0x000f
273e3d60c9bSAdrian Frost 
274e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_ECC_READ	(1 << 16)
275e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_ECC_SCRUB	(1 << 17)
276e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_PARITY	(1 << 18)
277e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_REDUNDANT_MEM	(1 << 19)
278e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_SPARE_MEM	(1 << 20)
279e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_ILLEGAL_ADDR	(1 << 21)
280e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_BAD_ID	(1 << 22)
281e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_ADDR_PARITY	(1 << 23)
282e3d60c9bSAdrian Frost #define	MSR_MC_STATUS_MEM_BYTE_PARITY	(1 << 24)
283e3d60c9bSAdrian Frost 
284e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_RTID		0x00000000000000ffULL
285e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_DIMM		0x0000000000030000ULL
286e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_DIMM_SHIFT	16
287e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_CHANNEL		0x00000000000c0000ULL
288e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_CHANNEL_SHIFT	18
289e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_SYNDROME	0xffffffff00000000ULL
290e3d60c9bSAdrian Frost #define	MSR_MC_MISC_MEM_SYNDROME_SHIFT	32
291e3d60c9bSAdrian Frost 
292f899e573SVuong Nguyen #define	OFFSET_ROW_BANK_COL	0x8000000000000000ULL
293f899e573SVuong Nguyen #define	OFFSET_RANK_SHIFT	52
294f899e573SVuong Nguyen #define	OFFSET_RAS_SHIFT	32
295f899e573SVuong Nguyen #define	OFFSET_BANK_SHIFT	24
296f899e573SVuong Nguyen #define	TCODE_OFFSET(rank, bank, ras, cas) (OFFSET_ROW_BANK_COL | \
297f899e573SVuong Nguyen 	((uint64_t)(rank) << OFFSET_RANK_SHIFT) | \
298f899e573SVuong Nguyen 	((uint64_t)(ras) << OFFSET_RAS_SHIFT) | \
299f899e573SVuong Nguyen 	((uint64_t)(bank) << OFFSET_BANK_SHIFT) | (cas))
300f899e573SVuong Nguyen 
301f899e573SVuong Nguyen #define	MAX_CAS_MASK	0xFFFFFF
302f899e573SVuong Nguyen #define	MAX_BANK_MASK	0xFF
303f899e573SVuong Nguyen #define	MAX_RAS_MASK	0xFFFFF
304f899e573SVuong Nguyen #define	MAX_RANK_MASK	0x7FF
305f899e573SVuong Nguyen #define	TCODE_OFFSET_RANK(tcode) \
306f899e573SVuong Nguyen 	(((tcode) >> OFFSET_RANK_SHIFT) & MAX_RANK_MASK)
307f899e573SVuong Nguyen #define	TCODE_OFFSET_RAS(tcode) (((tcode) >> OFFSET_RAS_SHIFT) & MAX_RAS_MASK)
308f899e573SVuong Nguyen #define	TCODE_OFFSET_BANK(tcode) \
309f899e573SVuong Nguyen 	(((tcode) >> OFFSET_BANK_SHIFT) & MAX_BANK_MASK)
310f899e573SVuong Nguyen #define	TCODE_OFFSET_CAS(tcode) ((tcode) & MAX_CAS_MASK)
311f899e573SVuong Nguyen 
31220c794b3Sgavinm #ifdef __cplusplus
31320c794b3Sgavinm }
31420c794b3Sgavinm #endif
31520c794b3Sgavinm 
31620c794b3Sgavinm #endif /* _MC_INTEL_H */
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