1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 * 21 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 22 * Use is subject to license terms. 23 */ 24 25 #ifndef _MC_AMD_H 26 #define _MC_AMD_H 27 28 #pragma ident "%Z%%M% %I% %E% SMI" 29 30 #include <sys/mc.h> 31 #include <sys/isa_defs.h> 32 #include <sys/x86_archext.h> 33 34 #ifdef __cplusplus 35 extern "C" { 36 #endif 37 38 /* 39 * Definitions, register offsets, register structure etc pertaining to 40 * the memory controller on AMD64 systems. These are used by both the 41 * AMD cpu module and the mc-amd driver. 42 */ 43 44 /* 45 * The mc-amd driver exports an nvlist to userland, where the primary 46 * consumer is the "chip" topology enumerator for this platform type which 47 * builds a full topology subtree from this information. Others can use 48 * it, too, but don't depend on it not changing without an ARC contract 49 * (and the contract should probably concern the topology, not this nvlist). 50 * 51 * In the initial mc-amd implementation this nvlist was not versioned; 52 * we'll think of that as version 0 and it may be recognised by the absence 53 * of a "mcamd-nvlist-version member. 54 * 55 * Version 1 is defined as follows. A name in square brackets indicates 56 * that member is optional (only present if the actual value is valid). 57 * 58 * Name Type Description 59 * -------------------- --------------- --------------------------------------- 60 * mcamd-nvlist-version uint8 Exported nvlist version number 61 * num uint64 Chip id of this memory controller 62 * revision uint64 cpuid_getchiprev() result 63 * revname string cpuid_getchiprevstr() result 64 * socket string "Socket 755|939|940|AM2|F(1207)|S1g1" 65 * ecc-type string "ChipKill 128/16" or "Normal 64/8" 66 * base-addr uint64 Node base address 67 * lim-addr uint64 Node limit address 68 * node-ilen uint64 0|1|3|7 for 0/2/4/8 way node interleave 69 * node-ilsel uint64 Node interleave position of this node 70 * cs-intlv-factor uint64 chip-select interleave: 1/2/4/8 71 * dram-hole-size uint64 size in bytes from dram hole addr reg 72 * access-width uint64 MC mode, 64 or 128 bit 73 * bank-mapping uint64 Raw DRAM Bank Address Mapping Register 74 * bankswizzle uint64 1 if bank swizzling enabled; else 0 75 * mismatched-dimm-support uint64 1 if active; else 0 76 * [spare-csnum] uint64 Chip-select pair number of any spare 77 * [bad-csnum] uint64 Chip-select pair number of swapped cs 78 * cslist nvlist array See below; may have 0 members 79 * dimmlist nvlist array See below; may have 0 members 80 * 81 * cslist is an array of nvlist, each as follows: 82 * 83 * Name Type Description 84 * -------------------- --------------- --------------------------------------- 85 * num uint64 Chip-select base/mask pair number 86 * base-addr uint64 Chip-select base address (rel to node) 87 * mask uint64 Chip-select mask 88 * size uint64 Chip-select size in bytes 89 * dimm1-num uint64 First dimm (lodimm if a pair) 90 * dimm1-csname string Socket cs# line name for 1st dimm rank 91 * [dimm2-num] uint64 Second dimm if applicable (updimm) 92 * [dimm2-csname] string Socket cs# line name for 2nd dimm rank 93 * 94 * dimmlist is an array of nvlist, each as follows: 95 * 96 * Name Type Description 97 * -------------------- --------------- --------------------------------------- 98 * num uint64 DIMM instance number 99 * size uint64 DIMM size in bytes 100 * csnums uint64 array CS base/mask pair(s) on this DIMM 101 * csnames string array Socket cs# line name(s) on this DIMM 102 * 103 * The n'th csnums entry corresponds to the n'th csnames entry 104 */ 105 #define MC_NVLIST_VERSTR "mcamd-nvlist-version" 106 #define MC_NVLIST_VERS0 0 107 #define MC_NVLIST_VERS1 1 108 #define MC_NVLIST_VERS MC_NVLIST_VERS1 109 110 /* 111 * Constants and feature/revision test macros that are not expected to vary 112 * among different AMD family 0xf processor revisions. 113 */ 114 115 /* 116 * Configuration constants 117 */ 118 #define MC_CHIP_MAXNODES 8 /* max number of MCs in system */ 119 #define MC_CHIP_NDIMM 8 /* max dimms per MC */ 120 #define MC_CHIP_NCS 8 /* number of chip-selects per MC */ 121 #define MC_CHIP_NDRAMCHAN 2 /* maximum number of dram channels */ 122 #define MC_CHIP_DIMMRANKMAX 4 /* largest number of ranks per dimm */ 123 #define MC_CHIP_DIMMPERCS 2 /* max number of dimms per cs */ 124 #define MC_CHIP_DIMMPAIR(csnum) (csnum / MC_CHIP_DIMMPERCS) 125 126 /* 127 * Memory controller registers are read via PCI config space accesses on 128 * bus 0, device 0x18 + NodeId, and function as follows: 129 * 130 * Function 0: HyperTransport Technology Configuration 131 * Function 1: Address Map 132 * Function 2: DRAM Controller & HyperTransport Technology Trace Mode 133 * Function 3: Miscellaneous Control 134 */ 135 136 #define MC_AMD_DEV_OFFSET 0x18 /* node ID + offset == PCI dev num */ 137 138 enum mc_funcnum { 139 MC_FUNC_HTCONFIG = 0, 140 MC_FUNC_ADDRMAP = 1, 141 MC_FUNC_DRAMCTL = 2, 142 MC_FUNC_MISCCTL = 3 143 }; 144 145 /* 146 * For a given (bus, device, function) a particular offset selects the 147 * desired register. All registers are 32-bits wide. 148 * 149 * Different family 0xf processor revisions vary slightly in the content 150 * of these configuration registers. The biggest change is with rev F 151 * where DDR2 support has been introduced along with some hardware-controlled 152 * correctable memory error thresholding. Fortunately most of the config info 153 * required by the mc-amd driver is similar across revisions. 154 * 155 * We will try to insulate most of the driver code from config register 156 * details by reading all memory-controller PCI config registers that we 157 * will need at driver attach time for each of functions 0 through 3, and 158 * storing them in a "cooked" form as memory controller properties. 159 * These are to be accessed directly where we have an mc_t to hand, otherwise 160 * through mcamd_get_numprop. As such we expect most/all use of the 161 * structures and macros defined below to be in those attach codepaths. 162 */ 163 164 /* 165 * Function 0 (HT Config) offsets 166 */ 167 #define MC_HT_REG_RTBL_NODE_0 0x40 168 #define MC_HT_REG_RTBL_INCR 4 169 #define MC_HT_REG_NODEID 0x60 170 #define MC_HT_REG_UNITID 0x64 171 172 /* 173 * Function 1 (address map) offsets for DRAM base, DRAM limit, DRAM hole 174 * registers. 175 */ 176 #define MC_AM_REG_DRAMBASE_0 0x40 /* Offset for DRAM Base 0 */ 177 #define MC_AM_REG_DRAMLIM_0 0x44 /* Offset for DRAM Limit 0 */ 178 #define MC_AM_REG_DRAM_INCR 8 /* incr between base/limit pairs */ 179 #define MC_AM_REG_HOLEADDR 0xf0 /* DRAM Hole Address Register */ 180 181 /* 182 * Function 2 (dram controller) offsets for chip-select base, chip-select mask, 183 * DRAM bank address mapping, DRAM configuration registers. 184 */ 185 #define MC_DC_REG_CS_INCR 4 /* incr for CS base and mask */ 186 #define MC_DC_REG_CSBASE_0 0x40 /* 0x40 - 0x5c */ 187 #define MC_DC_REG_CSMASK_0 0x60 /* 0x60 - 0x7c */ 188 #define MC_DC_REG_BANKADDRMAP 0x80 /* DRAM Bank Address Mapping */ 189 #define MC_DC_REG_DRAMCFGLO 0x90 /* DRAM Configuration Low */ 190 #define MC_DC_REG_DRAMCFGHI 0x94 /* DRAM Configuration High */ 191 #define MC_DC_REG_DRAMMISC 0xa0 /* DRAM Miscellaneous */ 192 193 /* 194 * Function 3 (misc control) offset for NB MCA config, scrubber control 195 * and online spare control. 196 */ 197 #define MC_CTL_REG_NBCFG 0x44 /* MCA NB configuration register */ 198 #define MC_CTL_REG_SCRUBCTL 0x58 /* Scrub control register */ 199 #define MC_CTL_REG_SCRUBADDR_LO 0x5c /* DRAM Scrub Address Low */ 200 #define MC_CTL_REG_SCRUBADDR_HI 0x60 /* DRAM Scrub Address High */ 201 #define MC_CTL_REG_SPARECTL 0xb0 /* On-line spare control register */ 202 203 /* 204 * MC4_MISC MSR and MC4_MISCj MSRs 205 */ 206 #define MC_MSR_NB_MISC0 0x413 207 #define MC_MSR_NB_MISC1 0xc0000408 208 #define MC_MSR_NB_MISC2 0xc0000409 209 #define MC_MSR_NB_MISC3 0xc000040a 210 #define MC_MSR_NB_MISC(j) \ 211 ((j) == 0 ? MC_MSR_NB_MISC0 : MC_MSR_NB_MISC1 + (j) - 1) 212 213 /* 214 * PCI registers will be represented as unions, with one fixed-width unsigned 215 * integer member providing access to the raw register value and one or more 216 * structs breaking the register out into bitfields (more than one struct if 217 * the register definitions varies across processor revisions). 218 * 219 * The "raw" union member will always be '_val32'. Use MCREG_VAL32 to 220 * access this member. 221 * 222 * The bitfield structs are all named _fmt_xxx where xxx identifies the 223 * processor revision to which it applies. At this point the only xxx 224 * values in use are: 225 * 'cmn' - applies to all revisions 226 * 'f_preF' - applies to revisions E and earlier 227 * 'f_revFG' - applies to revisions F and G 228 * 229 * Variants such as 'preD', 'revDE', 'postCG' etc should be introduced 230 * as requirements arise. The MC_REV_* and MC_REV_MATCH etc macros 231 * will also need to grow to match. Use MCREG_FIELD_* to access the 232 * individual bitfields of a register, perhaps using MC_REV_* and MC_REV_MATCH 233 * to decide which revision suffix to provide. Where a bitfield appears 234 * in different revisions but has the same use it should be named identically 235 * (even if the BKDG varies a little) so that the MC_REG_FIELD_* macros 236 * can lookup that member based on revision only. 237 */ 238 239 #define MC_REV_UNKNOWN X86_CHIPREV_UNKNOWN 240 241 #define MC_F_REV_B X86_CHIPREV_AMD_F_REV_B 242 #define MC_F_REV_C (X86_CHIPREV_AMD_F_REV_C0 | X86_CHIPREV_AMD_F_REV_CG) 243 #define MC_F_REV_D X86_CHIPREV_AMD_F_REV_D 244 #define MC_F_REV_E X86_CHIPREV_AMD_F_REV_E 245 #define MC_F_REV_F X86_CHIPREV_AMD_F_REV_F 246 #define MC_F_REV_G X86_CHIPREV_AMD_F_REV_G 247 248 #define MC_10_REV_A X86_CHIPREV_AMD_10_REV_A 249 #define MC_10_REV_B X86_CHIPREV_AMD_10_REV_B 250 251 /* 252 * The most common groupings for memory controller features. 253 */ 254 #define MC_F_REVS_BC (MC_F_REV_B | MC_F_REV_C) 255 #define MC_F_REVS_DE (MC_F_REV_D | MC_F_REV_E) 256 #define MC_F_REVS_BCDE (MC_F_REVS_BC | MC_F_REVS_DE) 257 #define MC_F_REVS_FG (MC_F_REV_F | MC_F_REV_G) 258 259 #define MC_10_REVS_AB (MC_10_REV_A | MC_10_REV_B) 260 261 /* 262 * Is 'rev' included in the 'revmask' bitmask? 263 */ 264 #define MC_REV_MATCH(rev, revmask) X86_CHIPREV_MATCH(rev, revmask) 265 266 /* 267 * Is 'rev' at least revision 'revmin' or greater 268 */ 269 #define MC_REV_ATLEAST(rev, minrev) X86_CHIPREV_ATLEAST(rev, minrev) 270 271 #define _MCREG_FIELD(up, revsuffix, field) ((up)->_fmt_##revsuffix.field) 272 273 #define MCREG_VAL32(up) ((up)->_val32) 274 275 /* 276 * Access a field that has the same structure in all families and revisions 277 */ 278 #define MCREG_FIELD_CMN(up, field) _MCREG_FIELD(up, cmn, field) 279 280 /* 281 * Access a field as defined for family 0xf prior to revision F 282 */ 283 #define MCREG_FIELD_F_preF(up, field) _MCREG_FIELD(up, f_preF, field) 284 285 /* 286 * Access a field as defined for family 0xf revisions F and G 287 */ 288 #define MCREG_FIELD_F_revFG(up, field) _MCREG_FIELD(up, f_revFG, field) 289 290 /* 291 * Access a field as defined for family 0x10 revisions A and 292 */ 293 #define MCREG_FIELD_10_revAB(up, field) _MCREG_FIELD(up, 10_revAB, field) 294 295 /* 296 * We will only define the register bitfields for little-endian order 297 */ 298 #ifdef _BIT_FIELDS_LTOH 299 300 /* 301 * Function 0 - HT Configuration: Routing Table Node Register 302 */ 303 union mcreg_htroute { 304 uint32_t _val32; 305 struct { 306 uint32_t RQRte:4; /* 3:0 */ 307 uint32_t reserved1:4; /* 7:4 */ 308 uint32_t RPRte:4; /* 11:8 */ 309 uint32_t reserved2:4; /* 15:12 */ 310 uint32_t BCRte:4; /* 19:16 */ 311 uint32_t reserved3:12; /* 31:20 */ 312 } _fmt_cmn; 313 }; 314 315 /* 316 * Function 0 - HT Configuration: Node ID Register 317 */ 318 union mcreg_nodeid { 319 uint32_t _val32; 320 struct { 321 uint32_t NodeId:3; /* 2:0 */ 322 uint32_t reserved1:1; /* 3:3 */ 323 uint32_t NodeCnt:3; /* 6:4 */ 324 uint32_t reserved2:1; /* 7:7 */ 325 uint32_t SbNode:3; /* 10:8 */ 326 uint32_t reserved3:1; /* 11:11 */ 327 uint32_t LkNode:3; /* 14:12 */ 328 uint32_t reserved4:1; /* 15:15 */ 329 uint32_t CpuCnt:4; /* 19:16 */ 330 uint32_t reserved:12; /* 31:20 */ 331 } _fmt_cmn; 332 }; 333 334 #define HT_COHERENTNODES(up) (MCREG_FIELD_CMN(up, NodeCnt) + 1) 335 #define HT_SYSTEMCORECOUNT(up) (MCREG_FIELD_CMN(up, CpuCnt) + 1) 336 337 /* 338 * Function 0 - HT Configuration: Unit ID Register 339 */ 340 union mcreg_unitid { 341 uint32_t _val32; 342 struct { 343 uint32_t C0Unit:2; /* 1:0 */ 344 uint32_t C1Unit:2; /* 3:2 */ 345 uint32_t McUnit:2; /* 5:4 */ 346 uint32_t HbUnit:2; /* 7:6 */ 347 uint32_t SbLink:2; /* 9:8 */ 348 uint32_t reserved:22; /* 31:10 */ 349 } _fmt_cmn; 350 }; 351 352 /* 353 * Function 1 - DRAM Address Map: DRAM Base i Registers 354 * 355 */ 356 357 union mcreg_drambase { 358 uint32_t _val32; 359 struct { 360 uint32_t RE:1; /* 0:0 - Read Enable */ 361 uint32_t WE:1; /* 1:1 - Write Enable */ 362 uint32_t reserved1:6; /* 7:2 */ 363 uint32_t IntlvEn:3; /* 10:8 - Interleave Enable */ 364 uint32_t reserved2:5; /* 15:11 */ 365 uint32_t DRAMBasei:16; /* 31:16 - Base Addr 39:24 */ 366 } _fmt_cmn; 367 }; 368 369 #define MC_DRAMBASE(up) ((uint64_t)MCREG_FIELD_CMN(up, DRAMBasei) << 24) 370 371 /* 372 * Function 1 - DRAM Address Map: DRAM Limit i Registers 373 * 374 */ 375 376 union mcreg_dramlimit { 377 uint32_t _val32; 378 struct { 379 uint32_t DstNode:3; /* 2:0 - Destination Node */ 380 uint32_t reserved1:5; /* 7:3 */ 381 uint32_t IntlvSel:3; /* 10:8 - Interleave Select */ 382 uint32_t reserved2:5; /* 15:11 */ 383 uint32_t DRAMLimiti:16; /* 31:16 - Limit Addr 39:24 */ 384 } _fmt_cmn; 385 }; 386 387 #define MC_DRAMLIM(up) \ 388 ((uint64_t)MCREG_FIELD_CMN(up, DRAMLimiti) << 24 | \ 389 (MCREG_FIELD_CMN(up, DRAMLimiti) ? ((1 << 24) - 1) : 0)) 390 391 /* 392 * Function 1 - DRAM Address Map: DRAM Hole Address Register 393 */ 394 395 union mcreg_dramhole { 396 uint32_t _val32; 397 struct { 398 uint32_t DramHoleValid:1; /* 0:0 */ 399 uint32_t reserved1:7; /* 7:1 */ 400 uint32_t DramHoleOffset:8; /* 15:8 */ 401 uint32_t reserved2:8; /* 23:16 */ 402 uint32_t DramHoleBase:8; /* 31:24 */ 403 } _fmt_cmn; 404 }; 405 406 #define MC_DRAMHOLE_SIZE(up) (MCREG_FIELD_CMN(up, DramHoleOffset) << 24) 407 408 /* 409 * Function 2 - DRAM Controller: DRAM CS Base Address Registers 410 */ 411 412 union mcreg_csbase { 413 uint32_t _val32; 414 /* 415 * Register format in family 0xf revisions E and earlier 416 */ 417 struct { 418 uint32_t CSEnable:1; /* 0:0 - CS Bank Enable */ 419 uint32_t reserved1:8; /* 8:1 */ 420 uint32_t BaseAddrLo:7; /* 15:9 - Base Addr 19:13 */ 421 uint32_t reserved2:5; /* 20:16 */ 422 uint32_t BaseAddrHi:11; /* 31:21 - Base Addr 35:25 */ 423 } _fmt_f_preF; 424 /* 425 * Register format in family 0xf revisions F and G 426 */ 427 struct { 428 uint32_t CSEnable:1; /* 0:0 - CS Bank Enable */ 429 uint32_t Spare:1; /* 1:1 - Spare Rank */ 430 uint32_t TestFail:1; /* 2:2 - Memory Test Failed */ 431 uint32_t reserved1:2; /* 4:3 */ 432 uint32_t BaseAddrLo:9; /* 13:5 - Base Addr 21:13 */ 433 uint32_t reserved2:5; /* 18:14 */ 434 uint32_t BaseAddrHi:10; /* 28:19 - Base Addr 36:27 */ 435 uint32_t reserved3:3; /* 31:39 */ 436 } _fmt_f_revFG; 437 }; 438 439 #define MC_CSBASE(up, rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? \ 440 (uint64_t)MCREG_FIELD_F_revFG(up, BaseAddrHi) << 27 | \ 441 (uint64_t)MCREG_FIELD_F_revFG(up, BaseAddrLo) << 13 : \ 442 (uint64_t)MCREG_FIELD_F_preF(up, BaseAddrHi) << 25 | \ 443 (uint64_t)MCREG_FIELD_F_preF(up, BaseAddrLo) << 13) 444 445 /* 446 * Function 2 - DRAM Controller: DRAM CS Mask Registers 447 */ 448 449 union mcreg_csmask { 450 uint32_t _val32; 451 /* 452 * Register format in family 0xf revisions E and earlier 453 */ 454 struct { 455 uint32_t reserved1:9; /* 8:0 */ 456 uint32_t AddrMaskLo:7; /* 15:9 - Addr Mask 19:13 */ 457 uint32_t reserved2:5; /* 20:16 */ 458 uint32_t AddrMaskHi:9; /* 29:21 - Addr Mask 33:25 */ 459 uint32_t reserved3:2; /* 31:30 */ 460 } _fmt_f_preF; 461 /* 462 * Register format in family 0xf revisions F and G 463 */ 464 struct { 465 uint32_t reserved1:5; /* 4:0 */ 466 uint32_t AddrMaskLo:9; /* 13:5 - Addr Mask 21:13 */ 467 uint32_t reserved2:5; /* 18:14 */ 468 uint32_t AddrMaskHi:10; /* 28:19 - Addr Mask 36:27 */ 469 uint32_t reserved3:3; /* 31:29 */ 470 } _fmt_f_revFG; 471 }; 472 473 #define MC_CSMASKLO_LOBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 13 : 13) 474 #define MC_CSMASKLO_HIBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 21 : 19) 475 476 #define MC_CSMASKHI_LOBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 27 : 25) 477 #define MC_CSMASKHI_HIBIT(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 36 : 33) 478 479 #define MC_CSMASK_UNMASKABLE(rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? 0 : 2) 480 481 #define MC_CSMASK(up, rev) (MC_REV_MATCH(rev, MC_F_REVS_FG) ? \ 482 (uint64_t)MCREG_FIELD_F_revFG(up, AddrMaskHi) << 27 | \ 483 (uint64_t)MCREG_FIELD_F_revFG(up, AddrMaskLo) << 13 | 0x7c01fff : \ 484 (uint64_t)MCREG_FIELD_F_preF(up, AddrMaskHi) << 25 | \ 485 (uint64_t)MCREG_FIELD_F_preF(up, AddrMaskLo) << 13 | 0x1f01fff) 486 487 /* 488 * Function 2 - DRAM Controller: DRAM Bank Address Mapping Registers 489 */ 490 491 union mcreg_bankaddrmap { 492 uint32_t _val32; 493 /* 494 * Register format in family 0xf revisions E and earlier 495 */ 496 struct { 497 uint32_t cs10:4; /* 3:0 - CS1/0 */ 498 uint32_t cs32:4; /* 7:4 - CS3/2 */ 499 uint32_t cs54:4; /* 11:8 - CS5/4 */ 500 uint32_t cs76:4; /* 15:12 - CS7/6 */ 501 uint32_t reserved1:14; /* 29:16 */ 502 uint32_t BankSwizzleMode:1; /* 30:30 */ 503 uint32_t reserved2:1; /* 31:31 */ 504 } _fmt_f_preF; 505 /* 506 * Register format in family 0xf revisions F and G 507 */ 508 struct { 509 uint32_t cs10:4; /* 3:0 - CS1/0 */ 510 uint32_t cs32:4; /* 7:4 - CS3/2 */ 511 uint32_t cs54:4; /* 11:8 - CS5/4 */ 512 uint32_t cs76:4; /* 15:12 - CS7/6 */ 513 uint32_t reserved1:16; /* 31:16 */ 514 } _fmt_f_revFG; 515 /* 516 * Accessing all mode encodings as one uint16 517 */ 518 struct { 519 uint32_t allcsmodes:16; /* 15:0 */ 520 uint32_t pad:16; /* 31:16 */ 521 } _fmt_bankmodes; 522 }; 523 524 #define MC_DC_BAM_CSBANK_MASK 0x0000000f 525 #define MC_DC_BAM_CSBANK_SHIFT 4 526 527 #define MC_CSBANKMODE(up, csnum) ((up)->_fmt_bankmodes.allcsmodes >> \ 528 MC_DC_BAM_CSBANK_SHIFT * MC_CHIP_DIMMPAIR(csnum) & MC_DC_BAM_CSBANK_MASK) 529 530 /* 531 * Function 2 - DRAM Controller: DRAM Configuration Low and High 532 */ 533 534 union mcreg_dramcfg_lo { 535 uint32_t _val32; 536 /* 537 * Register format in family 0xf revisions E and earlier. 538 * Bit 7 is a BIOS ScratchBit in revs D and earlier, 539 * PwrDwnTriEn in revision E; we don't use it so 540 * we'll call it ambig1. 541 */ 542 struct { 543 uint32_t DLL_Dis:1; /* 0 */ 544 uint32_t D_DRV:1; /* 1 */ 545 uint32_t QFC_EN:1; /* 2 */ 546 uint32_t DisDqsHys:1; /* 3 */ 547 uint32_t reserved1:1; /* 4 */ 548 uint32_t Burst2Opt:1; /* 5 */ 549 uint32_t Mod64BitMux:1; /* 6 */ 550 uint32_t ambig1:1; /* 7 */ 551 uint32_t DramInit:1; /* 8 */ 552 uint32_t DualDimmEn:1; /* 9 */ 553 uint32_t DramEnable:1; /* 10 */ 554 uint32_t MemClrStatus:1; /* 11 */ 555 uint32_t ESR:1; /* 12 */ 556 uint32_t SR_S:1; /* 13 */ 557 uint32_t RdWrQByp:2; /* 15:14 */ 558 uint32_t Width128:1; /* 16 */ 559 uint32_t DimmEcEn:1; /* 17 */ 560 uint32_t UnBufDimm:1; /* 18 */ 561 uint32_t ByteEn32:1; /* 19 */ 562 uint32_t x4DIMMs:4; /* 23:20 */ 563 uint32_t DisInRcvrs:1; /* 24 */ 564 uint32_t BypMax:3; /* 27:25 */ 565 uint32_t En2T:1; /* 28 */ 566 uint32_t UpperCSMap:1; /* 29 */ 567 uint32_t PwrDownCtl:2; /* 31:30 */ 568 } _fmt_f_preF; 569 /* 570 * Register format in family 0xf revisions F and G 571 */ 572 struct { 573 uint32_t InitDram:1; /* 0 */ 574 uint32_t ExitSelfRef:1; /* 1 */ 575 uint32_t reserved1:2; /* 3:2 */ 576 uint32_t DramTerm:2; /* 5:4 */ 577 uint32_t reserved2:1; /* 6 */ 578 uint32_t DramDrvWeak:1; /* 7 */ 579 uint32_t ParEn:1; /* 8 */ 580 uint32_t SelRefRateEn:1; /* 9 */ 581 uint32_t BurstLength32:1; /* 10 */ 582 uint32_t Width128:1; /* 11 */ 583 uint32_t x4DIMMs:4; /* 15:12 */ 584 uint32_t UnBuffDimm:1; /* 16 */ 585 uint32_t reserved3:2; /* 18:17 */ 586 uint32_t DimmEccEn:1; /* 19 */ 587 uint32_t reserved4:12; /* 31:20 */ 588 } _fmt_f_revFG; 589 }; 590 591 /* 592 * Function 2 - DRAM Controller: DRAM Controller Miscellaneous Data 593 */ 594 595 union mcreg_drammisc { 596 uint32_t _val32; 597 /* 598 * Register format in family 0xf revisions F and G 599 */ 600 struct { 601 uint32_t reserved2:1; /* 0 */ 602 uint32_t DisableJitter:1; /* 1 */ 603 uint32_t RdWrQByp:2; /* 3:2 */ 604 uint32_t Mod64Mux:1; /* 4 */ 605 uint32_t DCC_EN:1; /* 5 */ 606 uint32_t ILD_lmt:3; /* 8:6 */ 607 uint32_t DramEnabled:1; /* 9 */ 608 uint32_t PwrSavingsEn:1; /* 10 */ 609 uint32_t reserved1:13; /* 23:11 */ 610 uint32_t MemClkDis:8; /* 31:24 */ 611 } _fmt_f_revFG; 612 }; 613 614 union mcreg_dramcfg_hi { 615 uint32_t _val32; 616 /* 617 * Register format in family 0xf revisions E and earlier. 618 */ 619 struct { 620 uint32_t AsyncLat:4; /* 3:0 */ 621 uint32_t reserved1:4; /* 7:4 */ 622 uint32_t RdPreamble:4; /* 11:8 */ 623 uint32_t reserved2:1; /* 12 */ 624 uint32_t MemDQDrvStren:2; /* 14:13 */ 625 uint32_t DisableJitter:1; /* 15 */ 626 uint32_t ILD_lmt:3; /* 18:16 */ 627 uint32_t DCC_EN:1; /* 19 */ 628 uint32_t MemClk:3; /* 22:20 */ 629 uint32_t reserved3:2; /* 24:23 */ 630 uint32_t MCR:1; /* 25 */ 631 uint32_t MC0_EN:1; /* 26 */ 632 uint32_t MC1_EN:1; /* 27 */ 633 uint32_t MC2_EN:1; /* 28 */ 634 uint32_t MC3_EN:1; /* 29 */ 635 uint32_t reserved4:1; /* 30 */ 636 uint32_t OddDivisorCorrect:1; /* 31 */ 637 } _fmt_f_preF; 638 /* 639 * Register format in family 0xf revisions F and G 640 */ 641 struct { 642 uint32_t MemClkFreq:3; /* 2:0 */ 643 uint32_t MemClkFreqVal:1; /* 3 */ 644 uint32_t MaxAsyncLat:4; /* 7:4 */ 645 uint32_t reserved1:4; /* 11:8 */ 646 uint32_t RDqsEn:1; /* 12 */ 647 uint32_t reserved2:1; /* 13 */ 648 uint32_t DisDramInterface:1; /* 14 */ 649 uint32_t PowerDownEn:1; /* 15 */ 650 uint32_t PowerDownMode:1; /* 16 */ 651 uint32_t FourRankSODimm:1; /* 17 */ 652 uint32_t FourRankRDimm:1; /* 18 */ 653 uint32_t reserved3:1; /* 19 */ 654 uint32_t SlowAccessMode:1; /* 20 */ 655 uint32_t reserved4:1; /* 21 */ 656 uint32_t BankSwizzleMode:1; /* 22 */ 657 uint32_t undocumented1:1; /* 23 */ 658 uint32_t DcqBypassMax:4; /* 27:24 */ 659 uint32_t FourActWindow:4; /* 31:28 */ 660 } _fmt_f_revFG; 661 }; 662 663 /* 664 * Function 3 - Miscellaneous Control: Scrub Control Register 665 */ 666 667 union mcreg_scrubctl { 668 uint32_t _val32; 669 struct { 670 uint32_t DramScrub:5; /* 4:0 */ 671 uint32_t reserved3:3; /* 7:5 */ 672 uint32_t L2Scrub:5; /* 12:8 */ 673 uint32_t reserved2:3; /* 15:13 */ 674 uint32_t DcacheScrub:5; /* 20:16 */ 675 uint32_t reserved1:11; /* 31:21 */ 676 } _fmt_cmn; 677 }; 678 679 union mcreg_dramscrublo { 680 uint32_t _val32; 681 struct { 682 uint32_t ScrubReDirEn:1; /* 0 */ 683 uint32_t reserved:5; /* 5:1 */ 684 uint32_t ScrubAddrLo:26; /* 31:6 */ 685 } _fmt_cmn; 686 }; 687 688 union mcreg_dramscrubhi { 689 uint32_t _val32; 690 struct { 691 uint32_t ScrubAddrHi:8; /* 7:0 */ 692 uint32_t reserved:24; /* 31:8 */ 693 } _fmt_cmn; 694 }; 695 696 /* 697 * Function 3 - Miscellaneous Control: On-Line Spare Control Register 698 */ 699 700 union mcreg_nbcfg { 701 uint32_t _val32; 702 /* 703 * Register format in family 0xf revisions E and earlier. 704 */ 705 struct { 706 uint32_t CpuEccErrEn:1; /* 0 */ 707 uint32_t CpuRdDatErrEn:1; /* 1 */ 708 uint32_t SyncOnUcEccEn:1; /* 2 */ 709 uint32_t SyncPktGenDis:1; /* 3 */ 710 uint32_t SyncPktPropDis:1; /* 4 */ 711 uint32_t IoMstAbortDis:1; /* 5 */ 712 uint32_t CpuErrDis:1; /* 6 */ 713 uint32_t IoErrDis:1; /* 7 */ 714 uint32_t WdogTmrDis:1; /* 8 */ 715 uint32_t WdogTmrCntSel:3; /* 11:9 */ 716 uint32_t WdogTmrBaseSel:2; /* 13:12 */ 717 uint32_t LdtLinkSel:2; /* 15:14 */ 718 uint32_t GenCrcErrByte0:1; /* 16 */ 719 uint32_t GenCrcErrByte1:1; /* 17 */ 720 uint32_t reserved1:2; /* 19:18 */ 721 uint32_t SyncOnWdogEn:1; /* 20 */ 722 uint32_t SyncOnAnyErrEn:1; /* 21 */ 723 uint32_t EccEn:1; /* 22 */ 724 uint32_t ChipKillEccEn:1; /* 23 */ 725 uint32_t IoRdDatErrEn:1; /* 24 */ 726 uint32_t DisPciCfgCpuErrRsp:1; /* 25 */ 727 uint32_t reserved2:1; /* 26 */ 728 uint32_t NbMcaToMstCpuEn:1; /* 27 */ 729 uint32_t reserved3:4; /* 31:28 */ 730 } _fmt_f_preF; 731 /* 732 * Register format in family 0xf revisions F and G 733 */ 734 struct { 735 uint32_t CpuEccErrEn:1; /* 0 */ 736 uint32_t CpuRdDatErrEn:1; /* 1 */ 737 uint32_t SyncOnUcEccEn:1; /* 2 */ 738 uint32_t SyncPktGenDis:1; /* 3 */ 739 uint32_t SyncPktPropDis:1; /* 4 */ 740 uint32_t IoMstAbortDis:1; /* 5 */ 741 uint32_t CpuErrDis:1; /* 6 */ 742 uint32_t IoErrDis:1; /* 7 */ 743 uint32_t WdogTmrDis:1; /* 8 */ 744 uint32_t WdogTmrCntSel:3; /* 11:9 */ 745 uint32_t WdogTmrBaseSel:2; /* 13:12 */ 746 uint32_t LdtLinkSel:2; /* 15:14 */ 747 uint32_t GenCrcErrByte0:1; /* 16 */ 748 uint32_t GenCrcErrByte1:1; /* 17 */ 749 uint32_t reserved1:2; /* 19:18 */ 750 uint32_t SyncOnWdogEn:1; /* 20 */ 751 uint32_t SyncOnAnyErrEn:1; /* 21 */ 752 uint32_t EccEn:1; /* 22 */ 753 uint32_t ChipKillEccEn:1; /* 23 */ 754 uint32_t IoRdDatErrEn:1; /* 24 */ 755 uint32_t DisPciCfgCpuErrRsp:1; /* 25 */ 756 uint32_t reserved2:1; /* 26 */ 757 uint32_t NbMcaToMstCpuEn:1; /* 27 */ 758 uint32_t DisTgtAbtCpuErrRsp:1; /* 28 */ 759 uint32_t DisMstAbtCpuErrRsp:1; /* 29 */ 760 uint32_t SyncOnDramAdrParErrEn:1; /* 30 */ 761 uint32_t reserved3:1; /* 31 */ 762 763 } _fmt_f_revFG; 764 }; 765 766 /* 767 * Function 3 - Miscellaneous Control: On-Line Spare Control Register 768 */ 769 770 union mcreg_sparectl { 771 uint32_t _val32; 772 /* 773 * Register format in family 0xf revisions F and G 774 */ 775 struct { 776 uint32_t SwapEn:1; /* 0 */ 777 uint32_t SwapDone:1; /* 1 */ 778 uint32_t reserved1:2; /* 3:2 */ 779 uint32_t BadDramCs:3; /* 6:4 */ 780 uint32_t reserved2:5; /* 11:7 */ 781 uint32_t SwapDoneInt:2; /* 13:12 */ 782 uint32_t EccErrInt:2; /* 15:14 */ 783 uint32_t EccErrCntDramCs:3; /* 18:16 */ 784 uint32_t reserved3:1; /* 19 */ 785 uint32_t EccErrCntDramChan:1; /* 20 */ 786 uint32_t reserved4:2; /* 22:21 */ 787 uint32_t EccErrCntWrEn:1; /* 23 */ 788 uint32_t EccErrCnt:4; /* 27:24 */ 789 uint32_t reserved5:4; /* 31:28 */ 790 } _fmt_f_revFG; 791 /* 792 * Regiser format in family 0x10 revisions A and B 793 */ 794 struct { 795 uint32_t SwapEn0:1; /* 0 */ 796 uint32_t SwapDone0:1; /* 1 */ 797 uint32_t SwapEn1:1; /* 2 */ 798 uint32_t SwapDone1:1; /* 3 */ 799 uint32_t BadDramCs0:3; /* 6:4 */ 800 uint32_t reserved1:1; /* 7 */ 801 uint32_t BadDramCs1:3; /* 10:8 */ 802 uint32_t reserved2:1; /* 11 */ 803 uint32_t SwapDoneInt:2; /* 13:12 */ 804 uint32_t EccErrInt:2; /* 15:14 */ 805 uint32_t EccErrCntDramCs:4; /* 19:16 */ 806 uint32_t EccErrCntDramChan:2; /* 21:20 */ 807 uint32_t reserved4:1; /* 22 */ 808 uint32_t EccErrCntWrEn:1; /* 23 */ 809 uint32_t EccErrCnt:4; /* 27:24 */ 810 uint32_t LvtOffset:4; /* 31:28 */ 811 } _fmt_10_revAB; 812 }; 813 814 /* 815 * Since the NB is on-chip some registers are also accessible as MSRs. 816 * We will represent such registers as bitfields as in the 32-bit PCI 817 * registers above, with the restriction that we must compile for 32-bit 818 * kernels and so 64-bit bitfields cannot be used. 819 */ 820 821 #define _MCMSR_FIELD(up, revsuffix, field) ((up)->_fmt_##revsuffix.field) 822 823 #define MCMSR_VAL(up) ((up)->_val64) 824 825 #define MCMSR_FIELD_CMN(up, field) _MCMSR_FIELD(up, cmn, field) 826 #define MCMSR_FIELD_F_preF(up, field) _MCMSR_FIELD(up, f_preF, field) 827 #define MCMSR_FIELD_F_revFG(up, field) _MCMSR_FIELD(up, f_revFG, field) 828 #define MCMSR_FIELD_10_revAB(up, field) _MCMSR_FIELD(up, 10_revAB, field) 829 830 /* 831 * The NB MISC registers. On family 0xf rev F this was introduced with 832 * a 12-bit ECC error count of all ECC errors observed on this memory- 833 * controller (regardless of channel or chip-select) and the ability to 834 * raise an interrupt or SMI on overflow. In family 0x10 it has a similar 835 * purpose, but the register is is split into 4 misc registers 836 * MC4_MISC{0,1,2,3} accessible via both MSRs and PCI config space; 837 * they perform thresholding for dram, l3, HT errors. 838 */ 839 840 union mcmsr_nbmisc { 841 uint64_t _val64; 842 /* 843 * MSR format in family 0xf revision F and later 844 */ 845 struct { 846 /* 847 * Lower 32 bits 848 */ 849 struct { 850 uint32_t _reserved; /* 31:0 */ 851 } _mcimisc_lo; 852 /* 853 * Upper 32 bits 854 */ 855 struct { 856 uint32_t _ErrCount:12; /* 43:32 */ 857 uint32_t _reserved1:4; /* 47:44 */ 858 uint32_t _Ovrflw:1; /* 48 */ 859 uint32_t _IntType:2; /* 50:49 */ 860 uint32_t _CntEn:1; /* 51 */ 861 uint32_t _LvtOff:4; /* 55:52 */ 862 uint32_t _reserved2:5; /* 60:56 */ 863 uint32_t _Locked:1; /* 61 */ 864 uint32_t _CntP:1; /* 62 */ 865 uint32_t _Valid:1; /* 63 */ 866 } _mcimisc_hi; 867 } _fmt_f_revFG; 868 /* 869 * MSR format in family 0x10 revisions A and B 870 */ 871 struct { 872 /* 873 * Lower 32 bits 874 */ 875 struct { 876 uint32_t _reserved:24; /* 23:0 */ 877 uint32_t _BlkPtr:8; /* 31:24 */ 878 } _mcimisc_lo; 879 /* 880 * Upper 32 bits 881 */ 882 struct { 883 uint32_t _ErrCnt:12; /* 43:32 */ 884 uint32_t _reserved1:4; /* 47:44 */ 885 uint32_t _Ovrflw:1; /* 48 */ 886 uint32_t _IntType:2; /* 50:49 */ 887 uint32_t _CntEn:1; /* 51 */ 888 uint32_t _LvtOff:4; /* 55:52 */ 889 uint32_t _reserved2:5; /* 60:56 */ 890 uint32_t _Locked:1; /* 61 */ 891 uint32_t _CntP:1; /* 62 */ 892 uint32_t _Valid:1; /* 63 */ 893 894 } _mcimisc_hi; 895 } _fmt_10_revAB; 896 }; 897 898 #define mcmisc_BlkPtr _mcimisc_lo._BlkPtr 899 #define mcmisc_ErrCount _mcimisc_hi._ErrCount 900 #define mcmisc_Ovrflw _mcimisc_hi._Ovrflw 901 #define mcmisc_IntType _mcimisc_hi._IntType 902 #define mcmisc_CntEn _mcimisc_hi._CntEn 903 #define mcmisc_LvtOff _mcimisc_hi._LvtOff 904 #define mcmisc_Locked _mcimisc_hi._Locked 905 #define mcmisc_CntP _mcimisc_hi._CntP 906 #define mcmisc_Valid _mcimisc_hi._Valid 907 908 #endif /* _BIT_FIELDS_LTOH */ 909 910 #ifdef __cplusplus 911 } 912 #endif 913 914 #endif /* _MC_AMD_H */ 915