1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Performance Counter Back-End for AMD Opteron and AMD Athlon 64 processors. 30 */ 31 32 #include <sys/cpuvar.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/cpc_pcbe.h> 36 #include <sys/kmem.h> 37 #include <sys/sdt.h> 38 #include <sys/modctl.h> 39 #include <sys/errno.h> 40 #include <sys/debug.h> 41 #include <sys/archsystm.h> 42 #include <sys/x86_archext.h> 43 #include <sys/privregs.h> 44 #include <sys/ddi.h> 45 #include <sys/sunddi.h> 46 47 static int opt_pcbe_init(void); 48 static uint_t opt_pcbe_ncounters(void); 49 static const char *opt_pcbe_impl_name(void); 50 static const char *opt_pcbe_cpuref(void); 51 static char *opt_pcbe_list_events(uint_t picnum); 52 static char *opt_pcbe_list_attrs(void); 53 static uint64_t opt_pcbe_event_coverage(char *event); 54 static uint64_t opt_pcbe_overflow_bitmap(void); 55 static int opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, 56 uint32_t flags, uint_t nattrs, kcpc_attr_t *attrs, void **data, 57 void *token); 58 static void opt_pcbe_program(void *token); 59 static void opt_pcbe_allstop(void); 60 static void opt_pcbe_sample(void *token); 61 static void opt_pcbe_free(void *config); 62 63 static pcbe_ops_t opt_pcbe_ops = { 64 PCBE_VER_1, 65 CPC_CAP_OVERFLOW_INTERRUPT, 66 opt_pcbe_ncounters, 67 opt_pcbe_impl_name, 68 opt_pcbe_cpuref, 69 opt_pcbe_list_events, 70 opt_pcbe_list_attrs, 71 opt_pcbe_event_coverage, 72 opt_pcbe_overflow_bitmap, 73 opt_pcbe_configure, 74 opt_pcbe_program, 75 opt_pcbe_allstop, 76 opt_pcbe_sample, 77 opt_pcbe_free 78 }; 79 80 /* 81 * Define offsets and masks for the fields in the Performance 82 * Event-Select (PES) registers. 83 */ 84 #define OPT_PES_CMASK_SHIFT 24 85 #define OPT_PES_CMASK_MASK 0xFF 86 #define OPT_PES_INV_SHIFT 23 87 #define OPT_PES_ENABLE_SHIFT 22 88 #define OPT_PES_INT_SHIFT 20 89 #define OPT_PES_PC_SHIFT 19 90 #define OPT_PES_EDGE_SHIFT 18 91 #define OPT_PES_OS_SHIFT 17 92 #define OPT_PES_USR_SHIFT 16 93 #define OPT_PES_UMASK_SHIFT 8 94 #define OPT_PES_UMASK_MASK 0xFF 95 96 #define OPT_PES_INV (1 << OPT_PES_INV_SHIFT) 97 #define OPT_PES_ENABLE (1 << OPT_PES_ENABLE_SHIFT) 98 #define OPT_PES_INT (1 << OPT_PES_INT_SHIFT) 99 #define OPT_PES_PC (1 << OPT_PES_PC_SHIFT) 100 #define OPT_PES_EDGE (1 << OPT_PES_EDGE_SHIFT) 101 #define OPT_PES_OS (1 << OPT_PES_OS_SHIFT) 102 #define OPT_PES_USR (1 << OPT_PES_USR_SHIFT) 103 104 typedef struct _opt_pcbe_config { 105 uint8_t opt_picno; /* Counter number: 0, 1, 2, or 3 */ 106 uint64_t opt_evsel; /* Event Selection register */ 107 uint64_t opt_rawpic; /* Raw counter value */ 108 } opt_pcbe_config_t; 109 110 opt_pcbe_config_t nullcfgs[4] = { 111 { 0, 0, 0 }, 112 { 1, 0, 0 }, 113 { 2, 0, 0 }, 114 { 3, 0, 0 } 115 }; 116 117 typedef struct _opt_event { 118 char *name; 119 uint8_t emask; /* Event mask setting */ 120 uint8_t umask_valid; /* Mask of unreserved UNIT_MASK bits */ 121 } opt_event_t; 122 123 /* 124 * Base MSR addresses for the PerfEvtSel registers and the counters themselves. 125 * Add counter number to base address to get corresponding MSR address. 126 */ 127 #define PES_BASE_ADDR 0xC0010000 128 #define PIC_BASE_ADDR 0xC0010004 129 130 #define MASK48 0xFFFFFFFFFFFF 131 132 #define EV_END {NULL, 0, 0} 133 134 static opt_event_t opt_events[] = { 135 { "FP_dispatched_fpu_ops", 0x0, 0x1F }, 136 { "FP_cycles_no_fpu_ops_retired", 0x1, 0x0 }, 137 { "FP_dispatched_fpu_ops_ff", 0x2, 0x0 }, 138 { "LS_seg_reg_load", 0x20, 0x7F }, 139 { "LS_uarch_resync_self_modify", 0x21, 0x0 }, 140 { "LS_uarch_resync_snoop", 0x22, 0x0 }, 141 { "LS_buffer_2_full", 0x23, 0x0 }, 142 { "LS_locked_operation", 0x24, 0x7 }, 143 { "LS_uarch_late_cancel_op", 0x25, 0x0 }, 144 { "LS_retired_cflush", 0x26, 0x0 }, 145 { "LS_retired_cpuid", 0x27, 0x0 }, 146 { "DC_access", 0x40, 0x0 }, 147 { "DC_miss", 0x41, 0x0 }, 148 { "DC_refill_from_L2", 0x42, 0x1F }, 149 { "DC_refill_from_system", 0x43, 0x1F }, 150 { "DC_copyback", 0x44, 0x1F }, 151 { "DC_dtlb_L1_miss_L2_hit", 0x45, 0x0 }, 152 { "DC_dtlb_L1_miss_L2_miss", 0x46, 0x0 }, 153 { "DC_misaligned_data_ref", 0x47, 0x0 }, 154 { "DC_uarch_late_cancel_access", 0x48, 0x0 }, 155 { "DC_uarch_early_cancel_access", 0x49, 0x0 }, 156 { "DC_1bit_ecc_error_found", 0x4A, 0x3 }, 157 { "DC_dispatched_prefetch_instr", 0x4B, 0x7 }, 158 { "DC_dcache_accesses_by_locks", 0x4C, 0x3 }, 159 { "BU_memory_requests", 0x65, 0x83}, 160 { "BU_data_prefetch", 0x67, 0x3 }, 161 { "BU_system_read_responses", 0x6C, 0x7 }, 162 { "BU_quadwords_written_to_system", 0x6D, 0x1 }, 163 { "BU_cpu_clk_unhalted", 0x76, 0x0 }, 164 { "BU_internal_L2_req", 0x7D, 0x1F }, 165 { "BU_fill_req_missed_L2", 0x7E, 0x7 }, 166 { "BU_fill_into_L2", 0x7F, 0x3 }, 167 { "IC_fetch", 0x80, 0x0 }, 168 { "IC_miss", 0x81, 0x0 }, 169 { "IC_refill_from_L2", 0x82, 0x0 }, 170 { "IC_refill_from_system", 0x83, 0x0 }, 171 { "IC_itlb_L1_miss_L2_hit", 0x84, 0x0 }, 172 { "IC_itlb_L1_miss_L2_miss", 0x85, 0x0 }, 173 { "IC_uarch_resync_snoop", 0x86, 0x0 }, 174 { "IC_instr_fetch_stall", 0x87, 0x0 }, 175 { "IC_return_stack_hit", 0x88, 0x0 }, 176 { "IC_return_stack_overflow", 0x89, 0x0 }, 177 { "FR_retired_x86_instr_w_excp_intr", 0xC0, 0x0 }, 178 { "FR_retired_uops", 0xC1, 0x0 }, 179 { "FR_retired_branches_w_excp_intr", 0xC2, 0x0 }, 180 { "FR_retired_branches_mispred", 0xC3, 0x0 }, 181 { "FR_retired_taken_branches", 0xC4, 0x0 }, 182 { "FR_retired_taken_branches_mispred", 0xC5, 0x0 }, 183 { "FR_retired_far_ctl_transfer", 0xC6, 0x0 }, 184 { "FR_retired_resyncs", 0xC7, 0x0 }, 185 { "FR_retired_near_rets", 0xC8, 0x0 }, 186 { "FR_retired_near_rets_mispred", 0xC9, 0x0 }, 187 { "FR_retired_taken_branches_mispred_addr_miscomp", 0xCA, 0x0 }, 188 { "FR_retired_fpu_instr", 0xCB, 0xF }, 189 { "FR_retired_fastpath_double_op_instr", 0xCC, 0x7 }, 190 { "FR_intr_masked_cycles", 0xCD, 0x0 }, 191 { "FR_intr_masked_while_pending_cycles", 0xCE, 0x0 }, 192 { "FR_taken_hardware_intrs", 0xCF, 0x0 }, 193 { "FR_nothing_to_dispatch", 0xD0, 0x0 }, 194 { "FR_dispatch_stalls", 0xD1, 0x0 }, 195 { "FR_dispatch_stall_branch_abort_to_retire", 0xD2, 0x0 }, 196 { "FR_dispatch_stall_serialization", 0xD3, 0x0 }, 197 { "FR_dispatch_stall_segment_load", 0xD4, 0x0 }, 198 { "FR_dispatch_stall_reorder_buffer_full", 0xD5, 0x0 }, 199 { "FR_dispatch_stall_resv_stations_full", 0xD6, 0x0 }, 200 { "FR_dispatch_stall_fpu_full", 0xD7, 0x0 }, 201 { "FR_dispatch_stall_ls_full", 0xD8, 0x0 }, 202 { "FR_dispatch_stall_waiting_all_quiet", 0xD9, 0x0 }, 203 { "FR_dispatch_stall_far_ctl_trsfr_resync_branch_pend", 0xDA, 0x0 }, 204 { "FR_fpu_exception", 0xDB, 0xF }, 205 { "FR_num_brkpts_dr0", 0xDC, 0x0 }, 206 { "FR_num_brkpts_dr1", 0xDD, 0x0 }, 207 { "FR_num_brkpts_dr2", 0xDE, 0x0 }, 208 { "FR_num_brkpts_dr3", 0xDF, 0x0 }, 209 { "NB_mem_ctrlr_page_access", 0xE0, 0x7 }, 210 { "NB_mem_ctrlr_page_table_overflow", 0xE1, 0x0 }, 211 { "NB_mem_ctrlr_dram_cmd_slots_missed", 0xE2, 0x0 }, 212 { "NB_mem_ctrlr_turnaround", 0xE3, 0x7 }, 213 { "NB_mem_ctrlr_bypass_counter_saturation", 0xE4, 0xF }, 214 { "NB_sized_blocks_Rev_D", 0xE5, 0x3C}, 215 { "NB_ECC_errors", 0xE8, 0x80}, 216 { "NB_cpu_io_to_mem_io_Rev_E", 0xE9, 0xFF}, 217 { "NB_cache_block_commands_Rev_E", 0xEA, 0x3D}, 218 { "NB_sized_commands", 0xEB, 0x7F }, 219 { "NB_probe_result", 0xEC, 0x7F}, 220 { "NB_gart_events", 0xEE, 0x7 }, 221 { "NB_ht_bus0_bandwidth", 0xF6, 0xF }, 222 { "NB_ht_bus1_bandwidth", 0xF7, 0xF }, 223 { "NB_ht_bus2_bandwidth", 0xF8, 0xF }, 224 EV_END 225 }; 226 227 static char *evlist; 228 static size_t evlist_sz; 229 230 #define BITS(v, u, l) \ 231 (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1)) 232 233 #define OPTERON_FAMILY 15 234 235 static int 236 opt_pcbe_init(void) 237 { 238 opt_event_t *evp; 239 240 /* 241 * Make sure this really _is_ an Opteron or Athlon 64 system. The kernel 242 * loads this module based on its name in the module directory, but it 243 * could have been renamed. 244 */ 245 if (cpuid_getvendor(CPU) != X86_VENDOR_AMD || 246 cpuid_getfamily(CPU) != OPTERON_FAMILY) 247 return (-1); 248 249 /* 250 * Construct event list. 251 * 252 * First pass: Calculate size needed. We'll need an additional byte 253 * for the NULL pointer during the last strcat. 254 * 255 * Second pass: Copy strings. 256 */ 257 for (evp = opt_events; evp->name != NULL; evp++) 258 evlist_sz += strlen(evp->name) + 1; 259 260 evlist = kmem_alloc(evlist_sz + 1, KM_SLEEP); 261 evlist[0] = '\0'; 262 263 for (evp = opt_events; evp->name != NULL; evp++) { 264 (void) strcat(evlist, evp->name); 265 (void) strcat(evlist, ","); 266 } 267 /* 268 * Remove trailing comma. 269 */ 270 evlist[evlist_sz - 1] = '\0'; 271 272 return (0); 273 } 274 275 static uint_t 276 opt_pcbe_ncounters(void) 277 { 278 return (4); 279 } 280 281 static const char * 282 opt_pcbe_impl_name(void) 283 { 284 return ("AMD Opteron & Athlon64"); 285 } 286 287 static const char * 288 opt_pcbe_cpuref(void) 289 { 290 return ("See Chapter 10 of the \"BIOS and Kernel Developer's Guide " 291 "for the AMD Athlon 64 and AMD Opteron Processors,\" " 292 "AMD publication #26094"); 293 } 294 295 /*ARGSUSED*/ 296 static char * 297 opt_pcbe_list_events(uint_t picnum) 298 { 299 return (evlist); 300 } 301 302 static char * 303 opt_pcbe_list_attrs(void) 304 { 305 return ("edge,pc,inv,cmask,umask"); 306 } 307 308 /*ARGSUSED*/ 309 static uint64_t 310 opt_pcbe_event_coverage(char *event) 311 { 312 /* 313 * Fortunately, all counters can count all events. 314 */ 315 return (0xF); 316 } 317 318 static uint64_t 319 opt_pcbe_overflow_bitmap(void) 320 { 321 /* 322 * Unfortunately, this chip cannot detect which counter overflowed, so 323 * we must act as if they all did. 324 */ 325 return (0xF); 326 } 327 328 static opt_event_t * 329 find_event(char *name) 330 { 331 opt_event_t *evp; 332 333 for (evp = opt_events; evp->name != NULL; evp++) 334 if (strcmp(name, evp->name) == 0) 335 return (evp); 336 337 return (NULL); 338 } 339 340 /*ARGSUSED*/ 341 static int 342 opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, uint32_t flags, 343 uint_t nattrs, kcpc_attr_t *attrs, void **data, void *token) 344 { 345 opt_pcbe_config_t *cfg; 346 opt_event_t *evp; 347 opt_event_t ev_raw = { "raw", 0, 0xFF }; 348 int i; 349 uint32_t evsel = 0; 350 351 /* 352 * If we've been handed an existing configuration, we need only preset 353 * the counter value. 354 */ 355 if (*data != NULL) { 356 cfg = *data; 357 cfg->opt_rawpic = preset & MASK48; 358 return (0); 359 } 360 361 if (picnum >= 4) 362 return (CPC_INVALID_PICNUM); 363 364 if ((evp = find_event(event)) == NULL) { 365 long tmp; 366 367 /* 368 * If ddi_strtol() likes this event, use it as a raw event code. 369 */ 370 if (ddi_strtol(event, NULL, 0, &tmp) != 0) 371 return (CPC_INVALID_EVENT); 372 373 ev_raw.emask = tmp; 374 evp = &ev_raw; 375 } 376 377 evsel |= evp->emask; 378 379 if (flags & CPC_COUNT_USER) 380 evsel |= OPT_PES_USR; 381 if (flags & CPC_COUNT_SYSTEM) 382 evsel |= OPT_PES_OS; 383 if (flags & CPC_OVF_NOTIFY_EMT) 384 evsel |= OPT_PES_INT; 385 386 for (i = 0; i < nattrs; i++) { 387 if (strcmp(attrs[i].ka_name, "edge") == 0) { 388 if (attrs[i].ka_val != 0) 389 evsel |= OPT_PES_EDGE; 390 } else if (strcmp(attrs[i].ka_name, "pc") == 0) { 391 if (attrs[i].ka_val != 0) 392 evsel |= OPT_PES_PC; 393 } else if (strcmp(attrs[i].ka_name, "inv") == 0) { 394 if (attrs[i].ka_val != 0) 395 evsel |= OPT_PES_INV; 396 } else if (strcmp(attrs[i].ka_name, "cmask") == 0) { 397 if ((attrs[i].ka_val | OPT_PES_CMASK_MASK) != 398 OPT_PES_CMASK_MASK) 399 return (CPC_ATTRIBUTE_OUT_OF_RANGE); 400 evsel |= attrs[i].ka_val << OPT_PES_CMASK_SHIFT; 401 } else if (strcmp(attrs[i].ka_name, "umask") == 0) { 402 if ((attrs[i].ka_val | evp->umask_valid) != 403 evp->umask_valid) 404 return (CPC_ATTRIBUTE_OUT_OF_RANGE); 405 evsel |= attrs[i].ka_val << OPT_PES_UMASK_SHIFT; 406 } else 407 return (CPC_INVALID_ATTRIBUTE); 408 } 409 410 cfg = kmem_alloc(sizeof (*cfg), KM_SLEEP); 411 412 cfg->opt_picno = picnum; 413 cfg->opt_evsel = evsel; 414 cfg->opt_rawpic = preset & MASK48; 415 416 *data = cfg; 417 return (0); 418 } 419 420 static void 421 opt_pcbe_program(void *token) 422 { 423 opt_pcbe_config_t *cfgs[4] = { &nullcfgs[0], &nullcfgs[1], 424 &nullcfgs[2], &nullcfgs[3] }; 425 opt_pcbe_config_t *pcfg = NULL; 426 int i; 427 uint32_t curcr4 = getcr4(); 428 429 /* 430 * Allow nonprivileged code to read the performance counters if desired. 431 */ 432 if (kcpc_allow_nonpriv(token)) 433 setcr4(curcr4 | CR4_PCE); 434 else 435 setcr4(curcr4 & ~CR4_PCE); 436 437 /* 438 * Query kernel for all configs which will be co-programmed. 439 */ 440 do { 441 pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, NULL); 442 443 if (pcfg != NULL) { 444 ASSERT(pcfg->opt_picno < 4); 445 cfgs[pcfg->opt_picno] = pcfg; 446 } 447 } while (pcfg != NULL); 448 449 /* 450 * Program in two loops. The first configures and presets the counter, 451 * and the second loop enables the counters. This ensures that the 452 * counters are all enabled as closely together in time as possible. 453 */ 454 455 for (i = 0; i < 4; i++) { 456 wrmsr(PES_BASE_ADDR + i, cfgs[i]->opt_evsel); 457 wrmsr(PIC_BASE_ADDR + i, cfgs[i]->opt_rawpic); 458 } 459 460 for (i = 0; i < 4; i++) { 461 wrmsr(PES_BASE_ADDR + i, cfgs[i]->opt_evsel | 462 (uint64_t)(uintptr_t)OPT_PES_ENABLE); 463 } 464 } 465 466 static void 467 opt_pcbe_allstop(void) 468 { 469 int i; 470 471 for (i = 0; i < 4; i++) 472 wrmsr(PES_BASE_ADDR + i, 0ULL); 473 474 /* 475 * Disable non-privileged access to the counter registers. 476 */ 477 setcr4((uint32_t)getcr4() & ~CR4_PCE); 478 } 479 480 static void 481 opt_pcbe_sample(void *token) 482 { 483 opt_pcbe_config_t *cfgs[4] = { NULL, NULL, NULL, NULL }; 484 opt_pcbe_config_t *pcfg = NULL; 485 int i; 486 uint64_t curpic[4]; 487 uint64_t *addrs[4]; 488 uint64_t *tmp; 489 int64_t diff; 490 491 for (i = 0; i < 4; i++) 492 curpic[i] = rdmsr(PIC_BASE_ADDR + i); 493 494 /* 495 * Query kernel for all configs which are co-programmed. 496 */ 497 do { 498 pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, &tmp); 499 500 if (pcfg != NULL) { 501 ASSERT(pcfg->opt_picno < 4); 502 cfgs[pcfg->opt_picno] = pcfg; 503 addrs[pcfg->opt_picno] = tmp; 504 } 505 } while (pcfg != NULL); 506 507 for (i = 0; i < 4; i++) { 508 if (cfgs[i] == NULL) 509 continue; 510 511 diff = (curpic[i] - cfgs[i]->opt_rawpic) & MASK48; 512 *addrs[i] += diff; 513 DTRACE_PROBE4(opt__pcbe__sample, int, i, uint64_t, *addrs[i], 514 uint64_t, curpic[i], uint64_t, cfgs[i]->opt_rawpic); 515 cfgs[i]->opt_rawpic = *addrs[i] & MASK48; 516 } 517 } 518 519 static void 520 opt_pcbe_free(void *config) 521 { 522 kmem_free(config, sizeof (opt_pcbe_config_t)); 523 } 524 525 526 static struct modlpcbe modlpcbe = { 527 &mod_pcbeops, 528 "AMD Performance Counters v%I%", 529 &opt_pcbe_ops 530 }; 531 532 static struct modlinkage modl = { 533 MODREV_1, 534 &modlpcbe, 535 }; 536 537 int 538 _init(void) 539 { 540 int ret; 541 542 if (opt_pcbe_init() != 0) 543 return (ENOTSUP); 544 545 if ((ret = mod_install(&modl)) != 0) 546 kmem_free(evlist, evlist_sz + 1); 547 548 return (ret); 549 } 550 551 int 552 _fini(void) 553 { 554 int ret; 555 556 if ((ret = mod_remove(&modl)) == 0) 557 kmem_free(evlist, evlist_sz + 1); 558 return (ret); 559 } 560 561 int 562 _info(struct modinfo *mi) 563 { 564 return (mod_info(&modl, mi)); 565 } 566