1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2006 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 /* 29 * Performance Counter Back-End for AMD Opteron and AMD Athlon 64 processors. 30 */ 31 32 #include <sys/cpuvar.h> 33 #include <sys/param.h> 34 #include <sys/systm.h> 35 #include <sys/cpc_pcbe.h> 36 #include <sys/kmem.h> 37 #include <sys/sdt.h> 38 #include <sys/modctl.h> 39 #include <sys/errno.h> 40 #include <sys/debug.h> 41 #include <sys/archsystm.h> 42 #include <sys/x86_archext.h> 43 #include <sys/privregs.h> 44 45 static int opt_pcbe_init(void); 46 static uint_t opt_pcbe_ncounters(void); 47 static const char *opt_pcbe_impl_name(void); 48 static const char *opt_pcbe_cpuref(void); 49 static char *opt_pcbe_list_events(uint_t picnum); 50 static char *opt_pcbe_list_attrs(void); 51 static uint64_t opt_pcbe_event_coverage(char *event); 52 static uint64_t opt_pcbe_overflow_bitmap(void); 53 static int opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, 54 uint32_t flags, uint_t nattrs, kcpc_attr_t *attrs, void **data, 55 void *token); 56 static void opt_pcbe_program(void *token); 57 static void opt_pcbe_allstop(void); 58 static void opt_pcbe_sample(void *token); 59 static void opt_pcbe_free(void *config); 60 61 static pcbe_ops_t opt_pcbe_ops = { 62 PCBE_VER_1, 63 CPC_CAP_OVERFLOW_INTERRUPT, 64 opt_pcbe_ncounters, 65 opt_pcbe_impl_name, 66 opt_pcbe_cpuref, 67 opt_pcbe_list_events, 68 opt_pcbe_list_attrs, 69 opt_pcbe_event_coverage, 70 opt_pcbe_overflow_bitmap, 71 opt_pcbe_configure, 72 opt_pcbe_program, 73 opt_pcbe_allstop, 74 opt_pcbe_sample, 75 opt_pcbe_free 76 }; 77 78 /* 79 * Define offsets and masks for the fields in the Performance 80 * Event-Select (PES) registers. 81 */ 82 #define OPT_PES_CMASK_SHIFT 24 83 #define OPT_PES_CMASK_MASK 0xFF 84 #define OPT_PES_INV_SHIFT 23 85 #define OPT_PES_ENABLE_SHIFT 22 86 #define OPT_PES_INT_SHIFT 20 87 #define OPT_PES_PC_SHIFT 19 88 #define OPT_PES_EDGE_SHIFT 18 89 #define OPT_PES_OS_SHIFT 17 90 #define OPT_PES_USR_SHIFT 16 91 #define OPT_PES_UMASK_SHIFT 8 92 #define OPT_PES_UMASK_MASK 0xFF 93 94 #define OPT_PES_INV (1 << OPT_PES_INV_SHIFT) 95 #define OPT_PES_ENABLE (1 << OPT_PES_ENABLE_SHIFT) 96 #define OPT_PES_INT (1 << OPT_PES_INT_SHIFT) 97 #define OPT_PES_PC (1 << OPT_PES_PC_SHIFT) 98 #define OPT_PES_EDGE (1 << OPT_PES_EDGE_SHIFT) 99 #define OPT_PES_OS (1 << OPT_PES_OS_SHIFT) 100 #define OPT_PES_USR (1 << OPT_PES_USR_SHIFT) 101 102 typedef struct _opt_pcbe_config { 103 uint8_t opt_picno; /* Counter number: 0, 1, 2, or 3 */ 104 uint64_t opt_evsel; /* Event Selection register */ 105 uint64_t opt_rawpic; /* Raw counter value */ 106 } opt_pcbe_config_t; 107 108 opt_pcbe_config_t nullcfgs[4] = { 109 { 0, 0, 0 }, 110 { 1, 0, 0 }, 111 { 2, 0, 0 }, 112 { 3, 0, 0 } 113 }; 114 115 typedef struct _opt_event { 116 char *name; 117 uint8_t emask; /* Event mask setting */ 118 uint8_t umask_valid; /* Mask of unreserved UNIT_MASK bits */ 119 } opt_event_t; 120 121 /* 122 * Base MSR addresses for the PerfEvtSel registers and the counters themselves. 123 * Add counter number to base address to get corresponding MSR address. 124 */ 125 #define PES_BASE_ADDR 0xC0010000 126 #define PIC_BASE_ADDR 0xC0010004 127 128 #define MASK48 0xFFFFFFFFFFFF 129 130 #define EV_END {NULL, 0, 0} 131 132 static opt_event_t opt_events[] = { 133 { "FP_dispatched_fpu_ops", 0x0, 0x1F }, 134 { "FP_cycles_no_fpu_ops_retired", 0x1, 0x0 }, 135 { "FP_dispatched_fpu_ops_ff", 0x2, 0x0 }, 136 { "LS_seg_reg_load", 0x20, 0x7F }, 137 { "LS_uarch_resync_self_modify", 0x21, 0x0 }, 138 { "LS_uarch_resync_snoop", 0x22, 0x0 }, 139 { "LS_buffer_2_full", 0x23, 0x0 }, 140 { "LS_locked_operation", 0x24, 0x7 }, 141 { "LS_uarch_late_cancel_op", 0x25, 0x0 }, 142 { "LS_retired_cflush", 0x26, 0x0 }, 143 { "LS_retired_cpuid", 0x27, 0x0 }, 144 { "DC_access", 0x40, 0x0 }, 145 { "DC_miss", 0x41, 0x0 }, 146 { "DC_refill_from_L2", 0x42, 0x1F }, 147 { "DC_refill_from_system", 0x43, 0x1F }, 148 { "DC_copyback", 0x44, 0x1F }, 149 { "DC_dtlb_L1_miss_L2_hit", 0x45, 0x0 }, 150 { "DC_dtlb_L1_miss_L2_miss", 0x46, 0x0 }, 151 { "DC_misaligned_data_ref", 0x47, 0x0 }, 152 { "DC_uarch_late_cancel_access", 0x48, 0x0 }, 153 { "DC_uarch_early_cancel_access", 0x49, 0x0 }, 154 { "DC_1bit_ecc_error_found", 0x4A, 0x3 }, 155 { "DC_dispatched_prefetch_instr", 0x4B, 0x7 }, 156 { "DC_dcache_accesses_by_locks", 0x4C, 0x3 }, 157 { "BU_memory_requests", 0x65, 0x83}, 158 { "BU_data_prefetch", 0x67, 0x3 }, 159 { "BU_system_read_responses", 0x6C, 0x7 }, 160 { "BU_quadwords_written_to_system", 0x6D, 0x1 }, 161 { "BU_cpu_clk_unhalted", 0x76, 0x0 }, 162 { "BU_internal_L2_req", 0x7D, 0x1F }, 163 { "BU_fill_req_missed_L2", 0x7E, 0x7 }, 164 { "BU_fill_into_L2", 0x7F, 0x3 }, 165 { "IC_fetch", 0x80, 0x0 }, 166 { "IC_miss", 0x81, 0x0 }, 167 { "IC_refill_from_L2", 0x82, 0x0 }, 168 { "IC_refill_from_system", 0x83, 0x0 }, 169 { "IC_itlb_L1_miss_L2_hit", 0x84, 0x0 }, 170 { "IC_itlb_L1_miss_L2_miss", 0x85, 0x0 }, 171 { "IC_uarch_resync_snoop", 0x86, 0x0 }, 172 { "IC_instr_fetch_stall", 0x87, 0x0 }, 173 { "IC_return_stack_hit", 0x88, 0x0 }, 174 { "IC_return_stack_overflow", 0x89, 0x0 }, 175 { "FR_retired_x86_instr_w_excp_intr", 0xC0, 0x0 }, 176 { "FR_retired_uops", 0xC1, 0x0 }, 177 { "FR_retired_branches_w_excp_intr", 0xC2, 0x0 }, 178 { "FR_retired_branches_mispred", 0xC3, 0x0 }, 179 { "FR_retired_taken_branches", 0xC4, 0x0 }, 180 { "FR_retired_taken_branches_mispred", 0xC5, 0x0 }, 181 { "FR_retired_far_ctl_transfer", 0xC6, 0x0 }, 182 { "FR_retired_resyncs", 0xC7, 0x0 }, 183 { "FR_retired_near_rets", 0xC8, 0x0 }, 184 { "FR_retired_near_rets_mispred", 0xC9, 0x0 }, 185 { "FR_retired_taken_branches_mispred_addr_miscomp", 0xCA, 0x0 }, 186 { "FR_retired_fpu_instr", 0xCB, 0xF }, 187 { "FR_retired_fastpath_double_op_instr", 0xCC, 0x7 }, 188 { "FR_intr_masked_cycles", 0xCD, 0x0 }, 189 { "FR_intr_masked_while_pending_cycles", 0xCE, 0x0 }, 190 { "FR_taken_hardware_intrs", 0xCF, 0x0 }, 191 { "FR_nothing_to_dispatch", 0xD0, 0x0 }, 192 { "FR_dispatch_stalls", 0xD1, 0x0 }, 193 { "FR_dispatch_stall_branch_abort_to_retire", 0xD2, 0x0 }, 194 { "FR_dispatch_stall_serialization", 0xD3, 0x0 }, 195 { "FR_dispatch_stall_segment_load", 0xD4, 0x0 }, 196 { "FR_dispatch_stall_reorder_buffer_full", 0xD5, 0x0 }, 197 { "FR_dispatch_stall_resv_stations_full", 0xD6, 0x0 }, 198 { "FR_dispatch_stall_fpu_full", 0xD7, 0x0 }, 199 { "FR_dispatch_stall_ls_full", 0xD8, 0x0 }, 200 { "FR_dispatch_stall_waiting_all_quiet", 0xD9, 0x0 }, 201 { "FR_dispatch_stall_far_ctl_trsfr_resync_branch_pend", 0xDA, 0x0 }, 202 { "FR_fpu_exception", 0xDB, 0xF }, 203 { "FR_num_brkpts_dr0", 0xDC, 0x0 }, 204 { "FR_num_brkpts_dr1", 0xDD, 0x0 }, 205 { "FR_num_brkpts_dr2", 0xDE, 0x0 }, 206 { "FR_num_brkpts_dr3", 0xDF, 0x0 }, 207 { "NB_mem_ctrlr_page_access", 0xE0, 0x7 }, 208 { "NB_mem_ctrlr_page_table_overflow", 0xE1, 0x0 }, 209 { "NB_mem_ctrlr_dram_cmd_slots_missed", 0xE2, 0x0 }, 210 { "NB_mem_ctrlr_turnaround", 0xE3, 0x7 }, 211 { "NB_mem_ctrlr_bypass_counter_saturation", 0xE4, 0xF }, 212 { "NB_sized_blocks_Rev_D", 0xE5, 0x3C}, 213 { "NB_ECC_errors", 0xE8, 0x80}, 214 { "NB_cpu_io_to_mem_io_Rev_E", 0xE9, 0xFF}, 215 { "NB_cache_block_commands_Rev_E", 0xEA, 0x3D}, 216 { "NB_sized_commands", 0xEB, 0x7F }, 217 { "NB_probe_result", 0xEC, 0x7F}, 218 { "NB_gart_events", 0xEE, 0x7 }, 219 { "NB_ht_bus0_bandwidth", 0xF6, 0xF }, 220 { "NB_ht_bus1_bandwidth", 0xF7, 0xF }, 221 { "NB_ht_bus2_bandwidth", 0xF8, 0xF }, 222 EV_END 223 }; 224 225 static char *evlist; 226 static size_t evlist_sz; 227 228 #define BITS(v, u, l) \ 229 (((v) >> (l)) & ((1 << (1 + (u) - (l))) - 1)) 230 231 #define OPTERON_FAMILY 15 232 233 static int 234 opt_pcbe_init(void) 235 { 236 opt_event_t *evp; 237 238 /* 239 * Make sure this really _is_ an Opteron or Athlon 64 system. The kernel 240 * loads this module based on its name in the module directory, but it 241 * could have been renamed. 242 */ 243 if (cpuid_getvendor(CPU) != X86_VENDOR_AMD || 244 cpuid_getfamily(CPU) != OPTERON_FAMILY) 245 return (-1); 246 247 /* 248 * Construct event list. 249 * 250 * First pass: Calculate size needed. We'll need an additional byte 251 * for the NULL pointer during the last strcat. 252 * 253 * Second pass: Copy strings. 254 */ 255 for (evp = opt_events; evp->name != NULL; evp++) 256 evlist_sz += strlen(evp->name) + 1; 257 258 evlist = kmem_alloc(evlist_sz + 1, KM_SLEEP); 259 evlist[0] = '\0'; 260 261 for (evp = opt_events; evp->name != NULL; evp++) { 262 (void) strcat(evlist, evp->name); 263 (void) strcat(evlist, ","); 264 } 265 /* 266 * Remove trailing comma. 267 */ 268 evlist[evlist_sz - 1] = '\0'; 269 270 return (0); 271 } 272 273 static uint_t 274 opt_pcbe_ncounters(void) 275 { 276 return (4); 277 } 278 279 static const char * 280 opt_pcbe_impl_name(void) 281 { 282 return ("AMD Opteron & Athlon64"); 283 } 284 285 static const char * 286 opt_pcbe_cpuref(void) 287 { 288 return ("See Chapter 10 of the \"BIOS and Kernel Developer's Guide " 289 "for the AMD Athlon 64 and AMD Opteron Processors,\" " 290 "AMD publication #26094"); 291 } 292 293 /*ARGSUSED*/ 294 static char * 295 opt_pcbe_list_events(uint_t picnum) 296 { 297 return (evlist); 298 } 299 300 static char * 301 opt_pcbe_list_attrs(void) 302 { 303 return ("edge,pc,inv,cmask,umask"); 304 } 305 306 /*ARGSUSED*/ 307 static uint64_t 308 opt_pcbe_event_coverage(char *event) 309 { 310 /* 311 * Fortunately, all counters can count all events. 312 */ 313 return (0xF); 314 } 315 316 static uint64_t 317 opt_pcbe_overflow_bitmap(void) 318 { 319 /* 320 * Unfortunately, this chip cannot detect which counter overflowed, so 321 * we must act as if they all did. 322 */ 323 return (0xF); 324 } 325 326 static opt_event_t * 327 find_event(char *name) 328 { 329 opt_event_t *evp; 330 331 for (evp = opt_events; evp->name != NULL; evp++) 332 if (strcmp(name, evp->name) == 0) 333 return (evp); 334 335 return (NULL); 336 } 337 338 /*ARGSUSED*/ 339 static int 340 opt_pcbe_configure(uint_t picnum, char *event, uint64_t preset, uint32_t flags, 341 uint_t nattrs, kcpc_attr_t *attrs, void **data, void *token) 342 { 343 opt_pcbe_config_t *cfg; 344 opt_event_t *evp; 345 int i; 346 uint32_t evsel = 0; 347 348 /* 349 * If we've been handed an existing configuration, we need only preset 350 * the counter value. 351 */ 352 if (*data != NULL) { 353 cfg = *data; 354 cfg->opt_rawpic = preset & MASK48; 355 return (0); 356 } 357 358 if (picnum >= 4) 359 return (CPC_INVALID_PICNUM); 360 361 if ((evp = find_event(event)) == NULL) 362 return (CPC_INVALID_EVENT); 363 364 evsel |= evp->emask; 365 366 if (flags & CPC_COUNT_USER) 367 evsel |= OPT_PES_USR; 368 if (flags & CPC_COUNT_SYSTEM) 369 evsel |= OPT_PES_OS; 370 if (flags & CPC_OVF_NOTIFY_EMT) 371 evsel |= OPT_PES_INT; 372 373 for (i = 0; i < nattrs; i++) { 374 if (strcmp(attrs[i].ka_name, "edge") == 0) { 375 if (attrs[i].ka_val != 0) 376 evsel |= OPT_PES_EDGE; 377 } else if (strcmp(attrs[i].ka_name, "pc") == 0) { 378 if (attrs[i].ka_val != 0) 379 evsel |= OPT_PES_PC; 380 } else if (strcmp(attrs[i].ka_name, "inv") == 0) { 381 if (attrs[i].ka_val != 0) 382 evsel |= OPT_PES_INV; 383 } else if (strcmp(attrs[i].ka_name, "cmask") == 0) { 384 if ((attrs[i].ka_val | OPT_PES_CMASK_MASK) != 385 OPT_PES_CMASK_MASK) 386 return (CPC_ATTRIBUTE_OUT_OF_RANGE); 387 evsel |= attrs[i].ka_val << OPT_PES_CMASK_SHIFT; 388 } else if (strcmp(attrs[i].ka_name, "umask") == 0) { 389 if ((attrs[i].ka_val | evp->umask_valid) != 390 evp->umask_valid) 391 return (CPC_ATTRIBUTE_OUT_OF_RANGE); 392 evsel |= attrs[i].ka_val << OPT_PES_UMASK_SHIFT; 393 } else 394 return (CPC_INVALID_ATTRIBUTE); 395 } 396 397 cfg = kmem_alloc(sizeof (*cfg), KM_SLEEP); 398 399 cfg->opt_picno = picnum; 400 cfg->opt_evsel = evsel; 401 cfg->opt_rawpic = preset & MASK48; 402 403 *data = cfg; 404 return (0); 405 } 406 407 static void 408 opt_pcbe_program(void *token) 409 { 410 opt_pcbe_config_t *cfgs[4] = { &nullcfgs[0], &nullcfgs[1], 411 &nullcfgs[2], &nullcfgs[3] }; 412 opt_pcbe_config_t *pcfg = NULL; 413 int i; 414 uint32_t curcr4 = getcr4(); 415 416 /* 417 * Allow nonprivileged code to read the performance counters if desired. 418 */ 419 if (kcpc_allow_nonpriv(token)) 420 setcr4(curcr4 | CR4_PCE); 421 else 422 setcr4(curcr4 & ~CR4_PCE); 423 424 /* 425 * Query kernel for all configs which will be co-programmed. 426 */ 427 do { 428 pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, NULL); 429 430 if (pcfg != NULL) { 431 ASSERT(pcfg->opt_picno < 4); 432 cfgs[pcfg->opt_picno] = pcfg; 433 } 434 } while (pcfg != NULL); 435 436 /* 437 * Program in two loops. The first configures and presets the counter, 438 * and the second loop enables the counters. This ensures that the 439 * counters are all enabled as closely together in time as possible. 440 */ 441 442 for (i = 0; i < 4; i++) { 443 wrmsr(PES_BASE_ADDR + i, cfgs[i]->opt_evsel); 444 wrmsr(PIC_BASE_ADDR + i, cfgs[i]->opt_rawpic); 445 } 446 447 for (i = 0; i < 4; i++) { 448 wrmsr(PES_BASE_ADDR + i, cfgs[i]->opt_evsel | 449 (uint64_t)(uintptr_t)OPT_PES_ENABLE); 450 } 451 } 452 453 static void 454 opt_pcbe_allstop(void) 455 { 456 int i; 457 458 for (i = 0; i < 4; i++) 459 wrmsr(PES_BASE_ADDR + i, 0ULL); 460 461 /* 462 * Disable non-privileged access to the counter registers. 463 */ 464 setcr4((uint32_t)getcr4() & ~CR4_PCE); 465 } 466 467 static void 468 opt_pcbe_sample(void *token) 469 { 470 opt_pcbe_config_t *cfgs[4] = { NULL, NULL, NULL, NULL }; 471 opt_pcbe_config_t *pcfg = NULL; 472 int i; 473 uint64_t curpic[4]; 474 uint64_t *addrs[4]; 475 uint64_t *tmp; 476 int64_t diff; 477 478 for (i = 0; i < 4; i++) 479 curpic[i] = rdmsr(PIC_BASE_ADDR + i); 480 481 /* 482 * Query kernel for all configs which are co-programmed. 483 */ 484 do { 485 pcfg = (opt_pcbe_config_t *)kcpc_next_config(token, pcfg, &tmp); 486 487 if (pcfg != NULL) { 488 ASSERT(pcfg->opt_picno < 4); 489 cfgs[pcfg->opt_picno] = pcfg; 490 addrs[pcfg->opt_picno] = tmp; 491 } 492 } while (pcfg != NULL); 493 494 for (i = 0; i < 4; i++) { 495 if (cfgs[i] == NULL) 496 continue; 497 498 diff = (curpic[i] - cfgs[i]->opt_rawpic) & MASK48; 499 *addrs[i] += diff; 500 DTRACE_PROBE4(opt__pcbe__sample, int, i, uint64_t, *addrs[i], 501 uint64_t, curpic[i], uint64_t, cfgs[i]->opt_rawpic); 502 cfgs[i]->opt_rawpic = *addrs[i] & MASK48; 503 } 504 } 505 506 static void 507 opt_pcbe_free(void *config) 508 { 509 kmem_free(config, sizeof (opt_pcbe_config_t)); 510 } 511 512 513 static struct modlpcbe modlpcbe = { 514 &mod_pcbeops, 515 "AMD Performance Counters v%I%", 516 &opt_pcbe_ops 517 }; 518 519 static struct modlinkage modl = { 520 MODREV_1, 521 &modlpcbe, 522 }; 523 524 int 525 _init(void) 526 { 527 int ret; 528 529 if (opt_pcbe_init() != 0) 530 return (ENOTSUP); 531 532 if ((ret = mod_install(&modl)) != 0) 533 kmem_free(evlist, evlist_sz + 1); 534 535 return (ret); 536 } 537 538 int 539 _fini(void) 540 { 541 int ret; 542 543 if ((ret = mod_remove(&modl)) == 0) 544 kmem_free(evlist, evlist_sz + 1); 545 return (ret); 546 } 547 548 int 549 _info(struct modinfo *mi) 550 { 551 return (mod_info(&modl, mi)); 552 } 553