1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 /* 28 * Library file that has code for PCIe booting 29 */ 30 31 #include <sys/conf.h> 32 #include <sys/pci.h> 33 #include <sys/sunndi.h> 34 #include <sys/pcie.h> 35 #include <sys/pcie_impl.h> 36 #include <sys/pci_cfgspace.h> 37 #include <io/pciex/pcie_nvidia.h> 38 39 /* 40 * PCI Configuration (Nvidia chipsets, PCIe) related library functions 41 */ 42 43 /* Globals */ 44 extern int pci_boot_debug; 45 46 extern uint64_t mcfg_mem_base; 47 48 boolean_t 49 check_if_device_is_pciex(dev_info_t *cdip, uchar_t bus, uchar_t dev, 50 uchar_t func, ushort_t *slot_number, ushort_t *is_pci_bridge) 51 { 52 boolean_t found_pciex = B_FALSE; 53 ushort_t cap; 54 ushort_t capsp; 55 ushort_t cap_count = PCI_CAP_MAX_PTR; 56 ushort_t status; 57 uint32_t slot_cap; 58 59 *slot_number = 0; 60 61 status = (*pci_getw_func)(bus, dev, func, PCI_CONF_STAT); 62 if (!(status & PCI_STAT_CAP)) 63 return (B_FALSE); 64 65 capsp = (*pci_getb_func)(bus, dev, func, PCI_CONF_CAP_PTR); 66 while (cap_count-- && capsp >= PCI_CAP_PTR_OFF) { 67 capsp &= PCI_CAP_PTR_MASK; 68 cap = (*pci_getb_func)(bus, dev, func, capsp); 69 70 if (cap == PCI_CAP_ID_PCI_E) { 71 #ifdef DEBUG 72 if (pci_boot_debug) 73 cmn_err(CE_CONT, "PCI-Express (%x,%x,%x) " 74 "capability found\n", bus, dev, func); 75 #endif /* DEBUG */ 76 77 status = (*pci_getw_func)(bus, dev, func, capsp + 2); 78 /* 79 * See section 7.8.2 of PCI-Express Base Spec v1.0a 80 * for Device/Port Type. 81 * PCIE_PCIECAP_DEV_TYPE_PCIE2PCI implies that the 82 * device is a PCIe2PCI bridge 83 */ 84 *is_pci_bridge = 85 ((status & PCIE_PCIECAP_DEV_TYPE_MASK) == 86 PCIE_PCIECAP_DEV_TYPE_PCIE2PCI) ? 1 : 0; 87 88 /* 89 * Check for "Slot Implemented" bit 90 * PCIE_PCIECAP_SLOT_IMPL implies that. 91 */ 92 if (status & PCIE_PCIECAP_SLOT_IMPL) { 93 /* offset 14h is Slot Cap Register */ 94 slot_cap = (*pci_getl_func)(bus, dev, func, 95 capsp + PCIE_SLOTCAP); 96 *slot_number = 97 PCIE_SLOTCAP_PHY_SLOT_NUM(slot_cap); 98 99 /* Is PCI Express HotPlug capability set? */ 100 if (cdip && 101 (slot_cap & PCIE_SLOTCAP_HP_CAPABLE)) { 102 (void) ndi_prop_update_int( 103 DDI_DEV_T_NONE, cdip, 104 "pci-hotplug-type", 105 INBAND_HPC_PCIE); 106 } 107 } 108 109 found_pciex = B_TRUE; 110 } 111 112 if (cdip && (cap == PCI_CAP_ID_PCI_HOTPLUG)) { 113 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cdip, 114 "pci-hotplug-type", INBAND_HPC_SHPC); 115 } 116 117 capsp = (*pci_getb_func)(bus, dev, func, 118 capsp + PCI_CAP_NEXT_PTR); 119 } 120 121 return (found_pciex); 122 } 123 124 125 /* 126 * scan all buses, devices, functions to look for any 127 * PCI-Express device in the system. 128 * If found, return B_TRUE else B_FALSE 129 */ 130 boolean_t 131 look_for_any_pciex_device(uchar_t bus) 132 { 133 uchar_t dev, func; 134 uchar_t nfunc, header; 135 ushort_t venid, slot_num, is_pci_bridge = 0; 136 137 for (dev = 0; dev < 32; dev++) { 138 nfunc = 1; 139 for (func = 0; func < nfunc; func++) { 140 #ifdef DEBUG 141 if (pci_boot_debug) 142 cmn_err(CE_NOTE, "pciex dev 0x%x, func 0x%x", 143 dev, func); 144 #endif /* DEBUG */ 145 146 venid = (*pci_getw_func)(bus, dev, func, 147 PCI_CONF_VENID); 148 /* no function at this address */ 149 if ((venid == 0xffff) || (venid == 0)) 150 continue; 151 152 header = (*pci_getb_func)(bus, dev, func, 153 PCI_CONF_HEADER); 154 if (header == 0xff) 155 continue; /* illegal value */ 156 157 /* 158 * according to some mail from Microsoft posted to 159 * the pci-drivers alias, their only requirement for 160 * a multifunction device is for the 1st function to 161 * have to PCI_HEADER_MULTI bit set. 162 */ 163 if ((func == 0) && (header & PCI_HEADER_MULTI)) 164 nfunc = 8; 165 166 if (check_if_device_is_pciex(NULL, bus, dev, func, 167 &slot_num, &is_pci_bridge) == B_TRUE) 168 return (B_TRUE); 169 } /* end of func */ 170 } /* end of dev */ 171 172 return (B_FALSE); 173 } 174 175 boolean_t 176 create_pcie_root_bus(uchar_t bus, dev_info_t *dip) 177 { 178 pcie_bus_t *bus_p; 179 180 /* 181 * Currently this is being hard-coded. 182 * We need to figure out if the root bus does indeed 183 * have PCI-Ex in the path by looking for MCFG in 184 * the ACPI tables 185 */ 186 if (look_for_any_pciex_device(bus) == B_FALSE) 187 return (B_FALSE); 188 189 #ifdef DEBUG 190 if (pci_boot_debug) 191 cmn_err(CE_CONT, "Found PCI-Ex in the system\n"); 192 #endif /* DEBUG */ 193 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 194 "device_type", "pciex"); 195 (void) ndi_prop_update_string(DDI_DEV_T_NONE, dip, 196 "compatible", "pciex_root_complex"); 197 198 pcie_rc_init_bus(dip); 199 200 /* save base addr in bus_t for pci_cfgacc_xxx() */ 201 bus_p = PCIE_DIP2BUS(dip); 202 bus_p->bus_cfgacc_base = mcfg_mem_base; 203 204 return (B_TRUE); 205 } 206 207 208 /* 209 * add_nvidia_isa_bridge_props(): 210 * To enable native hotplug; we need to map in two I/O BARs 211 * from ISA bridge's config space 212 * 213 * NOTE: For now, this function is only used for Nvidia's CrushK 8-04 chipsets. 214 */ 215 void 216 add_nvidia_isa_bridge_props(dev_info_t *dip, uchar_t bus, uchar_t dev, 217 uchar_t func) 218 { 219 uint_t devloc, base; 220 pci_regspec_t regs[2] = {{0}}; 221 pci_regspec_t assigned[2] = {{0}}; 222 223 devloc = (uint_t)bus << PCI_REG_BUS_SHIFT | 224 (uint_t)dev << PCI_REG_DEV_SHIFT | 225 (uint_t)func << PCI_REG_FUNC_SHIFT; 226 regs[0].pci_phys_hi = devloc; 227 228 /* System Control BAR i/o space */ 229 base = (*pci_getl_func)(bus, dev, func, 230 NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF); 231 regs[0].pci_size_low = assigned[0].pci_size_low = PCI_CONF_HDR_SIZE; 232 assigned[0].pci_phys_hi = regs[0].pci_phys_hi = (PCI_RELOCAT_B | 233 PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_SYSCTRL_BAR_OFF); 234 assigned[0].pci_phys_low = regs[0].pci_phys_low = 235 base & PCI_BASE_IO_ADDR_M; 236 237 /* Analog BAR i/o space */ 238 base = (*pci_getl_func)(bus, dev, func, 239 NVIDIA_CK804_ISA_ANALOG_BAR_OFF); 240 regs[1].pci_size_low = assigned[1].pci_size_low = PCI_CONF_HDR_SIZE; 241 assigned[1].pci_phys_hi = regs[1].pci_phys_hi = (PCI_RELOCAT_B | 242 PCI_ADDR_IO | devloc | NVIDIA_CK804_ISA_ANALOG_BAR_OFF); 243 assigned[1].pci_phys_low = regs[1].pci_phys_low = 244 base & PCI_BASE_IO_ADDR_M; 245 246 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 247 (int *)regs, 2 * sizeof (pci_regspec_t) / sizeof (int)); 248 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 249 "assigned-addresses", 250 (int *)assigned, 2 * sizeof (pci_regspec_t) / sizeof (int)); 251 } 252