1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * PCI configurator (pcicfg) 28 */ 29 30 #include <sys/sysmacros.h> 31 #include <sys/conf.h> 32 #include <sys/kmem.h> 33 #include <sys/debug.h> 34 #include <sys/modctl.h> 35 #include <sys/autoconf.h> 36 #include <sys/hwconf.h> 37 #include <sys/pcie.h> 38 #include <sys/pcie_impl.h> 39 #include <sys/pci_cap.h> 40 #include <sys/ddi.h> 41 #include <sys/sunndi.h> 42 #include <sys/hotplug/pci/pcicfg.h> 43 #include <sys/ndi_impldefs.h> 44 #include <sys/pci_cfgacc.h> 45 #include <sys/pcie_impl.h> 46 47 /* 48 * ************************************************************************ 49 * *** Implementation specific local data structures/definitions. *** 50 * ************************************************************************ 51 */ 52 53 static int pcicfg_start_devno = 0; /* for Debug only */ 54 55 #define PCICFG_MAX_ARI_FUNCTION 256 56 57 #define PCICFG_NODEVICE 42 58 #define PCICFG_NOMEMORY 43 59 #define PCICFG_NOMULTI 44 60 #define PCICFG_NORESRC 45 61 62 #define PCICFG_HIADDR(n) ((uint32_t)(((uint64_t)(n) & \ 63 0xFFFFFFFF00000000ULL)>> 32)) 64 #define PCICFG_LOADDR(n) ((uint32_t)((uint64_t)(n) & 0x00000000FFFFFFFF)) 65 #define PCICFG_LADDR(lo, hi) (((uint64_t)(hi) << 32) | (uint32_t)(lo)) 66 67 #define PCICFG_HIWORD(n) ((uint16_t)(((uint32_t)(n) & 0xFFFF0000)>> 16)) 68 #define PCICFG_LOWORD(n) ((uint16_t)((uint32_t)(n) & 0x0000FFFF)) 69 #define PCICFG_HIBYTE(n) ((uint8_t)(((uint16_t)(n) & 0xFF00)>> 8)) 70 #define PCICFG_LOBYTE(n) ((uint8_t)((uint16_t)(n) & 0x00FF)) 71 72 #define PCICFG_ROUND_UP(addr, gran) ((uintptr_t)((gran+addr-1)&(~(gran-1)))) 73 #define PCICFG_ROUND_DOWN(addr, gran) ((uintptr_t)((addr) & ~(gran-1))) 74 75 #define PCICFG_MEMGRAN 0x100000 76 #define PCICFG_IOGRAN 0x1000 77 #define PCICFG_4GIG_LIMIT 0xFFFFFFFFUL 78 79 #define PCICFG_MEM_MULT 4 80 #define PCICFG_IO_MULT 4 81 #define PCICFG_RANGE_LEN 3 /* Number of range entries */ 82 83 static int pcicfg_slot_busnums = 8; 84 static int pcicfg_slot_memsize = 32 * PCICFG_MEMGRAN; /* 32MB per slot */ 85 static int pcicfg_slot_pf_memsize = 32 * PCICFG_MEMGRAN; /* 32MB per slot */ 86 static int pcicfg_slot_iosize = 64 * PCICFG_IOGRAN; /* 64K per slot */ 87 static int pcicfg_sec_reset_delay = 3000000; 88 static int pcicfg_do_legacy_props = 1; /* create legacy compatible prop */ 89 90 typedef struct hole hole_t; 91 92 struct hole { 93 uint64_t start; 94 uint64_t len; 95 hole_t *next; 96 }; 97 98 typedef struct pcicfg_phdl pcicfg_phdl_t; 99 100 struct pcicfg_phdl { 101 102 dev_info_t *dip; /* Associated with the bridge */ 103 dev_info_t *top_dip; /* top node of the attach point */ 104 pcicfg_phdl_t *next; 105 106 /* non-prefetchable memory space */ 107 uint64_t memory_base; /* Memory base for this attach point */ 108 uint64_t memory_last; 109 uint64_t memory_len; 110 111 /* prefetchable memory space */ 112 uint64_t pf_memory_base; /* PF Memory base for this Connection */ 113 uint64_t pf_memory_last; 114 uint64_t pf_memory_len; 115 116 /* io space */ 117 uint32_t io_base; /* I/O base for this attach point */ 118 uint32_t io_last; 119 uint32_t io_len; 120 121 int error; 122 uint_t highest_bus; /* Highest bus seen on the probe */ 123 124 hole_t mem_hole; /* Memory hole linked list. */ 125 hole_t pf_mem_hole; /* PF Memory hole linked list. */ 126 hole_t io_hole; /* IO hole linked list */ 127 128 ndi_ra_request_t mem_req; /* allocator request for memory */ 129 ndi_ra_request_t pf_mem_req; /* allocator request for PF memory */ 130 ndi_ra_request_t io_req; /* allocator request for I/O */ 131 }; 132 133 struct pcicfg_standard_prop_entry { 134 uchar_t *name; 135 uint_t config_offset; 136 uint_t size; 137 }; 138 139 140 struct pcicfg_name_entry { 141 uint32_t class_code; 142 char *name; 143 }; 144 145 struct pcicfg_find_ctrl { 146 uint_t device; 147 uint_t function; 148 dev_info_t *dip; 149 }; 150 151 /* 152 * List of Indirect Config Map Devices. At least the intent of the 153 * design is to look for a device in this list during the configure 154 * operation, and if the device is listed here, then it is a nontransparent 155 * bridge, hence load the driver and avail the config map services from 156 * the driver. Class and Subclass should be as defined in the PCI specs 157 * ie. class is 0x6, and subclass is 0x9. 158 */ 159 static struct { 160 uint8_t mem_range_bar_offset; 161 uint8_t io_range_bar_offset; 162 uint8_t prefetch_mem_range_bar_offset; 163 } pcicfg_indirect_map_devs[] = { 164 PCI_CONF_BASE3, PCI_CONF_BASE2, PCI_CONF_BASE3, 165 0, 0, 0, 166 }; 167 168 #define PCICFG_MAKE_REG_HIGH(busnum, devnum, funcnum, register)\ 169 (\ 170 ((ulong_t)(busnum & 0xff) << 16) |\ 171 ((ulong_t)(devnum & 0x1f) << 11) |\ 172 ((ulong_t)(funcnum & 0x7) << 8) |\ 173 ((ulong_t)(register & 0x3f))) 174 175 /* 176 * debug macros: 177 */ 178 #if defined(DEBUG) 179 extern void prom_printf(const char *, ...); 180 181 /* 182 * Following values are defined for this debug flag. 183 * 184 * 1 = dump configuration header only. 185 * 2 = dump generic debug data only (no config header dumped) 186 * 3 = dump everything (both 1 and 2) 187 */ 188 int pcicfg_debug = 0; 189 190 static void debug(char *, uintptr_t, uintptr_t, 191 uintptr_t, uintptr_t, uintptr_t); 192 193 #define DEBUG0(fmt)\ 194 debug(fmt, 0, 0, 0, 0, 0); 195 #define DEBUG1(fmt, a1)\ 196 debug(fmt, (uintptr_t)(a1), 0, 0, 0, 0); 197 #define DEBUG2(fmt, a1, a2)\ 198 debug(fmt, (uintptr_t)(a1), (uintptr_t)(a2), 0, 0, 0); 199 #define DEBUG3(fmt, a1, a2, a3)\ 200 debug(fmt, (uintptr_t)(a1), (uintptr_t)(a2),\ 201 (uintptr_t)(a3), 0, 0); 202 #define DEBUG4(fmt, a1, a2, a3, a4)\ 203 debug(fmt, (uintptr_t)(a1), (uintptr_t)(a2),\ 204 (uintptr_t)(a3), (uintptr_t)(a4), 0); 205 #define DEBUG5(fmt, a1, a2, a3, a4, a5)\ 206 debug(fmt, (uintptr_t)(a1), (uintptr_t)(a2),\ 207 (uintptr_t)(a3), (uintptr_t)(a4), (uintptr_t)(a5)); 208 #else 209 #define DEBUG0(fmt) 210 #define DEBUG1(fmt, a1) 211 #define DEBUG2(fmt, a1, a2) 212 #define DEBUG3(fmt, a1, a2, a3) 213 #define DEBUG4(fmt, a1, a2, a3, a4) 214 #define DEBUG5(fmt, a1, a2, a3, a4, a5) 215 #endif 216 217 /* 218 * forward declarations for routines defined in this module (called here) 219 */ 220 221 static int pcicfg_add_config_reg(dev_info_t *, 222 uint_t, uint_t, uint_t); 223 static int pcicfg_probe_children(dev_info_t *, uint_t, uint_t, uint_t, 224 uint_t *, pcicfg_flags_t, boolean_t); 225 static int pcicfg_match_dev(dev_info_t *, void *); 226 static dev_info_t *pcicfg_devi_find(dev_info_t *, uint_t, uint_t); 227 static pcicfg_phdl_t *pcicfg_find_phdl(dev_info_t *); 228 static pcicfg_phdl_t *pcicfg_create_phdl(dev_info_t *); 229 static int pcicfg_destroy_phdl(dev_info_t *); 230 static int pcicfg_sum_resources(dev_info_t *, void *); 231 static int pcicfg_device_assign(dev_info_t *); 232 static int pcicfg_bridge_assign(dev_info_t *, void *); 233 static int pcicfg_device_assign_readonly(dev_info_t *); 234 static int pcicfg_free_resources(dev_info_t *, pcicfg_flags_t); 235 static void pcicfg_setup_bridge(pcicfg_phdl_t *, ddi_acc_handle_t); 236 static void pcicfg_update_bridge(pcicfg_phdl_t *, ddi_acc_handle_t); 237 static int pcicfg_update_assigned_prop(dev_info_t *, pci_regspec_t *); 238 static void pcicfg_device_on(ddi_acc_handle_t); 239 static void pcicfg_device_off(ddi_acc_handle_t); 240 static int pcicfg_set_busnode_props(dev_info_t *, uint8_t); 241 static int pcicfg_free_bridge_resources(dev_info_t *); 242 static int pcicfg_free_device_resources(dev_info_t *); 243 static int pcicfg_teardown_device(dev_info_t *, pcicfg_flags_t, boolean_t); 244 static void pcicfg_reparent_node(dev_info_t *, dev_info_t *); 245 static int pcicfg_config_setup(dev_info_t *, ddi_acc_handle_t *); 246 static void pcicfg_config_teardown(ddi_acc_handle_t *); 247 static void pcicfg_get_mem(pcicfg_phdl_t *, uint32_t, uint64_t *); 248 static void pcicfg_get_pf_mem(pcicfg_phdl_t *, uint32_t, uint64_t *); 249 static void pcicfg_get_io(pcicfg_phdl_t *, uint32_t, uint32_t *); 250 static int pcicfg_update_ranges_prop(dev_info_t *, ppb_ranges_t *); 251 static int pcicfg_configure_ntbridge(dev_info_t *, uint_t, uint_t); 252 static uint_t pcicfg_ntbridge_child(dev_info_t *); 253 static uint_t pcicfg_get_ntbridge_child_range(dev_info_t *, uint64_t *, 254 uint64_t *, uint_t); 255 static int pcicfg_is_ntbridge(dev_info_t *); 256 static int pcicfg_ntbridge_allocate_resources(dev_info_t *); 257 static int pcicfg_ntbridge_configure_done(dev_info_t *); 258 static int pcicfg_ntbridge_program_child(dev_info_t *); 259 static uint_t pcicfg_ntbridge_unconfigure(dev_info_t *); 260 static int pcicfg_ntbridge_unconfigure_child(dev_info_t *, uint_t); 261 static void pcicfg_free_hole(hole_t *); 262 static uint64_t pcicfg_alloc_hole(hole_t *, uint64_t *, uint32_t); 263 static int pcicfg_device_type(dev_info_t *, ddi_acc_handle_t *); 264 static void pcicfg_update_phdl(dev_info_t *, uint8_t, uint8_t); 265 static int pcicfg_get_cap(ddi_acc_handle_t, uint8_t); 266 static uint8_t pcicfg_get_nslots(dev_info_t *, ddi_acc_handle_t); 267 static int pcicfg_pcie_dev(dev_info_t *, ddi_acc_handle_t); 268 static int pcicfg_pcie_device_type(dev_info_t *, ddi_acc_handle_t); 269 static int pcicfg_pcie_port_type(dev_info_t *, ddi_acc_handle_t); 270 static int pcicfg_probe_bridge(dev_info_t *, ddi_acc_handle_t, uint_t, 271 uint_t *, boolean_t); 272 static int pcicfg_find_resource_end(dev_info_t *, void *); 273 static boolean_t is_pcie_fabric(dev_info_t *); 274 275 static int pcicfg_populate_reg_props(dev_info_t *, ddi_acc_handle_t); 276 static int pcicfg_populate_props_from_bar(dev_info_t *, ddi_acc_handle_t); 277 static int pcicfg_update_assigned_prop_value(dev_info_t *, uint32_t, 278 uint32_t, uint32_t, uint_t); 279 static int pcicfg_ari_configure(dev_info_t *); 280 281 #ifdef DEBUG 282 static void pcicfg_dump_common_config(ddi_acc_handle_t config_handle); 283 static void pcicfg_dump_device_config(ddi_acc_handle_t); 284 static void pcicfg_dump_bridge_config(ddi_acc_handle_t config_handle); 285 static uint64_t pcicfg_unused_space(hole_t *, uint32_t *); 286 287 #define PCICFG_DUMP_COMMON_CONFIG(hdl) (void)pcicfg_dump_common_config(hdl) 288 #define PCICFG_DUMP_DEVICE_CONFIG(hdl) (void)pcicfg_dump_device_config(hdl) 289 #define PCICFG_DUMP_BRIDGE_CONFIG(hdl) (void)pcicfg_dump_bridge_config(hdl) 290 #else 291 #define PCICFG_DUMP_COMMON_CONFIG(handle) 292 #define PCICFG_DUMP_DEVICE_CONFIG(handle) 293 #define PCICFG_DUMP_BRIDGE_CONFIG(handle) 294 #endif 295 296 static kmutex_t pcicfg_list_mutex; /* Protects the probe handle list */ 297 static pcicfg_phdl_t *pcicfg_phdl_list = NULL; 298 299 #ifndef _DONT_USE_1275_GENERIC_NAMES 300 /* 301 * Class code table 302 */ 303 static struct pcicfg_name_entry pcicfg_class_lookup [] = { 304 305 { 0x001, "display" }, 306 { 0x100, "scsi" }, 307 { 0x101, "ide" }, 308 { 0x102, "fdc" }, 309 { 0x103, "ipi" }, 310 { 0x104, "raid" }, 311 { 0x105, "ata" }, 312 { 0x106, "sata" }, 313 { 0x200, "ethernet" }, 314 { 0x201, "token-ring" }, 315 { 0x202, "fddi" }, 316 { 0x203, "atm" }, 317 { 0x204, "isdn" }, 318 { 0x206, "mcd" }, 319 { 0x300, "display" }, 320 { 0x400, "video" }, 321 { 0x401, "sound" }, 322 { 0x500, "memory" }, 323 { 0x501, "flash" }, 324 { 0x600, "host" }, 325 { 0x601, "isa" }, 326 { 0x602, "eisa" }, 327 { 0x603, "mca" }, 328 { 0x604, "pci" }, 329 { 0x605, "pcmcia" }, 330 { 0x606, "nubus" }, 331 { 0x607, "cardbus" }, 332 { 0x609, "pci" }, 333 { 0x60a, "ib-pci" }, 334 { 0x700, "serial" }, 335 { 0x701, "parallel" }, 336 { 0x800, "interrupt-controller" }, 337 { 0x801, "dma-controller" }, 338 { 0x802, "timer" }, 339 { 0x803, "rtc" }, 340 { 0x900, "keyboard" }, 341 { 0x901, "pen" }, 342 { 0x902, "mouse" }, 343 { 0xa00, "dock" }, 344 { 0xb00, "cpu" }, 345 { 0xb01, "cpu" }, 346 { 0xb02, "cpu" }, 347 { 0xb10, "cpu" }, 348 { 0xb20, "cpu" }, 349 { 0xb30, "cpu" }, 350 { 0xb40, "coproc" }, 351 { 0xc00, "firewire" }, 352 { 0xc01, "access-bus" }, 353 { 0xc02, "ssa" }, 354 { 0xc03, "usb" }, 355 { 0xc04, "fibre-channel" }, 356 { 0xc05, "smbus" }, 357 { 0xc06, "ib" }, 358 { 0xd00, "irda" }, 359 { 0xd01, "ir" }, 360 { 0xd10, "rf" }, 361 { 0xd11, "btooth" }, 362 { 0xd12, "brdband" }, 363 { 0xd20, "802.11a" }, 364 { 0xd21, "802.11b" }, 365 { 0xe00, "i2o" }, 366 { 0xf01, "tv" }, 367 { 0xf02, "audio" }, 368 { 0xf03, "voice" }, 369 { 0xf04, "data" }, 370 { 0, 0 } 371 }; 372 #endif /* _DONT_USE_1275_GENERIC_NAMES */ 373 374 /* 375 * Module control operations 376 */ 377 378 extern struct mod_ops mod_miscops; 379 380 static struct modlmisc modlmisc = { 381 &mod_miscops, /* Type of module */ 382 "PCI configurator" 383 }; 384 385 static struct modlinkage modlinkage = { 386 MODREV_1, (void *)&modlmisc, NULL 387 }; 388 389 390 #ifdef DEBUG 391 392 static void 393 pcicfg_dump_common_config(ddi_acc_handle_t config_handle) 394 { 395 if ((pcicfg_debug & 1) == 0) 396 return; 397 prom_printf(" Vendor ID = [0x%x]\n", 398 pci_config_get16(config_handle, PCI_CONF_VENID)); 399 prom_printf(" Device ID = [0x%x]\n", 400 pci_config_get16(config_handle, PCI_CONF_DEVID)); 401 prom_printf(" Command REG = [0x%x]\n", 402 pci_config_get16(config_handle, PCI_CONF_COMM)); 403 prom_printf(" Status REG = [0x%x]\n", 404 pci_config_get16(config_handle, PCI_CONF_STAT)); 405 prom_printf(" Revision ID = [0x%x]\n", 406 pci_config_get8(config_handle, PCI_CONF_REVID)); 407 prom_printf(" Prog Class = [0x%x]\n", 408 pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 409 prom_printf(" Dev Class = [0x%x]\n", 410 pci_config_get8(config_handle, PCI_CONF_SUBCLASS)); 411 prom_printf(" Base Class = [0x%x]\n", 412 pci_config_get8(config_handle, PCI_CONF_BASCLASS)); 413 prom_printf(" Device ID = [0x%x]\n", 414 pci_config_get8(config_handle, PCI_CONF_CACHE_LINESZ)); 415 prom_printf(" Header Type = [0x%x]\n", 416 pci_config_get8(config_handle, PCI_CONF_HEADER)); 417 prom_printf(" BIST = [0x%x]\n", 418 pci_config_get8(config_handle, PCI_CONF_BIST)); 419 prom_printf(" BASE 0 = [0x%x]\n", 420 pci_config_get32(config_handle, PCI_CONF_BASE0)); 421 prom_printf(" BASE 1 = [0x%x]\n", 422 pci_config_get32(config_handle, PCI_CONF_BASE1)); 423 424 } 425 426 static void 427 pcicfg_dump_device_config(ddi_acc_handle_t config_handle) 428 { 429 if ((pcicfg_debug & 1) == 0) 430 return; 431 pcicfg_dump_common_config(config_handle); 432 433 prom_printf(" BASE 2 = [0x%x]\n", 434 pci_config_get32(config_handle, PCI_CONF_BASE2)); 435 prom_printf(" BASE 3 = [0x%x]\n", 436 pci_config_get32(config_handle, PCI_CONF_BASE3)); 437 prom_printf(" BASE 4 = [0x%x]\n", 438 pci_config_get32(config_handle, PCI_CONF_BASE4)); 439 prom_printf(" BASE 5 = [0x%x]\n", 440 pci_config_get32(config_handle, PCI_CONF_BASE5)); 441 prom_printf(" Cardbus CIS = [0x%x]\n", 442 pci_config_get32(config_handle, PCI_CONF_CIS)); 443 prom_printf(" Sub VID = [0x%x]\n", 444 pci_config_get16(config_handle, PCI_CONF_SUBVENID)); 445 prom_printf(" Sub SID = [0x%x]\n", 446 pci_config_get16(config_handle, PCI_CONF_SUBSYSID)); 447 prom_printf(" ROM = [0x%x]\n", 448 pci_config_get32(config_handle, PCI_CONF_ROM)); 449 prom_printf(" I Line = [0x%x]\n", 450 pci_config_get8(config_handle, PCI_CONF_ILINE)); 451 prom_printf(" I Pin = [0x%x]\n", 452 pci_config_get8(config_handle, PCI_CONF_IPIN)); 453 prom_printf(" Max Grant = [0x%x]\n", 454 pci_config_get8(config_handle, PCI_CONF_MIN_G)); 455 prom_printf(" Max Latent = [0x%x]\n", 456 pci_config_get8(config_handle, PCI_CONF_MAX_L)); 457 } 458 459 static void 460 pcicfg_dump_bridge_config(ddi_acc_handle_t config_handle) 461 { 462 if ((pcicfg_debug & 1) == 0) 463 return; 464 pcicfg_dump_common_config(config_handle); 465 466 prom_printf("........................................\n"); 467 468 prom_printf(" Pri Bus = [0x%x]\n", 469 pci_config_get8(config_handle, PCI_BCNF_PRIBUS)); 470 prom_printf(" Sec Bus = [0x%x]\n", 471 pci_config_get8(config_handle, PCI_BCNF_SECBUS)); 472 prom_printf(" Sub Bus = [0x%x]\n", 473 pci_config_get8(config_handle, PCI_BCNF_SUBBUS)); 474 prom_printf(" Latency = [0x%x]\n", 475 pci_config_get8(config_handle, PCI_BCNF_LATENCY_TIMER)); 476 prom_printf(" I/O Base LO = [0x%x]\n", 477 pci_config_get8(config_handle, PCI_BCNF_IO_BASE_LOW)); 478 prom_printf(" I/O Lim LO = [0x%x]\n", 479 pci_config_get8(config_handle, PCI_BCNF_IO_LIMIT_LOW)); 480 prom_printf(" Sec. Status = [0x%x]\n", 481 pci_config_get16(config_handle, PCI_BCNF_SEC_STATUS)); 482 prom_printf(" Mem Base = [0x%x]\n", 483 pci_config_get16(config_handle, PCI_BCNF_MEM_BASE)); 484 prom_printf(" Mem Limit = [0x%x]\n", 485 pci_config_get16(config_handle, PCI_BCNF_MEM_LIMIT)); 486 prom_printf(" PF Mem Base = [0x%x]\n", 487 pci_config_get16(config_handle, PCI_BCNF_PF_BASE_LOW)); 488 prom_printf(" PF Mem Lim = [0x%x]\n", 489 pci_config_get16(config_handle, PCI_BCNF_PF_LIMIT_LOW)); 490 prom_printf(" PF Base HI = [0x%x]\n", 491 pci_config_get32(config_handle, PCI_BCNF_PF_BASE_HIGH)); 492 prom_printf(" PF Lim HI = [0x%x]\n", 493 pci_config_get32(config_handle, PCI_BCNF_PF_LIMIT_HIGH)); 494 prom_printf(" I/O Base HI = [0x%x]\n", 495 pci_config_get16(config_handle, PCI_BCNF_IO_BASE_HI)); 496 prom_printf(" I/O Lim HI = [0x%x]\n", 497 pci_config_get16(config_handle, PCI_BCNF_IO_LIMIT_HI)); 498 prom_printf(" ROM addr = [0x%x]\n", 499 pci_config_get32(config_handle, PCI_BCNF_ROM)); 500 prom_printf(" Intr Line = [0x%x]\n", 501 pci_config_get8(config_handle, PCI_BCNF_ILINE)); 502 prom_printf(" Intr Pin = [0x%x]\n", 503 pci_config_get8(config_handle, PCI_BCNF_IPIN)); 504 prom_printf(" Bridge Ctrl = [0x%x]\n", 505 pci_config_get16(config_handle, PCI_BCNF_BCNTRL)); 506 } 507 #endif 508 509 int 510 _init() 511 { 512 DEBUG0(" PCI configurator installed\n"); 513 mutex_init(&pcicfg_list_mutex, NULL, MUTEX_DRIVER, NULL); 514 return (mod_install(&modlinkage)); 515 } 516 517 int 518 _fini(void) 519 { 520 int error; 521 522 error = mod_remove(&modlinkage); 523 if (error != 0) { 524 return (error); 525 } 526 mutex_destroy(&pcicfg_list_mutex); 527 return (0); 528 } 529 530 int 531 _info(struct modinfo *modinfop) 532 { 533 return (mod_info(&modlinkage, modinfop)); 534 } 535 536 /* 537 * In the following functions ndi_devi_enter() without holding the 538 * parent dip is sufficient. This is because pci dr is driven through 539 * opens on the nexus which is in the device tree path above the node 540 * being operated on, and implicitly held due to the open. 541 */ 542 543 /* 544 * This entry point is called to configure a device (and 545 * all its children) on the given bus. It is called when 546 * a new device is added to the PCI domain. This routine 547 * will create the device tree and program the devices 548 * registers. 549 */ 550 int 551 pcicfg_configure(dev_info_t *devi, uint_t device, uint_t function, 552 pcicfg_flags_t flags) 553 { 554 uint_t bus; 555 int len; 556 int func; 557 dev_info_t *attach_point; 558 pci_bus_range_t pci_bus_range; 559 int rv; 560 int circ; 561 uint_t highest_bus; 562 int ari_mode = B_FALSE; 563 int max_function = PCI_MAX_FUNCTIONS; 564 int trans_device; 565 dev_info_t *new_device; 566 boolean_t is_pcie; 567 568 if (flags == PCICFG_FLAG_ENABLE_ARI) 569 return (pcicfg_ari_configure(devi)); 570 571 /* 572 * Start probing at the device specified in "device" on the 573 * "bus" specified. 574 */ 575 len = sizeof (pci_bus_range_t); 576 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, devi, 0, "bus-range", 577 (caddr_t)&pci_bus_range, &len) != DDI_SUCCESS) { 578 DEBUG0("no bus-range property\n"); 579 return (PCICFG_FAILURE); 580 } 581 582 bus = pci_bus_range.lo; /* primary bus number of this bus node */ 583 584 attach_point = devi; 585 586 is_pcie = is_pcie_fabric(devi); 587 588 ndi_devi_enter(devi, &circ); 589 for (func = 0; func < max_function; ) { 590 591 if ((function != PCICFG_ALL_FUNC) && (function != func)) 592 goto next; 593 594 if (ari_mode) 595 trans_device = func >> 3; 596 else 597 trans_device = device; 598 599 switch (rv = pcicfg_probe_children(attach_point, 600 bus, trans_device, func & 7, &highest_bus, 601 flags, is_pcie)) { 602 case PCICFG_NORESRC: 603 case PCICFG_FAILURE: 604 DEBUG2("configure failed: bus [0x%x] device " 605 "[0x%x]\n", bus, trans_device); 606 goto cleanup; 607 case PCICFG_NODEVICE: 608 DEBUG3("no device : bus " 609 "[0x%x] slot [0x%x] func [0x%x]\n", 610 bus, trans_device, func &7); 611 612 if (func) 613 goto next; 614 break; 615 default: 616 DEBUG3("configure: bus => [%d] " 617 "slot => [%d] func => [%d]\n", 618 bus, trans_device, func & 7); 619 break; 620 } 621 622 if (rv != PCICFG_SUCCESS) 623 break; 624 625 if ((new_device = pcicfg_devi_find(attach_point, 626 trans_device, func & 7)) == NULL) { 627 DEBUG0("Did'nt find device node just created\n"); 628 goto cleanup; 629 } 630 631 /* 632 * Up until now, we have detected a non transparent bridge 633 * (ntbridge) as a part of the generic probe code and 634 * configured only one configuration 635 * header which is the side facing the host bus. 636 * Now, configure the other side and create children. 637 * 638 * In order to make the process simpler, lets load the device 639 * driver for the non transparent bridge as this is a 640 * Solaris bundled driver, and use its configuration map 641 * services rather than programming it here. 642 * If the driver is not bundled into Solaris, it must be 643 * first loaded and configured before performing any 644 * hotplug operations. 645 * 646 * This not only makes the code here simpler but also more 647 * generic. 648 * 649 * So here we go. 650 */ 651 652 /* 653 * check if this is a bridge in nontransparent mode 654 */ 655 if (pcicfg_is_ntbridge(new_device) != DDI_FAILURE) { 656 DEBUG0("pcicfg: Found nontransparent bridge.\n"); 657 658 rv = pcicfg_configure_ntbridge(new_device, bus, 659 trans_device); 660 if (rv != PCICFG_SUCCESS) 661 goto cleanup; 662 } 663 664 next: 665 /* 666 * Determine if ARI Forwarding should be enabled. 667 */ 668 if (func == 0) { 669 if ((pcie_ari_supported(devi) 670 == PCIE_ARI_FORW_SUPPORTED) && 671 (pcie_ari_device(new_device) == PCIE_ARI_DEVICE)) { 672 if (pcie_ari_enable(devi) == DDI_SUCCESS) { 673 (void) ddi_prop_create(DDI_DEV_T_NONE, 674 devi, DDI_PROP_CANSLEEP, 675 "ari-enabled", NULL, 0); 676 677 ari_mode = B_TRUE; 678 max_function = PCICFG_MAX_ARI_FUNCTION; 679 } 680 } 681 } 682 if (ari_mode == B_TRUE) { 683 int next_function; 684 685 DEBUG0("Next Function - ARI Device\n"); 686 if (pcie_ari_get_next_function(new_device, 687 &next_function) != DDI_SUCCESS) 688 goto cleanup; 689 690 /* 691 * Check if there are more fucntions to probe. 692 */ 693 if (next_function == 0) { 694 DEBUG0("Next Function - " 695 "No more ARI Functions\n"); 696 break; 697 } 698 func = next_function; 699 } else { 700 func++; 701 } 702 DEBUG1("Next Function - %x\n", func); 703 } 704 705 ndi_devi_exit(devi, circ); 706 707 if (func == 0) 708 return (PCICFG_FAILURE); /* probe failed */ 709 else 710 return (PCICFG_SUCCESS); 711 712 cleanup: 713 /* 714 * Clean up a partially created "probe state" tree. 715 * There are no resources allocated to the in the 716 * probe state. 717 */ 718 719 for (func = 0; func < PCI_MAX_FUNCTIONS; func++) { 720 if ((function != PCICFG_ALL_FUNC) && (function != func)) 721 continue; 722 723 if ((new_device = pcicfg_devi_find(devi, device, func)) 724 == NULL) { 725 continue; 726 } 727 728 DEBUG2("Cleaning up device [0x%x] function [0x%x]\n", 729 device, func); 730 /* 731 * If this was a bridge device it will have a 732 * probe handle - if not, no harm in calling this. 733 */ 734 (void) pcicfg_destroy_phdl(new_device); 735 if (is_pcie) { 736 /* 737 * free pcie_bus_t for the sub-tree 738 */ 739 if (ddi_get_child(new_device) != NULL) 740 pcie_fab_fini_bus(new_device, PCIE_BUS_ALL); 741 742 pcie_fini_bus(new_device, PCIE_BUS_ALL); 743 } 744 /* 745 * This will free up the node 746 */ 747 (void) ndi_devi_offline(new_device, NDI_DEVI_REMOVE); 748 } 749 ndi_devi_exit(devi, circ); 750 751 /* 752 * Use private return codes to help identify issues without debugging 753 * enabled. Resource limitations and mis-configurations are 754 * probably the most likely caue of configuration failures on x86. 755 * Convert return code back to values expected by the external 756 * consumer before returning so we will warn only once on the first 757 * encountered failure. 758 */ 759 if (rv == PCICFG_NORESRC) { 760 char *path = kmem_alloc(MAXPATHLEN, KM_SLEEP); 761 762 (void) ddi_pathname(devi, path); 763 cmn_err(CE_CONT, "?Not enough PCI resources to " 764 "configure: %s\n", path); 765 766 kmem_free(path, MAXPATHLEN); 767 rv = PCICFG_FAILURE; 768 } 769 770 return (rv); 771 } 772 773 /* 774 * configure the child nodes of ntbridge. new_device points to ntbridge itself 775 */ 776 /*ARGSUSED*/ 777 static int 778 pcicfg_configure_ntbridge(dev_info_t *new_device, uint_t bus, uint_t device) 779 { 780 int bus_range[2], rc = PCICFG_FAILURE, rc1, max_devs = 0; 781 int devno; 782 dev_info_t *new_ntbridgechild; 783 ddi_acc_handle_t config_handle; 784 uint16_t vid; 785 uint64_t next_bus; 786 uint64_t blen; 787 ndi_ra_request_t req; 788 uint8_t pcie_device_type = 0; 789 790 /* 791 * If we need to do indirect config, lets create a property here 792 * to let the child conf map routine know that it has to 793 * go through the DDI calls, and not assume the devices are 794 * mapped directly under the host. 795 */ 796 if ((rc = ndi_prop_update_int(DDI_DEV_T_NONE, new_device, 797 PCI_DEV_CONF_MAP_PROP, (int)DDI_SUCCESS)) != DDI_SUCCESS) { 798 DEBUG0("Cannot create indirect conf map property.\n"); 799 return ((int)PCICFG_FAILURE); 800 } 801 802 if (pci_config_setup(new_device, &config_handle) != DDI_SUCCESS) 803 return (PCICFG_FAILURE); 804 /* check if we are PCIe device */ 805 if (pcicfg_pcie_device_type(new_device, config_handle) == DDI_SUCCESS) { 806 DEBUG0("PCIe device detected\n"); 807 pcie_device_type = 1; 808 } 809 pci_config_teardown(&config_handle); 810 /* create Bus node properties for ntbridge. */ 811 if (pcicfg_set_busnode_props(new_device, pcie_device_type) 812 != PCICFG_SUCCESS) { 813 DEBUG0("Failed to set busnode props\n"); 814 return (rc); 815 } 816 817 /* For now: Lets only support one layer of child */ 818 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 819 req.ra_len = 1; 820 if (ndi_ra_alloc(ddi_get_parent(new_device), &req, &next_bus, &blen, 821 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS) != NDI_SUCCESS) { 822 DEBUG0("ntbridge: Failed to get a bus number\n"); 823 return (PCICFG_NORESRC); 824 } 825 826 DEBUG1("ntbridge bus range start ->[%d]\n", next_bus); 827 828 /* 829 * Following will change, as we detect more bridges 830 * on the way. 831 */ 832 bus_range[0] = (int)next_bus; 833 bus_range[1] = (int)next_bus; 834 835 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, new_device, "bus-range", 836 bus_range, 2) != DDI_SUCCESS) { 837 DEBUG0("Cannot set ntbridge bus-range property"); 838 return (rc); 839 } 840 841 /* 842 * The other interface (away from the host) will be 843 * initialized by the nexus driver when it loads. 844 * We just have to set the registers and the nexus driver 845 * figures out the rest. 846 */ 847 848 /* 849 * finally, lets load and attach the driver 850 * before configuring children of ntbridge. 851 */ 852 rc = ndi_devi_online(new_device, NDI_ONLINE_ATTACH|NDI_CONFIG); 853 if (rc != NDI_SUCCESS) { 854 cmn_err(CE_WARN, 855 "pcicfg: Fail:cant load nontransparent bridgd driver..\n"); 856 rc = PCICFG_FAILURE; 857 return (rc); 858 } 859 DEBUG0("pcicfg: Success loading nontransparent bridge nexus driver.."); 860 861 /* Now set aside pci resource allocation requests for our children */ 862 if (pcicfg_ntbridge_allocate_resources(new_device) != PCICFG_SUCCESS) { 863 max_devs = 0; 864 rc = PCICFG_FAILURE; 865 } else 866 max_devs = PCI_MAX_DEVICES; 867 868 /* Probe devices on 2nd bus */ 869 rc = PCICFG_SUCCESS; 870 for (devno = pcicfg_start_devno; devno < max_devs; devno++) { 871 872 ndi_devi_alloc_sleep(new_device, DEVI_PSEUDO_NEXNAME, 873 (pnode_t)DEVI_SID_NODEID, &new_ntbridgechild); 874 875 if (pcicfg_add_config_reg(new_ntbridgechild, next_bus, devno, 0) 876 != DDI_PROP_SUCCESS) { 877 cmn_err(CE_WARN, 878 "Failed to add conf reg for ntbridge child.\n"); 879 (void) ndi_devi_free(new_ntbridgechild); 880 rc = PCICFG_FAILURE; 881 break; 882 } 883 884 if (pci_config_setup(new_ntbridgechild, &config_handle) 885 != DDI_SUCCESS) { 886 cmn_err(CE_WARN, 887 "Cannot map ntbridge child %x\n", devno); 888 (void) ndi_devi_free(new_ntbridgechild); 889 rc = PCICFG_FAILURE; 890 break; 891 } 892 893 /* 894 * See if there is any PCI HW at this location 895 * by reading the Vendor ID. If it returns with 0xffff 896 * then there is no hardware at this location. 897 */ 898 vid = pci_config_get16(config_handle, PCI_CONF_VENID); 899 900 pci_config_teardown(&config_handle); 901 (void) ndi_devi_free(new_ntbridgechild); 902 if (vid == 0xffff) 903 continue; 904 905 /* Lets fake attachments points for each child, */ 906 rc = pcicfg_configure(new_device, devno, PCICFG_ALL_FUNC, 0); 907 if (rc != PCICFG_SUCCESS) { 908 int old_dev = pcicfg_start_devno; 909 910 cmn_err(CE_WARN, 911 "Error configuring ntbridge child dev=%d\n", devno); 912 913 while (old_dev != devno) { 914 if (pcicfg_ntbridge_unconfigure_child( 915 new_device, old_dev) == PCICFG_FAILURE) 916 cmn_err(CE_WARN, "Unconfig Error " 917 "ntbridge child dev=%d\n", old_dev); 918 old_dev++; 919 } 920 break; 921 } 922 } /* devno loop */ 923 DEBUG1("ntbridge: finish probing 2nd bus, rc=%d\n", rc); 924 925 if (rc == PCICFG_SUCCESS) 926 rc = pcicfg_ntbridge_configure_done(new_device); 927 else { 928 pcicfg_phdl_t *entry = pcicfg_find_phdl(new_device); 929 uint_t *bus; 930 int k; 931 932 if (ddi_getlongprop(DDI_DEV_T_ANY, new_device, 933 DDI_PROP_DONTPASS, "bus-range", (caddr_t)&bus, &k) 934 != DDI_PROP_SUCCESS) { 935 DEBUG0("Failed to read bus-range property\n"); 936 rc = PCICFG_FAILURE; 937 return (rc); 938 } 939 940 DEBUG2("Need to free bus [%d] range [%d]\n", 941 bus[0], bus[1] - bus[0] + 1); 942 943 if (ndi_ra_free(ddi_get_parent(new_device), (uint64_t)bus[0], 944 (uint64_t)(bus[1] - bus[0] + 1), NDI_RA_TYPE_PCI_BUSNUM, 945 NDI_RA_PASS) != NDI_SUCCESS) { 946 DEBUG0("Failed to free a bus number\n"); 947 rc = PCICFG_FAILURE; 948 kmem_free(bus, k); 949 return (rc); 950 } 951 952 /* 953 * Since no memory allocations are done for non transparent 954 * bridges (but instead we just set the handle with the 955 * already allocated memory, we just need to reset the 956 * following values before calling the destroy_phdl() 957 * function next, otherwise the it will try to free 958 * memory allocated as in case of a transparent bridge. 959 */ 960 entry->memory_len = 0; 961 entry->pf_memory_len = 0; 962 entry->io_len = 0; 963 kmem_free(bus, k); 964 /* the following will free hole data. */ 965 (void) pcicfg_destroy_phdl(new_device); 966 } 967 968 /* 969 * Unload driver just in case child configure failed! 970 */ 971 rc1 = ndi_devi_offline(new_device, 0); 972 DEBUG1("pcicfg: now unloading the ntbridge driver. rc1=%d\n", rc1); 973 if (rc1 != NDI_SUCCESS) { 974 cmn_err(CE_WARN, 975 "pcicfg: cant unload ntbridge driver..children.\n"); 976 rc = PCICFG_FAILURE; 977 } 978 979 return (rc); 980 } 981 982 static int 983 pcicfg_ntbridge_allocate_resources(dev_info_t *dip) 984 { 985 pcicfg_phdl_t *phdl; 986 ndi_ra_request_t *mem_request; 987 ndi_ra_request_t *pf_mem_request; 988 ndi_ra_request_t *io_request; 989 uint64_t boundbase, boundlen; 990 991 phdl = pcicfg_find_phdl(dip); 992 ASSERT(phdl); 993 994 mem_request = &phdl->mem_req; 995 pf_mem_request = &phdl->pf_mem_req; 996 io_request = &phdl->io_req; 997 998 phdl->error = PCICFG_SUCCESS; 999 1000 /* Set Memory space handle for ntbridge */ 1001 if (pcicfg_get_ntbridge_child_range(dip, &boundbase, &boundlen, 1002 PCI_BASE_SPACE_MEM) != DDI_SUCCESS) { 1003 cmn_err(CE_WARN, 1004 "ntbridge: Mem resource information failure\n"); 1005 phdl->memory_len = 0; 1006 return (PCICFG_FAILURE); 1007 } 1008 mem_request->ra_boundbase = boundbase; 1009 mem_request->ra_boundlen = boundbase + boundlen; 1010 mem_request->ra_len = boundlen; 1011 mem_request->ra_align_mask = 1012 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ 1013 mem_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 1014 1015 /* 1016 * mem_request->ra_len = 1017 * PCICFG_ROUND_UP(mem_request->ra_len, PCICFG_MEMGRAN); 1018 */ 1019 1020 phdl->memory_base = phdl->memory_last = boundbase; 1021 phdl->memory_len = boundlen; 1022 phdl->mem_hole.start = phdl->memory_base; 1023 phdl->mem_hole.len = mem_request->ra_len; 1024 phdl->mem_hole.next = (hole_t *)NULL; 1025 1026 DEBUG2("Connector requested [0x%llx], needs [0x%llx] bytes of memory\n", 1027 boundlen, mem_request->ra_len); 1028 1029 /* Set IO space handle for ntbridge */ 1030 if (pcicfg_get_ntbridge_child_range(dip, &boundbase, &boundlen, 1031 PCI_BASE_SPACE_IO) != DDI_SUCCESS) { 1032 cmn_err(CE_WARN, "ntbridge: IO resource information failure\n"); 1033 phdl->io_len = 0; 1034 return (PCICFG_FAILURE); 1035 } 1036 io_request->ra_len = boundlen; 1037 io_request->ra_align_mask = 1038 PCICFG_IOGRAN - 1; /* 4K alignment on I/O space */ 1039 io_request->ra_boundbase = boundbase; 1040 io_request->ra_boundlen = boundbase + boundlen; 1041 io_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 1042 1043 /* 1044 * io_request->ra_len = 1045 * PCICFG_ROUND_UP(io_request->ra_len, PCICFG_IOGRAN); 1046 */ 1047 1048 phdl->io_base = phdl->io_last = (uint32_t)boundbase; 1049 phdl->io_len = (uint32_t)boundlen; 1050 phdl->io_hole.start = phdl->io_base; 1051 phdl->io_hole.len = io_request->ra_len; 1052 phdl->io_hole.next = (hole_t *)NULL; 1053 1054 DEBUG2("Connector requested [0x%llx], needs [0x%llx] bytes of IO\n", 1055 boundlen, io_request->ra_len); 1056 1057 /* Set Prefetchable Memory space handle for ntbridge */ 1058 if (pcicfg_get_ntbridge_child_range(dip, &boundbase, &boundlen, 1059 PCI_BASE_SPACE_MEM | PCI_BASE_PREF_M) != DDI_SUCCESS) { 1060 cmn_err(CE_WARN, 1061 "ntbridge: PF Mem resource information failure\n"); 1062 phdl->pf_memory_len = 0; 1063 return (PCICFG_FAILURE); 1064 } 1065 pf_mem_request->ra_boundbase = boundbase; 1066 pf_mem_request->ra_boundlen = boundbase + boundlen; 1067 pf_mem_request->ra_len = boundlen; 1068 pf_mem_request->ra_align_mask = 1069 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ 1070 pf_mem_request->ra_flags |= NDI_RA_ALLOC_BOUNDED; 1071 1072 /* 1073 * pf_mem_request->ra_len = 1074 * PCICFG_ROUND_UP(pf_mem_request->ra_len, PCICFG_MEMGRAN); 1075 */ 1076 1077 phdl->pf_memory_base = phdl->pf_memory_last = boundbase; 1078 phdl->pf_memory_len = boundlen; 1079 phdl->pf_mem_hole.start = phdl->pf_memory_base; 1080 phdl->pf_mem_hole.len = pf_mem_request->ra_len; 1081 phdl->pf_mem_hole.next = (hole_t *)NULL; 1082 1083 DEBUG2("Connector requested [0x%llx], needs [0x%llx] bytes of PF " 1084 "memory\n", boundlen, pf_mem_request->ra_len); 1085 1086 DEBUG2("MEMORY BASE = [0x%lx] length [0x%lx]\n", 1087 phdl->memory_base, phdl->memory_len); 1088 DEBUG2("IO BASE = [0x%x] length [0x%x]\n", 1089 phdl->io_base, phdl->io_len); 1090 DEBUG2("PF MEMORY BASE = [0x%lx] length [0x%lx]\n", 1091 phdl->pf_memory_base, phdl->pf_memory_len); 1092 1093 return (PCICFG_SUCCESS); 1094 } 1095 1096 static int 1097 pcicfg_ntbridge_configure_done(dev_info_t *dip) 1098 { 1099 ppb_ranges_t range[PCICFG_RANGE_LEN]; 1100 pcicfg_phdl_t *entry; 1101 uint_t len; 1102 pci_bus_range_t bus_range; 1103 int new_bus_range[2]; 1104 1105 DEBUG1("Configuring children for %p\n", dip); 1106 1107 entry = pcicfg_find_phdl(dip); 1108 ASSERT(entry); 1109 1110 bzero((caddr_t)range, sizeof (ppb_ranges_t) * PCICFG_RANGE_LEN); 1111 range[1].child_high = range[1].parent_high |= 1112 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1113 range[1].child_low = range[1].parent_low = (uint32_t)entry->memory_base; 1114 1115 range[0].child_high = range[0].parent_high |= 1116 (PCI_REG_REL_M | PCI_ADDR_IO); 1117 range[0].child_low = range[0].parent_low = (uint32_t)entry->io_base; 1118 1119 range[2].child_high = range[2].parent_high |= 1120 (PCI_REG_REL_M | PCI_ADDR_MEM32 | PCI_REG_PF_M); 1121 range[2].child_low = range[2].parent_low = 1122 (uint32_t)entry->pf_memory_base; 1123 1124 len = sizeof (pci_bus_range_t); 1125 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1126 "bus-range", (caddr_t)&bus_range, (int *)&len) != DDI_SUCCESS) { 1127 DEBUG0("no bus-range property\n"); 1128 return (PCICFG_FAILURE); 1129 } 1130 1131 new_bus_range[0] = bus_range.lo; /* primary bus number */ 1132 if (entry->highest_bus) { /* secondary bus number */ 1133 if (entry->highest_bus < bus_range.lo) { 1134 cmn_err(CE_WARN, 1135 "ntbridge bus range invalid !(%d,%d)\n", 1136 bus_range.lo, entry->highest_bus); 1137 new_bus_range[1] = bus_range.lo + entry->highest_bus; 1138 } 1139 else 1140 new_bus_range[1] = entry->highest_bus; 1141 } 1142 else 1143 new_bus_range[1] = bus_range.hi; 1144 1145 DEBUG2("ntbridge: bus range lo=%x, hi=%x\n", new_bus_range[0], 1146 new_bus_range[1]); 1147 1148 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "bus-range", 1149 new_bus_range, 2) != DDI_SUCCESS) { 1150 DEBUG0("Failed to set bus-range property"); 1151 entry->error = PCICFG_FAILURE; 1152 return (PCICFG_FAILURE); 1153 } 1154 1155 #ifdef DEBUG 1156 { 1157 uint64_t unused; 1158 unused = pcicfg_unused_space(&entry->io_hole, &len); 1159 DEBUG2("ntbridge: Unused IO space %llx bytes over %d holes\n", 1160 unused, len); 1161 } 1162 #endif 1163 1164 range[0].size_low = entry->io_len; 1165 if (pcicfg_update_ranges_prop(dip, &range[0])) { 1166 DEBUG0("Failed to update ranges (i/o)\n"); 1167 entry->error = PCICFG_FAILURE; 1168 return (PCICFG_FAILURE); 1169 } 1170 1171 #ifdef DEBUG 1172 { 1173 uint64_t unused; 1174 unused = pcicfg_unused_space(&entry->mem_hole, &len); 1175 DEBUG2("ntbridge: Unused Mem space %llx bytes over %d holes\n", 1176 unused, len); 1177 } 1178 #endif 1179 1180 range[1].size_low = entry->memory_len; 1181 if (pcicfg_update_ranges_prop(dip, &range[1])) { 1182 DEBUG0("Failed to update ranges (memory)\n"); 1183 entry->error = PCICFG_FAILURE; 1184 return (PCICFG_FAILURE); 1185 } 1186 1187 #ifdef DEBUG 1188 { 1189 uint64_t unused; 1190 unused = pcicfg_unused_space(&entry->pf_mem_hole, &len); 1191 DEBUG2("ntbridge: Unused PF Mem space %llx bytes over" 1192 " %d holes\n", unused, len); 1193 } 1194 #endif 1195 1196 range[2].size_low = entry->pf_memory_len; 1197 if (pcicfg_update_ranges_prop(dip, &range[2])) { 1198 DEBUG0("Failed to update ranges (PF memory)\n"); 1199 entry->error = PCICFG_FAILURE; 1200 return (PCICFG_FAILURE); 1201 } 1202 1203 return (PCICFG_SUCCESS); 1204 } 1205 1206 static int 1207 pcicfg_ntbridge_program_child(dev_info_t *dip) 1208 { 1209 pcicfg_phdl_t *entry; 1210 int rc = PCICFG_SUCCESS; 1211 dev_info_t *anode = dip; 1212 1213 /* Find the Hotplug Connection (CN) node */ 1214 while ((anode != NULL) && 1215 (strcmp(ddi_binding_name(anode), "hp_attachment") != 0)) { 1216 anode = ddi_get_parent(anode); 1217 } 1218 1219 if (anode == NULL) { 1220 DEBUG0("ntbridge child tree not in PROBE state\n"); 1221 return (PCICFG_FAILURE); 1222 } 1223 entry = pcicfg_find_phdl(ddi_get_parent(anode)); 1224 ASSERT(entry); 1225 1226 if (pcicfg_bridge_assign(dip, entry) == DDI_WALK_TERMINATE) { 1227 cmn_err(CE_WARN, 1228 "ntbridge: Error assigning range for child %s\n", 1229 ddi_get_name(dip)); 1230 rc = PCICFG_FAILURE; 1231 } 1232 return (rc); 1233 } 1234 1235 static int 1236 pcicfg_ntbridge_unconfigure_child(dev_info_t *new_device, uint_t devno) 1237 { 1238 1239 dev_info_t *new_ntbridgechild; 1240 int len, bus; 1241 uint16_t vid; 1242 ddi_acc_handle_t config_handle; 1243 pci_bus_range_t pci_bus_range; 1244 1245 len = sizeof (pci_bus_range_t); 1246 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, new_device, DDI_PROP_DONTPASS, 1247 "bus-range", (caddr_t)&pci_bus_range, &len) != DDI_SUCCESS) { 1248 DEBUG0("no bus-range property\n"); 1249 return (PCICFG_FAILURE); 1250 } 1251 1252 bus = pci_bus_range.lo; /* primary bus number of this bus node */ 1253 1254 ndi_devi_alloc_sleep(new_device, DEVI_PSEUDO_NEXNAME, 1255 (pnode_t)DEVI_SID_NODEID, &new_ntbridgechild); 1256 1257 if (pcicfg_add_config_reg(new_ntbridgechild, bus, devno, 0) 1258 != DDI_PROP_SUCCESS) { 1259 cmn_err(CE_WARN, "Unconfigure: Failed to add conf reg prop for " 1260 "ntbridge child.\n"); 1261 (void) ndi_devi_free(new_ntbridgechild); 1262 return (PCICFG_FAILURE); 1263 } 1264 1265 if (pci_config_setup(new_ntbridgechild, &config_handle) 1266 != DDI_SUCCESS) { 1267 cmn_err(CE_WARN, "pcicfg: Cannot map ntbridge child %x\n", 1268 devno); 1269 (void) ndi_devi_free(new_ntbridgechild); 1270 return (PCICFG_FAILURE); 1271 } 1272 1273 /* 1274 * See if there is any PCI HW at this location 1275 * by reading the Vendor ID. If it returns with 0xffff 1276 * then there is no hardware at this location. 1277 */ 1278 vid = pci_config_get16(config_handle, PCI_CONF_VENID); 1279 1280 pci_config_teardown(&config_handle); 1281 (void) ndi_devi_free(new_ntbridgechild); 1282 if (vid == 0xffff) 1283 return (PCICFG_NODEVICE); 1284 1285 return (pcicfg_unconfigure(new_device, devno, PCICFG_ALL_FUNC, 0)); 1286 } 1287 1288 static uint_t 1289 pcicfg_ntbridge_unconfigure(dev_info_t *dip) 1290 { 1291 pcicfg_phdl_t *entry = pcicfg_find_phdl(dip); 1292 uint_t *bus; 1293 int k, rc = DDI_FAILURE; 1294 1295 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "bus-range", 1296 (caddr_t)&bus, &k) != DDI_PROP_SUCCESS) { 1297 DEBUG0("ntbridge: Failed to read bus-range property\n"); 1298 return (rc); 1299 } 1300 1301 DEBUG2("ntbridge: Need to free bus [%d] range [%d]\n", 1302 bus[0], bus[1] - bus[0] + 1); 1303 1304 if (ndi_ra_free(ddi_get_parent(dip), (uint64_t)bus[0], 1305 (uint64_t)(bus[1] - bus[0] + 1), 1306 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS) != NDI_SUCCESS) { 1307 DEBUG0("ntbridge: Failed to free a bus number\n"); 1308 kmem_free(bus, k); 1309 return (rc); 1310 } 1311 1312 /* 1313 * Since our resources will be freed at the parent level, 1314 * just reset these values. 1315 */ 1316 entry->memory_len = 0; 1317 entry->io_len = 0; 1318 entry->pf_memory_len = 0; 1319 1320 kmem_free(bus, k); 1321 1322 /* the following will also free hole data. */ 1323 return (pcicfg_destroy_phdl(dip)); 1324 1325 } 1326 1327 static int 1328 pcicfg_is_ntbridge(dev_info_t *dip) 1329 { 1330 ddi_acc_handle_t config_handle; 1331 uint8_t class, subclass; 1332 int rc = DDI_SUCCESS; 1333 1334 if (pci_config_setup(dip, &config_handle) != DDI_SUCCESS) { 1335 cmn_err(CE_WARN, 1336 "pcicfg: cannot map config space, to get map type\n"); 1337 return (DDI_FAILURE); 1338 } 1339 class = pci_config_get8(config_handle, PCI_CONF_BASCLASS); 1340 subclass = pci_config_get8(config_handle, PCI_CONF_SUBCLASS); 1341 1342 /* check for class=6, subclass=9, for non transparent bridges. */ 1343 if ((class != PCI_CLASS_BRIDGE) || (subclass != PCI_BRIDGE_STBRIDGE)) 1344 rc = DDI_FAILURE; 1345 1346 DEBUG3("pcicfg: checking device %x,%x for indirect map. rc=%d\n", 1347 pci_config_get16(config_handle, PCI_CONF_VENID), 1348 pci_config_get16(config_handle, PCI_CONF_DEVID), 1349 rc); 1350 pci_config_teardown(&config_handle); 1351 return (rc); 1352 } 1353 1354 static uint_t 1355 pcicfg_ntbridge_child(dev_info_t *dip) 1356 { 1357 int len, val, rc = DDI_FAILURE; 1358 dev_info_t *anode = dip; 1359 1360 /* 1361 * Find the Hotplug Connection (CN) node 1362 */ 1363 while ((anode != NULL) && (strcmp(ddi_binding_name(anode), 1364 "hp_attachment") != 0)) { 1365 anode = ddi_get_parent(anode); 1366 } 1367 1368 if (anode == NULL) { 1369 DEBUG0("ntbridge child tree not in PROBE state\n"); 1370 return (rc); 1371 } 1372 len = sizeof (int); 1373 if (ddi_getlongprop_buf(DDI_DEV_T_ANY, ddi_get_parent(anode), 1374 DDI_PROP_DONTPASS, PCI_DEV_CONF_MAP_PROP, (caddr_t)&val, &len) 1375 != DDI_SUCCESS) { 1376 1377 DEBUG1("ntbridge child: no \"%s\" property\n", 1378 PCI_DEV_CONF_MAP_PROP); 1379 return (rc); 1380 } 1381 DEBUG0("ntbridge child: success\n"); 1382 return (DDI_SUCCESS); 1383 } 1384 1385 static uint_t 1386 pcicfg_get_ntbridge_child_range(dev_info_t *dip, uint64_t *boundbase, 1387 uint64_t *boundlen, uint_t space_type) 1388 { 1389 int length, found = DDI_FAILURE, acount, i, ibridge; 1390 pci_regspec_t *assigned; 1391 1392 if ((ibridge = pcicfg_is_ntbridge(dip)) == DDI_FAILURE) 1393 return (found); 1394 1395 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 1396 "assigned-addresses", (caddr_t)&assigned, &length) 1397 != DDI_PROP_SUCCESS) { 1398 DEBUG1("Failed to get assigned-addresses property %llx\n", dip); 1399 return (found); 1400 } 1401 DEBUG1("pcicfg: ntbridge child range: dip = %s\n", 1402 ddi_driver_name(dip)); 1403 1404 acount = length / sizeof (pci_regspec_t); 1405 1406 for (i = 0; i < acount; i++) { 1407 if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == 1408 pcicfg_indirect_map_devs[ibridge].mem_range_bar_offset) && 1409 (space_type == PCI_BASE_SPACE_MEM)) { 1410 found = DDI_SUCCESS; 1411 break; 1412 } else if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == 1413 pcicfg_indirect_map_devs[ibridge].io_range_bar_offset) && 1414 (space_type == PCI_BASE_SPACE_IO)) { 1415 found = DDI_SUCCESS; 1416 break; 1417 } else if ((PCI_REG_REG_G(assigned[i].pci_phys_hi) == 1418 pcicfg_indirect_map_devs[ibridge]. 1419 prefetch_mem_range_bar_offset) && 1420 (space_type == (PCI_BASE_SPACE_MEM | 1421 PCI_BASE_PREF_M))) { 1422 found = DDI_SUCCESS; 1423 break; 1424 } 1425 } 1426 DEBUG3("pcicfg: ntbridge child range: space=%x, base=%lx, len=%lx\n", 1427 space_type, assigned[i].pci_phys_low, assigned[i].pci_size_low); 1428 1429 if (found == DDI_SUCCESS) { 1430 *boundbase = assigned[i].pci_phys_low; 1431 *boundlen = assigned[i].pci_size_low; 1432 } 1433 1434 kmem_free(assigned, length); 1435 return (found); 1436 } 1437 1438 /* 1439 * This will turn resources allocated by pcicfg_configure() 1440 * and remove the device tree from the Hotplug Connection (CN) 1441 * and below. The routine assumes the devices have their 1442 * drivers detached. 1443 */ 1444 int 1445 pcicfg_unconfigure(dev_info_t *devi, uint_t device, uint_t function, 1446 pcicfg_flags_t flags) 1447 { 1448 dev_info_t *child_dip; 1449 int func; 1450 int i; 1451 int max_function, trans_device; 1452 int circ; 1453 boolean_t is_pcie; 1454 1455 if (pcie_ari_is_enabled(devi) == PCIE_ARI_FORW_ENABLED) 1456 max_function = PCICFG_MAX_ARI_FUNCTION; 1457 else 1458 max_function = PCI_MAX_FUNCTIONS; 1459 1460 /* 1461 * Cycle through devices to make sure none are busy. 1462 * If a single device is busy fail the whole unconfigure. 1463 */ 1464 is_pcie = is_pcie_fabric(devi); 1465 1466 ndi_devi_enter(devi, &circ); 1467 for (func = 0; func < max_function; func++) { 1468 if ((function != PCICFG_ALL_FUNC) && (function != func)) 1469 continue; 1470 1471 if (max_function == PCICFG_MAX_ARI_FUNCTION) 1472 trans_device = func >> 3; /* ARI Device */ 1473 else 1474 trans_device = device; 1475 1476 if ((child_dip = pcicfg_devi_find(devi, trans_device, 1477 func & 7)) == NULL) 1478 continue; 1479 1480 if (ndi_devi_offline(child_dip, NDI_UNCONFIG) == NDI_SUCCESS) 1481 continue; 1482 1483 /* 1484 * Device function is busy. Before returning we have to 1485 * put all functions back online which were taken 1486 * offline during the process. 1487 */ 1488 DEBUG2("Device [0x%x] function [0x%x] is busy\n", 1489 trans_device, func & 7); 1490 /* 1491 * If we are only asked to offline one specific function, 1492 * and that fails, we just simply return. 1493 */ 1494 if (function != PCICFG_ALL_FUNC) 1495 return (PCICFG_FAILURE); 1496 1497 for (i = 0; i < func; i++) { 1498 if (max_function == PCICFG_MAX_ARI_FUNCTION) 1499 trans_device = i >> 3; 1500 1501 if ((child_dip = pcicfg_devi_find(devi, trans_device, 1502 i & 7)) == NULL) { 1503 DEBUG0("No more devices to put back " 1504 "on line!!\n"); 1505 /* 1506 * Made it through all functions 1507 */ 1508 continue; 1509 } 1510 if (ndi_devi_online(child_dip, NDI_CONFIG) 1511 != NDI_SUCCESS) { 1512 DEBUG0("Failed to put back devices state\n"); 1513 goto fail; 1514 } 1515 } 1516 goto fail; 1517 } 1518 1519 /* 1520 * Now, tear down all devinfo nodes for this Connector. 1521 */ 1522 for (func = 0; func < max_function; func++) { 1523 if ((function != PCICFG_ALL_FUNC) && (function != func)) 1524 continue; 1525 1526 if (max_function == PCICFG_MAX_ARI_FUNCTION) 1527 trans_device = func >> 3; /* ARI Device */ 1528 else 1529 trans_device = device; 1530 1531 if ((child_dip = pcicfg_devi_find(devi, trans_device, func & 7)) 1532 == NULL) { 1533 DEBUG2("No device at %x,%x\n", trans_device, func & 7); 1534 continue; 1535 } 1536 1537 DEBUG2("Tearing down device [0x%x] function [0x%x]\n", 1538 trans_device, func & 7); 1539 1540 if (pcicfg_is_ntbridge(child_dip) != DDI_FAILURE) 1541 if (pcicfg_ntbridge_unconfigure(child_dip) != 1542 PCICFG_SUCCESS) { 1543 cmn_err(CE_WARN, 1544 "ntbridge: unconfigure failed\n"); 1545 goto fail; 1546 } 1547 1548 if (pcicfg_teardown_device(child_dip, flags, is_pcie) 1549 != PCICFG_SUCCESS) { 1550 DEBUG2("Failed to tear down device [0x%x]" 1551 "function [0x%x]\n", trans_device, func & 7); 1552 goto fail; 1553 } 1554 } 1555 1556 if (pcie_ari_is_enabled(devi) == PCIE_ARI_FORW_ENABLED) { 1557 (void) ddi_prop_remove(DDI_DEV_T_NONE, devi, "ari-enabled"); 1558 (void) pcie_ari_disable(devi); 1559 } 1560 1561 ndi_devi_exit(devi, circ); 1562 return (PCICFG_SUCCESS); 1563 1564 fail: 1565 ndi_devi_exit(devi, circ); 1566 return (PCICFG_FAILURE); 1567 } 1568 1569 static int 1570 pcicfg_teardown_device(dev_info_t *dip, pcicfg_flags_t flags, boolean_t is_pcie) 1571 { 1572 ddi_acc_handle_t handle; 1573 1574 /* 1575 * Free up resources associated with 'dip' 1576 */ 1577 if (pcicfg_free_resources(dip, flags) != PCICFG_SUCCESS) { 1578 DEBUG0("Failed to free resources\n"); 1579 return (PCICFG_FAILURE); 1580 } 1581 1582 /* 1583 * disable the device 1584 */ 1585 if (pcicfg_config_setup(dip, &handle) != PCICFG_SUCCESS) 1586 return (PCICFG_FAILURE); 1587 pcicfg_device_off(handle); 1588 pcicfg_config_teardown(&handle); 1589 1590 if (is_pcie) { 1591 /* 1592 * free pcie_bus_t for the sub-tree 1593 */ 1594 if (ddi_get_child(dip) != NULL) 1595 pcie_fab_fini_bus(dip, PCIE_BUS_ALL); 1596 1597 pcie_fini_bus(dip, PCIE_BUS_ALL); 1598 } 1599 1600 /* 1601 * The framework provides this routine which can 1602 * tear down a sub-tree. 1603 */ 1604 if (ndi_devi_offline(dip, NDI_DEVI_REMOVE) != NDI_SUCCESS) { 1605 DEBUG0("Failed to offline and remove node\n"); 1606 return (PCICFG_FAILURE); 1607 } 1608 1609 return (PCICFG_SUCCESS); 1610 } 1611 1612 /* 1613 * BEGIN GENERIC SUPPORT ROUTINES 1614 */ 1615 static pcicfg_phdl_t * 1616 pcicfg_find_phdl(dev_info_t *dip) 1617 { 1618 pcicfg_phdl_t *entry; 1619 mutex_enter(&pcicfg_list_mutex); 1620 for (entry = pcicfg_phdl_list; entry != NULL; entry = entry->next) { 1621 if (entry->dip == dip) { 1622 mutex_exit(&pcicfg_list_mutex); 1623 return (entry); 1624 } 1625 } 1626 mutex_exit(&pcicfg_list_mutex); 1627 1628 /* 1629 * Did'nt find entry - create one 1630 */ 1631 return (pcicfg_create_phdl(dip)); 1632 } 1633 1634 static pcicfg_phdl_t * 1635 pcicfg_create_phdl(dev_info_t *dip) 1636 { 1637 pcicfg_phdl_t *new; 1638 1639 new = (pcicfg_phdl_t *)kmem_zalloc(sizeof (pcicfg_phdl_t), KM_SLEEP); 1640 1641 new->dip = dip; 1642 mutex_enter(&pcicfg_list_mutex); 1643 new->next = pcicfg_phdl_list; 1644 pcicfg_phdl_list = new; 1645 mutex_exit(&pcicfg_list_mutex); 1646 1647 return (new); 1648 } 1649 1650 static int 1651 pcicfg_destroy_phdl(dev_info_t *dip) 1652 { 1653 pcicfg_phdl_t *entry; 1654 pcicfg_phdl_t *follow = NULL; 1655 1656 mutex_enter(&pcicfg_list_mutex); 1657 for (entry = pcicfg_phdl_list; entry != NULL; follow = entry, 1658 entry = entry->next) { 1659 if (entry->dip == dip) { 1660 if (entry == pcicfg_phdl_list) { 1661 pcicfg_phdl_list = entry->next; 1662 } else { 1663 follow->next = entry->next; 1664 } 1665 /* 1666 * If this entry has any allocated memory 1667 * or IO space associated with it, that 1668 * must be freed up. 1669 */ 1670 if (entry->memory_len > 0) { 1671 (void) ndi_ra_free(ddi_get_parent(dip), 1672 entry->memory_base, entry->memory_len, 1673 NDI_RA_TYPE_MEM, NDI_RA_PASS); 1674 } 1675 pcicfg_free_hole(&entry->mem_hole); 1676 1677 if (entry->io_len > 0) { 1678 (void) ndi_ra_free(ddi_get_parent(dip), 1679 entry->io_base, entry->io_len, 1680 NDI_RA_TYPE_IO, NDI_RA_PASS); 1681 } 1682 pcicfg_free_hole(&entry->io_hole); 1683 1684 if (entry->pf_memory_len > 0) { 1685 (void) ndi_ra_free(ddi_get_parent(dip), 1686 entry->pf_memory_base, entry->pf_memory_len, 1687 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 1688 } 1689 pcicfg_free_hole(&entry->pf_mem_hole); 1690 1691 /* 1692 * Destroy this entry 1693 */ 1694 kmem_free((caddr_t)entry, sizeof (pcicfg_phdl_t)); 1695 mutex_exit(&pcicfg_list_mutex); 1696 return (PCICFG_SUCCESS); 1697 } 1698 } 1699 mutex_exit(&pcicfg_list_mutex); 1700 /* 1701 * Did'nt find the entry 1702 */ 1703 return (PCICFG_FAILURE); 1704 } 1705 1706 static int 1707 pcicfg_bridge_assign(dev_info_t *dip, void *hdl) 1708 { 1709 ddi_acc_handle_t handle; 1710 pci_regspec_t *reg; 1711 int length; 1712 int rcount; 1713 int i; 1714 int offset; 1715 uint64_t mem_answer; 1716 uint32_t io_answer; 1717 int count; 1718 uint8_t header_type; 1719 ppb_ranges_t range[PCICFG_RANGE_LEN]; 1720 int bus_range[2]; 1721 uint64_t mem_residual; 1722 uint64_t pf_mem_residual; 1723 uint64_t io_residual; 1724 1725 pcicfg_phdl_t *entry = (pcicfg_phdl_t *)hdl; 1726 1727 DEBUG1("bridge assign: assigning addresses to %s\n", ddi_get_name(dip)); 1728 1729 entry->error = PCICFG_SUCCESS; 1730 1731 if (entry == NULL) { 1732 DEBUG0("Failed to get entry\n"); 1733 entry->error = PCICFG_FAILURE; 1734 return (DDI_WALK_TERMINATE); 1735 } 1736 1737 if (pcicfg_config_setup(dip, &handle) != DDI_SUCCESS) { 1738 DEBUG0("Failed to map config space!\n"); 1739 entry->error = PCICFG_FAILURE; 1740 return (DDI_WALK_TERMINATE); 1741 } 1742 1743 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 1744 1745 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 1746 1747 bzero((caddr_t)range, sizeof (ppb_ranges_t) * PCICFG_RANGE_LEN); 1748 1749 (void) pcicfg_setup_bridge(entry, handle); 1750 1751 range[0].child_high = range[0].parent_high |= 1752 (PCI_REG_REL_M | PCI_ADDR_IO); 1753 range[0].child_low = range[0].parent_low = entry->io_last; 1754 range[1].child_high = range[1].parent_high |= 1755 (PCI_REG_REL_M | PCI_ADDR_MEM32); 1756 range[1].child_low = range[1].parent_low = 1757 entry->memory_last; 1758 range[2].child_high = range[2].parent_high |= 1759 (PCI_REG_REL_M | PCI_ADDR_MEM32 | PCI_REG_PF_M); 1760 range[2].child_low = range[2].parent_low = 1761 entry->pf_memory_last; 1762 1763 ndi_devi_enter(dip, &count); 1764 ddi_walk_devs(ddi_get_child(dip), 1765 pcicfg_bridge_assign, (void *)entry); 1766 ndi_devi_exit(dip, count); 1767 1768 (void) pcicfg_update_bridge(entry, handle); 1769 1770 bus_range[0] = pci_config_get8(handle, PCI_BCNF_SECBUS); 1771 bus_range[1] = pci_config_get8(handle, PCI_BCNF_SUBBUS); 1772 1773 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 1774 "bus-range", bus_range, 2) != DDI_SUCCESS) { 1775 DEBUG0("Failed to set bus-range property"); 1776 entry->error = PCICFG_FAILURE; 1777 (void) pcicfg_config_teardown(&handle); 1778 return (DDI_WALK_TERMINATE); 1779 } 1780 1781 /* 1782 * Put back memory and I/O space not allocated 1783 * under the bridge. 1784 */ 1785 mem_residual = entry->memory_len - 1786 (entry->memory_last - entry->memory_base); 1787 if (mem_residual > 0) { 1788 (void) ndi_ra_free(ddi_get_parent(dip), 1789 entry->memory_last, mem_residual, 1790 NDI_RA_TYPE_MEM, NDI_RA_PASS); 1791 } 1792 1793 io_residual = entry->io_len - (entry->io_last - entry->io_base); 1794 if (io_residual > 0) { 1795 (void) ndi_ra_free(ddi_get_parent(dip), entry->io_last, 1796 io_residual, NDI_RA_TYPE_IO, NDI_RA_PASS); 1797 } 1798 1799 pf_mem_residual = entry->pf_memory_len - 1800 (entry->pf_memory_last - entry->pf_memory_base); 1801 if (pf_mem_residual > 0) { 1802 (void) ndi_ra_free(ddi_get_parent(dip), 1803 entry->pf_memory_last, pf_mem_residual, 1804 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 1805 } 1806 1807 if (entry->io_len > 0) { 1808 range[0].size_low = entry->io_last - entry->io_base; 1809 if (pcicfg_update_ranges_prop(dip, &range[0])) { 1810 DEBUG0("Failed to update ranges (i/o)\n"); 1811 entry->error = PCICFG_FAILURE; 1812 (void) pcicfg_config_teardown(&handle); 1813 return (DDI_WALK_TERMINATE); 1814 } 1815 } 1816 if (entry->memory_len > 0) { 1817 range[1].size_low = 1818 entry->memory_last - entry->memory_base; 1819 if (pcicfg_update_ranges_prop(dip, &range[1])) { 1820 DEBUG0("Failed to update ranges (memory)\n"); 1821 entry->error = PCICFG_FAILURE; 1822 (void) pcicfg_config_teardown(&handle); 1823 return (DDI_WALK_TERMINATE); 1824 } 1825 } 1826 if (entry->pf_memory_len > 0) { 1827 range[2].size_low = 1828 entry->pf_memory_last - entry->pf_memory_base; 1829 if (pcicfg_update_ranges_prop(dip, &range[2])) { 1830 DEBUG0("Failed to update ranges (PF memory)\n"); 1831 entry->error = PCICFG_FAILURE; 1832 (void) pcicfg_config_teardown(&handle); 1833 return (DDI_WALK_TERMINATE); 1834 } 1835 } 1836 1837 (void) pcicfg_device_on(handle); 1838 1839 PCICFG_DUMP_BRIDGE_CONFIG(handle); 1840 1841 (void) pcicfg_config_teardown(&handle); 1842 1843 return (DDI_WALK_PRUNECHILD); 1844 } 1845 1846 /* 1847 * If there is an interrupt pin set program 1848 * interrupt line with default values. 1849 */ 1850 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 1851 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 1852 } 1853 1854 /* 1855 * A single device (under a bridge). 1856 * For each "reg" property with a length, allocate memory 1857 * and program the base registers. 1858 */ 1859 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "reg", 1860 (caddr_t)®, &length) != DDI_PROP_SUCCESS) { 1861 DEBUG0("Failed to read reg property\n"); 1862 entry->error = PCICFG_FAILURE; 1863 (void) pcicfg_config_teardown(&handle); 1864 return (DDI_WALK_TERMINATE); 1865 } 1866 1867 rcount = length / sizeof (pci_regspec_t); 1868 offset = PCI_CONF_BASE0; 1869 for (i = 0; i < rcount; i++) { 1870 if ((reg[i].pci_size_low != 0) || (reg[i].pci_size_hi != 0)) { 1871 1872 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); 1873 1874 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 1875 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 1876 1877 if (reg[i].pci_phys_hi & PCI_REG_PF_M) { 1878 /* allocate prefetchable memory */ 1879 pcicfg_get_pf_mem(entry, 1880 reg[i].pci_size_low, &mem_answer); 1881 } else { /* get non prefetchable memory */ 1882 pcicfg_get_mem(entry, 1883 reg[i].pci_size_low, &mem_answer); 1884 } 1885 pci_config_put64(handle, offset, mem_answer); 1886 DEBUG2("REGISTER off %x (64)LO ----> [0x%x]\n", 1887 offset, pci_config_get32(handle, offset)); 1888 DEBUG2("REGISTER off %x (64)HI ----> [0x%x]\n", 1889 offset + 4, 1890 pci_config_get32(handle, offset + 4)); 1891 1892 reg[i].pci_phys_hi |= PCI_REG_REL_M; 1893 reg[i].pci_phys_low = PCICFG_LOADDR(mem_answer); 1894 reg[i].pci_phys_mid = PCICFG_HIADDR(mem_answer); 1895 break; 1896 1897 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 1898 if (reg[i].pci_phys_hi & PCI_REG_PF_M) { 1899 /* allocate prefetchable memory */ 1900 pcicfg_get_pf_mem(entry, 1901 reg[i].pci_size_low, &mem_answer); 1902 } else { 1903 /* get non prefetchable memory */ 1904 pcicfg_get_mem(entry, 1905 reg[i].pci_size_low, &mem_answer); 1906 } 1907 1908 pci_config_put32(handle, offset, 1909 (uint32_t)mem_answer); 1910 1911 DEBUG2("REGISTER off %x(32)LO ----> [0x%x]\n", 1912 offset, pci_config_get32(handle, offset)); 1913 1914 reg[i].pci_phys_hi |= PCI_REG_REL_M; 1915 reg[i].pci_phys_low = (uint32_t)mem_answer; 1916 1917 break; 1918 case PCI_REG_ADDR_G(PCI_ADDR_IO): 1919 /* allocate I/O space from the allocator */ 1920 1921 (void) pcicfg_get_io(entry, reg[i].pci_size_low, 1922 &io_answer); 1923 pci_config_put32(handle, offset, io_answer); 1924 1925 DEBUG2("REGISTER off %x (I/O)LO ----> [0x%x]\n", 1926 offset, pci_config_get32(handle, offset)); 1927 1928 reg[i].pci_phys_hi |= PCI_REG_REL_M; 1929 reg[i].pci_phys_low = io_answer; 1930 1931 break; 1932 default: 1933 DEBUG0("Unknown register type\n"); 1934 kmem_free(reg, length); 1935 (void) pcicfg_config_teardown(&handle); 1936 entry->error = PCICFG_FAILURE; 1937 return (DDI_WALK_TERMINATE); 1938 } /* switch */ 1939 1940 /* 1941 * Now that memory locations are assigned, 1942 * update the assigned address property. 1943 */ 1944 if (pcicfg_update_assigned_prop(dip, ®[i]) 1945 != PCICFG_SUCCESS) { 1946 kmem_free(reg, length); 1947 (void) pcicfg_config_teardown(&handle); 1948 entry->error = PCICFG_FAILURE; 1949 return (DDI_WALK_TERMINATE); 1950 } 1951 } 1952 } 1953 (void) pcicfg_device_on(handle); 1954 1955 PCICFG_DUMP_DEVICE_CONFIG(handle); 1956 1957 (void) pcicfg_config_teardown(&handle); 1958 kmem_free((caddr_t)reg, length); 1959 return (DDI_WALK_CONTINUE); 1960 } 1961 1962 static int 1963 pcicfg_device_assign(dev_info_t *dip) 1964 { 1965 ddi_acc_handle_t handle; 1966 pci_regspec_t *reg; 1967 int length; 1968 int rcount; 1969 int i; 1970 int offset; 1971 ndi_ra_request_t request; 1972 uint64_t answer; 1973 uint64_t alen; 1974 1975 DEBUG1("%llx now under configuration\n", dip); 1976 1977 /* request.ra_len = PCICFG_ROUND_UP(request.ra_len, PCICFG_IOGRAN); */ 1978 if (pcicfg_ntbridge_child(dip) == DDI_SUCCESS) { 1979 1980 return (pcicfg_ntbridge_program_child(dip)); 1981 } 1982 /* 1983 * XXX Failure here should be noted 1984 */ 1985 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "reg", 1986 (caddr_t)®, &length) != DDI_PROP_SUCCESS) { 1987 DEBUG0("Failed to read reg property\n"); 1988 return (PCICFG_FAILURE); 1989 } 1990 1991 if (pcicfg_config_setup(dip, &handle) != DDI_SUCCESS) { 1992 DEBUG0("Failed to map config space!\n"); 1993 kmem_free(reg, length); 1994 return (PCICFG_FAILURE); 1995 } 1996 1997 /* 1998 * A single device 1999 * 2000 * For each "reg" property with a length, allocate memory 2001 * and program the base registers. 2002 */ 2003 2004 /* 2005 * If there is an interrupt pin set program 2006 * interrupt line with default values. 2007 */ 2008 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 2009 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 2010 } 2011 2012 bzero((caddr_t)&request, sizeof (ndi_ra_request_t)); 2013 2014 /* 2015 * Note: Both non-prefetchable and prefetchable memory space 2016 * allocations are made within 32bit space. Currently, BIOSs 2017 * allocate device memory for PCI devices within the 32bit space 2018 * so this will not be a problem. 2019 */ 2020 request.ra_flags |= NDI_RA_ALIGN_SIZE | NDI_RA_ALLOC_BOUNDED; 2021 request.ra_boundbase = 0; 2022 request.ra_boundlen = PCICFG_4GIG_LIMIT; 2023 2024 rcount = length / sizeof (pci_regspec_t); 2025 offset = PCI_CONF_BASE0; 2026 for (i = 0; i < rcount; i++) { 2027 char *mem_type; 2028 2029 if ((reg[i].pci_size_low != 0)|| (reg[i].pci_size_hi != 0)) { 2030 2031 offset = PCI_REG_REG_G(reg[i].pci_phys_hi); 2032 request.ra_len = reg[i].pci_size_low; 2033 2034 switch (PCI_REG_ADDR_G(reg[i].pci_phys_hi)) { 2035 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2036 if (reg[i].pci_phys_hi & PCI_REG_PF_M) { 2037 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2038 } else { 2039 mem_type = NDI_RA_TYPE_MEM; 2040 } 2041 /* allocate memory space from the allocator */ 2042 if (ndi_ra_alloc(ddi_get_parent(dip), &request, 2043 &answer, &alen, mem_type, NDI_RA_PASS) 2044 != NDI_SUCCESS) { 2045 DEBUG0("Failed to allocate 64b mem\n"); 2046 kmem_free(reg, length); 2047 (void) pcicfg_config_teardown(&handle); 2048 return (PCICFG_NORESRC); 2049 } 2050 DEBUG3("64 addr = [0x%x.0x%x] len [0x%x]\n", 2051 PCICFG_HIADDR(answer), 2052 PCICFG_LOADDR(answer), alen); 2053 /* program the low word */ 2054 pci_config_put32(handle, offset, 2055 PCICFG_LOADDR(answer)); 2056 /* program the high word */ 2057 pci_config_put32(handle, offset + 4, 2058 PCICFG_HIADDR(answer)); 2059 2060 reg[i].pci_phys_hi |= PCI_REG_REL_M; 2061 reg[i].pci_phys_low = PCICFG_LOADDR(answer); 2062 reg[i].pci_phys_mid = PCICFG_HIADDR(answer); 2063 /* 2064 * currently support 32b address space 2065 * assignments only. 2066 */ 2067 reg[i].pci_phys_hi ^= 2068 PCI_ADDR_MEM64 ^ PCI_ADDR_MEM32; 2069 2070 offset += 8; 2071 break; 2072 2073 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2074 if (reg[i].pci_phys_hi & PCI_REG_PF_M) 2075 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2076 else 2077 mem_type = NDI_RA_TYPE_MEM; 2078 /* allocate memory space from the allocator */ 2079 if (ndi_ra_alloc(ddi_get_parent(dip), &request, 2080 &answer, &alen, mem_type, NDI_RA_PASS) 2081 != NDI_SUCCESS) { 2082 DEBUG0("Failed to allocate 32b mem\n"); 2083 kmem_free(reg, length); 2084 (void) pcicfg_config_teardown(&handle); 2085 return (PCICFG_NORESRC); 2086 } 2087 DEBUG3("32 addr = [0x%x.0x%x] len [0x%x]\n", 2088 PCICFG_HIADDR(answer), 2089 PCICFG_LOADDR(answer), 2090 alen); 2091 /* program the low word */ 2092 pci_config_put32(handle, offset, 2093 PCICFG_LOADDR(answer)); 2094 2095 reg[i].pci_phys_hi |= PCI_REG_REL_M; 2096 reg[i].pci_phys_low = PCICFG_LOADDR(answer); 2097 reg[i].pci_phys_mid = 0; 2098 2099 offset += 4; 2100 break; 2101 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2102 /* allocate I/O space from the allocator */ 2103 if (ndi_ra_alloc(ddi_get_parent(dip), &request, 2104 &answer, &alen, NDI_RA_TYPE_IO, NDI_RA_PASS) 2105 != NDI_SUCCESS) { 2106 DEBUG0("Failed to allocate I/O\n"); 2107 kmem_free(reg, length); 2108 (void) pcicfg_config_teardown(&handle); 2109 return (PCICFG_NORESRC); 2110 } 2111 DEBUG3("I/O addr = [0x%x.0x%x] len [0x%x]\n", 2112 PCICFG_HIADDR(answer), 2113 PCICFG_LOADDR(answer), alen); 2114 pci_config_put32(handle, offset, 2115 PCICFG_LOADDR(answer)); 2116 2117 reg[i].pci_phys_hi |= PCI_REG_REL_M; 2118 reg[i].pci_phys_low = PCICFG_LOADDR(answer); 2119 2120 offset += 4; 2121 break; 2122 default: 2123 DEBUG0("Unknown register type\n"); 2124 kmem_free(reg, length); 2125 (void) pcicfg_config_teardown(&handle); 2126 return (PCICFG_FAILURE); 2127 } /* switch */ 2128 2129 /* 2130 * Now that memory locations are assigned, 2131 * update the assigned address property. 2132 */ 2133 2134 if (pcicfg_update_assigned_prop(dip, ®[i]) 2135 != PCICFG_SUCCESS) { 2136 kmem_free(reg, length); 2137 (void) pcicfg_config_teardown(&handle); 2138 return (PCICFG_FAILURE); 2139 } 2140 } 2141 } 2142 2143 (void) pcicfg_device_on(handle); 2144 kmem_free(reg, length); 2145 2146 PCICFG_DUMP_DEVICE_CONFIG(handle); 2147 2148 (void) pcicfg_config_teardown(&handle); 2149 return (PCICFG_SUCCESS); 2150 } 2151 2152 static int 2153 pcicfg_device_assign_readonly(dev_info_t *dip) 2154 { 2155 ddi_acc_handle_t handle; 2156 pci_regspec_t *assigned; 2157 int length; 2158 int acount; 2159 int i; 2160 ndi_ra_request_t request; 2161 uint64_t answer; 2162 uint64_t alen; 2163 2164 DEBUG1("%llx now under configuration\n", dip); 2165 2166 /* 2167 * we don't support ntbridges for readonly probe. 2168 */ 2169 if (pcicfg_ntbridge_child(dip) == DDI_SUCCESS) { 2170 return (PCICFG_FAILURE); 2171 } 2172 2173 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 2174 DDI_PROP_DONTPASS, "assigned-addresses", (caddr_t)&assigned, 2175 &length) != DDI_PROP_SUCCESS) { 2176 DEBUG0("Failed to read assigned-addresses property\n"); 2177 return (PCICFG_FAILURE); 2178 } 2179 2180 if (pcicfg_config_setup(dip, &handle) != DDI_SUCCESS) { 2181 DEBUG0("Failed to map config space!\n"); 2182 kmem_free(assigned, length); 2183 return (PCICFG_FAILURE); 2184 } 2185 2186 /* 2187 * If there is an interrupt pin set program 2188 * interrupt line with default values. 2189 */ 2190 if (pci_config_get8(handle, PCI_CONF_IPIN)) { 2191 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 2192 } 2193 /* 2194 * Note: Both non-prefetchable and prefetchable memory space 2195 * allocations are made within 32bit space. Currently, BIOSs 2196 * allocate device memory for PCI devices within the 32bit space 2197 * so this will not be a problem. 2198 */ 2199 bzero((caddr_t)&request, sizeof (ndi_ra_request_t)); 2200 2201 request.ra_flags = NDI_RA_ALLOC_SPECIFIED; /* specified addr */ 2202 request.ra_boundbase = 0; 2203 request.ra_boundlen = PCICFG_4GIG_LIMIT; 2204 2205 acount = length / sizeof (pci_regspec_t); 2206 for (i = 0; i < acount; i++) { 2207 char *mem_type; 2208 2209 if ((assigned[i].pci_size_low != 0)|| 2210 (assigned[i].pci_size_hi != 0)) { 2211 2212 request.ra_len = assigned[i].pci_size_low; 2213 2214 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { 2215 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2216 request.ra_addr = (uint64_t)PCICFG_LADDR( 2217 assigned[i].pci_phys_low, 2218 assigned[i].pci_phys_mid); 2219 2220 if (assigned[i].pci_phys_hi & PCI_REG_PF_M) { 2221 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2222 } else { 2223 mem_type = NDI_RA_TYPE_MEM; 2224 } 2225 /* allocate memory space from the allocator */ 2226 if (ndi_ra_alloc(ddi_get_parent(dip), &request, 2227 &answer, &alen, mem_type, NDI_RA_PASS) 2228 != NDI_SUCCESS) { 2229 DEBUG0("Failed to allocate 64b mem\n"); 2230 kmem_free(assigned, length); 2231 return (PCICFG_NORESRC); 2232 } 2233 2234 break; 2235 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2236 request.ra_addr = (uint64_t) 2237 assigned[i].pci_phys_low; 2238 2239 if (assigned[i].pci_phys_hi & PCI_REG_PF_M) 2240 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2241 else 2242 mem_type = NDI_RA_TYPE_MEM; 2243 /* allocate memory space from the allocator */ 2244 if (ndi_ra_alloc(ddi_get_parent(dip), &request, 2245 &answer, &alen, mem_type, NDI_RA_PASS) 2246 != NDI_SUCCESS) { 2247 DEBUG0("Failed to allocate 32b mem\n"); 2248 kmem_free(assigned, length); 2249 return (PCICFG_NORESRC); 2250 } 2251 2252 break; 2253 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2254 request.ra_addr = (uint64_t) 2255 assigned[i].pci_phys_low; 2256 2257 /* allocate I/O space from the allocator */ 2258 if (ndi_ra_alloc(ddi_get_parent(dip), &request, 2259 &answer, &alen, NDI_RA_TYPE_IO, NDI_RA_PASS) 2260 != NDI_SUCCESS) { 2261 DEBUG0("Failed to allocate I/O\n"); 2262 kmem_free(assigned, length); 2263 return (PCICFG_NORESRC); 2264 } 2265 2266 break; 2267 default: 2268 DEBUG0("Unknown register type\n"); 2269 kmem_free(assigned, length); 2270 return (PCICFG_FAILURE); 2271 } /* switch */ 2272 } 2273 } 2274 2275 (void) pcicfg_device_on(handle); 2276 kmem_free(assigned, length); 2277 2278 PCICFG_DUMP_DEVICE_CONFIG(handle); 2279 2280 (void) pcicfg_config_teardown(&handle); 2281 return (PCICFG_SUCCESS); 2282 } 2283 2284 #ifdef DEBUG 2285 /* 2286 * This function is useful in debug mode, where we can measure how 2287 * much memory was wasted/unallocated in bridge device's domain. 2288 */ 2289 static uint64_t 2290 pcicfg_unused_space(hole_t *hole, uint32_t *hole_count) 2291 { 2292 uint64_t len = 0; 2293 uint32_t count = 0; 2294 2295 do { 2296 len += hole->len; 2297 hole = hole->next; 2298 count++; 2299 } while (hole); 2300 *hole_count = count; 2301 return (len); 2302 } 2303 #endif 2304 2305 /* 2306 * This function frees data structures that hold the hole information 2307 * which are allocated in pcicfg_alloc_hole(). This is not freeing 2308 * any memory allocated through NDI calls. 2309 */ 2310 static void 2311 pcicfg_free_hole(hole_t *addr_hole) 2312 { 2313 hole_t *nhole, *hole = addr_hole->next; 2314 2315 while (hole) { 2316 nhole = hole->next; 2317 kmem_free(hole, sizeof (hole_t)); 2318 hole = nhole; 2319 } 2320 } 2321 2322 static uint64_t 2323 pcicfg_alloc_hole(hole_t *addr_hole, uint64_t *alast, uint32_t length) 2324 { 2325 uint64_t actual_hole_start, ostart, olen; 2326 hole_t *hole = addr_hole, *thole, *nhole; 2327 2328 do { 2329 actual_hole_start = PCICFG_ROUND_UP(hole->start, length); 2330 if (((actual_hole_start - hole->start) + length) <= hole->len) { 2331 DEBUG3("hole found. start %llx, len %llx, req=0x%x\n", 2332 hole->start, hole->len, length); 2333 ostart = hole->start; 2334 olen = hole->len; 2335 /* current hole parameters adjust */ 2336 if ((actual_hole_start - hole->start) == 0) { 2337 hole->start += length; 2338 hole->len -= length; 2339 if (hole->start > *alast) 2340 *alast = hole->start; 2341 } else { 2342 hole->len = actual_hole_start - hole->start; 2343 nhole = (hole_t *)kmem_zalloc(sizeof (hole_t), 2344 KM_SLEEP); 2345 nhole->start = actual_hole_start + length; 2346 nhole->len = (ostart + olen) - nhole->start; 2347 nhole->next = NULL; 2348 thole = hole->next; 2349 hole->next = nhole; 2350 nhole->next = thole; 2351 if (nhole->start > *alast) 2352 *alast = nhole->start; 2353 DEBUG2("put new hole to %llx, %llx\n", 2354 nhole->start, nhole->len); 2355 } 2356 DEBUG2("adjust current hole to %llx, %llx\n", 2357 hole->start, hole->len); 2358 break; 2359 } 2360 actual_hole_start = 0; 2361 hole = hole->next; 2362 } while (hole); 2363 2364 DEBUG1("return hole at %llx\n", actual_hole_start); 2365 return (actual_hole_start); 2366 } 2367 2368 static void 2369 pcicfg_get_mem(pcicfg_phdl_t *entry, uint32_t length, uint64_t *ans) 2370 { 2371 uint64_t new_mem; 2372 2373 /* See if there is a hole, that can hold this request. */ 2374 new_mem = pcicfg_alloc_hole(&entry->mem_hole, &entry->memory_last, 2375 length); 2376 if (new_mem) { /* if non-zero, found a hole. */ 2377 if (ans != NULL) 2378 *ans = new_mem; 2379 } else 2380 cmn_err(CE_WARN, "No %u bytes memory window for %s\n", 2381 length, ddi_get_name(entry->dip)); 2382 } 2383 2384 static void 2385 pcicfg_get_io(pcicfg_phdl_t *entry, 2386 uint32_t length, uint32_t *ans) 2387 { 2388 uint32_t new_io; 2389 uint64_t io_last; 2390 2391 /* 2392 * See if there is a hole, that can hold this request. 2393 * Pass 64 bit parameters and then truncate to 32 bit. 2394 */ 2395 io_last = entry->io_last; 2396 new_io = (uint32_t)pcicfg_alloc_hole(&entry->io_hole, &io_last, length); 2397 if (new_io) { /* if non-zero, found a hole. */ 2398 entry->io_last = (uint32_t)io_last; 2399 if (ans != NULL) 2400 *ans = new_io; 2401 } else 2402 cmn_err(CE_WARN, "No %u bytes IO space window for %s\n", 2403 length, ddi_get_name(entry->dip)); 2404 } 2405 2406 static void 2407 pcicfg_get_pf_mem(pcicfg_phdl_t *entry, uint32_t length, uint64_t *ans) 2408 { 2409 uint64_t new_mem; 2410 2411 /* See if there is a hole, that can hold this request. */ 2412 new_mem = pcicfg_alloc_hole(&entry->pf_mem_hole, &entry->pf_memory_last, 2413 length); 2414 if (new_mem) { /* if non-zero, found a hole. */ 2415 if (ans != NULL) 2416 *ans = new_mem; 2417 } else 2418 cmn_err(CE_WARN, "No %u bytes PF memory window for %s\n", 2419 length, ddi_get_name(entry->dip)); 2420 } 2421 2422 static int 2423 pcicfg_sum_resources(dev_info_t *dip, void *hdl) 2424 { 2425 pcicfg_phdl_t *entry = (pcicfg_phdl_t *)hdl; 2426 pci_regspec_t *pci_rp; 2427 int length; 2428 int rcount; 2429 int i; 2430 ndi_ra_request_t *pf_mem_request; 2431 ndi_ra_request_t *mem_request; 2432 ndi_ra_request_t *io_request; 2433 uint8_t header_type; 2434 ddi_acc_handle_t handle; 2435 2436 entry->error = PCICFG_SUCCESS; 2437 2438 pf_mem_request = &entry->pf_mem_req; 2439 mem_request = &entry->mem_req; 2440 io_request = &entry->io_req; 2441 2442 if (pcicfg_config_setup(dip, &handle) != DDI_SUCCESS) { 2443 DEBUG0("Failed to map config space!\n"); 2444 entry->error = PCICFG_FAILURE; 2445 return (DDI_WALK_TERMINATE); 2446 } 2447 2448 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 2449 2450 /* 2451 * If its a bridge - just record the highest bus seen 2452 */ 2453 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 2454 2455 if (entry->highest_bus < pci_config_get8(handle, 2456 PCI_BCNF_SECBUS)) { 2457 entry->highest_bus = 2458 pci_config_get8(handle, PCI_BCNF_SECBUS); 2459 } 2460 (void) pcicfg_config_teardown(&handle); 2461 entry->error = PCICFG_FAILURE; 2462 return (DDI_WALK_CONTINUE); 2463 } else { 2464 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2465 "reg", (caddr_t)&pci_rp, &length) != DDI_PROP_SUCCESS) { 2466 /* 2467 * If one node in (the subtree of nodes) 2468 * doesn't have a "reg" property fail the 2469 * allocation. 2470 */ 2471 entry->memory_len = 0; 2472 entry->io_len = 0; 2473 entry->pf_memory_len = 0; 2474 entry->error = PCICFG_FAILURE; 2475 (void) pcicfg_config_teardown(&handle); 2476 return (DDI_WALK_TERMINATE); 2477 } 2478 /* 2479 * For each "reg" property with a length, add that to the 2480 * total memory (or I/O) to allocate. 2481 */ 2482 rcount = length / sizeof (pci_regspec_t); 2483 2484 for (i = 0; i < rcount; i++) { 2485 2486 switch (PCI_REG_ADDR_G(pci_rp[i].pci_phys_hi)) { 2487 2488 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2489 if (pci_rp[i].pci_phys_hi & PCI_REG_PF_M) { 2490 pf_mem_request->ra_len = 2491 pci_rp[i].pci_size_low + 2492 PCICFG_ROUND_UP( 2493 pf_mem_request->ra_len, 2494 pci_rp[i].pci_size_low); 2495 DEBUG1("ADDING 32 --->0x%x\n", 2496 pci_rp[i].pci_size_low); 2497 } else { 2498 mem_request->ra_len = 2499 pci_rp[i].pci_size_low + 2500 PCICFG_ROUND_UP(mem_request->ra_len, 2501 pci_rp[i].pci_size_low); 2502 DEBUG1("ADDING 32 --->0x%x\n", 2503 pci_rp[i].pci_size_low); 2504 } 2505 2506 break; 2507 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2508 if (pci_rp[i].pci_phys_hi & PCI_REG_PF_M) { 2509 pf_mem_request->ra_len = 2510 pci_rp[i].pci_size_low + 2511 PCICFG_ROUND_UP( 2512 pf_mem_request->ra_len, 2513 pci_rp[i].pci_size_low); 2514 DEBUG1("ADDING 64 --->0x%x\n", 2515 pci_rp[i].pci_size_low); 2516 } else { 2517 mem_request->ra_len = 2518 pci_rp[i].pci_size_low + 2519 PCICFG_ROUND_UP(mem_request->ra_len, 2520 pci_rp[i].pci_size_low); 2521 DEBUG1("ADDING 64 --->0x%x\n", 2522 pci_rp[i].pci_size_low); 2523 } 2524 2525 break; 2526 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2527 io_request->ra_len = 2528 pci_rp[i].pci_size_low + 2529 PCICFG_ROUND_UP(io_request->ra_len, 2530 pci_rp[i].pci_size_low); 2531 DEBUG1("ADDING I/O --->0x%x\n", 2532 pci_rp[i].pci_size_low); 2533 break; 2534 default: 2535 /* Config space register - not included */ 2536 break; 2537 } 2538 } 2539 2540 /* 2541 * free the memory allocated by ddi_getlongprop 2542 */ 2543 kmem_free(pci_rp, length); 2544 2545 /* 2546 * continue the walk to the next sibling to sum memory 2547 */ 2548 2549 (void) pcicfg_config_teardown(&handle); 2550 2551 return (DDI_WALK_CONTINUE); 2552 } 2553 } 2554 2555 static int 2556 pcicfg_free_bridge_resources(dev_info_t *dip) 2557 { 2558 ppb_ranges_t *ranges; 2559 uint_t *bus; 2560 int k; 2561 int length = 0; 2562 int i; 2563 2564 2565 if ((i = ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2566 "ranges", (caddr_t)&ranges, &length)) != DDI_PROP_SUCCESS) { 2567 DEBUG0("Failed to read ranges property\n"); 2568 if (ddi_get_child(dip)) { 2569 cmn_err(CE_WARN, "No ranges property found for %s", 2570 ddi_get_name(dip)); 2571 /* 2572 * strictly speaking, we can check for children with 2573 * assigned-addresses but for now it is better to 2574 * be conservative and assume that if there are child 2575 * nodes, then they do consume PCI memory or IO 2576 * resources, Hence return failure. 2577 */ 2578 return (PCICFG_FAILURE); 2579 } 2580 length = 0; 2581 } 2582 2583 for (i = 0; i < length / sizeof (ppb_ranges_t); i++) { 2584 char *mem_type; 2585 2586 if (ranges[i].size_low != 0 || ranges[i].size_high != 0) { 2587 switch (ranges[i].parent_high & PCI_REG_ADDR_M) { 2588 case PCI_ADDR_IO: 2589 DEBUG2("Free I/O base/length = " 2590 "[0x%x]/[0x%x]\n", ranges[i].child_low, 2591 ranges[i].size_low); 2592 if (ndi_ra_free(ddi_get_parent(dip), 2593 (uint64_t)ranges[i].child_low, 2594 (uint64_t)ranges[i].size_low, 2595 NDI_RA_TYPE_IO, NDI_RA_PASS) 2596 != NDI_SUCCESS) { 2597 DEBUG0("Trouble freeing " 2598 "PCI i/o space\n"); 2599 kmem_free(ranges, length); 2600 return (PCICFG_FAILURE); 2601 } 2602 break; 2603 case PCI_ADDR_MEM32: 2604 case PCI_ADDR_MEM64: 2605 if (ranges[i].parent_high & PCI_REG_PF_M) { 2606 DEBUG3("Free PF Memory base/length = " 2607 "[0x%x.0x%x]/[0x%x]\n", 2608 ranges[i].child_mid, 2609 ranges[i].child_low, 2610 ranges[i].size_low); 2611 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2612 } else { 2613 DEBUG3("Free Memory base/length" 2614 " = [0x%x.0x%x]/[0x%x]\n", 2615 ranges[i].child_mid, 2616 ranges[i].child_low, 2617 ranges[i].size_low) 2618 mem_type = NDI_RA_TYPE_MEM; 2619 } 2620 if (ndi_ra_free(ddi_get_parent(dip), 2621 PCICFG_LADDR(ranges[i].child_low, 2622 ranges[i].child_mid), 2623 (uint64_t)ranges[i].size_low, 2624 mem_type, NDI_RA_PASS) != NDI_SUCCESS) { 2625 DEBUG0("Trouble freeing " 2626 "PCI memory space\n"); 2627 kmem_free(ranges, length); 2628 return (PCICFG_FAILURE); 2629 } 2630 break; 2631 default: 2632 DEBUG0("Unknown memory space\n"); 2633 break; 2634 } 2635 } 2636 } 2637 2638 if (length) 2639 kmem_free(ranges, length); 2640 2641 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2642 "bus-range", (caddr_t)&bus, &k) != DDI_PROP_SUCCESS) { 2643 DEBUG0("Failed to read bus-range property\n"); 2644 return (PCICFG_FAILURE); 2645 } 2646 2647 DEBUG2("Need to free bus [%d] range [%d]\n", 2648 bus[0], bus[1] - bus[0] + 1); 2649 2650 if (ndi_ra_free(ddi_get_parent(dip), (uint64_t)bus[0], 2651 (uint64_t)(bus[1] - bus[0] + 1), NDI_RA_TYPE_PCI_BUSNUM, 2652 NDI_RA_PASS) != NDI_SUCCESS) { 2653 DEBUG0("Failed to free a bus number\n"); 2654 kmem_free(bus, k); 2655 return (PCICFG_FAILURE); 2656 } 2657 2658 kmem_free(bus, k); 2659 return (PCICFG_SUCCESS); 2660 } 2661 2662 static int 2663 pcicfg_free_device_resources(dev_info_t *dip) 2664 { 2665 pci_regspec_t *assigned; 2666 2667 int length; 2668 int acount; 2669 int i; 2670 2671 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2672 "assigned-addresses", (caddr_t)&assigned, &length) 2673 != DDI_PROP_SUCCESS) { 2674 DEBUG0("Failed to read assigned-addresses property\n"); 2675 return (PCICFG_FAILURE); 2676 } 2677 2678 /* 2679 * For each "assigned-addresses" property entry with a length, 2680 * call the memory allocation routines to return the 2681 * resource. 2682 */ 2683 acount = length / sizeof (pci_regspec_t); 2684 for (i = 0; i < acount; i++) { 2685 char *mem_type; 2686 2687 /* 2688 * Free the resource if the size of it is not zero. 2689 */ 2690 if ((assigned[i].pci_size_low != 0)|| 2691 (assigned[i].pci_size_hi != 0)) { 2692 switch (PCI_REG_ADDR_G(assigned[i].pci_phys_hi)) { 2693 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 2694 /* 2695 * Check the assigned address for zero. 2696 * (Workaround for Devconf (x86) bug to 2697 * skip bogus entry for ROM base address 2698 * register. If the assigned address is 2699 * zero then ignore the entry 2700 * (see bugid 4281306)). 2701 */ 2702 if (assigned[i].pci_phys_low == 0) 2703 break; /* ignore the entry */ 2704 2705 if (assigned[i].pci_phys_hi & PCI_REG_PF_M) 2706 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2707 else 2708 mem_type = NDI_RA_TYPE_MEM; 2709 2710 if (ndi_ra_free(ddi_get_parent(dip), 2711 (uint64_t)assigned[i].pci_phys_low, 2712 (uint64_t)assigned[i].pci_size_low, 2713 mem_type, NDI_RA_PASS) != NDI_SUCCESS) { 2714 DEBUG0("Trouble freeing " 2715 "PCI memory space\n"); 2716 kmem_free(assigned, length); 2717 return (PCICFG_FAILURE); 2718 } 2719 2720 DEBUG4("Returned 0x%x of 32 bit %s space" 2721 " @ 0x%x from register 0x%x\n", 2722 assigned[i].pci_size_low, mem_type, 2723 assigned[i].pci_phys_low, 2724 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2725 2726 break; 2727 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 2728 if (assigned[i].pci_phys_hi & PCI_REG_PF_M) 2729 mem_type = NDI_RA_TYPE_PCI_PREFETCH_MEM; 2730 else 2731 mem_type = NDI_RA_TYPE_MEM; 2732 2733 if (ndi_ra_free(ddi_get_parent(dip), 2734 PCICFG_LADDR(assigned[i].pci_phys_low, 2735 assigned[i].pci_phys_mid), 2736 (uint64_t)assigned[i].pci_size_low, 2737 mem_type, NDI_RA_PASS) != NDI_SUCCESS) { 2738 DEBUG0("Trouble freeing " 2739 "PCI memory space\n"); 2740 kmem_free(assigned, length); 2741 return (PCICFG_FAILURE); 2742 } 2743 2744 DEBUG5("Returned 0x%x of 64 bit %s space" 2745 " @ 0x%x.0x%x from register 0x%x\n", 2746 assigned[i].pci_size_low, 2747 mem_type, assigned[i].pci_phys_mid, 2748 assigned[i].pci_phys_low, 2749 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2750 2751 break; 2752 case PCI_REG_ADDR_G(PCI_ADDR_IO): 2753 if (ndi_ra_free(ddi_get_parent(dip), 2754 (uint64_t)assigned[i].pci_phys_low, 2755 (uint64_t)assigned[i].pci_size_low, 2756 NDI_RA_TYPE_IO, NDI_RA_PASS) != 2757 NDI_SUCCESS) { 2758 DEBUG0("Trouble freeing " 2759 "PCI IO space\n"); 2760 kmem_free(assigned, length); 2761 return (PCICFG_FAILURE); 2762 } 2763 DEBUG3("Returned 0x%x of IO space @ 0x%x from " 2764 "register 0x%x\n", assigned[i].pci_size_low, 2765 assigned[i].pci_phys_low, 2766 PCI_REG_REG_G(assigned[i].pci_phys_hi)); 2767 break; 2768 default: 2769 DEBUG0("Unknown register type\n"); 2770 kmem_free(assigned, length); 2771 return (PCICFG_FAILURE); 2772 } /* switch */ 2773 } 2774 } 2775 kmem_free(assigned, length); 2776 return (PCICFG_SUCCESS); 2777 } 2778 2779 static int 2780 pcicfg_free_resources(dev_info_t *dip, pcicfg_flags_t flags) 2781 { 2782 ddi_acc_handle_t handle; 2783 uint8_t header_type; 2784 2785 if (pci_config_setup(dip, &handle) != DDI_SUCCESS) { 2786 DEBUG0("Failed to map config space!\n"); 2787 return (PCICFG_FAILURE); 2788 } 2789 2790 header_type = pci_config_get8(handle, PCI_CONF_HEADER); 2791 2792 (void) pci_config_teardown(&handle); 2793 2794 /* 2795 * A different algorithm is used for bridges and leaf devices. 2796 */ 2797 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 2798 /* 2799 * We only support readonly probing for leaf devices. 2800 */ 2801 if (flags & PCICFG_FLAG_READ_ONLY) 2802 return (PCICFG_FAILURE); 2803 2804 if (pcicfg_free_bridge_resources(dip) != PCICFG_SUCCESS) { 2805 DEBUG0("Failed freeing up bridge resources\n"); 2806 return (PCICFG_FAILURE); 2807 } 2808 } else { 2809 if (pcicfg_free_device_resources(dip) != PCICFG_SUCCESS) { 2810 DEBUG0("Failed freeing up device resources\n"); 2811 return (PCICFG_FAILURE); 2812 } 2813 } 2814 2815 return (PCICFG_SUCCESS); 2816 } 2817 2818 #ifndef _DONT_USE_1275_GENERIC_NAMES 2819 static char * 2820 pcicfg_get_class_name(uint32_t classcode) 2821 { 2822 struct pcicfg_name_entry *ptr; 2823 2824 for (ptr = &pcicfg_class_lookup[0]; ptr->name != NULL; ptr++) { 2825 if (ptr->class_code == classcode) { 2826 return (ptr->name); 2827 } 2828 } 2829 return (NULL); 2830 } 2831 #endif /* _DONT_USE_1275_GENERIC_NAMES */ 2832 2833 static dev_info_t * 2834 pcicfg_devi_find(dev_info_t *dip, uint_t device, uint_t function) 2835 { 2836 struct pcicfg_find_ctrl ctrl; 2837 int count; 2838 2839 ctrl.device = device; 2840 ctrl.function = function; 2841 ctrl.dip = NULL; 2842 2843 ndi_devi_enter(dip, &count); 2844 ddi_walk_devs(ddi_get_child(dip), pcicfg_match_dev, (void *)&ctrl); 2845 ndi_devi_exit(dip, count); 2846 2847 return (ctrl.dip); 2848 } 2849 2850 static int 2851 pcicfg_match_dev(dev_info_t *dip, void *hdl) 2852 { 2853 struct pcicfg_find_ctrl *ctrl = (struct pcicfg_find_ctrl *)hdl; 2854 pci_regspec_t *pci_rp; 2855 int length; 2856 int pci_dev; 2857 int pci_func; 2858 2859 if (ddi_prop_lookup_int_array(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2860 "reg", (int **)&pci_rp, (uint_t *)&length) != DDI_PROP_SUCCESS) { 2861 ctrl->dip = NULL; 2862 return (DDI_WALK_TERMINATE); 2863 } 2864 2865 /* get the PCI device address info */ 2866 pci_dev = PCI_REG_DEV_G(pci_rp->pci_phys_hi); 2867 pci_func = PCI_REG_FUNC_G(pci_rp->pci_phys_hi); 2868 2869 /* 2870 * free the memory allocated by ddi_prop_lookup_int_array 2871 */ 2872 ddi_prop_free(pci_rp); 2873 2874 2875 if ((pci_dev == ctrl->device) && (pci_func == ctrl->function)) { 2876 /* found the match for the specified device address */ 2877 ctrl->dip = dip; 2878 return (DDI_WALK_TERMINATE); 2879 } 2880 2881 /* 2882 * continue the walk to the next sibling to look for a match. 2883 */ 2884 return (DDI_WALK_PRUNECHILD); 2885 } 2886 2887 static int 2888 pcicfg_update_assigned_prop(dev_info_t *dip, pci_regspec_t *newone) 2889 { 2890 int alen; 2891 pci_regspec_t *assigned; 2892 caddr_t newreg; 2893 uint_t status; 2894 2895 status = ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2896 "assigned-addresses", (caddr_t)&assigned, &alen); 2897 switch (status) { 2898 case DDI_PROP_SUCCESS: 2899 break; 2900 case DDI_PROP_NO_MEMORY: 2901 DEBUG0("no memory for assigned-addresses property\n"); 2902 return (PCICFG_FAILURE); 2903 default: 2904 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2905 "assigned-addresses", (int *)newone, 2906 sizeof (*newone)/sizeof (int)); 2907 return (PCICFG_SUCCESS); 2908 } 2909 2910 /* 2911 * Allocate memory for the existing 2912 * assigned-addresses(s) plus one and then 2913 * build it. 2914 */ 2915 2916 newreg = kmem_zalloc(alen+sizeof (*newone), KM_SLEEP); 2917 2918 bcopy(assigned, newreg, alen); 2919 bcopy(newone, newreg + alen, sizeof (*newone)); 2920 2921 /* 2922 * Write out the new "assigned-addresses" spec 2923 */ 2924 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, 2925 "assigned-addresses", (int *)newreg, 2926 (alen + sizeof (*newone))/sizeof (int)); 2927 2928 kmem_free((caddr_t)newreg, alen+sizeof (*newone)); 2929 kmem_free(assigned, alen); 2930 2931 return (PCICFG_SUCCESS); 2932 } 2933 2934 static int 2935 pcicfg_update_ranges_prop(dev_info_t *dip, ppb_ranges_t *addition) 2936 { 2937 int rlen; 2938 ppb_ranges_t *ranges; 2939 caddr_t newreg; 2940 uint_t status; 2941 2942 status = ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, 2943 "ranges", (caddr_t)&ranges, &rlen); 2944 2945 2946 switch (status) { 2947 case DDI_PROP_SUCCESS: 2948 break; 2949 case DDI_PROP_NO_MEMORY: 2950 DEBUG0("ranges present, but unable to get memory\n"); 2951 return (PCICFG_FAILURE); 2952 default: 2953 DEBUG0("no ranges property - creating one\n"); 2954 if (ndi_prop_update_int_array(DDI_DEV_T_NONE, 2955 dip, "ranges", (int *)addition, 2956 sizeof (ppb_ranges_t)/sizeof (int)) 2957 != DDI_SUCCESS) { 2958 DEBUG0("Did'nt create ranges property\n"); 2959 return (PCICFG_FAILURE); 2960 } 2961 return (PCICFG_SUCCESS); 2962 } 2963 2964 /* 2965 * Allocate memory for the existing ranges plus one and then 2966 * build it. 2967 */ 2968 newreg = kmem_zalloc(rlen+sizeof (ppb_ranges_t), KM_SLEEP); 2969 2970 bcopy(ranges, newreg, rlen); 2971 bcopy(addition, newreg + rlen, sizeof (ppb_ranges_t)); 2972 2973 /* 2974 * Write out the new "ranges" property 2975 */ 2976 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "ranges", 2977 (int *)newreg, (rlen + sizeof (ppb_ranges_t))/sizeof (int)); 2978 2979 DEBUG1("Updating ranges property for %d entries", 2980 rlen / sizeof (ppb_ranges_t) + 1); 2981 2982 kmem_free((caddr_t)newreg, rlen+sizeof (ppb_ranges_t)); 2983 2984 kmem_free((caddr_t)ranges, rlen); 2985 2986 return (PCICFG_SUCCESS); 2987 } 2988 2989 static int 2990 pcicfg_update_reg_prop(dev_info_t *dip, uint32_t regvalue, uint_t reg_offset) 2991 { 2992 int rlen; 2993 pci_regspec_t *reg; 2994 caddr_t newreg; 2995 uint32_t hiword; 2996 pci_regspec_t addition; 2997 uint32_t size; 2998 uint_t status; 2999 3000 status = ddi_getlongprop(DDI_DEV_T_ANY, 3001 dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen); 3002 3003 switch (status) { 3004 case DDI_PROP_SUCCESS: 3005 break; 3006 case DDI_PROP_NO_MEMORY: 3007 DEBUG0("reg present, but unable to get memory\n"); 3008 return (PCICFG_FAILURE); 3009 default: 3010 DEBUG0("no reg property\n"); 3011 return (PCICFG_FAILURE); 3012 } 3013 3014 /* 3015 * Allocate memory for the existing reg(s) plus one and then 3016 * build it. 3017 */ 3018 newreg = kmem_zalloc(rlen+sizeof (pci_regspec_t), KM_SLEEP); 3019 3020 /* 3021 * Build the regspec, then add it to the existing one(s) 3022 */ 3023 3024 hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 3025 PCI_REG_DEV_G(reg->pci_phys_hi), 3026 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset); 3027 3028 if (reg_offset == PCI_CONF_ROM) { 3029 size = (~(PCI_BASE_ROM_ADDR_M & regvalue))+1; 3030 hiword |= PCI_ADDR_MEM32; 3031 } else { 3032 size = (~(PCI_BASE_M_ADDR_M & regvalue))+1; 3033 3034 if ((PCI_BASE_SPACE_M & regvalue) == PCI_BASE_SPACE_MEM) { 3035 if ((PCI_BASE_TYPE_M & regvalue) == PCI_BASE_TYPE_MEM) { 3036 hiword |= PCI_ADDR_MEM32; 3037 } else if ((PCI_BASE_TYPE_M & regvalue) 3038 == PCI_BASE_TYPE_ALL) { 3039 hiword |= PCI_ADDR_MEM64; 3040 } 3041 if (regvalue & PCI_BASE_PREF_M) 3042 hiword |= PCI_REG_PF_M; 3043 } else { 3044 hiword |= PCI_ADDR_IO; 3045 } 3046 } 3047 3048 addition.pci_phys_hi = hiword; 3049 addition.pci_phys_mid = 0; 3050 addition.pci_phys_low = 0; 3051 addition.pci_size_hi = 0; 3052 addition.pci_size_low = size; 3053 3054 bcopy(reg, newreg, rlen); 3055 bcopy(&addition, newreg + rlen, sizeof (pci_regspec_t)); 3056 3057 DEBUG3("updating BAR@off %x with %x,%x\n", reg_offset, hiword, size); 3058 /* 3059 * Write out the new "reg" property 3060 */ 3061 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", 3062 (int *)newreg, (rlen + sizeof (pci_regspec_t))/sizeof (int)); 3063 3064 kmem_free((caddr_t)newreg, rlen+sizeof (pci_regspec_t)); 3065 kmem_free((caddr_t)reg, rlen); 3066 3067 return (PCICFG_SUCCESS); 3068 } 3069 3070 static int 3071 pcicfg_update_assigned_prop_value(dev_info_t *dip, uint32_t size, 3072 uint32_t base, uint32_t base_hi, uint_t reg_offset) 3073 { 3074 int rlen; 3075 pci_regspec_t *reg; 3076 uint32_t hiword; 3077 pci_regspec_t addition; 3078 uint_t status; 3079 3080 status = ddi_getlongprop(DDI_DEV_T_ANY, 3081 dip, DDI_PROP_DONTPASS, "reg", (caddr_t)®, &rlen); 3082 3083 switch (status) { 3084 case DDI_PROP_SUCCESS: 3085 break; 3086 case DDI_PROP_NO_MEMORY: 3087 DEBUG0("reg present, but unable to get memory\n"); 3088 return (PCICFG_FAILURE); 3089 default: 3090 /* 3091 * Since the config space "reg" entry should have been 3092 * created, we expect a "reg" property already 3093 * present here. 3094 */ 3095 DEBUG0("no reg property\n"); 3096 return (PCICFG_FAILURE); 3097 } 3098 3099 /* 3100 * Build the regspec, then add it to the existing one(s) 3101 */ 3102 3103 hiword = PCICFG_MAKE_REG_HIGH(PCI_REG_BUS_G(reg->pci_phys_hi), 3104 PCI_REG_DEV_G(reg->pci_phys_hi), 3105 PCI_REG_FUNC_G(reg->pci_phys_hi), reg_offset); 3106 3107 hiword |= PCI_REG_REL_M; 3108 3109 if (reg_offset == PCI_CONF_ROM) { 3110 hiword |= PCI_ADDR_MEM32; 3111 3112 base = PCI_BASE_ROM_ADDR_M & base; 3113 } else { 3114 if ((PCI_BASE_SPACE_M & base) == PCI_BASE_SPACE_MEM) { 3115 if ((PCI_BASE_TYPE_M & base) == PCI_BASE_TYPE_MEM) { 3116 hiword |= PCI_ADDR_MEM32; 3117 } else if ((PCI_BASE_TYPE_M & base) 3118 == PCI_BASE_TYPE_ALL) { 3119 hiword |= PCI_ADDR_MEM64; 3120 } 3121 if (base & PCI_BASE_PREF_M) 3122 hiword |= PCI_REG_PF_M; 3123 3124 base = PCI_BASE_M_ADDR_M & base; 3125 } else { 3126 hiword |= PCI_ADDR_IO; 3127 3128 base = PCI_BASE_IO_ADDR_M & base; 3129 base_hi = 0; 3130 } 3131 } 3132 3133 addition.pci_phys_hi = hiword; 3134 addition.pci_phys_mid = base_hi; 3135 addition.pci_phys_low = base; 3136 addition.pci_size_hi = 0; 3137 addition.pci_size_low = size; 3138 3139 DEBUG3("updating BAR@off %x with %x,%x\n", reg_offset, hiword, size); 3140 3141 kmem_free((caddr_t)reg, rlen); 3142 3143 return (pcicfg_update_assigned_prop(dip, &addition)); 3144 } 3145 3146 static void 3147 pcicfg_device_on(ddi_acc_handle_t config_handle) 3148 { 3149 /* 3150 * Enable memory, IO, and bus mastership 3151 * XXX should we enable parity, SERR#, 3152 * fast back-to-back, and addr. stepping? 3153 */ 3154 pci_config_put16(config_handle, PCI_CONF_COMM, 3155 pci_config_get16(config_handle, PCI_CONF_COMM) | 0x7); 3156 } 3157 3158 static void 3159 pcicfg_device_off(ddi_acc_handle_t config_handle) 3160 { 3161 /* 3162 * Disable I/O and memory traffic through the bridge 3163 */ 3164 pci_config_put16(config_handle, PCI_CONF_COMM, 0x0); 3165 } 3166 3167 /* 3168 * Setup the basic 1275 properties based on information found in the config 3169 * header of the PCI device 3170 */ 3171 static int 3172 pcicfg_set_standard_props(dev_info_t *dip, ddi_acc_handle_t config_handle, 3173 uint8_t pcie_dev) 3174 { 3175 int ret; 3176 uint16_t cap_id_loc, val; 3177 uint32_t wordval; 3178 uint8_t byteval; 3179 3180 /* These two exists only for non-bridges */ 3181 if (((pci_config_get8(config_handle, PCI_CONF_HEADER) & 3182 PCI_HEADER_TYPE_M) == PCI_HEADER_ZERO) && !pcie_dev) { 3183 byteval = pci_config_get8(config_handle, PCI_CONF_MIN_G); 3184 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3185 "min-grant", byteval)) != DDI_SUCCESS) { 3186 return (ret); 3187 } 3188 3189 byteval = pci_config_get8(config_handle, PCI_CONF_MAX_L); 3190 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3191 "max-latency", byteval)) != DDI_SUCCESS) { 3192 return (ret); 3193 } 3194 } 3195 3196 /* 3197 * These should always exist and have the value of the 3198 * corresponding register value 3199 */ 3200 val = pci_config_get16(config_handle, PCI_CONF_VENID); 3201 3202 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, "vendor-id", val)) 3203 != DDI_SUCCESS) { 3204 return (ret); 3205 } 3206 val = pci_config_get16(config_handle, PCI_CONF_DEVID); 3207 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, "device-id", val)) 3208 != DDI_SUCCESS) { 3209 return (ret); 3210 } 3211 byteval = pci_config_get8(config_handle, PCI_CONF_REVID); 3212 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3213 "revision-id", byteval)) != DDI_SUCCESS) { 3214 return (ret); 3215 } 3216 3217 wordval = (pci_config_get16(config_handle, PCI_CONF_SUBCLASS)<< 8) | 3218 (pci_config_get8(config_handle, PCI_CONF_PROGCLASS)); 3219 3220 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3221 "class-code", wordval)) != DDI_SUCCESS) { 3222 return (ret); 3223 } 3224 val = (pci_config_get16(config_handle, PCI_CONF_STAT) & 3225 PCI_STAT_DEVSELT); 3226 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3227 "devsel-speed", val)) != DDI_SUCCESS) { 3228 return (ret); 3229 } 3230 3231 /* 3232 * The next three are bits set in the status register. The property is 3233 * present (but with no value other than its own existence) if the bit 3234 * is set, non-existent otherwise 3235 */ 3236 if ((!pcie_dev) && 3237 (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_FBBC)) { 3238 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3239 "fast-back-to-back", 0)) != DDI_SUCCESS) { 3240 return (ret); 3241 } 3242 } 3243 if ((!pcie_dev) && 3244 (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_66MHZ)) { 3245 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3246 "66mhz-capable", 0)) != DDI_SUCCESS) { 3247 return (ret); 3248 } 3249 } 3250 if (pci_config_get16(config_handle, PCI_CONF_STAT) & PCI_STAT_UDF) { 3251 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3252 "udf-supported", 0)) != DDI_SUCCESS) { 3253 return (ret); 3254 } 3255 } 3256 3257 /* 3258 * These next three are optional and are not present 3259 * if the corresponding register is zero. If the value 3260 * is non-zero then the property exists with the value 3261 * of the register. 3262 */ 3263 if ((val = pci_config_get16(config_handle, PCI_CONF_SUBVENID)) != 0) { 3264 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3265 "subsystem-vendor-id", val)) != DDI_SUCCESS) { 3266 return (ret); 3267 } 3268 } 3269 if ((val = pci_config_get16(config_handle, PCI_CONF_SUBSYSID)) != 0) { 3270 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3271 "subsystem-id", val)) != DDI_SUCCESS) { 3272 return (ret); 3273 } 3274 } 3275 if ((val = pci_config_get16(config_handle, PCI_CONF_CACHE_LINESZ)) 3276 != 0) { 3277 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3278 "cache-line-size", val)) != DDI_SUCCESS) { 3279 return (ret); 3280 } 3281 } 3282 3283 /* 3284 * If the Interrupt Pin register is non-zero then the 3285 * interrupts property exists 3286 */ 3287 if ((byteval = pci_config_get8(config_handle, PCI_CONF_IPIN)) != 0) { 3288 /* 3289 * If interrupt pin is non-zero, 3290 * record the interrupt line used 3291 */ 3292 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3293 "interrupts", byteval)) != DDI_SUCCESS) { 3294 return (ret); 3295 } 3296 } 3297 (void) PCI_CAP_LOCATE(config_handle, PCI_CAP_ID_PCI_E, &cap_id_loc); 3298 if (pcie_dev && cap_id_loc != PCI_CAP_NEXT_PTR_NULL) { 3299 val = pci_config_get16(config_handle, cap_id_loc + PCIE_PCIECAP) 3300 & PCIE_PCIECAP_SLOT_IMPL; 3301 /* if slot implemented, get physical slot number */ 3302 if (val) { 3303 wordval = pci_config_get32(config_handle, cap_id_loc + 3304 PCIE_SLOTCAP); 3305 /* create the property only if slotnum set correctly? */ 3306 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3307 "physical-slot#", PCIE_SLOTCAP_PHY_SLOT_NUM( 3308 wordval))) != DDI_SUCCESS) { 3309 return (ret); 3310 } 3311 } 3312 } 3313 3314 return (PCICFG_SUCCESS); 3315 } 3316 3317 static int 3318 pcicfg_set_busnode_props(dev_info_t *dip, uint8_t pcie_device_type) 3319 { 3320 int ret; 3321 char device_type[8]; 3322 3323 if (pcie_device_type) 3324 (void) strcpy(device_type, "pciex"); 3325 else 3326 (void) strcpy(device_type, "pci"); 3327 3328 if ((ret = ndi_prop_update_string(DDI_DEV_T_NONE, dip, 3329 "device_type", device_type)) != DDI_SUCCESS) { 3330 return (ret); 3331 } 3332 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, 3333 "#address-cells", 3)) != DDI_SUCCESS) { 3334 return (ret); 3335 } 3336 if ((ret = ndi_prop_update_int(DDI_DEV_T_NONE, dip, "#size-cells", 2)) 3337 != DDI_SUCCESS) { 3338 return (ret); 3339 } 3340 return (PCICFG_SUCCESS); 3341 } 3342 3343 static int 3344 pcicfg_set_childnode_props(dev_info_t *dip, ddi_acc_handle_t config_handle, 3345 uint8_t pcie_dev) 3346 { 3347 3348 int ret; 3349 char *name; 3350 char buffer[64], pprefix[8], nprefix[8]; 3351 uint16_t classcode; 3352 uint8_t revid, pif, pclass, psubclass; 3353 char *compat[24]; 3354 int i; 3355 int n; 3356 uint16_t sub_vid, sub_sid, vid, did; 3357 /* set the property prefix based on the device type */ 3358 if (pcie_dev) { 3359 (void) sprintf(pprefix, "pciex"); 3360 } else 3361 (void) sprintf(pprefix, "pci"); 3362 3363 /* set the prefix right for name property */ 3364 /* x86 platforms need to go with pci for upgrade purposes */ 3365 (void) sprintf(nprefix, "pci"); 3366 3367 /* 3368 * NOTE: These are for both a child and PCI-PCI bridge node 3369 */ 3370 sub_vid = pci_config_get16(config_handle, PCI_CONF_SUBVENID); 3371 sub_sid = pci_config_get16(config_handle, PCI_CONF_SUBSYSID); 3372 vid = pci_config_get16(config_handle, PCI_CONF_VENID); 3373 did = pci_config_get16(config_handle, PCI_CONF_DEVID); 3374 revid = pci_config_get8(config_handle, PCI_CONF_REVID); 3375 pif = pci_config_get8(config_handle, PCI_CONF_PROGCLASS); 3376 classcode = pci_config_get16(config_handle, PCI_CONF_SUBCLASS); 3377 pclass = pci_config_get8(config_handle, PCI_CONF_BASCLASS); 3378 psubclass = pci_config_get8(config_handle, PCI_CONF_SUBCLASS); 3379 3380 if (!sub_vid) 3381 (void) sprintf(buffer, "%s%x,%x", nprefix, vid, did); 3382 else 3383 (void) sprintf(buffer, "%s%x,%x", nprefix, sub_vid, sub_sid); 3384 3385 /* 3386 * In some environments, trying to use "generic" 1275 names is 3387 * not the convention. In those cases use the name as created 3388 * above. In all the rest of the cases, check to see if there 3389 * is a generic name first. 3390 */ 3391 #ifdef _DONT_USE_1275_GENERIC_NAMES 3392 name = buffer; 3393 #else 3394 if ((name = pcicfg_get_class_name(classcode)) == NULL) { 3395 /* 3396 * Set name to the above fabricated name 3397 */ 3398 name = buffer; 3399 } 3400 #endif 3401 3402 /* 3403 * The node name field needs to be filled in with the name 3404 */ 3405 if (ndi_devi_set_nodename(dip, name, 0) != NDI_SUCCESS) { 3406 DEBUG0("Failed to set nodename for node\n"); 3407 return (PCICFG_FAILURE); 3408 } 3409 3410 /* 3411 * Create the compatible property as an array of pointers 3412 * to strings. Start with the buffer created above. 3413 */ 3414 n = 0; 3415 3416 /* 3417 * Setup 'compatible' as per the PCI2.1 bindings document. 3418 * pci[ex]VVVV,DDDD.SSSS.ssss.RR 3419 * pci[ex]VVVV,DDDD.SSSS.ssss 3420 * pciSSSS.ssss -> not created for PCIe as per PCIe bindings 3421 * pci[ex]VVVV,DDDD.RR 3422 * pci[ex]VVVV,DDDD 3423 * pci[ex]class,CCSSPP 3424 * pci[ex]class,CCSS 3425 * Add legacy entries for compatibility with legacy devices and OS 3426 * for x86. 3427 * pciVVVV,DDDD.SSSS.ssss.RR 3428 * pciVVVV,DDDD.SSSS.ssss 3429 * pciSSSS.ssss 3430 * pciVVVV,DDDD.RR 3431 * pciVVVV,DDDD 3432 * pciclass,CCSSPP 3433 * pciclass,CCSS 3434 */ 3435 3436 do { 3437 if (sub_vid) { 3438 /* pci[ex]VVVV,DDDD.SSSS.ssss.RR */ 3439 (void) sprintf(buffer, "%s%x,%x.%x.%x.%x", pprefix, vid, 3440 did, sub_vid, sub_sid, revid); 3441 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3442 (void) strcpy(compat[n++], buffer); 3443 3444 /* pci[ex]VVVV,DDDD.SSSS.ssss */ 3445 (void) sprintf(buffer, "%s%x,%x.%x.%x", pprefix, vid, 3446 did, sub_vid, sub_sid); 3447 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3448 (void) strcpy(compat[n++], buffer); 3449 3450 /* pciSSSS.ssss -> not created for PCIe as per PCIe */ 3451 /* binding to IEEE 1275 spec. */ 3452 if (!pcie_dev && pcicfg_do_legacy_props) { 3453 (void) sprintf(buffer, "pci%x,%x", sub_vid, 3454 sub_sid); 3455 compat[n] = kmem_alloc(strlen(buffer) + 1, 3456 KM_SLEEP); 3457 (void) strcpy(compat[n++], buffer); 3458 } 3459 } 3460 3461 /* pci[ex]VVVV,DDDD.RR */ 3462 (void) sprintf(buffer, "%s%x,%x.%x", pprefix, vid, did, revid); 3463 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3464 (void) strcpy(compat[n++], buffer); 3465 3466 /* pci[ex]VVVV,DDDD */ 3467 (void) sprintf(buffer, "%s%x,%x", pprefix, vid, did); 3468 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3469 (void) strcpy(compat[n++], buffer); 3470 3471 /* pci[ex]class,CCSSPP */ 3472 (void) sprintf(buffer, "%sclass,%02x%02x%02x", pprefix, pclass, 3473 psubclass, pif); 3474 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3475 (void) strcpy(compat[n++], buffer); 3476 3477 /* pci[ex]class,CCSS */ 3478 (void) sprintf(buffer, "%sclass,%04x", pprefix, classcode); 3479 compat[n] = kmem_alloc(strlen(buffer) + 1, KM_SLEEP); 3480 (void) strcpy(compat[n++], buffer); 3481 3482 if (!pcie_dev) 3483 break; 3484 3485 /* also add compatible names using "pci" prefix */ 3486 (void) sprintf(pprefix, "pci"); 3487 pcie_dev = 0; 3488 3489 } while (pcicfg_do_legacy_props); 3490 3491 ret = ndi_prop_update_string_array(DDI_DEV_T_NONE, dip, "compatible", 3492 (char **)compat, n); 3493 3494 for (i = 0; i < n; i++) { 3495 kmem_free(compat[i], strlen(compat[i]) + 1); 3496 } 3497 3498 return (ret); 3499 } 3500 3501 /* 3502 * Program the bus numbers into the bridge 3503 */ 3504 static void 3505 pcicfg_set_bus_numbers(ddi_acc_handle_t config_handle, 3506 uint_t primary, uint_t secondary, uint_t subordinate) 3507 { 3508 DEBUG3("Setting bridge bus-range %d,%d,%d\n", primary, secondary, 3509 subordinate); 3510 /* 3511 * Primary bus# 3512 */ 3513 pci_config_put8(config_handle, PCI_BCNF_PRIBUS, primary); 3514 3515 /* 3516 * Secondary bus# 3517 */ 3518 pci_config_put8(config_handle, PCI_BCNF_SECBUS, secondary); 3519 3520 /* 3521 * Set the subordinate bus number to ff in order to pass through any 3522 * type 1 cycle with a bus number higher than the secondary bus# 3523 */ 3524 pci_config_put8(config_handle, PCI_BCNF_SUBBUS, subordinate); 3525 } 3526 3527 /* 3528 * Put bridge registers into initial state 3529 */ 3530 static void 3531 pcicfg_setup_bridge(pcicfg_phdl_t *entry, 3532 ddi_acc_handle_t handle) 3533 { 3534 /* 3535 * The highest bus seen during probing is the max-subordinate bus 3536 */ 3537 pci_config_put8(handle, PCI_BCNF_SUBBUS, entry->highest_bus); 3538 3539 /* 3540 * Reset the secondary bus 3541 */ 3542 pci_config_put16(handle, PCI_BCNF_BCNTRL, 3543 pci_config_get16(handle, PCI_BCNF_BCNTRL) | 0x40); 3544 drv_usecwait(1000); 3545 pci_config_put16(handle, PCI_BCNF_BCNTRL, 3546 pci_config_get16(handle, PCI_BCNF_BCNTRL) & ~0x40); 3547 drv_usecwait(1000); 3548 3549 /* 3550 * Program the memory base register with the 3551 * start of the memory range 3552 */ 3553 pci_config_put16(handle, PCI_BCNF_MEM_BASE, 3554 PCICFG_HIWORD(PCICFG_LOADDR(entry->memory_last))); 3555 3556 /* 3557 * Program the I/O base register with the start of the I/O range 3558 */ 3559 pci_config_put8(handle, PCI_BCNF_IO_BASE_LOW, 3560 PCICFG_HIBYTE(PCICFG_LOWORD(PCICFG_LOADDR(entry->io_last)))); 3561 pci_config_put16(handle, PCI_BCNF_IO_BASE_HI, 3562 PCICFG_HIWORD(PCICFG_LOADDR(entry->io_last))); 3563 3564 /* 3565 * Program the PF memory base register with the start of 3566 * PF memory range 3567 */ 3568 pci_config_put16(handle, PCI_BCNF_PF_BASE_LOW, 3569 PCICFG_HIWORD(PCICFG_LOADDR(entry->pf_memory_last))); 3570 pci_config_put32(handle, PCI_BCNF_PF_BASE_HIGH, 3571 PCICFG_HIADDR(entry->pf_memory_last)); 3572 3573 /* 3574 * Clear status bits 3575 */ 3576 pci_config_put16(handle, PCI_BCNF_SEC_STATUS, 0xffff); 3577 3578 /* 3579 * Needs to be set to this value 3580 */ 3581 pci_config_put8(handle, PCI_CONF_ILINE, 0xf); 3582 3583 /* 3584 * XXX - may be delay should be used since noone configures 3585 * devices in the interrupt context 3586 */ 3587 drv_usecwait(pcicfg_sec_reset_delay); /* 1 sec wait */ 3588 } 3589 3590 static void 3591 pcicfg_update_bridge(pcicfg_phdl_t *entry, 3592 ddi_acc_handle_t handle) 3593 { 3594 uint_t length; 3595 3596 /* 3597 * Program the memory limit register with the end of the memory range 3598 */ 3599 3600 DEBUG1("DOWN ROUNDED ===>[0x%x]\n", 3601 PCICFG_ROUND_DOWN(entry->memory_last, PCICFG_MEMGRAN)); 3602 3603 pci_config_put16(handle, PCI_BCNF_MEM_LIMIT, 3604 PCICFG_HIWORD(PCICFG_LOADDR( 3605 PCICFG_ROUND_DOWN(entry->memory_last, PCICFG_MEMGRAN)))); 3606 /* 3607 * Since this is a bridge, the rest of this range will 3608 * be responded to by the bridge. We have to round up 3609 * so no other device claims it. 3610 */ 3611 if ((length = (PCICFG_ROUND_UP(entry->memory_last, PCICFG_MEMGRAN) 3612 - entry->memory_last)) > 0) { 3613 (void) pcicfg_get_mem(entry, length, NULL); 3614 DEBUG1("Added [0x%x]at the top of the bridge (mem)\n", length); 3615 } 3616 3617 /* 3618 * Program the PF memory limit register with the end of the memory range 3619 */ 3620 3621 DEBUG1("DOWN ROUNDED ===>[0x%x]\n", 3622 PCICFG_ROUND_DOWN(entry->pf_memory_last, PCICFG_MEMGRAN)); 3623 3624 pci_config_put16(handle, PCI_BCNF_PF_LIMIT_LOW, 3625 PCICFG_HIWORD(PCICFG_LOADDR(PCICFG_ROUND_DOWN( 3626 entry->pf_memory_last, PCICFG_MEMGRAN)))); 3627 pci_config_put32(handle, PCI_BCNF_PF_LIMIT_HIGH, PCICFG_HIADDR( 3628 PCICFG_ROUND_DOWN(entry->pf_memory_last, PCICFG_MEMGRAN))); 3629 if ((length = (PCICFG_ROUND_UP(entry->pf_memory_last, PCICFG_MEMGRAN) 3630 - entry->pf_memory_last)) > 0) { 3631 (void) pcicfg_get_pf_mem(entry, length, NULL); 3632 DEBUG1("Added [0x%x]at the top of the bridge (PF mem)\n", 3633 length); 3634 } 3635 3636 /* 3637 * Program the I/O limit register with the end of the I/O range 3638 */ 3639 pci_config_put8(handle, PCI_BCNF_IO_LIMIT_LOW, 3640 PCICFG_HIBYTE(PCICFG_LOWORD( 3641 PCICFG_LOADDR(PCICFG_ROUND_DOWN(entry->io_last, PCICFG_IOGRAN))))); 3642 3643 pci_config_put16(handle, PCI_BCNF_IO_LIMIT_HI, PCICFG_HIWORD( 3644 PCICFG_LOADDR(PCICFG_ROUND_DOWN(entry->io_last, PCICFG_IOGRAN)))); 3645 3646 /* 3647 * Same as above for I/O space. Since this is a 3648 * bridge, the rest of this range will be responded 3649 * to by the bridge. We have to round up so no 3650 * other device claims it. 3651 */ 3652 if ((length = (PCICFG_ROUND_UP(entry->io_last, PCICFG_IOGRAN) 3653 - entry->io_last)) > 0) { 3654 (void) pcicfg_get_io(entry, length, NULL); 3655 DEBUG1("Added [0x%x]at the top of the bridge (I/O)\n", length); 3656 } 3657 } 3658 3659 static int 3660 pcicfg_probe_children(dev_info_t *parent, uint_t bus, uint_t device, 3661 uint_t func, uint_t *highest_bus, pcicfg_flags_t flags, boolean_t is_pcie) 3662 { 3663 dev_info_t *new_child; 3664 ddi_acc_handle_t config_handle; 3665 uint8_t header_type, pcie_dev = 0; 3666 int ret = PCICFG_FAILURE; 3667 3668 /* 3669 * This node will be put immediately below 3670 * "parent". Allocate a blank device node. It will either 3671 * be filled in or freed up based on further probing. 3672 */ 3673 3674 ndi_devi_alloc_sleep(parent, DEVI_PSEUDO_NEXNAME, 3675 (pnode_t)DEVI_SID_NODEID, &new_child); 3676 3677 if (pcicfg_add_config_reg(new_child, bus, device, func) 3678 != DDI_SUCCESS) { 3679 DEBUG0("pcicfg_probe_children():Failed to add candidate REG\n"); 3680 goto failedconfig; 3681 } 3682 3683 if ((ret = pcicfg_config_setup(new_child, &config_handle)) 3684 != PCICFG_SUCCESS) { 3685 if (ret == PCICFG_NODEVICE) { 3686 (void) ndi_devi_free(new_child); 3687 return (ret); 3688 } 3689 DEBUG0("pcicfg_probe_children():" 3690 "Failed to setup config space\n"); 3691 goto failedconfig; 3692 } 3693 3694 if (is_pcie) 3695 (void) pcie_init_bus(new_child, PCI_GETBDF(bus, device, func), 3696 PCIE_BUS_INITIAL); 3697 3698 /* 3699 * As soon as we have access to config space, 3700 * turn off device. It will get turned on 3701 * later (after memory is assigned). 3702 */ 3703 (void) pcicfg_device_off(config_handle); 3704 3705 /* check if we are PCIe device */ 3706 if (pcicfg_pcie_dev(new_child, config_handle) == DDI_SUCCESS) { 3707 DEBUG0("PCIe device detected\n"); 3708 pcie_dev = 1; 3709 } 3710 3711 /* 3712 * Set 1275 properties common to all devices 3713 */ 3714 if (pcicfg_set_standard_props(new_child, config_handle, pcie_dev) 3715 != PCICFG_SUCCESS) { 3716 DEBUG0("Failed to set standard properties\n"); 3717 goto failedchild; 3718 } 3719 3720 /* 3721 * Child node properties NOTE: Both for PCI-PCI bridge and child node 3722 */ 3723 if (pcicfg_set_childnode_props(new_child, config_handle, pcie_dev) 3724 != PCICFG_SUCCESS) { 3725 goto failedchild; 3726 } 3727 3728 header_type = pci_config_get8(config_handle, PCI_CONF_HEADER); 3729 3730 /* 3731 * If this is not a multi-function card only probe function zero. 3732 */ 3733 if ((!(header_type & PCI_HEADER_MULTI)) && (func != 0)) { 3734 3735 ret = PCICFG_NODEVICE; 3736 goto failedchild; 3737 } 3738 3739 /* 3740 * Attach the child to its parent 3741 */ 3742 (void) i_ndi_config_node(new_child, DS_LINKED, 0); 3743 3744 if ((header_type & PCI_HEADER_TYPE_M) == PCI_HEADER_PPB) { 3745 3746 DEBUG3("--Bridge found bus [0x%x] device[0x%x] func [0x%x]\n", 3747 bus, device, func); 3748 3749 /* Only support read-only probe for leaf device */ 3750 if (flags & PCICFG_FLAG_READ_ONLY) 3751 goto failedchild; 3752 3753 ret = pcicfg_probe_bridge(new_child, config_handle, bus, 3754 highest_bus, is_pcie); 3755 if (ret != PCICFG_SUCCESS) { 3756 (void) pcicfg_free_bridge_resources(new_child); 3757 goto failedchild; 3758 } 3759 3760 } else { 3761 3762 DEBUG3("--Leaf device found bus [0x%x] device" 3763 "[0x%x] func [0x%x]\n", bus, device, func); 3764 3765 if (flags & PCICFG_FLAG_READ_ONLY) { 3766 /* 3767 * with read-only probe, don't do any resource 3768 * allocation, just read the BARs and update props. 3769 */ 3770 ret = pcicfg_populate_props_from_bar(new_child, 3771 config_handle); 3772 if (ret != PCICFG_SUCCESS) 3773 goto failedchild; 3774 3775 /* 3776 * now allocate the resources, just remove the 3777 * resources from the parent busra pool. 3778 */ 3779 ret = pcicfg_device_assign_readonly(new_child); 3780 if (ret != PCICFG_SUCCESS) { 3781 (void) pcicfg_free_device_resources(new_child); 3782 goto failedchild; 3783 } 3784 3785 } else { 3786 /* 3787 * update "reg" property by sizing the BARs. 3788 */ 3789 ret = pcicfg_populate_reg_props(new_child, 3790 config_handle); 3791 if (ret != PCICFG_SUCCESS) 3792 goto failedchild; 3793 3794 /* now allocate & program the resources */ 3795 ret = pcicfg_device_assign(new_child); 3796 if (ret != PCICFG_SUCCESS) { 3797 (void) pcicfg_free_device_resources(new_child); 3798 goto failedchild; 3799 } 3800 } 3801 3802 (void) ndi_devi_bind_driver(new_child, 0); 3803 } 3804 3805 (void) pcicfg_config_teardown(&config_handle); 3806 3807 /* 3808 * Properties have been setted up, so initialize the remaining 3809 * bus_t fields 3810 */ 3811 if (is_pcie) 3812 pcie_init_bus(new_child, 0, PCIE_BUS_FINAL); 3813 3814 return (PCICFG_SUCCESS); 3815 3816 failedchild: 3817 /* 3818 * XXX check if it should be taken offline (if online) 3819 */ 3820 (void) pcicfg_config_teardown(&config_handle); 3821 3822 if (is_pcie) 3823 pcie_fini_bus(new_child, PCIE_BUS_FINAL); 3824 3825 failedconfig: 3826 3827 (void) ndi_devi_free(new_child); 3828 return (ret); 3829 } 3830 3831 /* 3832 * Sizing the BARs and update "reg" property 3833 */ 3834 static int 3835 pcicfg_populate_reg_props(dev_info_t *new_child, 3836 ddi_acc_handle_t config_handle) 3837 { 3838 int i; 3839 uint32_t request; 3840 3841 i = PCI_CONF_BASE0; 3842 3843 while (i <= PCI_CONF_BASE5) { 3844 3845 pci_config_put32(config_handle, i, 0xffffffff); 3846 3847 request = pci_config_get32(config_handle, i); 3848 /* 3849 * If its a zero length, don't do 3850 * any programming. 3851 */ 3852 if (request != 0) { 3853 /* 3854 * Add to the "reg" property 3855 */ 3856 if (pcicfg_update_reg_prop(new_child, 3857 request, i) != PCICFG_SUCCESS) { 3858 goto failedchild; 3859 } 3860 } else { 3861 DEBUG1("BASE register [0x%x] asks for " 3862 "[0x0]=[0x0](32)\n", i); 3863 i += 4; 3864 continue; 3865 } 3866 3867 /* 3868 * Increment by eight if it is 64 bit address space 3869 */ 3870 if ((PCI_BASE_TYPE_M & request) == PCI_BASE_TYPE_ALL) { 3871 DEBUG3("BASE register [0x%x] asks for " 3872 "[0x%x]=[0x%x] (64)\n", 3873 i, request, (~(PCI_BASE_M_ADDR_M & request))+1); 3874 i += 8; 3875 } else { 3876 DEBUG3("BASE register [0x%x] asks for " 3877 "[0x%x]=[0x%x](32)\n", 3878 i, request, (~(PCI_BASE_M_ADDR_M & request))+1); 3879 i += 4; 3880 } 3881 } 3882 3883 /* 3884 * Get the ROM size and create register for it 3885 */ 3886 pci_config_put32(config_handle, PCI_CONF_ROM, 0xfffffffe); 3887 3888 request = pci_config_get32(config_handle, PCI_CONF_ROM); 3889 /* 3890 * If its a zero length, don't do 3891 * any programming. 3892 */ 3893 3894 if (request != 0) { 3895 DEBUG3("BASE register [0x%x] asks for [0x%x]=[0x%x]\n", 3896 PCI_CONF_ROM, request, 3897 (~(PCI_BASE_ROM_ADDR_M & request)) + 1); 3898 /* 3899 * Add to the "reg" property 3900 */ 3901 if (pcicfg_update_reg_prop(new_child, request, PCI_CONF_ROM) 3902 != PCICFG_SUCCESS) { 3903 goto failedchild; 3904 } 3905 } 3906 3907 return (PCICFG_SUCCESS); 3908 3909 failedchild: 3910 return (PCICFG_FAILURE); 3911 } 3912 3913 /* 3914 * Read the BARs and update properties. Used in virtual hotplug. 3915 */ 3916 static int 3917 pcicfg_populate_props_from_bar(dev_info_t *new_child, 3918 ddi_acc_handle_t config_handle) 3919 { 3920 uint32_t request, base, base_hi, size; 3921 int i; 3922 3923 i = PCI_CONF_BASE0; 3924 3925 while (i <= PCI_CONF_BASE5) { 3926 /* 3927 * determine the size of the address space 3928 */ 3929 base = pci_config_get32(config_handle, i); 3930 pci_config_put32(config_handle, i, 0xffffffff); 3931 request = pci_config_get32(config_handle, i); 3932 pci_config_put32(config_handle, i, base); 3933 3934 /* 3935 * If its a zero length, don't do any programming. 3936 */ 3937 if (request != 0) { 3938 /* 3939 * Add to the "reg" property 3940 */ 3941 if (pcicfg_update_reg_prop(new_child, 3942 request, i) != PCICFG_SUCCESS) { 3943 goto failedchild; 3944 } 3945 3946 if ((PCI_BASE_SPACE_IO & request) == 0 && 3947 (PCI_BASE_TYPE_M & request) == PCI_BASE_TYPE_ALL) { 3948 base_hi = pci_config_get32(config_handle, i+4); 3949 } else { 3950 base_hi = 0; 3951 } 3952 /* 3953 * Add to "assigned-addresses" property 3954 */ 3955 size = (~(PCI_BASE_M_ADDR_M & request))+1; 3956 if (pcicfg_update_assigned_prop_value(new_child, 3957 size, base, base_hi, i) != PCICFG_SUCCESS) { 3958 goto failedchild; 3959 } 3960 } else { 3961 DEBUG1("BASE register [0x%x] asks for [0x0]=[0x0]" 3962 "(32)\n", i); 3963 i += 4; 3964 continue; 3965 } 3966 3967 /* 3968 * Increment by eight if it is 64 bit address space 3969 */ 3970 if ((PCI_BASE_TYPE_M & request) == PCI_BASE_TYPE_ALL) { 3971 DEBUG3("BASE register [0x%x] asks for [0x%x]=[0x%x]" 3972 "(64)\n", i, request, 3973 (~(PCI_BASE_M_ADDR_M & request)) + 1); 3974 i += 8; 3975 } else { 3976 DEBUG3("BASE register [0x%x] asks for [0x%x]=[0x%x]" 3977 "(32)\n", i, request, 3978 (~(PCI_BASE_M_ADDR_M & request)) + 1); 3979 i += 4; 3980 } 3981 } 3982 3983 /* 3984 * Get the ROM size and create register for it 3985 */ 3986 base = pci_config_get32(config_handle, PCI_CONF_ROM); 3987 pci_config_put32(config_handle, PCI_CONF_ROM, 0xfffffffe); 3988 request = pci_config_get32(config_handle, PCI_CONF_ROM); 3989 pci_config_put32(config_handle, PCI_CONF_ROM, base); 3990 3991 /* 3992 * If its a zero length, don't do 3993 * any programming. 3994 */ 3995 if (request != 0) { 3996 DEBUG3("BASE register [0x%x] asks for [0x%x]=[0x%x]\n", 3997 PCI_CONF_ROM, request, 3998 (~(PCI_BASE_ROM_ADDR_M & request)) + 1); 3999 /* 4000 * Add to the "reg" property 4001 */ 4002 if (pcicfg_update_reg_prop(new_child, request, PCI_CONF_ROM) 4003 != PCICFG_SUCCESS) { 4004 goto failedchild; 4005 } 4006 /* 4007 * Add to "assigned-addresses" property 4008 */ 4009 size = (~(PCI_BASE_ROM_ADDR_M & request))+1; 4010 if (pcicfg_update_assigned_prop_value(new_child, size, 4011 base, 0, PCI_CONF_ROM) != PCICFG_SUCCESS) { 4012 goto failedchild; 4013 } 4014 } 4015 4016 return (PCICFG_SUCCESS); 4017 4018 failedchild: 4019 return (PCICFG_FAILURE); 4020 } 4021 4022 static int 4023 pcicfg_probe_bridge(dev_info_t *new_child, ddi_acc_handle_t h, uint_t bus, 4024 uint_t *highest_bus, boolean_t is_pcie) 4025 { 4026 uint64_t next_bus; 4027 uint_t new_bus, num_slots; 4028 ndi_ra_request_t req; 4029 int rval, i, j; 4030 uint64_t mem_answer, io_answer, mem_base, io_base, mem_alen, io_alen; 4031 uint64_t pf_mem_answer, pf_mem_base, pf_mem_alen; 4032 uint64_t mem_size, io_size, pf_mem_size; 4033 uint64_t mem_end, pf_mem_end, io_end; 4034 uint64_t round_answer, round_len; 4035 ppb_ranges_t range[PCICFG_RANGE_LEN]; 4036 int bus_range[2]; 4037 pcicfg_phdl_t phdl; 4038 int count; 4039 uint64_t pcibus_base, pcibus_alen; 4040 uint64_t max_bus; 4041 uint8_t pcie_device_type = 0; 4042 uint_t pf_mem_supported = 0; 4043 dev_info_t *new_device; 4044 int trans_device; 4045 int ari_mode = B_FALSE; 4046 int max_function = PCI_MAX_FUNCTIONS; 4047 4048 io_answer = io_base = io_alen = io_size = 0; 4049 pf_mem_answer = pf_mem_base = pf_mem_size = pf_mem_alen = 0; 4050 4051 /* 4052 * Set "device_type" to "pci", the actual type will be set later 4053 * by pcicfg_set_busnode_props() below. This is needed as the 4054 * pcicfg_ra_free() below would update "available" property based 4055 * on "device_type". 4056 * 4057 * This code can be removed later after PCI configurator is changed 4058 * to use PCIRM, which automatically update properties upon allocation 4059 * and free, at that time we'll be able to remove the code inside 4060 * ndi_ra_alloc/free() which currently updates "available" property 4061 * for pci/pcie devices in pcie fabric. 4062 */ 4063 if (ndi_prop_update_string(DDI_DEV_T_NONE, new_child, 4064 "device_type", "pci") != DDI_SUCCESS) { 4065 DEBUG0("Failed to set \"device_type\" props\n"); 4066 return (PCICFG_FAILURE); 4067 } 4068 4069 /* 4070 * setup resource maps for the bridge node 4071 */ 4072 if (ndi_ra_map_setup(new_child, NDI_RA_TYPE_PCI_BUSNUM) 4073 == NDI_FAILURE) { 4074 DEBUG0("Can not setup resource map - NDI_RA_TYPE_PCI_BUSNUM\n"); 4075 rval = PCICFG_FAILURE; 4076 goto cleanup; 4077 } 4078 if (ndi_ra_map_setup(new_child, NDI_RA_TYPE_MEM) == NDI_FAILURE) { 4079 DEBUG0("Can not setup resource map - NDI_RA_TYPE_MEM\n"); 4080 rval = PCICFG_FAILURE; 4081 goto cleanup; 4082 } 4083 if (ndi_ra_map_setup(new_child, NDI_RA_TYPE_IO) == NDI_FAILURE) { 4084 DEBUG0("Can not setup resource map - NDI_RA_TYPE_IO\n"); 4085 rval = PCICFG_FAILURE; 4086 goto cleanup; 4087 } 4088 if (ndi_ra_map_setup(new_child, NDI_RA_TYPE_PCI_PREFETCH_MEM) == 4089 NDI_FAILURE) { 4090 DEBUG0("Can not setup resource map -" 4091 " NDI_RA_TYPE_PCI_PREFETCH_MEM\n"); 4092 rval = PCICFG_FAILURE; 4093 goto cleanup; 4094 } 4095 4096 /* 4097 * Allocate bus range pool for the bridge. 4098 */ 4099 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4100 req.ra_flags = (NDI_RA_ALLOC_BOUNDED | NDI_RA_ALLOC_PARTIAL_OK); 4101 req.ra_boundbase = 0; 4102 req.ra_boundlen = req.ra_len = (PCI_MAX_BUS_NUM -1); 4103 req.ra_align_mask = 0; /* no alignment needed */ 4104 4105 rval = ndi_ra_alloc(ddi_get_parent(new_child), &req, 4106 &pcibus_base, &pcibus_alen, NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS); 4107 4108 if (rval != NDI_SUCCESS) { 4109 if (rval == NDI_RA_PARTIAL_REQ) { 4110 /*EMPTY*/ 4111 DEBUG0("NDI_RA_PARTIAL_REQ returned for bus range\n"); 4112 } else { 4113 DEBUG0( 4114 "Failed to allocate bus range for bridge\n"); 4115 rval = PCICFG_NORESRC; 4116 goto cleanup; 4117 } 4118 } 4119 4120 DEBUG2("Bus Range Allocated [base=%d] [len=%d]\n", 4121 pcibus_base, pcibus_alen); 4122 4123 /* 4124 * Put available bus range into the pool. 4125 * Take the first one for this bridge to use and don't give 4126 * to child. 4127 */ 4128 (void) ndi_ra_free(new_child, pcibus_base+1, pcibus_alen-1, 4129 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS); 4130 4131 next_bus = pcibus_base; 4132 max_bus = pcibus_base + pcibus_alen - 1; 4133 4134 new_bus = next_bus; 4135 4136 DEBUG1("NEW bus found ->[%d]\n", new_bus); 4137 4138 /* Keep track of highest bus for subordinate bus programming */ 4139 *highest_bus = new_bus; 4140 4141 /* 4142 * Allocate (non-prefetchable) Memory Space for Bridge 4143 */ 4144 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4145 req.ra_flags = (NDI_RA_ALLOC_BOUNDED | NDI_RA_ALLOC_PARTIAL_OK); 4146 req.ra_boundbase = 0; 4147 /* 4148 * limit the boundlen,len to a 32b quantity. It should be Ok to 4149 * lose alignment-based-size of resource due to this. 4150 */ 4151 req.ra_boundlen = PCICFG_4GIG_LIMIT; 4152 req.ra_len = PCICFG_4GIG_LIMIT; /* Get as big as possible */ 4153 req.ra_align_mask = 4154 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ 4155 4156 rval = ndi_ra_alloc(ddi_get_parent(new_child), &req, 4157 &mem_answer, &mem_alen, NDI_RA_TYPE_MEM, NDI_RA_PASS); 4158 4159 if (rval != NDI_SUCCESS) { 4160 if (rval == NDI_RA_PARTIAL_REQ) { 4161 /*EMPTY*/ 4162 DEBUG0("NDI_RA_PARTIAL_REQ returned\n"); 4163 } else { 4164 DEBUG0( 4165 "Failed to allocate memory for bridge\n"); 4166 rval = PCICFG_NORESRC; 4167 goto cleanup; 4168 } 4169 } 4170 4171 DEBUG3("Bridge Memory Allocated [0x%x.%x] len [0x%x]\n", 4172 PCICFG_HIADDR(mem_answer), 4173 PCICFG_LOADDR(mem_answer), 4174 mem_alen); 4175 4176 /* 4177 * Put available memory into the pool. 4178 */ 4179 (void) ndi_ra_free(new_child, mem_answer, mem_alen, NDI_RA_TYPE_MEM, 4180 NDI_RA_PASS); 4181 4182 mem_base = mem_answer; 4183 4184 /* 4185 * Allocate I/O Space for Bridge 4186 */ 4187 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4188 req.ra_align_mask = PCICFG_IOGRAN - 1; /* 4k alignment */ 4189 req.ra_boundbase = 0; 4190 req.ra_boundlen = PCICFG_4GIG_LIMIT; 4191 req.ra_flags = (NDI_RA_ALLOC_BOUNDED | NDI_RA_ALLOC_PARTIAL_OK); 4192 req.ra_len = PCICFG_4GIG_LIMIT; /* Get as big as possible */ 4193 4194 rval = ndi_ra_alloc(ddi_get_parent(new_child), &req, &io_answer, 4195 &io_alen, NDI_RA_TYPE_IO, NDI_RA_PASS); 4196 4197 if (rval != NDI_SUCCESS) { 4198 if (rval == NDI_RA_PARTIAL_REQ) { 4199 /*EMPTY*/ 4200 DEBUG0("NDI_RA_PARTIAL_REQ returned\n"); 4201 } else { 4202 DEBUG0("Failed to allocate io space for bridge\n"); 4203 /* i/o space is an optional requirement so continue */ 4204 } 4205 } 4206 4207 DEBUG3("Bridge IO Space Allocated [0x%x.%x] len [0x%x]\n", 4208 PCICFG_HIADDR(io_answer), PCICFG_LOADDR(io_answer), io_alen); 4209 4210 /* 4211 * Put available I/O into the pool. 4212 */ 4213 (void) ndi_ra_free(new_child, io_answer, io_alen, NDI_RA_TYPE_IO, 4214 NDI_RA_PASS); 4215 4216 io_base = io_answer; 4217 4218 /* 4219 * Check if the bridge supports Prefetchable memory range. 4220 * If it does, then we setup PF memory range for the bridge. 4221 * Otherwise, we skip the step of setting up PF memory 4222 * range for it. This could cause config operation to 4223 * fail if any devices under the bridge need PF memory. 4224 */ 4225 /* write a non zero value to the PF BASE register */ 4226 pci_config_put16(h, PCI_BCNF_PF_BASE_LOW, 0xfff0); 4227 /* if the read returns zero then PF range is not supported */ 4228 if (pci_config_get16(h, PCI_BCNF_PF_BASE_LOW) == 0) { 4229 /* bridge doesn't support PF memory range */ 4230 goto pf_setup_end; 4231 } else { 4232 pf_mem_supported = 1; 4233 /* reset the PF BASE register */ 4234 pci_config_put16(h, PCI_BCNF_PF_BASE_LOW, 0); 4235 } 4236 4237 /* 4238 * Bridge supports PF mem range; Allocate PF Memory Space for it. 4239 * 4240 * Note: Both non-prefetchable and prefetchable memory space 4241 * allocations are made within 32bit space. Currently, BIOSs 4242 * allocate device memory for PCI devices within the 32bit space 4243 * so this will not be a problem. 4244 */ 4245 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4246 req.ra_flags = NDI_RA_ALLOC_PARTIAL_OK | NDI_RA_ALLOC_BOUNDED; 4247 req.ra_boundbase = 0; 4248 req.ra_len = PCICFG_4GIG_LIMIT; /* Get as big as possible */ 4249 req.ra_align_mask = 4250 PCICFG_MEMGRAN - 1; /* 1M alignment on memory space */ 4251 4252 rval = ndi_ra_alloc(ddi_get_parent(new_child), &req, 4253 &pf_mem_answer, &pf_mem_alen, NDI_RA_TYPE_PCI_PREFETCH_MEM, 4254 NDI_RA_PASS); 4255 4256 if (rval != NDI_SUCCESS) { 4257 if (rval == NDI_RA_PARTIAL_REQ) { 4258 /*EMPTY*/ 4259 DEBUG0("NDI_RA_PARTIAL_REQ returned\n"); 4260 } else { 4261 DEBUG0( 4262 "Failed to allocate PF memory for bridge\n"); 4263 /* PF mem is an optional requirement so continue */ 4264 } 4265 } 4266 4267 DEBUG3("Bridge PF Memory Allocated [0x%x.%x] len [0x%x]\n", 4268 PCICFG_HIADDR(pf_mem_answer), 4269 PCICFG_LOADDR(pf_mem_answer), 4270 pf_mem_alen); 4271 4272 /* 4273 * Put available PF memory into the pool. 4274 */ 4275 (void) ndi_ra_free(new_child, pf_mem_answer, pf_mem_alen, 4276 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 4277 4278 pf_mem_base = pf_mem_answer; 4279 4280 /* 4281 * Program the PF memory base register with the 4282 * start of the memory range 4283 */ 4284 pci_config_put16(h, PCI_BCNF_PF_BASE_LOW, 4285 PCICFG_HIWORD(PCICFG_LOADDR(pf_mem_answer))); 4286 pci_config_put32(h, PCI_BCNF_PF_BASE_HIGH, 4287 PCICFG_HIADDR(pf_mem_answer)); 4288 4289 /* 4290 * Program the PF memory limit register with the 4291 * end of the memory range. 4292 */ 4293 pci_config_put16(h, PCI_BCNF_PF_LIMIT_LOW, 4294 PCICFG_HIWORD(PCICFG_LOADDR( 4295 PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), 4296 PCICFG_MEMGRAN) - 1))); 4297 pci_config_put32(h, PCI_BCNF_PF_LIMIT_HIGH, 4298 PCICFG_HIADDR(PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), 4299 PCICFG_MEMGRAN) - 1)); 4300 4301 /* 4302 * Allocate the chunk of PF memory (if any) not programmed into the 4303 * bridge because of the round down. 4304 */ 4305 if (PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), PCICFG_MEMGRAN) 4306 != (pf_mem_answer + pf_mem_alen)) { 4307 DEBUG0("Need to allocate Memory round off chunk\n"); 4308 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4309 req.ra_flags = NDI_RA_ALLOC_SPECIFIED; 4310 req.ra_addr = PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), 4311 PCICFG_MEMGRAN); 4312 req.ra_len = (pf_mem_answer + pf_mem_alen) - 4313 (PCICFG_ROUND_DOWN((pf_mem_answer + pf_mem_alen), 4314 PCICFG_MEMGRAN)); 4315 4316 (void) ndi_ra_alloc(new_child, &req, 4317 &round_answer, &round_len, NDI_RA_TYPE_PCI_PREFETCH_MEM, 4318 NDI_RA_PASS); 4319 } 4320 4321 pf_setup_end: 4322 4323 /* 4324 * Program the memory base register with the 4325 * start of the memory range 4326 */ 4327 pci_config_put16(h, PCI_BCNF_MEM_BASE, 4328 PCICFG_HIWORD(PCICFG_LOADDR(mem_answer))); 4329 4330 /* 4331 * Program the memory limit register with the 4332 * end of the memory range. 4333 */ 4334 4335 pci_config_put16(h, PCI_BCNF_MEM_LIMIT, 4336 PCICFG_HIWORD(PCICFG_LOADDR( 4337 PCICFG_ROUND_DOWN((mem_answer + mem_alen), PCICFG_MEMGRAN) - 1))); 4338 4339 /* 4340 * Allocate the chunk of memory (if any) not programmed into the 4341 * bridge because of the round down. 4342 */ 4343 if (PCICFG_ROUND_DOWN((mem_answer + mem_alen), PCICFG_MEMGRAN) 4344 != (mem_answer + mem_alen)) { 4345 DEBUG0("Need to allocate Memory round off chunk\n"); 4346 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4347 req.ra_flags = NDI_RA_ALLOC_SPECIFIED; 4348 req.ra_addr = PCICFG_ROUND_DOWN((mem_answer + mem_alen), 4349 PCICFG_MEMGRAN); 4350 req.ra_len = (mem_answer + mem_alen) - 4351 (PCICFG_ROUND_DOWN((mem_answer + mem_alen), 4352 PCICFG_MEMGRAN)); 4353 4354 (void) ndi_ra_alloc(new_child, &req, 4355 &round_answer, &round_len, NDI_RA_TYPE_MEM, NDI_RA_PASS); 4356 } 4357 4358 /* 4359 * Program the I/O Space Base 4360 */ 4361 pci_config_put8(h, PCI_BCNF_IO_BASE_LOW, 4362 PCICFG_HIBYTE(PCICFG_LOWORD( 4363 PCICFG_LOADDR(io_answer)))); 4364 4365 pci_config_put16(h, PCI_BCNF_IO_BASE_HI, 4366 PCICFG_HIWORD(PCICFG_LOADDR(io_answer))); 4367 4368 /* 4369 * Program the I/O Space Limit 4370 */ 4371 pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW, 4372 PCICFG_HIBYTE(PCICFG_LOWORD( 4373 PCICFG_LOADDR(PCICFG_ROUND_DOWN(io_answer + io_alen, 4374 PCICFG_IOGRAN)))) - 1); 4375 4376 pci_config_put16(h, PCI_BCNF_IO_LIMIT_HI, 4377 PCICFG_HIWORD(PCICFG_LOADDR( 4378 PCICFG_ROUND_DOWN(io_answer + io_alen, PCICFG_IOGRAN))) 4379 - 1); 4380 4381 /* 4382 * Allocate the chunk of I/O (if any) not programmed into the 4383 * bridge because of the round down. 4384 */ 4385 if (PCICFG_ROUND_DOWN((io_answer + io_alen), PCICFG_IOGRAN) 4386 != (io_answer + io_alen)) { 4387 DEBUG0("Need to allocate I/O round off chunk\n"); 4388 bzero((caddr_t)&req, sizeof (ndi_ra_request_t)); 4389 req.ra_flags = NDI_RA_ALLOC_SPECIFIED; 4390 req.ra_addr = PCICFG_ROUND_DOWN((io_answer + io_alen), 4391 PCICFG_IOGRAN); 4392 req.ra_len = (io_answer + io_alen) - 4393 (PCICFG_ROUND_DOWN((io_answer + io_alen), 4394 PCICFG_IOGRAN)); 4395 4396 (void) ndi_ra_alloc(new_child, &req, 4397 &round_answer, &round_len, NDI_RA_TYPE_IO, NDI_RA_PASS); 4398 } 4399 4400 (void) pcicfg_set_bus_numbers(h, bus, new_bus, max_bus); 4401 4402 /* 4403 * Setup "ranges" and "bus-range" properties before onlining 4404 * the bridge. 4405 */ 4406 bzero((caddr_t)range, sizeof (ppb_ranges_t) * PCICFG_RANGE_LEN); 4407 4408 range[0].child_high = range[0].parent_high |= (PCI_REG_REL_M | 4409 PCI_ADDR_IO); 4410 range[0].child_low = range[0].parent_low = io_base; 4411 range[1].child_high = range[1].parent_high |= 4412 (PCI_REG_REL_M | PCI_ADDR_MEM32); 4413 range[1].child_low = range[1].parent_low = mem_base; 4414 range[2].child_high = range[2].parent_high |= 4415 (PCI_REG_REL_M | PCI_ADDR_MEM64 | PCI_REG_PF_M); 4416 range[2].child_low = range[2].parent_low = pf_mem_base; 4417 4418 range[0].size_low = io_alen; 4419 (void) pcicfg_update_ranges_prop(new_child, &range[0]); 4420 range[1].size_low = mem_alen; 4421 (void) pcicfg_update_ranges_prop(new_child, &range[1]); 4422 range[2].size_low = pf_mem_alen; 4423 (void) pcicfg_update_ranges_prop(new_child, &range[2]); 4424 4425 bus_range[0] = new_bus; 4426 bus_range[1] = max_bus; 4427 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, new_child, 4428 "bus-range", bus_range, 2); 4429 4430 /* 4431 * Reset the secondary bus 4432 */ 4433 pci_config_put16(h, PCI_BCNF_BCNTRL, 4434 pci_config_get16(h, PCI_BCNF_BCNTRL) | 0x40); 4435 4436 drv_usecwait(100); 4437 4438 pci_config_put16(h, PCI_BCNF_BCNTRL, 4439 pci_config_get16(h, PCI_BCNF_BCNTRL) & ~0x40); 4440 4441 /* 4442 * Clear status bits 4443 */ 4444 pci_config_put16(h, PCI_BCNF_SEC_STATUS, 0xffff); 4445 4446 /* 4447 * Needs to be set to this value 4448 */ 4449 pci_config_put8(h, PCI_CONF_ILINE, 0xf); 4450 4451 /* check our device_type as defined by Open Firmware */ 4452 if (pcicfg_pcie_device_type(new_child, h) == DDI_SUCCESS) 4453 pcie_device_type = 1; 4454 4455 /* 4456 * Set bus properties 4457 */ 4458 if (pcicfg_set_busnode_props(new_child, pcie_device_type) 4459 != PCICFG_SUCCESS) { 4460 DEBUG0("Failed to set busnode props\n"); 4461 rval = PCICFG_FAILURE; 4462 goto cleanup; 4463 } 4464 4465 (void) pcicfg_device_on(h); 4466 4467 if (is_pcie) 4468 pcie_init_bus(new_child, 0, PCIE_BUS_FINAL); 4469 if (ndi_devi_online(new_child, NDI_NO_EVENT|NDI_CONFIG) 4470 != NDI_SUCCESS) { 4471 DEBUG0("Unable to online bridge\n"); 4472 rval = PCICFG_FAILURE; 4473 goto cleanup; 4474 } 4475 4476 DEBUG0("Bridge is ONLINE\n"); 4477 4478 /* 4479 * After a Reset, we need to wait 2^25 clock cycles before the 4480 * first Configuration access. The worst case is 33MHz, which 4481 * is a 1 second wait. 4482 */ 4483 drv_usecwait(pcicfg_sec_reset_delay); 4484 4485 /* 4486 * Probe all children devices 4487 */ 4488 DEBUG0("Bridge Programming Complete - probe children\n"); 4489 ndi_devi_enter(new_child, &count); 4490 for (i = 0; ((i < PCI_MAX_DEVICES) && (ari_mode == B_FALSE)); 4491 i++) { 4492 for (j = 0; j < max_function; ) { 4493 if (ari_mode) 4494 trans_device = j >> 3; 4495 else 4496 trans_device = i; 4497 4498 if ((rval = pcicfg_probe_children(new_child, 4499 new_bus, trans_device, j & 7, highest_bus, 4500 0, is_pcie)) != PCICFG_SUCCESS) { 4501 if (rval == PCICFG_NODEVICE) { 4502 DEBUG3("No Device at bus [0x%x]" 4503 "device [0x%x] " 4504 "func [0x%x]\n", new_bus, 4505 trans_device, j & 7); 4506 4507 if (j) 4508 goto next; 4509 } else 4510 /*EMPTY*/ 4511 DEBUG3("Failed to configure bus " 4512 "[0x%x] device [0x%x] " 4513 "func [0x%x]\n", new_bus, 4514 trans_device, j & 7); 4515 break; 4516 } 4517 next: 4518 new_device = pcicfg_devi_find(new_child, trans_device, 4519 (j & 7)); 4520 4521 /* 4522 * Determine if ARI Forwarding should be enabled. 4523 */ 4524 if (j == 0) { 4525 if (new_device == NULL) 4526 break; 4527 4528 if ((pcie_ari_supported(new_child) == 4529 PCIE_ARI_FORW_SUPPORTED) && 4530 (pcie_ari_device(new_device) == 4531 PCIE_ARI_DEVICE)) { 4532 if (pcie_ari_enable(new_child) == 4533 DDI_SUCCESS) { 4534 (void) ddi_prop_create( 4535 DDI_DEV_T_NONE, 4536 new_child, 4537 DDI_PROP_CANSLEEP, 4538 "ari-enabled", NULL, 0); 4539 ari_mode = B_TRUE; 4540 max_function = 4541 PCICFG_MAX_ARI_FUNCTION; 4542 } 4543 } 4544 } 4545 if (ari_mode == B_TRUE) { 4546 int next_function; 4547 4548 if (new_device == NULL) 4549 break; 4550 4551 if (pcie_ari_get_next_function(new_device, 4552 &next_function) != DDI_SUCCESS) 4553 break; 4554 4555 j = next_function; 4556 4557 if (next_function == 0) 4558 break; 4559 } else 4560 j++; 4561 4562 } 4563 /* if any function fails to be configured, no need to proceed */ 4564 if (rval != PCICFG_NODEVICE) 4565 break; 4566 } 4567 ndi_devi_exit(new_child, count); 4568 4569 /* 4570 * Offline the bridge to allow reprogramming of resources. 4571 * 4572 * This should always succeed since nobody else has started to 4573 * use it yet, failing to detach the driver would indicate a bug. 4574 * Also in that case it's better just panic than allowing the 4575 * configurator to proceed with BAR reprogramming without bridge 4576 * driver detached. 4577 */ 4578 VERIFY(ndi_devi_offline(new_child, NDI_NO_EVENT|NDI_UNCONFIG) 4579 == NDI_SUCCESS); 4580 if (is_pcie) 4581 pcie_fini_bus(new_child, PCIE_BUS_INITIAL); 4582 4583 phdl.dip = new_child; 4584 phdl.memory_base = mem_answer; 4585 phdl.io_base = io_answer; 4586 phdl.pf_memory_base = pf_mem_answer; 4587 phdl.error = PCICFG_SUCCESS; /* in case of empty child tree */ 4588 4589 ndi_devi_enter(ddi_get_parent(new_child), &count); 4590 ddi_walk_devs(new_child, pcicfg_find_resource_end, (void *)&phdl); 4591 ndi_devi_exit(ddi_get_parent(new_child), count); 4592 4593 num_slots = pcicfg_get_nslots(new_child, h); 4594 mem_end = PCICFG_ROUND_UP(phdl.memory_base, PCICFG_MEMGRAN); 4595 io_end = PCICFG_ROUND_UP(phdl.io_base, PCICFG_IOGRAN); 4596 pf_mem_end = PCICFG_ROUND_UP(phdl.pf_memory_base, PCICFG_MEMGRAN); 4597 4598 DEBUG4("Start of Unallocated Bridge(%d slots) Resources Mem=0x%lx " 4599 "I/O=0x%lx PF_mem=%x%lx\n", num_slots, mem_end, io_end, pf_mem_end); 4600 4601 /* 4602 * Before probing the children we've allocated maximum MEM/IO 4603 * resources from parent, and updated "available" property 4604 * accordingly. Later we'll be giving up unused resources to 4605 * the parent, thus we need to destroy "available" property 4606 * here otherwise it will be out-of-sync with the actual free 4607 * resources this bridge has. This property will be rebuilt below 4608 * with the actual free resources reserved for hotplug slots 4609 * (if any). 4610 */ 4611 (void) ndi_prop_remove(DDI_DEV_T_NONE, new_child, "available"); 4612 /* 4613 * if the bridge a slots, then preallocate. If not, assume static 4614 * configuration. Also check for preallocation limits and spit 4615 * warning messages appropriately (perhaps some can be in debug mode). 4616 */ 4617 if (num_slots) { 4618 uint64_t mem_reqd = mem_answer + 4619 (num_slots * pcicfg_slot_memsize); 4620 uint64_t io_reqd = io_answer + 4621 (num_slots * pcicfg_slot_iosize); 4622 uint64_t pf_mem_reqd = pf_mem_answer + 4623 (num_slots * pcicfg_slot_pf_memsize); 4624 uint8_t highest_bus_reqd = new_bus + 4625 (num_slots * pcicfg_slot_busnums); 4626 #ifdef DEBUG 4627 if (mem_end > mem_reqd) 4628 DEBUG3("Memory space consumed by bridge more " 4629 "than planned for %d slot(s)(%" PRIx64 ",%" 4630 PRIx64 ")", num_slots, mem_answer, mem_end); 4631 if (io_end > io_reqd) 4632 DEBUG3("IO space consumed by bridge more than" 4633 " planned for %d slot(s)(%" PRIx64 ",%" PRIx64 ")", 4634 num_slots, io_answer, io_end); 4635 if (pf_mem_end > pf_mem_reqd) 4636 DEBUG3("PF Memory space consumed by bridge" 4637 " more than planned for %d slot(s)(%" PRIx64 ",%" 4638 PRIx64 ")", num_slots, pf_mem_answer, pf_mem_end); 4639 if (*highest_bus > highest_bus_reqd) 4640 DEBUG3("Buses consumed by bridge more " 4641 "than planned for %d slot(s)(%x, %x)", 4642 num_slots, new_bus, *highest_bus); 4643 4644 if (mem_reqd > (mem_answer + mem_alen)) 4645 DEBUG3("Memory space required by bridge more " 4646 "than available for %d slot(s)(%" PRIx64 ",%" 4647 PRIx64 ")", num_slots, mem_answer, mem_end); 4648 if (io_reqd > (io_answer + io_alen)) 4649 DEBUG3("IO space required by bridge more than" 4650 "available for %d slot(s)(%" PRIx64 ",%" PRIx64 ")", 4651 num_slots, io_answer, io_end); 4652 if (pf_mem_reqd > (pf_mem_answer + pf_mem_alen)) 4653 DEBUG3("PF Memory space required by bridge" 4654 " more than available for %d slot(s)(%" PRIx64 ",%" 4655 PRIx64 ")", num_slots, pf_mem_answer, pf_mem_end); 4656 if (highest_bus_reqd > max_bus) 4657 DEBUG3("Bus numbers required by bridge more " 4658 "than available for %d slot(s)(%x, %x)", 4659 num_slots, new_bus, *highest_bus); 4660 #endif 4661 mem_end = MAX((MIN(mem_reqd, (mem_answer + mem_alen))), 4662 mem_end); 4663 io_end = MAX((MIN(io_reqd, (io_answer + io_alen))), io_end); 4664 pf_mem_end = MAX((MIN(pf_mem_reqd, (pf_mem_answer + 4665 pf_mem_alen))), pf_mem_end); 4666 *highest_bus = MAX((MIN(highest_bus_reqd, max_bus)), 4667 *highest_bus); 4668 DEBUG4("mem_end %lx, io_end %lx, pf_mem_end %lx" 4669 " highest_bus %x\n", mem_end, io_end, pf_mem_end, 4670 *highest_bus); 4671 } 4672 4673 /* 4674 * Give back unused memory space to parent. 4675 */ 4676 (void) ndi_ra_free(ddi_get_parent(new_child), mem_end, 4677 (mem_answer + mem_alen) - mem_end, NDI_RA_TYPE_MEM, NDI_RA_PASS); 4678 4679 if (mem_end == mem_answer) { 4680 DEBUG0("No memory resources used\n"); 4681 /* 4682 * To prevent the bridge from forwarding any Memory 4683 * transactions, the Memory Limit will be programmed 4684 * with a smaller value than the Memory Base. 4685 */ 4686 pci_config_put16(h, PCI_BCNF_MEM_BASE, 0xffff); 4687 pci_config_put16(h, PCI_BCNF_MEM_LIMIT, 0); 4688 4689 mem_size = 0; 4690 } else { 4691 /* 4692 * Reprogram the end of the memory. 4693 */ 4694 pci_config_put16(h, PCI_BCNF_MEM_LIMIT, 4695 PCICFG_HIWORD(mem_end) - 1); 4696 mem_size = mem_end - mem_base; 4697 } 4698 4699 /* 4700 * Give back unused io space to parent. 4701 */ 4702 (void) ndi_ra_free(ddi_get_parent(new_child), 4703 io_end, (io_answer + io_alen) - io_end, 4704 NDI_RA_TYPE_IO, NDI_RA_PASS); 4705 4706 if (io_end == io_answer) { 4707 DEBUG0("No IO Space resources used\n"); 4708 4709 /* 4710 * To prevent the bridge from forwarding any I/O 4711 * transactions, the I/O Limit will be programmed 4712 * with a smaller value than the I/O Base. 4713 */ 4714 pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW, 0); 4715 pci_config_put16(h, PCI_BCNF_IO_LIMIT_HI, 0); 4716 pci_config_put8(h, PCI_BCNF_IO_BASE_LOW, 0xff); 4717 pci_config_put16(h, PCI_BCNF_IO_BASE_HI, 0); 4718 4719 io_size = 0; 4720 } else { 4721 /* 4722 * Reprogram the end of the io space. 4723 */ 4724 pci_config_put8(h, PCI_BCNF_IO_LIMIT_LOW, 4725 PCICFG_HIBYTE(PCICFG_LOWORD( 4726 PCICFG_LOADDR(io_end) - 1))); 4727 4728 pci_config_put16(h, PCI_BCNF_IO_LIMIT_HI, 4729 PCICFG_HIWORD(PCICFG_LOADDR(io_end - 1))); 4730 4731 io_size = io_end - io_base; 4732 } 4733 4734 /* 4735 * Give back unused PF memory space to parent. 4736 */ 4737 if (pf_mem_supported) { 4738 (void) ndi_ra_free(ddi_get_parent(new_child), 4739 pf_mem_end, (pf_mem_answer + pf_mem_alen) - pf_mem_end, 4740 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 4741 4742 if (pf_mem_end == pf_mem_answer) { 4743 DEBUG0("No PF memory resources used\n"); 4744 /* 4745 * To prevent the bridge from forwarding any PF Memory 4746 * transactions, the PF Memory Limit will be programmed 4747 * with a smaller value than the Memory Base. 4748 */ 4749 pci_config_put16(h, PCI_BCNF_PF_BASE_LOW, 0xfff0); 4750 pci_config_put32(h, PCI_BCNF_PF_BASE_HIGH, 0xffffffff); 4751 pci_config_put16(h, PCI_BCNF_PF_LIMIT_LOW, 0); 4752 pci_config_put32(h, PCI_BCNF_PF_LIMIT_HIGH, 0); 4753 4754 pf_mem_size = 0; 4755 } else { 4756 /* 4757 * Reprogram the end of the PF memory range. 4758 */ 4759 pci_config_put16(h, PCI_BCNF_PF_LIMIT_LOW, 4760 PCICFG_HIWORD(PCICFG_LOADDR(pf_mem_end - 1))); 4761 pci_config_put32(h, PCI_BCNF_PF_LIMIT_HIGH, 4762 PCICFG_HIADDR(pf_mem_end - 1)); 4763 pf_mem_size = pf_mem_end - pf_mem_base; 4764 } 4765 } 4766 4767 if ((max_bus - *highest_bus) > 0) { 4768 /* 4769 * Give back unused bus numbers 4770 */ 4771 (void) ndi_ra_free(ddi_get_parent(new_child), 4772 *highest_bus+1, max_bus - *highest_bus, 4773 NDI_RA_TYPE_PCI_BUSNUM, NDI_RA_PASS); 4774 } 4775 4776 /* 4777 * Set bus numbers to ranges encountered during scan 4778 */ 4779 (void) pcicfg_set_bus_numbers(h, bus, new_bus, *highest_bus); 4780 4781 /* 4782 * Remove the ranges property if it exists since we will create 4783 * a new one. 4784 */ 4785 (void) ndi_prop_remove(DDI_DEV_T_NONE, new_child, "ranges"); 4786 4787 DEBUG2("Creating Ranges property - Mem Address %lx Mem Size %x\n", 4788 mem_base, mem_size); 4789 DEBUG2(" - I/O Address %lx I/O Size %x\n", 4790 io_base, io_size); 4791 DEBUG2(" - PF Mem address %lx PF Mem Size %x\n", 4792 pf_mem_base, pf_mem_size); 4793 4794 bzero((caddr_t)range, sizeof (ppb_ranges_t) * PCICFG_RANGE_LEN); 4795 4796 range[0].child_high = range[0].parent_high |= (PCI_REG_REL_M | 4797 PCI_ADDR_IO); 4798 range[0].child_low = range[0].parent_low = io_base; 4799 range[1].child_high = range[1].parent_high |= 4800 (PCI_REG_REL_M | PCI_ADDR_MEM32); 4801 range[1].child_low = range[1].parent_low = mem_base; 4802 range[2].child_high = range[2].parent_high |= 4803 (PCI_REG_REL_M | PCI_ADDR_MEM64 | PCI_REG_PF_M); 4804 range[2].child_low = range[2].parent_low = pf_mem_base; 4805 4806 if (io_size > 0) { 4807 range[0].size_low = io_size; 4808 (void) pcicfg_update_ranges_prop(new_child, &range[0]); 4809 } 4810 if (mem_size > 0) { 4811 range[1].size_low = mem_size; 4812 (void) pcicfg_update_ranges_prop(new_child, &range[1]); 4813 } 4814 if (pf_mem_size > 0) { 4815 range[2].size_low = pf_mem_size; 4816 (void) pcicfg_update_ranges_prop(new_child, &range[2]); 4817 } 4818 4819 bus_range[0] = pci_config_get8(h, PCI_BCNF_SECBUS); 4820 bus_range[1] = pci_config_get8(h, PCI_BCNF_SUBBUS); 4821 DEBUG1("End of bridge probe: bus_range[0] = %d\n", bus_range[0]); 4822 DEBUG1("End of bridge probe: bus_range[1] = %d\n", bus_range[1]); 4823 4824 (void) ndi_prop_update_int_array(DDI_DEV_T_NONE, new_child, 4825 "bus-range", bus_range, 2); 4826 4827 rval = PCICFG_SUCCESS; 4828 4829 PCICFG_DUMP_BRIDGE_CONFIG(h); 4830 4831 cleanup: 4832 /* free up resources (for error return case only) */ 4833 if (rval != PCICFG_SUCCESS) { 4834 if (mem_alen) 4835 (void) ndi_ra_free(ddi_get_parent(new_child), mem_base, 4836 mem_alen, NDI_RA_TYPE_MEM, NDI_RA_PASS); 4837 if (io_alen) 4838 (void) ndi_ra_free(ddi_get_parent(new_child), io_base, 4839 io_alen, NDI_RA_TYPE_IO, NDI_RA_PASS); 4840 if (pf_mem_alen) 4841 (void) ndi_ra_free(ddi_get_parent(new_child), 4842 pf_mem_base, pf_mem_alen, 4843 NDI_RA_TYPE_PCI_PREFETCH_MEM, NDI_RA_PASS); 4844 if (pcibus_alen) 4845 (void) ndi_ra_free(ddi_get_parent(new_child), 4846 pcibus_base, pcibus_alen, NDI_RA_TYPE_PCI_BUSNUM, 4847 NDI_RA_PASS); 4848 } 4849 4850 /* free up any resource maps setup for the bridge node */ 4851 (void) ndi_ra_map_destroy(new_child, NDI_RA_TYPE_PCI_BUSNUM); 4852 (void) ndi_ra_map_destroy(new_child, NDI_RA_TYPE_IO); 4853 (void) ndi_ra_map_destroy(new_child, NDI_RA_TYPE_MEM); 4854 (void) ndi_ra_map_destroy(new_child, NDI_RA_TYPE_PCI_PREFETCH_MEM); 4855 4856 return (rval); 4857 } 4858 4859 static int 4860 pcicfg_find_resource_end(dev_info_t *dip, void *hdl) 4861 { 4862 pcicfg_phdl_t *entry = (pcicfg_phdl_t *)hdl; 4863 pci_regspec_t *pci_ap; 4864 int length; 4865 int rcount; 4866 int i; 4867 4868 entry->error = PCICFG_SUCCESS; 4869 4870 if (dip == entry->dip) { 4871 DEBUG0("Don't include parent bridge node\n"); 4872 return (DDI_WALK_CONTINUE); 4873 } else { 4874 if (ddi_getlongprop(DDI_DEV_T_ANY, dip, 4875 DDI_PROP_DONTPASS, "assigned-addresses", 4876 (caddr_t)&pci_ap, &length) != DDI_PROP_SUCCESS) { 4877 DEBUG0("Node doesn't have assigned-addresses\n"); 4878 return (DDI_WALK_CONTINUE); 4879 } 4880 4881 rcount = length / sizeof (pci_regspec_t); 4882 4883 for (i = 0; i < rcount; i++) { 4884 4885 switch (PCI_REG_ADDR_G(pci_ap[i].pci_phys_hi)) { 4886 4887 case PCI_REG_ADDR_G(PCI_ADDR_MEM32): 4888 if (pci_ap[i].pci_phys_hi & PCI_REG_PF_M) { 4889 if ((pci_ap[i].pci_phys_low + 4890 pci_ap[i].pci_size_low) > 4891 entry->pf_memory_base) { 4892 entry->pf_memory_base = 4893 pci_ap[i].pci_phys_low + 4894 pci_ap[i].pci_size_low; 4895 } 4896 } else { 4897 if ((pci_ap[i].pci_phys_low + 4898 pci_ap[i].pci_size_low) > 4899 entry->memory_base) { 4900 entry->memory_base = 4901 pci_ap[i].pci_phys_low + 4902 pci_ap[i].pci_size_low; 4903 } 4904 } 4905 break; 4906 case PCI_REG_ADDR_G(PCI_ADDR_MEM64): 4907 if (pci_ap[i].pci_phys_hi & PCI_REG_PF_M) { 4908 if ((PCICFG_LADDR( 4909 pci_ap[i].pci_phys_low, 4910 pci_ap[i].pci_phys_mid) + 4911 pci_ap[i].pci_size_low) > 4912 entry->pf_memory_base) { 4913 entry->pf_memory_base = 4914 PCICFG_LADDR( 4915 pci_ap[i].pci_phys_low, 4916 pci_ap[i].pci_phys_mid) + 4917 pci_ap[i].pci_size_low; 4918 } 4919 } else { 4920 if ((PCICFG_LADDR( 4921 pci_ap[i].pci_phys_low, 4922 pci_ap[i].pci_phys_mid) + 4923 pci_ap[i].pci_size_low) > 4924 entry->memory_base) { 4925 entry->memory_base = 4926 PCICFG_LADDR( 4927 pci_ap[i].pci_phys_low, 4928 pci_ap[i].pci_phys_mid) + 4929 pci_ap[i].pci_size_low; 4930 } 4931 } 4932 break; 4933 case PCI_REG_ADDR_G(PCI_ADDR_IO): 4934 if ((pci_ap[i].pci_phys_low + 4935 pci_ap[i].pci_size_low) > 4936 entry->io_base) { 4937 entry->io_base = 4938 pci_ap[i].pci_phys_low + 4939 pci_ap[i].pci_size_low; 4940 } 4941 break; 4942 } 4943 } 4944 4945 /* 4946 * free the memory allocated by ddi_getlongprop 4947 */ 4948 kmem_free(pci_ap, length); 4949 4950 /* 4951 * continue the walk to the next sibling to sum memory 4952 */ 4953 return (DDI_WALK_CONTINUE); 4954 } 4955 } 4956 4957 /* 4958 * Make "parent" be the parent of the "child" dip 4959 */ 4960 static void 4961 pcicfg_reparent_node(dev_info_t *child, dev_info_t *parent) 4962 { 4963 int circ; 4964 dev_info_t *opdip; 4965 4966 ASSERT(i_ddi_node_state(child) <= DS_LINKED); 4967 /* 4968 * Unlink node from tree before reparenting 4969 */ 4970 opdip = ddi_get_parent(child); 4971 ndi_devi_enter(opdip, &circ); 4972 (void) i_ndi_unconfig_node(child, DS_PROTO, 0); 4973 ndi_devi_exit(opdip, circ); 4974 4975 DEVI(child)->devi_parent = DEVI(parent); 4976 DEVI(child)->devi_bus_ctl = DEVI(parent); 4977 (void) ndi_devi_bind_driver(child, 0); 4978 } 4979 4980 /* 4981 * Return PCICFG_SUCCESS if device exists at the specified address. 4982 * Return PCICFG_NODEVICE is no device exists at the specified address. 4983 */ 4984 int 4985 pcicfg_config_setup(dev_info_t *dip, ddi_acc_handle_t *handle) 4986 { 4987 caddr_t cfgaddr; 4988 ddi_device_acc_attr_t attr; 4989 dev_info_t *anode; 4990 int status; 4991 int rlen; 4992 pci_regspec_t *reg; 4993 int ret = DDI_SUCCESS; 4994 int16_t tmp; 4995 4996 /* 4997 * Get the pci register spec from the node 4998 */ 4999 status = ddi_getlongprop(DDI_DEV_T_ANY, dip, DDI_PROP_DONTPASS, "reg", 5000 (caddr_t)®, &rlen); 5001 5002 switch (status) { 5003 case DDI_PROP_SUCCESS: 5004 break; 5005 case DDI_PROP_NO_MEMORY: 5006 DEBUG0("reg present, but unable to get memory\n"); 5007 return (PCICFG_FAILURE); 5008 default: 5009 DEBUG0("no reg property\n"); 5010 return (PCICFG_FAILURE); 5011 } 5012 5013 anode = dip; 5014 DEBUG2("conf_map: dip=%p, anode=%p\n", dip, anode); 5015 5016 attr.devacc_attr_version = DDI_DEVICE_ATTR_V0; 5017 attr.devacc_attr_endian_flags = DDI_STRUCTURE_LE_ACC; 5018 attr.devacc_attr_dataorder = DDI_STRICTORDER_ACC; 5019 5020 if (ddi_regs_map_setup(anode, 0, &cfgaddr, 0, 0, &attr, handle) 5021 != DDI_SUCCESS) { 5022 DEBUG0("Failed to setup registers\n"); 5023 kmem_free((caddr_t)reg, rlen); 5024 return (PCICFG_FAILURE); 5025 } 5026 5027 /* 5028 * need to use DDI interfaces as the conf space is 5029 * cannot be directly accessed by the host. 5030 */ 5031 tmp = (int16_t)ddi_get16(*handle, (uint16_t *)cfgaddr); 5032 if ((tmp == (int16_t)0xffff) || (tmp == -1)) { 5033 DEBUG1("NO DEVICEFOUND, read %x\n", tmp); 5034 ret = PCICFG_NODEVICE; 5035 } else { 5036 if (tmp == 0) { 5037 DEBUG0("Device Not Ready yet ?"); 5038 ret = PCICFG_NODEVICE; 5039 } else { 5040 DEBUG1("DEVICEFOUND, read %x\n", tmp); 5041 ret = PCICFG_SUCCESS; 5042 } 5043 } 5044 5045 if (ret == PCICFG_NODEVICE) 5046 ddi_regs_map_free(handle); 5047 kmem_free((caddr_t)reg, rlen); 5048 5049 return (ret); 5050 5051 } 5052 5053 static void 5054 pcicfg_config_teardown(ddi_acc_handle_t *handle) 5055 { 5056 (void) ddi_regs_map_free(handle); 5057 } 5058 5059 static int 5060 pcicfg_add_config_reg(dev_info_t *dip, 5061 uint_t bus, uint_t device, uint_t func) 5062 { 5063 int reg[10] = { PCI_ADDR_CONFIG, 0, 0, 0, 0}; 5064 5065 reg[0] = PCICFG_MAKE_REG_HIGH(bus, device, func, 0); 5066 5067 return (ndi_prop_update_int_array(DDI_DEV_T_NONE, dip, "reg", reg, 5)); 5068 } 5069 5070 static int 5071 pcicfg_ari_configure(dev_info_t *dip) 5072 { 5073 if (pcie_ari_supported(dip) == PCIE_ARI_FORW_NOT_SUPPORTED) 5074 return (DDI_FAILURE); 5075 5076 /* 5077 * Until we have resource balancing, dynamically configure 5078 * ARI functions without firmware assistamce. 5079 */ 5080 return (DDI_FAILURE); 5081 } 5082 5083 5084 #ifdef DEBUG 5085 static void 5086 debug(char *fmt, uintptr_t a1, uintptr_t a2, uintptr_t a3, 5087 uintptr_t a4, uintptr_t a5) 5088 { 5089 if (pcicfg_debug > 1) { 5090 prom_printf("pcicfg: "); 5091 prom_printf(fmt, a1, a2, a3, a4, a5); 5092 } 5093 } 5094 #endif 5095 5096 /*ARGSUSED*/ 5097 static uint8_t 5098 pcicfg_get_nslots(dev_info_t *dip, ddi_acc_handle_t handle) 5099 { 5100 uint16_t cap_id_loc, slot_id_loc; 5101 uint8_t num_slots = 0; 5102 5103 /* just depend on the pcie_cap for now. */ 5104 (void) PCI_CAP_LOCATE(handle, PCI_CAP_ID_PCI_E, &cap_id_loc); 5105 (void) PCI_CAP_LOCATE(handle, PCI_CAP_ID_SLOT_ID, &slot_id_loc); 5106 if (cap_id_loc != PCI_CAP_NEXT_PTR_NULL) { 5107 if (pci_config_get8(handle, cap_id_loc + PCI_CAP_ID_REGS_OFF) & 5108 PCIE_PCIECAP_SLOT_IMPL) 5109 num_slots = 1; 5110 } else /* not a PCIe switch/bridge. Must be a PCI-PCI[-X] bridge */ 5111 if (slot_id_loc != PCI_CAP_NEXT_PTR_NULL) { 5112 uint8_t esr_reg = pci_config_get8(handle, slot_id_loc + 2); 5113 num_slots = PCI_CAPSLOT_NSLOTS(esr_reg); 5114 } 5115 /* XXX - need to cover PCI-PCIe bridge with n slots */ 5116 return (num_slots); 5117 } 5118 5119 /*ARGSUSED*/ 5120 static int 5121 pcicfg_pcie_dev(dev_info_t *dip, ddi_acc_handle_t handle) 5122 { 5123 /* get parent device's device_type property */ 5124 char *device_type; 5125 int val; 5126 dev_info_t *pdip = ddi_get_parent(dip); 5127 5128 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, DDI_PROP_DONTPASS, 5129 "device_type", &device_type) != DDI_PROP_SUCCESS) { 5130 DEBUG2("device_type property missing for %s#%d", 5131 ddi_get_name(pdip), ddi_get_instance(pdip)); 5132 return (DDI_FAILURE); 5133 } 5134 DEBUG1("device_type=<%s>\n", device_type); 5135 5136 val = DDI_FAILURE; 5137 if (strcmp(device_type, "pciex") == 0) 5138 val = DDI_SUCCESS; 5139 ddi_prop_free(device_type); 5140 return (val); 5141 } 5142 5143 static int 5144 pcicfg_pcie_device_type(dev_info_t *dip, ddi_acc_handle_t handle) 5145 { 5146 int port_type = pcicfg_pcie_port_type(dip, handle); 5147 5148 DEBUG1("device port_type = %x\n", port_type); 5149 /* No PCIe CAP regs, we are not PCIe device_type */ 5150 if (port_type < 0) 5151 return (DDI_FAILURE); 5152 5153 /* check for all PCIe device_types */ 5154 if ((port_type == PCIE_PCIECAP_DEV_TYPE_UP) || 5155 (port_type == PCIE_PCIECAP_DEV_TYPE_DOWN) || 5156 (port_type == PCIE_PCIECAP_DEV_TYPE_ROOT) || 5157 (port_type == PCIE_PCIECAP_DEV_TYPE_PCI2PCIE)) 5158 return (DDI_SUCCESS); 5159 5160 return (DDI_FAILURE); 5161 5162 } 5163 5164 /*ARGSUSED*/ 5165 static int 5166 pcicfg_pcie_port_type(dev_info_t *dip, ddi_acc_handle_t handle) 5167 { 5168 int port_type = -1; 5169 uint16_t cap_loc; 5170 5171 /* Note: need to look at the port type information here */ 5172 (void) PCI_CAP_LOCATE(handle, PCI_CAP_ID_PCI_E, &cap_loc); 5173 if (cap_loc != PCI_CAP_NEXT_PTR_NULL) 5174 port_type = pci_config_get16(handle, 5175 cap_loc + PCIE_PCIECAP) & PCIE_PCIECAP_DEV_TYPE_MASK; 5176 5177 return (port_type); 5178 } 5179 5180 /* 5181 * Return true if the devinfo node is in a PCI Express hierarchy. 5182 */ 5183 static boolean_t 5184 is_pcie_fabric(dev_info_t *dip) 5185 { 5186 dev_info_t *root = ddi_root_node(); 5187 dev_info_t *pdip; 5188 boolean_t found = B_FALSE; 5189 char *bus; 5190 5191 /* 5192 * Does this device reside in a pcie fabric ? 5193 */ 5194 for (pdip = dip; pdip && (pdip != root) && !found; 5195 pdip = ddi_get_parent(pdip)) { 5196 if (ddi_prop_lookup_string(DDI_DEV_T_ANY, pdip, 5197 DDI_PROP_DONTPASS, "device_type", &bus) != 5198 DDI_PROP_SUCCESS) 5199 break; 5200 5201 if (strcmp(bus, "pciex") == 0) 5202 found = B_TRUE; 5203 5204 ddi_prop_free(bus); 5205 } 5206 5207 return (found); 5208 } 5209