1 /* BEGIN CSTYLED */ 2 3 /* i915_drv.h -- Private header for the I915 driver -*- linux-c -*- 4 */ 5 /* 6 * 7 * Copyright 2003 Tungsten Graphics, Inc., Cedar Park, Texas. 8 * All Rights Reserved. 9 * 10 * Permission is hereby granted, free of charge, to any person obtaining a 11 * copy of this software and associated documentation files (the 12 * "Software"), to deal in the Software without restriction, including 13 * without limitation the rights to use, copy, modify, merge, publish, 14 * distribute, sub license, and/or sell copies of the Software, and to 15 * permit persons to whom the Software is furnished to do so, subject to 16 * the following conditions: 17 * 18 * The above copyright notice and this permission notice (including the 19 * next paragraph) shall be included in all copies or substantial portions 20 * of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 23 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF 24 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. 25 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR 26 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, 27 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE 28 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 29 * 30 */ 31 32 /* 33 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 34 * Use is subject to license terms. 35 */ 36 37 #ifndef _I915_DRV_H 38 #define _I915_DRV_H 39 40 /* General customization: 41 */ 42 43 #define DRIVER_AUTHOR "Tungsten Graphics, Inc." 44 45 #define DRIVER_NAME "i915" 46 #define DRIVER_DESC "Intel Graphics" 47 #define DRIVER_DATE "20060929" 48 49 #if defined(__SVR4) && defined(__sun) 50 #define spinlock_t kmutex_t 51 #endif 52 53 /* Interface history: 54 * 55 * 1.1: Original. 56 * 1.2: Add Power Management 57 * 1.3: Add vblank support 58 * 1.4: Fix cmdbuffer path, add heap destroy 59 */ 60 #define DRIVER_MAJOR 1 61 #define DRIVER_MINOR 5 62 #define DRIVER_PATCHLEVEL 0 63 64 #if defined(__linux__) 65 #define I915_HAVE_FENCE 66 #define I915_HAVE_BUFFER 67 #endif 68 69 typedef struct _drm_i915_ring_buffer { 70 int tail_mask; 71 unsigned long Size; 72 u8 *virtual_start; 73 int head; 74 int tail; 75 int space; 76 drm_local_map_t map; 77 } drm_i915_ring_buffer_t; 78 79 struct mem_block { 80 struct mem_block *next; 81 struct mem_block *prev; 82 int start; 83 int size; 84 drm_file_t *filp; /* 0: free, -1: heap, other: real files */ 85 }; 86 87 typedef struct _drm_i915_vbl_swap { 88 struct list_head head; 89 drm_drawable_t drw_id; 90 unsigned int plane; 91 unsigned int sequence; 92 int flip; 93 } drm_i915_vbl_swap_t; 94 95 typedef struct s3_i915_private { 96 ddi_acc_handle_t saveHandle; 97 caddr_t saveAddr; 98 uint32_t pgtbl_ctl; 99 uint8_t saveLBB; 100 uint32_t saveDSPACNTR; 101 uint32_t saveDSPBCNTR; 102 uint32_t saveDSPARB; 103 uint32_t savePIPEACONF; 104 uint32_t savePIPEBCONF; 105 uint32_t savePIPEASRC; 106 uint32_t savePIPEBSRC; 107 uint32_t saveFPA0; 108 uint32_t saveFPA1; 109 uint32_t saveDPLL_A; 110 uint32_t saveDPLL_A_MD; 111 uint32_t saveHTOTAL_A; 112 uint32_t saveHBLANK_A; 113 uint32_t saveHSYNC_A; 114 uint32_t saveVTOTAL_A; 115 uint32_t saveVBLANK_A; 116 uint32_t saveVSYNC_A; 117 uint32_t saveBCLRPAT_A; 118 uint32_t saveDSPASTRIDE; 119 uint32_t saveDSPASIZE; 120 uint32_t saveDSPAPOS; 121 uint32_t saveDSPABASE; 122 uint32_t saveDSPASURF; 123 uint32_t saveDSPATILEOFF; 124 uint32_t savePFIT_PGM_RATIOS; 125 uint32_t saveBLC_PWM_CTL; 126 uint32_t saveBLC_PWM_CTL2; 127 uint32_t saveFPB0; 128 uint32_t saveFPB1; 129 uint32_t saveDPLL_B; 130 uint32_t saveDPLL_B_MD; 131 uint32_t saveHTOTAL_B; 132 uint32_t saveHBLANK_B; 133 uint32_t saveHSYNC_B; 134 uint32_t saveVTOTAL_B; 135 uint32_t saveVBLANK_B; 136 uint32_t saveVSYNC_B; 137 uint32_t saveBCLRPAT_B; 138 uint32_t saveDSPBSTRIDE; 139 uint32_t saveDSPBSIZE; 140 uint32_t saveDSPBPOS; 141 uint32_t saveDSPBBASE; 142 uint32_t saveDSPBSURF; 143 uint32_t saveDSPBTILEOFF; 144 uint32_t saveVCLK_DIVISOR_VGA0; 145 uint32_t saveVCLK_DIVISOR_VGA1; 146 uint32_t saveVCLK_POST_DIV; 147 uint32_t saveVGACNTRL; 148 uint32_t saveADPA; 149 uint32_t saveLVDS; 150 uint32_t saveLVDSPP_ON; 151 uint32_t saveLVDSPP_OFF; 152 uint32_t saveDVOA; 153 uint32_t saveDVOB; 154 uint32_t saveDVOC; 155 uint32_t savePP_ON; 156 uint32_t savePP_OFF; 157 uint32_t savePP_CONTROL; 158 uint32_t savePP_CYCLE; 159 uint32_t savePFIT_CONTROL; 160 uint32_t save_palette_a[256]; 161 uint32_t save_palette_b[256]; 162 uint32_t saveFBC_CFB_BASE; 163 uint32_t saveFBC_LL_BASE; 164 uint32_t saveFBC_CONTROL; 165 uint32_t saveFBC_CONTROL2; 166 uint32_t saveIER; 167 uint32_t saveIIR; 168 uint32_t saveIMR; 169 uint32_t saveD_STATE; 170 uint32_t saveCG_2D_DIS; 171 uint32_t saveMI_ARB_STATE; 172 uint32_t savePIPEASTAT; 173 uint32_t savePIPEBSTAT; 174 uint32_t saveCACHE_MODE_0; 175 uint32_t saveSWF0[16]; 176 uint32_t saveSWF1[16]; 177 uint32_t saveSWF2[3]; 178 uint8_t saveMSR; 179 uint8_t saveSR[8]; 180 uint8_t saveGR[25]; 181 uint8_t saveAR_INDEX; 182 uint8_t saveAR[21]; 183 uint8_t saveDACMASK; 184 uint8_t saveDACDATA[256*3]; /* 256 3-byte colors */ 185 uint8_t saveCR[37]; 186 } s3_i915_private_t; 187 188 typedef struct drm_i915_private { 189 struct drm_device *dev; 190 191 drm_local_map_t *sarea; 192 drm_local_map_t *mmio_map; 193 194 drm_i915_sarea_t *sarea_priv; 195 drm_i915_ring_buffer_t ring; 196 197 drm_dma_handle_t *status_page_dmah; 198 void *hw_status_page; 199 dma_addr_t dma_status_page; 200 uint32_t counter; 201 unsigned int status_gfx_addr; 202 drm_local_map_t hws_map; 203 204 unsigned int cpp; 205 206 wait_queue_head_t irq_queue; 207 atomic_t irq_received; 208 209 int tex_lru_log_granularity; 210 int allow_batchbuffer; 211 struct mem_block *agp_heap; 212 unsigned int sr01, adpa, ppcr, dvob, dvoc, lvds; 213 int vblank_pipe; 214 spinlock_t user_irq_lock; 215 int user_irq_refcount; 216 int fence_irq_on; 217 uint32_t irq_mask_reg; 218 int irq_enabled; 219 220 #ifdef I915_HAVE_FENCE 221 uint32_t flush_sequence; 222 uint32_t flush_flags; 223 uint32_t flush_pending; 224 uint32_t saved_flush_status; 225 #endif 226 #ifdef I915_HAVE_BUFFER 227 void *agp_iomap; 228 #endif 229 spinlock_t swaps_lock; 230 drm_i915_vbl_swap_t vbl_swaps; 231 unsigned int swaps_pending; 232 233 } drm_i915_private_t; 234 235 enum intel_chip_family { 236 CHIP_I8XX = 0x01, 237 CHIP_I9XX = 0x02, 238 CHIP_I915 = 0x04, 239 CHIP_I965 = 0x08, 240 }; 241 242 extern drm_ioctl_desc_t i915_ioctls[]; 243 extern int i915_max_ioctl; 244 245 /* i915_dma.c */ 246 extern void i915_kernel_lost_context(drm_device_t * dev); 247 extern int i915_driver_load(struct drm_device *, unsigned long flags); 248 extern int i915_driver_unload(struct drm_device *dev); 249 extern void i915_driver_lastclose(drm_device_t * dev); 250 extern void i915_driver_preclose(drm_device_t * dev, drm_file_t *filp); 251 extern int i915_driver_device_is_agp(drm_device_t * dev); 252 extern long i915_compat_ioctl(struct file *filp, unsigned int cmd, 253 unsigned long arg); 254 extern int i915_emit_box(struct drm_device *dev, 255 struct drm_clip_rect __user *boxes, 256 int i, int DR1, int DR4); 257 extern void i915_emit_breadcrumb(struct drm_device *dev); 258 extern void i915_dispatch_flip(struct drm_device * dev, int pipes, int sync); 259 extern void i915_emit_mi_flush(drm_device_t *dev, uint32_t flush); 260 261 262 /* i915_irq.c */ 263 extern int i915_irq_emit(DRM_IOCTL_ARGS); 264 extern int i915_irq_wait(DRM_IOCTL_ARGS); 265 266 extern int i915_enable_vblank(struct drm_device *dev, int crtc); 267 extern void i915_disable_vblank(struct drm_device *dev, int crtc); 268 extern u32 i915_get_vblank_counter(struct drm_device *dev, int crtc); 269 extern irqreturn_t i915_driver_irq_handler(DRM_IRQ_ARGS); 270 extern void i915_driver_irq_preinstall(drm_device_t * dev); 271 extern void i915_driver_irq_postinstall(drm_device_t * dev); 272 extern void i915_driver_irq_uninstall(drm_device_t * dev); 273 extern int i915_emit_irq(drm_device_t * dev); 274 extern int i915_vblank_swap(DRM_IOCTL_ARGS); 275 extern void i915_user_irq_on(drm_i915_private_t *dev_priv); 276 extern void i915_user_irq_off(drm_i915_private_t *dev_priv); 277 extern int i915_vblank_pipe_set(DRM_IOCTL_ARGS); 278 extern int i915_vblank_pipe_get(DRM_IOCTL_ARGS); 279 280 /* i915_mem.c */ 281 extern int i915_mem_alloc(DRM_IOCTL_ARGS); 282 extern int i915_mem_free(DRM_IOCTL_ARGS); 283 extern int i915_mem_init_heap(DRM_IOCTL_ARGS); 284 extern int i915_mem_destroy_heap(DRM_IOCTL_ARGS); 285 extern void i915_mem_takedown(struct mem_block **heap); 286 extern void i915_mem_release(drm_device_t * dev, 287 drm_file_t *filp, struct mem_block *heap); 288 extern struct mem_block **get_heap(drm_i915_private_t *, int); 289 extern struct mem_block *find_block_by_proc(struct mem_block *, drm_file_t *); 290 extern void mark_block(drm_device_t *, struct mem_block *, int); 291 extern void free_block(struct mem_block *); 292 293 #ifdef I915_HAVE_FENCE 294 /* i915_fence.c */ 295 296 297 extern void i915_fence_handler(drm_device_t *dev); 298 extern int i915_fence_emit_sequence(drm_device_t *dev, uint32_t class, 299 uint32_t flags, 300 uint32_t *sequence, 301 uint32_t *native_type); 302 extern void i915_poke_flush(drm_device_t *dev, uint32_t class); 303 extern int i915_fence_has_irq(drm_device_t *dev, uint32_t class, uint32_t flags); 304 #endif 305 306 #ifdef I915_HAVE_BUFFER 307 /* i915_buffer.c */ 308 extern drm_ttm_backend_t *i915_create_ttm_backend_entry(drm_device_t *dev); 309 extern int i915_fence_types(drm_buffer_object_t *bo, uint32_t *class, uint32_t *type); 310 extern int i915_invalidate_caches(drm_device_t *dev, uint32_t buffer_flags); 311 extern int i915_init_mem_type(drm_device_t *dev, uint32_t type, 312 drm_mem_type_manager_t *man); 313 extern uint32_t i915_evict_mask(drm_buffer_object_t *bo); 314 extern int i915_move(drm_buffer_object_t *bo, int evict, 315 int no_wait, drm_bo_mem_reg_t *new_mem); 316 317 #endif 318 319 #define I915_READ(reg) DRM_READ32(dev_priv->mmio_map, (reg)) 320 #define I915_WRITE(reg,val) DRM_WRITE32(dev_priv->mmio_map, (reg), (val)) 321 #define I915_READ16(reg) DRM_READ16(dev_priv->mmio_map, (reg)) 322 #define I915_WRITE16(reg,val) DRM_WRITE16(dev_priv->mmio_map, (reg), (val)) 323 #define S3_READ(reg) \ 324 *(uint32_t volatile *)((uintptr_t)s3_priv->saveAddr + (reg)) 325 #define S3_WRITE(reg, val) \ 326 *(uint32_t volatile *)((uintptr_t)s3_priv->saveAddr + (reg)) = (val) 327 328 #define I915_VERBOSE 0 329 #define I915_RING_VALIDATE 0 330 331 #if I915_RING_VALIDATE 332 void i915_ring_validate(struct drm_device *dev, const char *func, int line); 333 #define I915_RING_DO_VALIDATE(dev) i915_ring_validate(dev, __FUNCTION__, __LINE__) 334 #else 335 #define I915_RING_DO_VALIDATE(dev) 336 #endif 337 338 #define RING_LOCALS unsigned int outring, ringmask, outcount; \ 339 volatile unsigned char *virt; 340 341 #if I915_VERBOSE 342 #define BEGIN_LP_RING(n) do { \ 343 DRM_DEBUG("BEGIN_LP_RING(%d)\n", (n)); \ 344 I915_RING_DO_VALIDATE(dev); \ 345 if (dev_priv->ring.space < (n)*4) \ 346 (void) i915_wait_ring(dev, (n)*4, __FUNCTION__); \ 347 outcount = 0; \ 348 outring = dev_priv->ring.tail; \ 349 ringmask = dev_priv->ring.tail_mask; \ 350 virt = dev_priv->ring.virtual_start; \ 351 } while (*"\0") 352 #else 353 #define BEGIN_LP_RING(n) do { \ 354 I915_RING_DO_VALIDATE(dev); \ 355 if (dev_priv->ring.space < (n)*4) \ 356 (void) i915_wait_ring(dev, (n)*4, __FUNCTION__); \ 357 outcount = 0; \ 358 outring = dev_priv->ring.tail; \ 359 ringmask = dev_priv->ring.tail_mask; \ 360 virt = dev_priv->ring.virtual_start; \ 361 } while (*"\0") 362 #endif 363 364 #if I915_VERBOSE 365 #define OUT_RING(n) do { \ 366 DRM_DEBUG(" OUT_RING %x\n", (int)(n)); \ 367 *(volatile unsigned int *)(void *)(virt + outring) = (n); \ 368 outcount++; \ 369 outring += 4; \ 370 outring &= ringmask; \ 371 } while (*"\0") 372 #else 373 #define OUT_RING(n) do { \ 374 *(volatile unsigned int *)(void *)(virt + outring) = (n); \ 375 outcount++; \ 376 outring += 4; \ 377 outring &= ringmask; \ 378 } while (*"\0") 379 #endif 380 381 #if I915_VERBOSE 382 #define ADVANCE_LP_RING() do { \ 383 DRM_DEBUG("ADVANCE_LP_RING %x\n", outring); \ 384 I915_RING_DO_VALIDATE(dev); \ 385 dev_priv->ring.tail = outring; \ 386 dev_priv->ring.space -= outcount * 4; \ 387 I915_WRITE(PRB0_TAIL, outring); \ 388 } while (*"\0") 389 #else 390 #define ADVANCE_LP_RING() do { \ 391 I915_RING_DO_VALIDATE(dev); \ 392 dev_priv->ring.tail = outring; \ 393 dev_priv->ring.space -= outcount * 4; \ 394 I915_WRITE(PRB0_TAIL, outring); \ 395 } while (*"\0") 396 #endif 397 398 extern int i915_wait_ring(drm_device_t * dev, int n, const char *caller); 399 400 /* Extended config space */ 401 #define LBB 0xf4 402 403 /* VGA stuff */ 404 405 #define VGA_ST01_MDA 0x3ba 406 #define VGA_ST01_CGA 0x3da 407 408 #define VGA_MSR_WRITE 0x3c2 409 #define VGA_MSR_READ 0x3cc 410 #define VGA_MSR_MEM_EN (1<<1) 411 #define VGA_MSR_CGA_MODE (1<<0) 412 413 #define VGA_SR_INDEX 0x3c4 414 #define VGA_SR_DATA 0x3c5 415 416 #define VGA_AR_INDEX 0x3c0 417 #define VGA_AR_VID_EN (1<<5) 418 #define VGA_AR_DATA_WRITE 0x3c0 419 #define VGA_AR_DATA_READ 0x3c1 420 421 #define VGA_GR_INDEX 0x3ce 422 #define VGA_GR_DATA 0x3cf 423 /* GR05 */ 424 #define VGA_GR_MEM_READ_MODE_SHIFT 3 425 #define VGA_GR_MEM_READ_MODE_PLANE 1 426 /* GR06 */ 427 #define VGA_GR_MEM_MODE_MASK 0xc 428 #define VGA_GR_MEM_MODE_SHIFT 2 429 #define VGA_GR_MEM_A0000_AFFFF 0 430 #define VGA_GR_MEM_A0000_BFFFF 1 431 #define VGA_GR_MEM_B0000_B7FFF 2 432 #define VGA_GR_MEM_B0000_BFFFF 3 433 434 #define VGA_DACMASK 0x3c6 435 #define VGA_DACRX 0x3c7 436 #define VGA_DACWX 0x3c8 437 #define VGA_DACDATA 0x3c9 438 439 #define VGA_CR_INDEX_MDA 0x3b4 440 #define VGA_CR_DATA_MDA 0x3b5 441 #define VGA_CR_INDEX_CGA 0x3d4 442 #define VGA_CR_DATA_CGA 0x3d5 443 444 445 #define GFX_OP_USER_INTERRUPT ((0<<29)|(2<<23)) 446 #define GFX_OP_BREAKPOINT_INTERRUPT ((0<<29)|(1<<23)) 447 #define CMD_REPORT_HEAD (7<<23) 448 #define CMD_STORE_DWORD_IDX ((0x21<<23) | 0x1) 449 #define CMD_OP_BATCH_BUFFER ((0x0<<29)|(0x30<<23)|0x1) 450 451 #define INST_PARSER_CLIENT 0x00000000 452 #define INST_OP_FLUSH 0x02000000 453 #define INST_FLUSH_MAP_CACHE 0x00000001 454 455 #define MI_INSTR(opcode, flags) (((opcode) << 23) | (flags)) 456 #define MI_USER_INTERRUPT MI_INSTR(2, (0 << 29)) 457 #define MI_FLUSH (0x04 << 23) 458 #define MI_NO_WRITE_FLUSH (1 << 2) 459 #define MI_READ_FLUSH (1 << 0) 460 #define MI_EXE_FLUSH (1 << 1) 461 #define MI_STORE_DWORD_INDEX MI_INSTR(0x21, 1) 462 #define MI_STORE_DWORD_INDEX_SHIFT 2 463 464 #define BB1_START_ADDR_MASK (~0x7) 465 #define BB1_PROTECTED (1<<0) 466 #define BB1_UNPROTECTED (0<<0) 467 #define BB2_END_ADDR_MASK (~0x7) 468 469 #define I915REG_PGTBL_CTRL 0x2020 470 #define HWSTAM 0x02098 471 #define IIR 0x020a4 472 #define IMR 0x020a8 473 #define IER 0x020a0 474 #define INSTPM 0x020c0 475 #define ACTHD 0x020c8 476 #define PIPEASTAT 0x70024 477 #define PIPEBSTAT 0x71024 478 #define ACTHD_I965 0x02074 479 #define HWS_PGA 0x02080 480 481 #define PIPE_VBLANK_INTERRUPT_ENABLE (1UL<<17) 482 #define I915_VBLANK_CLEAR (1UL<<1) 483 484 #define SRX_INDEX 0x3c4 485 #define SRX_DATA 0x3c5 486 #define SR01 1 487 #define SR01_SCREEN_OFF (1<<5) 488 489 #define PPCR 0x61204 490 #define PPCR_ON (1<<0) 491 492 #define DVOB 0x61140 493 #define DVOB_ON (1<<31) 494 #define DVOC 0x61160 495 #define DVOC_ON (1<<31) 496 #define LVDS 0x61180 497 #define LVDS_ON (1<<31) 498 499 #define ADPA 0x61100 500 #define ADPA_DPMS_MASK (~(3<<10)) 501 #define ADPA_DPMS_ON (0<<10) 502 #define ADPA_DPMS_SUSPEND (1<<10) 503 #define ADPA_DPMS_STANDBY (2<<10) 504 #define ADPA_DPMS_OFF (3<<10) 505 506 #ifdef NOPID 507 #undef NOPID 508 #endif 509 #define NOPID 0x2094 510 #define LP_RING 0x2030 511 #define HP_RING 0x2040 512 #define TAIL_ADDR 0x001FFFF8 513 #define HEAD_WRAP_COUNT 0xFFE00000 514 #define HEAD_WRAP_ONE 0x00200000 515 #define HEAD_ADDR 0x001FFFFC 516 #define RING_START 0x08 517 #define START_ADDR 0x0xFFFFF000 518 #define RING_LEN 0x0C 519 #define RING_NR_PAGES 0x001FF000 520 #define RING_REPORT_MASK 0x00000006 521 #define RING_REPORT_64K 0x00000002 522 #define RING_REPORT_128K 0x00000004 523 #define RING_NO_REPORT 0x00000000 524 #define RING_VALID_MASK 0x00000001 525 #define RING_VALID 0x00000001 526 #define RING_INVALID 0x00000000 527 #define PRB0_TAIL 0x02030 528 #define PRB0_HEAD 0x02034 529 #define PRB0_CTL 0x0203c 530 #define GFX_OP_SCISSOR ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 531 #define SC_UPDATE_SCISSOR (0x1<<1) 532 #define SC_ENABLE_MASK (0x1<<0) 533 #define SC_ENABLE (0x1<<0) 534 535 #define GFX_OP_SCISSOR_INFO ((0x3<<29)|(0x1d<<24)|(0x81<<16)|(0x1)) 536 #define SCI_YMIN_MASK (0xffff<<16) 537 #define SCI_XMIN_MASK (0xffff<<0) 538 #define SCI_YMAX_MASK (0xffff<<16) 539 #define SCI_XMAX_MASK (0xffff<<0) 540 541 #define GFX_OP_SCISSOR_ENABLE ((0x3<<29)|(0x1c<<24)|(0x10<<19)) 542 #define GFX_OP_SCISSOR_RECT ((0x3<<29)|(0x1d<<24)|(0x81<<16)|1) 543 #define GFX_OP_COLOR_FACTOR ((0x3<<29)|(0x1d<<24)|(0x1<<16)|0x0) 544 #define GFX_OP_STIPPLE ((0x3<<29)|(0x1d<<24)|(0x83<<16)) 545 #define GFX_OP_MAP_INFO ((0x3<<29)|(0x1d<<24)|0x4) 546 #define GFX_OP_DESTBUFFER_VARS ((0x3<<29)|(0x1d<<24)|(0x85<<16)|0x0) 547 #define GFX_OP_DRAWRECT_INFO ((0x3<<29)|(0x1d<<24)|(0x80<<16)|(0x3)) 548 549 #define GFX_OP_DRAWRECT_INFO_I965 ((0x7900<<16)|0x2) 550 551 #define SRC_COPY_BLT_CMD ((2<<29)|(0x43<<22)|4) 552 #define XY_SRC_COPY_BLT_CMD ((2<<29)|(0x53<<22)|6) 553 #define XY_SRC_COPY_BLT_WRITE_ALPHA (1<<21) 554 #define XY_SRC_COPY_BLT_WRITE_RGB (1<<20) 555 #define XY_SRC_COPY_BLT_SRC_TILED (1<<15) 556 #define XY_SRC_COPY_BLT_DST_TILED (1<<11) 557 558 #define MI_BATCH_BUFFER ((0x30<<23)|1) 559 #define MI_BATCH_BUFFER_START (0x31<<23) 560 #define MI_BATCH_BUFFER_END (0xA<<23) 561 #define MI_BATCH_NON_SECURE (1) 562 563 #define MI_BATCH_NON_SECURE_I965 (1<<8) 564 565 #define MI_WAIT_FOR_EVENT ((0x3<<23)) 566 #define MI_WAIT_FOR_PLANE_B_FLIP (1<<6) 567 #define MI_WAIT_FOR_PLANE_A_FLIP (1<<2) 568 #define MI_WAIT_FOR_PLANE_A_SCANLINES (1<<1) 569 570 #define MI_LOAD_SCAN_LINES_INCL ((0x12<<23)) 571 572 #define CMD_OP_DISPLAYBUFFER_INFO ((0x0<<29)|(0x14<<23)|2) 573 #define ASYNC_FLIP (1<<22) 574 #define DISPLAY_PLANE_A (0<<20) 575 #define DISPLAY_PLANE_B (1<<20) 576 577 #define CMD_OP_DESTBUFFER_INFO ((0x3<<29)|(0x1d<<24)|(0x8e<<16)|1) 578 579 #define BREADCRUMB_BITS 31 580 #define BREADCRUMB_MASK ((1U << BREADCRUMB_BITS) - 1) 581 582 #define READ_BREADCRUMB(dev_priv) (((volatile u32*)(dev_priv->hw_status_page))[5]) 583 #define READ_HWSP(dev_priv, reg) (((volatile u32*)(dev_priv->hw_status_page))[reg]) 584 585 /* 586 * add here for S3 support 587 */ 588 #define DPLL_A 0x06014 589 #define DPLL_B 0x06018 590 # define DPLL_VCO_ENABLE 0x80000000 /* (1 << 31) */ 591 # define DPLL_DVO_HIGH_SPEED (1 << 30) 592 # define DPLL_SYNCLOCK_ENABLE (1 << 29) 593 # define DPLL_VGA_MODE_DIS (1 << 28) 594 # define DPLLB_MODE_DAC_SERIAL (1 << 26) /* i915 */ 595 # define DPLLB_MODE_LVDS (2 << 26) /* i915 */ 596 # define DPLL_MODE_MASK (3 << 26) 597 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_10 (0 << 24) /* i915 */ 598 # define DPLL_DAC_SERIAL_P2_CLOCK_DIV_5 (1 << 24) /* i915 */ 599 # define DPLLB_LVDS_P2_CLOCK_DIV_14 (0 << 24) /* i915 */ 600 # define DPLLB_LVDS_P2_CLOCK_DIV_7 (1 << 24) /* i915 */ 601 # define DPLL_P2_CLOCK_DIV_MASK 0x03000000 /* i915 */ 602 # define DPLL_FPA01_P1_POST_DIV_MASK 0x00ff0000 /* i915 */ 603 604 /** 605 * The i830 generation, in DAC/serial mode, defines p1 as two plus this 606 * bitfield, or just 2 if PLL_P1_DIVIDE_BY_TWO is set. 607 */ 608 # define DPLL_FPA01_P1_POST_DIV_MASK_I830 0x001f0000 609 /** 610 * The i830 generation, in LVDS mode, defines P1 as the bit number set within 611 * this field (only one bit may be set). 612 */ 613 # define DPLL_FPA01_P1_POST_DIV_MASK_I830_LVDS 0x003f0000 614 # define DPLL_FPA01_P1_POST_DIV_SHIFT 16 615 # define PLL_P2_DIVIDE_BY_4 (1 << 23) /* i830, required in DVO non-gang */ 616 # define PLL_P1_DIVIDE_BY_TWO (1 << 21) /* i830 */ 617 # define PLL_REF_INPUT_DREFCLK (0 << 13) 618 # define PLL_REF_INPUT_TVCLKINA (1 << 13) /* i830 */ 619 # define PLL_REF_INPUT_TVCLKINBC (2 << 13) /* SDVO TVCLKIN */ 620 # define PLLB_REF_INPUT_SPREADSPECTRUMIN (3 << 13) 621 # define PLL_REF_INPUT_MASK (3 << 13) 622 # define PLL_LOAD_PULSE_PHASE_SHIFT 9 623 /* 624 * Parallel to Serial Load Pulse phase selection. 625 * Selects the phase for the 10X DPLL clock for the PCIe 626 * digital display port. The range is 4 to 13; 10 or more 627 * is just a flip delay. The default is 6 628 */ 629 # define PLL_LOAD_PULSE_PHASE_MASK (0xf << PLL_LOAD_PULSE_PHASE_SHIFT) 630 # define DISPLAY_RATE_SELECT_FPA1 (1 << 8) 631 632 /** 633 * SDVO multiplier for 945G/GM. Not used on 965. 634 * 635 * \sa DPLL_MD_UDI_MULTIPLIER_MASK 636 */ 637 # define SDVO_MULTIPLIER_MASK 0x000000ff 638 # define SDVO_MULTIPLIER_SHIFT_HIRES 4 639 # define SDVO_MULTIPLIER_SHIFT_VGA 0 640 641 /** @defgroup DPLL_MD 642 * @{ 643 */ 644 /** Pipe A SDVO/UDI clock multiplier/divider register for G965. */ 645 #define DPLL_A_MD 0x0601c 646 /** Pipe B SDVO/UDI clock multiplier/divider register for G965. */ 647 #define DPLL_B_MD 0x06020 648 /** 649 * UDI pixel divider, controlling how many pixels are stuffed into a packet. 650 * 651 * Value is pixels minus 1. Must be set to 1 pixel for SDVO. 652 */ 653 # define DPLL_MD_UDI_DIVIDER_MASK 0x3f000000 654 # define DPLL_MD_UDI_DIVIDER_SHIFT 24 655 /** UDI pixel divider for VGA, same as DPLL_MD_UDI_DIVIDER_MASK. */ 656 # define DPLL_MD_VGA_UDI_DIVIDER_MASK 0x003f0000 657 # define DPLL_MD_VGA_UDI_DIVIDER_SHIFT 16 658 /** 659 * SDVO/UDI pixel multiplier. 660 * 661 * SDVO requires that the bus clock rate be between 1 and 2 Ghz, and the bus 662 * clock rate is 10 times the DPLL clock. At low resolution/refresh rate 663 * modes, the bus rate would be below the limits, so SDVO allows for stuffing 664 * dummy bytes in the datastream at an increased clock rate, with both sides of 665 * the link knowing how many bytes are fill. 666 * 667 * So, for a mode with a dotclock of 65Mhz, we would want to double the clock 668 * rate to 130Mhz to get a bus rate of 1.30Ghz. The DPLL clock rate would be 669 * set to 130Mhz, and the SDVO multiplier set to 2x in this register and 670 * through an SDVO command. 671 * 672 * This register field has values of multiplication factor minus 1, with 673 * a maximum multiplier of 5 for SDVO. 674 */ 675 # define DPLL_MD_UDI_MULTIPLIER_MASK 0x00003f00 676 # define DPLL_MD_UDI_MULTIPLIER_SHIFT 8 677 /** SDVO/UDI pixel multiplier for VGA, same as DPLL_MD_UDI_MULTIPLIER_MASK. 678 * This best be set to the default value (3) or the CRT won't work. No, 679 * I don't entirely understand what this does... 680 */ 681 # define DPLL_MD_VGA_UDI_MULTIPLIER_MASK 0x0000003f 682 # define DPLL_MD_VGA_UDI_MULTIPLIER_SHIFT 0 683 /** @} */ 684 685 #define DPLL_TEST 0x606c 686 # define DPLLB_TEST_SDVO_DIV_1 (0 << 22) 687 # define DPLLB_TEST_SDVO_DIV_2 (1 << 22) 688 # define DPLLB_TEST_SDVO_DIV_4 (2 << 22) 689 # define DPLLB_TEST_SDVO_DIV_MASK (3 << 22) 690 # define DPLLB_TEST_N_BYPASS (1 << 19) 691 # define DPLLB_TEST_M_BYPASS (1 << 18) 692 # define DPLLB_INPUT_BUFFER_ENABLE (1 << 16) 693 # define DPLLA_TEST_N_BYPASS (1 << 3) 694 # define DPLLA_TEST_M_BYPASS (1 << 2) 695 # define DPLLA_INPUT_BUFFER_ENABLE (1 << 0) 696 697 /* 698 * Palette registers 699 */ 700 #define PALETTE_A 0x0a000 701 #define PALETTE_B 0x0a800 702 703 #define FPA0 0x06040 704 #define FPA1 0x06044 705 #define FPB0 0x06048 706 #define FPB1 0x0604c 707 708 #define D_STATE 0x6104 709 #define CG_2D_DIS 0x6200 710 #define CG_3D_DIS 0x6204 711 712 #define MI_ARB_STATE 0x20e4 713 714 /* 715 * Cache mode 0 reg. 716 * - Manipulating render cache behaviour is central 717 * to the concept of zone rendering, tuning this reg can help avoid 718 * unnecessary render cache reads and even writes (for z/stencil) 719 * at beginning and end of scene. 720 * 721 * - To change a bit, write to this reg with a mask bit set and the 722 * bit of interest either set or cleared. EG: (BIT<<16) | BIT to set. 723 */ 724 #define CACHE_MODE_0 0x2120 725 726 /* I830 CRTC registers */ 727 #define HTOTAL_A 0x60000 728 #define HBLANK_A 0x60004 729 #define HSYNC_A 0x60008 730 #define VTOTAL_A 0x6000c 731 #define VBLANK_A 0x60010 732 #define VSYNC_A 0x60014 733 #define PIPEASRC 0x6001c 734 #define BCLRPAT_A 0x60020 735 #define VSYNCSHIFT_A 0x60028 736 737 #define HTOTAL_B 0x61000 738 #define HBLANK_B 0x61004 739 #define HSYNC_B 0x61008 740 #define VTOTAL_B 0x6100c 741 #define VBLANK_B 0x61010 742 #define VSYNC_B 0x61014 743 #define PIPEBSRC 0x6101c 744 #define BCLRPAT_B 0x61020 745 #define VSYNCSHIFT_B 0x61028 746 747 #define DSPACNTR 0x70180 748 #define DSPBCNTR 0x71180 749 #define DISPLAY_PLANE_ENABLE (1<<31) 750 #define DISPLAY_PLANE_DISABLE 0 751 #define DISPPLANE_GAMMA_ENABLE (1<<30) 752 #define DISPPLANE_GAMMA_DISABLE 0 753 #define DISPPLANE_PIXFORMAT_MASK (0xf<<26) 754 #define DISPPLANE_8BPP (0x2<<26) 755 #define DISPPLANE_15_16BPP (0x4<<26) 756 #define DISPPLANE_16BPP (0x5<<26) 757 #define DISPPLANE_32BPP_NO_ALPHA (0x6<<26) 758 #define DISPPLANE_32BPP (0x7<<26) 759 #define DISPPLANE_STEREO_ENABLE (1<<25) 760 #define DISPPLANE_STEREO_DISABLE 0 761 #define DISPPLANE_SEL_PIPE_MASK (1<<24) 762 #define DISPPLANE_SEL_PIPE_A 0 763 #define DISPPLANE_SEL_PIPE_B (1<<24) 764 #define DISPPLANE_SRC_KEY_ENABLE (1<<22) 765 #define DISPPLANE_SRC_KEY_DISABLE 0 766 #define DISPPLANE_LINE_DOUBLE (1<<20) 767 #define DISPPLANE_NO_LINE_DOUBLE 0 768 #define DISPPLANE_STEREO_POLARITY_FIRST 0 769 #define DISPPLANE_STEREO_POLARITY_SECOND (1<<18) 770 /* plane B only */ 771 #define DISPPLANE_ALPHA_TRANS_ENABLE (1<<15) 772 #define DISPPLANE_ALPHA_TRANS_DISABLE 0 773 #define DISPPLANE_SPRITE_ABOVE_DISPLAYA 0 774 #define DISPPLANE_SPRITE_ABOVE_OVERLAY (1) 775 776 #define DSPABASE 0x70184 777 #define DSPASTRIDE 0x70188 778 779 #define DSPBBASE 0x71184 780 #define DSPBADDR DSPBBASE 781 #define DSPBSTRIDE 0x71188 782 783 #define DSPAKEYVAL 0x70194 784 #define DSPAKEYMASK 0x70198 785 786 #define DSPAPOS 0x7018C /* reserved */ 787 #define DSPASIZE 0x70190 788 #define DSPBPOS 0x7118C 789 #define DSPBSIZE 0x71190 790 791 #define DSPASURF 0x7019C 792 #define DSPATILEOFF 0x701A4 793 794 #define DSPBSURF 0x7119C 795 #define DSPBTILEOFF 0x711A4 796 797 #define PIPEACONF 0x70008 798 #define PIPEACONF_ENABLE (1UL<<31) 799 #define PIPEACONF_DISABLE 0 800 #define PIPEACONF_DOUBLE_WIDE (1<<30) 801 #define I965_PIPECONF_ACTIVE (1<<30) 802 #define PIPEACONF_SINGLE_WIDE 0 803 #define PIPEACONF_PIPE_UNLOCKED 0 804 #define PIPEACONF_PIPE_LOCKED (1<<25) 805 #define PIPEACONF_PALETTE 0 806 #define PIPEACONF_GAMMA (1<<24) 807 #define PIPECONF_FORCE_BORDER (1<<25) 808 #define PIPECONF_PROGRESSIVE (0 << 21) 809 #define PIPECONF_INTERLACE_W_FIELD_INDICATION (6 << 21) 810 #define PIPECONF_INTERLACE_FIELD_0_ONLY (7 << 21) 811 812 #define PIPEBCONF 0x71008 813 #define PIPEBCONF_ENABLE (1UL<<31) 814 #define PIPEBCONF_DISABLE 0 815 #define PIPEBCONF_DOUBLE_WIDE (1<<30) 816 #define PIPEBCONF_DISABLE 0 817 #define PIPEBCONF_GAMMA (1<<24) 818 #define PIPEBCONF_PALETTE 0 819 820 #define BLC_PWM_CTL 0x61254 821 #define BACKLIGHT_MODULATION_FREQ_SHIFT (17) 822 823 #define BLC_PWM_CTL2 0x61250 824 825 #define PFIT_CONTROL 0x61230 826 #define PFIT_PGM_RATIOS 0x61234 827 828 /** 829 * Indicates that all dependencies of the panel are on: 830 * 831 * - PLL enabled 832 * - pipe enabled 833 * - LVDS/DVOB/DVOC on 834 */ 835 # define PP_READY (1 << 30) # define PP_SEQUENCE_NONE (0 << 28) 836 # define PP_SEQUENCE_ON (1 << 28) # define PP_SEQUENCE_OFF (2 << 28) 837 # define PP_SEQUENCE_MASK 0x30000000 838 #define PP_CONTROL 0x61204 839 # define POWER_TARGET_ON (1 << 0) 840 841 #define LVDSPP_ON 0x61208 842 #define LVDSPP_OFF 0x6120c 843 #define PP_CYCLE 0x61210 844 845 /* Framebuffer compression */ 846 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 847 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 848 #define FBC_CONTROL 0x03208 849 850 #define VGACNTRL 0x71400 851 852 #define VCLK_DIVISOR_VGA0 0x6000 853 #define VCLK_DIVISOR_VGA1 0x6004 854 #define VCLK_POST_DIV 0x6010 855 856 /* Framebuffer compression */ 857 #define FBC_CFB_BASE 0x03200 /* 4k page aligned */ 858 #define FBC_LL_BASE 0x03204 /* 4k page aligned */ 859 #define FBC_CONTROL 0x03208 860 #define FBC_CTL_EN (1<<31) 861 #define FBC_CTL_PERIODIC (1<<30) 862 #define FBC_CTL_INTERVAL_SHIFT (16) 863 #define FBC_CTL_UNCOMPRESSIBLE (1<<14) 864 #define FBC_CTL_STRIDE_SHIFT (5) 865 #define FBC_CTL_FENCENO (1<<0) #define FBC_COMMAND 0x0320c 866 #define FBC_CMD_COMPRESS (1<<0) #define FBC_STATUS 0x03210 867 #define FBC_STAT_COMPRESSING (1<<31) 868 #define FBC_STAT_COMPRESSED (1<<30) 869 #define FBC_STAT_MODIFIED (1<<29) 870 #define FBC_STAT_CURRENT_LINE (1<<0) 871 #define FBC_CONTROL2 0x03214 872 #define FBC_CTL_FENCE_DBL (0<<4) 873 #define FBC_CTL_IDLE_IMM (0<<2) 874 #define FBC_CTL_IDLE_FULL (1<<2) 875 #define FBC_CTL_IDLE_LINE (2<<2) 876 #define FBC_CTL_IDLE_DEBUG (3<<2) 877 #define FBC_CTL_CPU_FENCE (1<<1) 878 #define FBC_CTL_PLANEA (0<<0) 879 #define FBC_CTL_PLANEB (1<<0) 880 #define FBC_FENCE_OFF 0x0321b 881 882 #define FBC_LL_SIZE (1536) 883 #define FBC_LL_PAD (32) 884 885 #define DSPARB 0x70030 886 887 #define PIPEAFRAMEHIGH 0x70040 888 #define PIPEBFRAMEHIGH 0x71040 889 #define PIPE_FRAME_HIGH_MASK 0x0000ffff 890 #define PIPE_FRAME_HIGH_SHIFT 0 891 #define PIPEAFRAMEPIXEL 0x70044 892 #define PIPEBFRAMEPIXEL 0x71044 893 894 #define PIPE_FRAME_LOW_MASK 0xff000000 895 #define PIPE_FRAME_LOW_SHIFT 24 896 897 /* Interrupt bits: 898 */ 899 #define I915_PIPE_CONTROL_NOTIFY_INTERRUPT (1<<18) 900 #define I915_DISPLAY_PORT_INTERRUPT (1<<17) 901 #define I915_RENDER_COMMAND_PARSER_ERROR_INTERRUPT (1<<15) 902 #define I915_GMCH_THERMAL_SENSOR_EVENT_INTERRUPT (1<<14) 903 #define I915_HWB_OOM_INTERRUPT (1<<13) /* binner out of memory */ 904 #define I915_SYNC_STATUS_INTERRUPT (1<<12) 905 #define I915_DISPLAY_PLANE_A_FLIP_PENDING_INTERRUPT (1<<11) 906 #define I915_DISPLAY_PLANE_B_FLIP_PENDING_INTERRUPT (1<<10) 907 #define I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT (1<<9) 908 #define I915_DISPLAY_PLANE_C_FLIP_PENDING_INTERRUPT (1<<8) 909 #define I915_DISPLAY_PIPE_A_VBLANK_INTERRUPT (1<<7) 910 #define I915_DISPLAY_PIPE_A_EVENT_INTERRUPT (1<<6) 911 #define I915_DISPLAY_PIPE_B_VBLANK_INTERRUPT (1<<5) 912 #define I915_DISPLAY_PIPE_B_EVENT_INTERRUPT (1<<4) 913 #define I915_DEBUG_INTERRUPT (1<<2) 914 #define I915_USER_INTERRUPT (1<<1) 915 916 #define I915_FIFO_UNDERRUN_STATUS (1UL<<31) 917 #define I915_CRC_ERROR_ENABLE (1UL<<29) 918 #define I915_CRC_DONE_ENABLE (1UL<<28) 919 #define I915_GMBUS_EVENT_ENABLE (1UL<<27) 920 #define I915_VSYNC_INTERRUPT_ENABLE (1UL<<25) 921 #define I915_DISPLAY_LINE_COMPARE_ENABLE (1UL<<24) 922 #define I915_DPST_EVENT_ENABLE (1UL<<23) 923 #define I915_LEGACY_BLC_EVENT_ENABLE (1UL<<22) 924 #define I915_ODD_FIELD_INTERRUPT_ENABLE (1UL<<21) 925 #define I915_EVEN_FIELD_INTERRUPT_ENABLE (1UL<<20) 926 #define PIPE_START_VBLANK_INTERRUPT_ENABLE (1UL<<18) /* 965 or later */ 927 #define I915_VBLANK_INTERRUPT_ENABLE (1UL<<17) 928 #define I915_OVERLAY_UPDATED_ENABLE (1UL<<16) 929 #define I915_CRC_ERROR_INTERRUPT_STATUS (1UL<<13) 930 #define I915_CRC_DONE_INTERRUPT_STATUS (1UL<<12) 931 #define I915_GMBUS_INTERRUPT_STATUS (1UL<<11) 932 #define I915_VSYNC_INTERRUPT_STATUS (1UL<<9) 933 #define I915_DISPLAY_LINE_COMPARE_STATUS (1UL<<8) 934 #define I915_DPST_EVENT_STATUS (1UL<<7) 935 #define I915_LEGACY_BLC_EVENT_STATUS (1UL<<6) 936 #define I915_ODD_FIELD_INTERRUPT_STATUS (1UL<<5) 937 #define I915_EVEN_FIELD_INTERRUPT_STATUS (1UL<<4) 938 #define PIPE_START_VBLANK_INTERRUPT_STATUS (1UL<<2) /* 965 or later */ 939 #define PIPE_VBLANK_INTERRUPT_STATUS (1UL<<1) 940 #define I915_OVERLAY_UPDATED_STATUS (1UL<<0) 941 942 /* 943 * Some BIOS scratch area registers. The 845 (and 830?) store the amount 944 * of video memory available to the BIOS in SWF1. 945 */ 946 947 #define SWF0 0x71410 948 949 /* 950 * 855 scratch registers. 951 */ 952 #define SWF10 0x70410 953 954 #define SWF30 0x72414 955 956 #define PCI_DEVICE_ID_INTEL_82830_CGC 0x3577 957 #define PCI_DEVICE_ID_INTEL_82845G_IG 0x2562 958 #define PCI_DEVICE_ID_INTEL_82855GM_IG 0x3582 959 #define PCI_DEVICE_ID_INTEL_82865_IG 0x2572 960 #define PCI_DEVICE_ID_INTEL_82915G_IG 0x2582 961 #define PCI_DEVICE_ID_INTEL_82915GM_IG 0x2592 962 #define PCI_DEVICE_ID_INTEL_82945G_IG 0x2772 963 #define PCI_DEVICE_ID_INTEL_82945GM_IG 0x27A2 964 #define PCI_DEVICE_ID_INTEL_82945GME_IG 0x27AE 965 #define PCI_DEVICE_ID_INTEL_82946_GZ 0x2972 966 #define PCI_DEVICE_ID_INTEL_82G35_IG 0x2982 967 #define PCI_DEVICE_ID_INTEL_82Q963_IG 0x2992 968 #define PCI_DEVICE_ID_INTEL_82G965_IG 0x29a2 969 #define PCI_DEVICE_ID_INTEL_GM965_IG 0x2a02 970 #define PCI_DEVICE_ID_INTEL_GME965_IG 0x2a12 971 #define PCI_DEVICE_ID_INTEL_82G33_IG 0x29c2 972 #define PCI_DEVICE_ID_INTEL_82Q35_IG 0x29b2 973 #define PCI_DEVICE_ID_INTEL_82Q33_IG 0x29d2 974 #define PCI_DEVICE_ID_INTEL_CANTIGA_IG 0x2a42 975 #define PCI_DEVICE_ID_INTEL_EL_IG 0x2e02 976 #define PCI_DEVICE_ID_INTEL_82Q45_IG 0x2e12 977 #define PCI_DEVICE_ID_INTEL_82G45_IG 0x2e22 978 #define PCI_DEVICE_ID_INTEL_82G41_IG 0x2e32 979 980 981 #define IS_I830(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82830_CGC) 982 #define IS_845G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82845G_IG) 983 #define IS_I85X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) 984 #define IS_I855(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82855GM_IG) 985 #define IS_I865G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82865_IG) 986 987 #define IS_I915G(dev) (dev->pci_device == PCI_DEVICE_ID_INTEL_82915G_IG) 988 #define IS_I915GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82915GM_IG) 989 #define IS_I945G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945G_IG) 990 #define IS_I945GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GM_IG || \ 991 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82945GME_IG) 992 993 #define IS_I965G(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82946_GZ || \ 994 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G35_IG || \ 995 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q963_IG || \ 996 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G965_IG || \ 997 (dev)->pci_device == PCI_DEVICE_ID_INTEL_GM965_IG || \ 998 (dev)->pci_device == PCI_DEVICE_ID_INTEL_GME965_IG || \ 999 (dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG || \ 1000 (dev)->pci_device == PCI_DEVICE_ID_INTEL_EL_IG || \ 1001 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q45_IG || \ 1002 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G45_IG || \ 1003 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G41_IG) 1004 1005 #define IS_I965GM(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_GM965_IG) 1006 1007 #define IS_GM45(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_CANTIGA_IG) 1008 1009 #define IS_G4X(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_EL_IG || \ 1010 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q45_IG || \ 1011 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G45_IG || \ 1012 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82G41_IG) 1013 1014 #define IS_G33(dev) ((dev)->pci_device == PCI_DEVICE_ID_INTEL_82G33_IG || \ 1015 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q35_IG || \ 1016 (dev)->pci_device == PCI_DEVICE_ID_INTEL_82Q33_IG) 1017 1018 #define IS_I9XX(dev) (IS_I915G(dev) || IS_I915GM(dev) || IS_I945G(dev) || \ 1019 IS_I945GM(dev) || IS_I965G(dev) || IS_G33(dev)) 1020 1021 #define IS_MOBILE(dev) (IS_I830(dev) || IS_I85X(dev) || IS_I915GM(dev) || \ 1022 IS_I945GM(dev) || IS_I965GM(dev) || IS_GM45(dev)) 1023 1024 #define I915_NEED_GFX_HWS(dev) (IS_G33(dev) || IS_GM45(dev) || IS_G4X(dev)) 1025 1026 #endif /* _I915_DRV_H */ 1027