1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _DNET_H 27 #define _DNET_H 28 29 /* debug flags */ 30 #define DNETTRACE 0x01 31 #define DNETERRS 0x02 32 #define DNETRECV 0x04 33 #define DNETDDI 0x08 34 #define DNETSEND 0x10 35 #define DNETINT 0x20 36 #define DNETSENSE 0x40 37 #define DNETREGCFG 0x80 38 39 #ifdef DEBUG 40 #define DNETDEBUG 1 41 #endif 42 43 /* Misc */ 44 #define DNETHIWAT 32768 /* driver flow control high water */ 45 #define DNETLOWAT 4096 /* driver flow control low water */ 46 #define DNETMAXPKT 1500 /* maximum media frame size */ 47 #define DNETIDNUM 0 /* DNET Id; zero works */ 48 #define DNET_MAX_FRAG 6 /* max mblk in msg before we pullup */ 49 50 /* board state */ 51 #define DNET_IDLE 0 52 #define DNET_WAITRCV 1 53 #define DNET_XMTBUSY 2 54 #define DNET_ERROR 3 55 56 #define SUCCESS 0 57 #define FAILURE 1 58 59 #define DEC_VENDOR_ID 0x1011 60 #define DEVICE_ID_21040 0x0002 61 #define DEVICE_ID_21041 0x0014 62 #define DEVICE_ID_21140 0x0009 63 64 /* Apparently, the 21143 and 142 are distinguished by revision ID */ 65 #define DEVICE_ID_21142 0x0019 66 #define DEVICE_ID_21143 0x0019 67 #define COGENT_EM100 0x12 68 #define COGENT_QUARTET400 0x13 69 #define COGENT_EM110TX 0x14 70 #define VENDOR_ID_OFFSET 32 71 #define VENDOR_REVISION_OFFSET 33 /* Cogent */ 72 #define ASANTE_ETHER 0x000094 73 #define COGENT_ETHER 0x000092 74 #define ADAPTEC_ETHER 0x0000d1 75 #define ZNYX_ETHER 0x00c095 76 #define COGENT_SROM_ID 0x7c 77 #define COGENT_ANA6911A_C 0x2a 78 #define COGENT_ANA6911AC_C 0x2b 79 enum { DEFAULT_TYPE, COGENT_EM_TYPE, ASANTE_TYPE}; 80 81 #define GLD_TX_RESEND 1 /* return code for GLD resend */ 82 #define GLD_TX_OK 0 /* return code for GLD Tx ok */ 83 84 #ifndef GLD_INTR_WAIT 85 /* Temporary until this makes it into the build environment's gld.h */ 86 #define GLD_INTR_WAIT 0x0002 /* waiting for interrupt to do scheduling */ 87 #endif 88 89 #define MAX_TX_DESC 128 /* Should be a multiple of 4 <= 256 */ 90 #define MAX_RX_DESC_21040 16 /* Should be a multiple of 4 <= 256 */ 91 #define MAX_RX_DESC_21140 32 /* Should be a multiple of 4 <= 256 */ 92 93 #define SROM_SIZE 128 94 #define SETUPBUF_SIZE 192 /* Setup buffer size */ 95 #define MCASTBUF_SIZE 512 /* multicast hash table size in bits */ 96 #define PRIORITY_LEVEL 5 97 #define HASH_POLY 0x04C11DB6 98 #define HASH_CRC 0xFFFFFFFFU 99 100 #define DNET_100MBPS 100 /* 21140 chip speeds */ 101 #define DNET_10MBPS 10 102 103 /* User defined PCI config space registers */ 104 #define PCI_DNET_CONF_CFDD 0x40 105 #define CFDD_SLEEP (1UL<<31) 106 #define CFDD_SNOOZE (1UL<<30) 107 /* CSR Description */ 108 #define BUS_MODE_REG 0x00 109 #define TX_POLL_REG 0x08 110 #define RX_POLL_REG 0x10 111 #define RX_BASE_ADDR_REG 0x18 112 #define TX_BASE_ADDR_REG 0x20 113 #define STATUS_REG 0x28 114 #define OPN_MODE_REG 0x30 115 #define INT_MASK_REG 0x38 116 #define MISSED_FRAME_REG 0x40 117 #define ETHER_ROM_REG 0x48 118 #define BOOT_ROM_REG 0x50 /* 041, 140A, 142 */ 119 #define FULL_DUPLEX_REG 0x58 /* 040 */ 120 #define GP_TIMER_REG 0x58 /* 140-143 */ 121 #define SIA_STATUS_REG 0x60 /* 040, 041, 142 */ 122 #define SIA_CONNECT_REG 0x68 /* 040, 041, 142 */ 123 #define SIA_TXRX_REG 0x70 /* 041, 041, 142 */ 124 #define SIA_GENERAL_REG 0x78 /* 040, 041, 142 */ 125 #define GP_REG 0x60 /* 140, 140A */ 126 127 /* Helpful defines for register access */ 128 #define REG32(reg, off) ((uint32_t *)((uintptr_t)(reg) + off)) 129 #define REG16(reg, off) ((uint16_t *)((uintptr_t)(reg) + off)) 130 #define REG8(reg, off) ((uint8_t *)((uintptr_t)(reg) + off)) 131 132 /* Bit descriptions of CSR registers */ 133 134 /* BUS_MODE_REG, CSR0 */ 135 #define SW_RESET 0x01UL 136 #define BURST_SIZE 0x2000UL 137 #define CACHE_ALIGN 0x04000UL /* 8 long word boundary align */ 138 139 /* TX_POLL_REG, CSR1 */ 140 #define TX_POLL_DEMAND 0x01 141 142 /* RX_POLL_REG, CSR2 */ 143 #define RX_POLL_DEMAND 0x01 144 145 /* STATUS_REG, CSR5 */ 146 #define TX_INTR 0x01UL 147 #define TX_STOPPED 0x02UL 148 #define TX_BUFFER_UNAVAILABLE 0x04UL 149 #define TX_JABBER_TIMEOUT 0x08UL 150 #define TX_UNDERFLOW 0x20UL 151 #define RX_INTR 0x40UL 152 #define RX_UNAVAIL_INTR 0x80UL 153 #define RX_STOP_INTR 0x0100UL 154 #define LINK_INTR 0x1000UL 155 #define SYS_ERR 0x2000UL 156 #define ABNORMAL_INTR_SUMM 0x8000UL 157 #define NORMAL_INTR_SUMM 0x10000UL 158 #define RECEIVE_PROCESS_STATE 0xe0000UL 159 #define SYS_ERR_BITS 0x3800000UL 160 #define PARITY_ERROR 0x00000000UL 161 #define MASTER_ABORT 0x00800000UL 162 #define TARGET_ABORT 0x01000000UL 163 164 /* OPN_REG , CSR6 */ 165 #define HASH_FILTERING (1UL<<0) 166 #define START_RECEIVE (1UL<<1) 167 #define HASH_ONLY (1UL<<2) 168 #define PASSBAD (1UL<<3) 169 #define INV_FILTER (1UL<<4) 170 #define START_BACKOFF (1UL<<5) 171 #define PROM_MODE (1UL<<6) 172 #define PASS_MULTICAST (1UL<<7) 173 #define FULL_DUPLEX (1UL<<9) 174 #define OPERATING_MODE (3UL<<10) /* 143 */ 175 #define FORCE_COLLISION (1UL<<12) 176 #define START_TRANSMIT (1UL<<13) 177 #define TX_THRESHOLD_160 (3UL<<14) 178 #define CAPTURE_ENABLE (1UL<<17) 179 #define PORT_SELECT (1UL<<18) /* 140, 140A, 142 */ 180 #define HEARTBEAT_DISABLE (1UL<<19) /* 140, 140A, 142 */ 181 #define STORE_AND_FORWARD (1UL<<21) /* 140, 140A, 142 */ 182 #define TX_THRESHOLD_MODE (1UL<<22) /* 140, 140A, 142 */ 183 #define PCS_FUNCTION (1UL<<23) /* 140, 140A */ 184 #define SCRAMBLER_MODE (1UL<<24) /* 140, 140A */ 185 #define OPN_REG_MB1 (1UL<<25) 186 #define RECEIVEALL (1UL<<30) 187 #define SPECIAL_CAPTURE (1UL<<31) 188 189 /* INT_MASK_REG , CSR7 */ 190 #define TX_INTERRUPT_MASK 0x01UL 191 #define TX_STOPPED_MASK 0x02UL 192 #define TX_BUFFER_UNAVAIL_MASK 0x04UL 193 #define TX_JABBER_MASK 0x08UL 194 #define TX_UNDERFLOW_MASK 0x20UL 195 #define RX_INTERRUPT_MASK 0x40UL 196 #define RX_UNAVAIL_MASK 0x80UL 197 #define RX_STOP_MASK 0x00100UL 198 #define GPTIMER_INTR 0x800UL 199 #define LINK_INTR_MASK 0x01000UL 200 #define SYSTEM_ERROR_MASK 0x02000UL 201 #define ABNORMAL_INTR_MASK 0x08000UL 202 #define NORMAL_INTR_MASK 0x10000UL 203 204 /* MISSED_FRAME_REG, CSR8 */ 205 #define MISSED_FRAME_MASK 0x0ffffUL 206 #define OVERFLOW_COUNTER_MASK 0xffe0000UL 207 208 /* Serial ROM Register CSR9 */ 209 #define SROM_MAX_CYCLES 5UL 210 #define SEL_CHIP 0x01UL 211 #define SEL_CLK 0x02UL 212 #define DATA_IN 0x04UL 213 #define DATA_OUT 0x08UL 214 #define HIGH_ADDRESS_BIT 0x20UL 215 #define SEL_ROM 0x800UL 216 #define READ_OP 0x4000UL 217 218 #define MII_WRITE ((uint32_t)(0x00002000)) 219 #define MII_CLOCK ((uint32_t)(0x00010000)) 220 #define MII_WRITE_DATA ((uint32_t)(0x00020000)) 221 #define MII_DATA_IN ((uint32_t)(0x00080000)) 222 #define MII_PHY_ADDR_ALIGN 23 223 #define MII_REG_ADDR_ALIGN 18 224 #define MII_WRITE_DATA_POSITION 17 225 #define MII_DATA_IN_POSITION 19 226 #define MII_DELAY 1 /* 1 microsecond */ 227 #define MII_PRE ((uint32_t)(0xFFFFFFFF)) 228 #define MII_READ_FRAME ((uint32_t)(0x60000000)) 229 #define MII_WRITE_FRAME ((uint32_t)(0x50020000)) 230 #define MII_READ ((uint32_t)(0x00044000)) 231 #define MII_WRITE_TS ((uint32_t)(0x00042000)) 232 233 234 /* GPR Timer reg, CSR11 */ 235 #define GPTIMER_CONT (1UL<<16) 236 /* SIA Connectivity reg, CSR13 (040, 041, 142) */ 237 #define AUTO_CONFIG 0x05UL 238 #define BNC_CONFIG 0x0DUL 239 #define SIA_CONNECT_MASK 0xFFFF0000UL 240 #define SIA_TXRX_MASK 0xFFFFFFFFUL 241 #define SIA_GENERAL_MASK 0xFFFF0000UL 242 243 #define SIA_TXRX_MASK_TP 0xFFFFFFFFUL 244 #define SIA_GENRL_MASK_TP 0x00UL 245 #define SIA_CONN_MASK_AUI 0xEF09UL 246 #define SIA_TXRX_MASK_AUI 0x0000F73DUL 247 #define SIA_GENRL_MASK_AUI 0x0000000EUL 248 249 #define CWE_21140 0x00000100UL /* This is moved in the 21143 */ 250 #define CSR15_C 251 #define MEDIA_TP 0 252 #define MEDIA_BNC 1 253 #define MEDIA_AUI 2 254 #define MEDIA_SYM_SCR 3 255 #define MEDIA_TP_FD 4 256 #define MEDIA_SYM_SCR_FD 5 257 #define MEDIA_100T4 6 258 #define MEDIA_100FX 7 259 #define MEDIA_100FX_FD 8 260 #define MEDIA_MII 9 261 262 263 /* CSR15 */ 264 #define CWE_21143 (1UL<<11) 265 266 #define MEDIA_CAP_100T4 0x8000UL 267 #define MEDIA_CAP_100FDX 0x4000UL 268 #define MEDIA_CAP_100HDX 0x2000UL 269 #define MEDIA_CAP_10FDX 0x1000UL 270 #define MEDIA_CAP_10HDX 0x800UL 271 272 /* 273 * In GPR and reset sequences in the ROM this is used to decide wheather the 274 * CWE bit should be set when writing to the GPR. However, the CWE bit is 275 * different on the 143 and 140, so we pick a bit where we can safely store 276 * this information in the ROM structure before writing it out to the GPR 277 * register itself 278 */ 279 #define GPR_CONTROL_WRITE (1UL<<31) 280 281 /* command block bit flags from SROM */ 282 #define CMD_PS (1<<0) 283 #define CMD_TTM (1<<4) 284 #define CMD_PCS (1<<5) 285 #define CMD_SCR (1<<6) 286 #define CMD_POL (1<<7) 287 #define CMD_DEFAULT_MEDIUM (1<<14) 288 #define CMD_ACTIVE_INVALID (1<<15) 289 #define CMD_MEDIABIT_MASK 0xE 290 291 #define MAX_SEQ 8 292 #define MAX_ADAPTERS 8 293 #define MAX_MEDIA 8 294 295 296 297 struct dnetinstance; 298 299 typedef void (*timercb_t)(struct dnetinstance *); 300 301 302 typedef struct _media_block_t { 303 int type; 304 uint16_t command; 305 int gprseqlen; 306 int rstseqlen; 307 int media_code; 308 uint16_t gprseq[8]; 309 uint16_t rstseq[8]; 310 unsigned int hassia:1; 311 union { 312 struct { 313 int phy_num; 314 uint16_t nwayadvert; 315 uint16_t fdxmask; 316 uint16_t ttmmask; 317 uint16_t miiintr; 318 uint16_t mediacaps; 319 } mii; 320 struct { 321 uint32_t csr13; 322 uint32_t csr14; 323 uint32_t csr15; 324 } sia; 325 } un; 326 } media_block_t; 327 328 typedef struct leaf_format { 329 uint16_t device_number; 330 uint16_t gpr; 331 uint16_t selected_contype; 332 int block_count; 333 media_block_t *default_block; 334 media_block_t *mii_block; 335 media_block_t block[MAX_MEDIA]; 336 int is_static; 337 } LEAF_FORMAT; 338 339 340 typedef struct srom_format { 341 int init_from_srom; 342 /* elements used to store Version 1,3 and proprietary formats */ 343 uchar_t version; 344 uchar_t adapters; 345 uchar_t netaddr[ETHERADDRL]; 346 LEAF_FORMAT *leaf; 347 } SROM_FORMAT; 348 349 #define SROM_VERSION 18 350 #define SROM_ADAPTER_CNT 19 351 #define SROM_NETADDR 20 352 #define SROM_LEAF_OFFSET 26 353 #define SROM_MBZ 6 354 #define SROM_MBZ2 15 355 #define SROM_MBZ3 17 356 357 #define MEDIA_CODE_MASK 0x3F 358 #define EXT_BIT 0x40 359 360 struct dnetinstance { 361 caddr_t io_reg; /* mapped register */ 362 int board_type; /* board type: 21040 or 21140 */ 363 int full_duplex; 364 int bnc_indicator; /* Flag for BNC connector */ 365 uint64_t speed; /* data rate: 10 or 100 */ 366 int secondary; /* SROM read as all zero */ 367 SROM_FORMAT sr; 368 int leaf; 369 int vendor_21140; 370 int vendor_revision; 371 int promisc; 372 int need_saddr; 373 int max_tx_desc; /* max xmit descriptors */ 374 caddr_t setup_buf_vaddr; /* setup buffer (virt) */ 375 uint32_t setup_buf_paddr; /* setup buffer (phys) */ 376 struct tx_desc_type *tx_desc; /* virtual addr of xmit desc */ 377 uint32_t tx_desc_paddr; /* physical addr of xmit desc */ 378 struct rx_desc_type *rx_desc; /* virtual addr of recv desc */ 379 uint32_t rx_desc_paddr; /* physical addr of recv desc */ 380 char multicast_cnt[MCASTBUF_SIZE]; 381 ddi_acc_handle_t io_handle; /* ddi I/O handle */ 382 dev_info_t *devinfo; 383 int max_rx_desc; /* max recv descriptors */ 384 ddi_dma_handle_t dma_handle; 385 ddi_dma_handle_t dma_handle_tx; 386 ddi_dma_handle_t dma_handle_txdesc; 387 ddi_dma_handle_t dma_handle_setbuf; 388 int pgmask; 389 ddi_acc_handle_t setup_buf_acchdl; 390 int nxmit_desc; /* #of xmit descriptors */ 391 int nrecv_desc; /* #of recv descriptors */ 392 ddi_acc_handle_t tx_desc_acchdl; 393 ddi_acc_handle_t rx_desc_acchdl; 394 mblk_t **tx_msgbufp; /* streams message buffers */ 395 /* used for xmit */ 396 caddr_t *rx_buf_vaddr; /* recv buf addresses (virt) */ 397 uint32_t *rx_buf_paddr; /* recv buf addresses (phys) */ 398 ddi_iblock_cookie_t icookie; 399 kmutex_t txlock; 400 kmutex_t intrlock; 401 boolean_t suspended; 402 boolean_t running; 403 boolean_t need_tx_update; 404 mac_handle_t mac_handle; 405 uint32_t stat_errrcv; 406 uint32_t stat_overflow; 407 uint32_t stat_intr; 408 uint32_t stat_defer; 409 uint32_t stat_missed; 410 uint32_t stat_norcvbuf; 411 uint32_t stat_crc; 412 uint32_t stat_short; 413 uint32_t stat_frame; 414 uint32_t stat_errxmt; 415 uint32_t stat_collisions; 416 uint32_t stat_xmtlatecoll; 417 uint32_t stat_excoll; 418 uint32_t stat_underflow; 419 uint32_t stat_nocarrier; 420 int tx_current_desc; /* Current Tx descriptor */ 421 int rx_current_desc; /* Current descriptor of Rx */ 422 int transmitted_desc; /* Descriptor count xmitted */ 423 int free_desc; /* Descriptors available */ 424 mii_handle_t mii; 425 int mii_speed; 426 int mii_duplex; 427 int phyaddr; 428 uchar_t vendor_addr[ETHERADDRL]; 429 uchar_t curr_macaddr[ETHERADDRL]; 430 media_block_t *selected_media_block; 431 uint32_t disallowed_media; 432 int disable_scrambler; 433 int overrun_workaround; 434 int interrupts_disabled; 435 int mii_up; 436 uint32_t gprsia; /* Write-through for 143's gprsia reg */ 437 struct hackintr_inf *hackintr_inf; 438 struct { 439 timercb_t cb; 440 uint32_t start_ticks; 441 } timer; 442 }; 443 444 #pragma pack(1) 445 446 #define BCOPY(from, to, len) bcopy(from, to, len) 447 448 /* 449 * Receive descriptor description 450 */ 451 struct rx_desc_type { 452 struct { 453 volatile uint32_t 454 overflow : 01, 455 crc : 01, 456 dribbling : 01, 457 mii_err : 01, 458 rcv_watchdog : 01, 459 frame_type : 01, 460 collision : 01, 461 frame2long : 01, 462 last_desc : 01, 463 first_desc : 01, 464 multi_frame : 01, 465 runt_frame : 01, 466 u_data_type : 02, 467 desc_err : 01, 468 err_summary : 01, 469 frame_len : 14, 470 filter_fail : 01, 471 own : 01; 472 } desc0; 473 struct { 474 volatile uint32_t 475 buffer_size1 : 11, 476 buffer_size2 : 11, 477 not_used : 02, 478 chaining : 01, 479 end_of_ring : 01, 480 rsvd1 : 06; 481 } desc1; 482 volatile uint32_t buffer1; 483 volatile uint32_t buffer2; 484 }; 485 486 /* 487 * Receive descriptor description 488 */ 489 struct tx_desc_type { 490 struct { 491 volatile uint32_t 492 deferred : 1, 493 underflow : 1, 494 link_fail : 1, 495 collision_count : 4, 496 heartbeat_fail : 1, 497 excess_collision : 1, 498 late_collision : 1, 499 no_carrier : 1, 500 carrier_loss : 1, 501 rsvd1 : 2, 502 tx_jabber_to : 1, 503 err_summary : 1, 504 rsvd : 15, 505 own : 1; 506 } desc0; 507 struct { 508 volatile uint32_t 509 buffer_size1 : 11, 510 buffer_size2 : 11, 511 filter_type0 : 1, 512 disable_padding : 1, 513 chaining : 1, 514 end_of_ring : 1, 515 crc_disable : 1, 516 setup_packet : 1, 517 filter_type1 : 1, 518 first_desc : 1, 519 last_desc : 1, 520 int_on_comp : 1; 521 } desc1; 522 volatile uint32_t buffer1; 523 volatile uint32_t buffer2; 524 }; 525 526 527 #define DNET_END_OF_RING 0x2000000 528 529 #pragma pack() 530 531 #endif /* _DNET_H */ 532