1 /* 2 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 3 * Use is subject to license terms. 4 */ 5 6 #ifndef AMD8111S_HW_H 7 #define AMD8111S_HW_H 8 9 #pragma ident "%Z%%M% %I% %E% SMI" 10 11 /* 12 * Copyright (c) 2001-2006 Advanced Micro Devices, Inc. All rights reserved. 13 * 14 * Redistribution and use in source and binary forms, with or without 15 * modification, are permitted provided that the following conditions are met: 16 * 17 * + Redistributions of source code must retain the above copyright notice, 18 * + this list of conditions and the following disclaimer. 19 * 20 * + Redistributions in binary form must reproduce the above copyright 21 * + notice, this list of conditions and the following disclaimer in the 22 * + documentation and/or other materials provided with the distribution. 23 * 24 * + Neither the name of Advanced Micro Devices, Inc. nor the names of its 25 * + contributors may be used to endorse or promote products derived from 26 * + this software without specific prior written permission. 27 * 28 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND 29 * CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, 30 * INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF 31 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE 32 * DISCLAIMED. IN NO EVENT SHALL ADVANCED MICRO DEVICES, INC. OR 33 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 35 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; 36 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 37 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 38 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 39 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, 40 * EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 41 * 42 * Import/Export/Re-Export/Use/Release/Transfer Restrictions and 43 * Compliance with Applicable Laws. Notice is hereby given that 44 * the software may be subject to restrictions on use, release, 45 * transfer, importation, exportation and/or re-exportation under 46 * the laws and regulations of the United States or other 47 * countries ("Applicable Laws"), which include but are not 48 * limited to U.S. export control laws such as the Export 49 * Administration Regulations and national security controls as 50 * defined thereunder, as well as State Department controls under 51 * the U.S. Munitions List. Permission to use and/or 52 * redistribute the software is conditioned upon compliance with 53 * all Applicable Laws, including U.S. export control laws 54 * regarding specifically designated persons, countries and 55 * nationals of countries subject to national security controls. 56 */ 57 58 59 /* Definitions for the type of Memory allocations needed */ 60 61 #define ETH_LENGTH_OF_ADDRESS 6 62 #define ETH_MAC_HDR_SIZE 14 63 64 65 #define ADD_MULTICAST 1 66 67 #define ENABLE_MULTICAST 2 68 #define DISABLE_MULTICAST 3 69 70 #define ENABLE_ALL_MULTICAST 4 71 #define DISABLE_ALL_MULTICAST 5 72 73 #define ENABLE_BROADCAST 6 74 #define DISABLE_BROADCAST 7 75 76 #define ADD_WAKE_UP_PATTERN 8 77 #define REMOVE_WAKE_UP_PATTERN 9 78 #define ENABLE_MAGIC_PACKET_WAKE_UP 10 79 80 #define SET_SINGLE_MULTICAST 11 81 #define UNSET_SINGLE_MULTICAST 12 82 #define DELETE_MULTICAST 13 83 84 #define LINK_DOWN 1 85 #define LINK_UP 2 86 #define LINK_UNKNOWN 3 87 88 /* Setting the MODE */ 89 #define PROMISCOUS 1 90 #define DISABLE_PROM 2 91 92 #define VIRTUAL 1 93 94 #define ALIGNMENT 0x0f 95 96 #define TX_RING_LEN_BITS 10 /* 1024 descriptors */ 97 #define RX_RING_LEN_BITS 10 /* 1024 descriptors */ 98 #define TX_BUF_SIZE 2048 99 #define RX_BUF_SIZE 2048 100 101 #define TX_RING_SIZE (1 << (TX_RING_LEN_BITS)) 102 #define TX_COALESC_SIZE (1 << 11) 103 #define TX_RING_MOD_MASK (2 * TX_RING_SIZE - 1) 104 105 #define TX_RESCHEDULE_THRESHOLD (TX_RING_SIZE >> 1) 106 107 #define RX_RING_SIZE (1 << (RX_RING_LEN_BITS)) 108 #define RX_RING_MOD_MASK (RX_RING_SIZE - 1) 109 110 #define MAX_MULTICAST_ADDRESSES 32 111 #define JUMBO_ENABLED 0 112 #define JUMBO_DISABLED 1 113 114 /* Default value of IPG convergence time */ 115 #define MIN_IPG_DEFAULT 96 116 #define MAX_IPG_DEFAULT 255 117 #define MAX_BUFFER_COUNT 8 /* full coalesce */ 118 119 #define ULONG unsigned long 120 #define UCHAR unsigned char 121 122 /* Generic MII registers. */ 123 #define MII_BMCR 0x00 /* Basic mode control register */ 124 #define MII_BMSR 0x01 /* Basic mode status register */ 125 #define MII_PHYSID1 0x02 /* PHYS ID 1 */ 126 #define MII_PHYSID2 0x03 /* PHYS ID 2 */ 127 #define MII_ADVERTISE 0x04 /* Advertisement control reg */ 128 #define MII_LPA 0x05 /* Link partner ability reg */ 129 #define MII_EXPANSION 0x06 /* Expansion register */ 130 #define MII_DCOUNTER 0x12 /* Disconnect counter */ 131 #define MII_FCSCOUNTER 0x13 /* False carrier counter */ 132 #define MII_NWAYTEST 0x14 /* N-way auto-neg test reg */ 133 #define MII_RERRCOUNTER 0x15 /* Receive error counter */ 134 #define MII_SREVISION 0x16 /* Silicon revision */ 135 #define MII_RESV1 0x17 /* Reserved... */ 136 #define MII_LBRERROR 0x18 /* Lpback, rx, bypass error */ 137 #define MII_PHYADDR 0x19 /* PHY address */ 138 #define MII_RESV2 0x1a /* Reserved... */ 139 #define MII_TPISTATUS 0x1b /* TPI status for 10mbps */ 140 #define MII_NCONFIG 0x1c /* Network interface config */ 141 142 143 #define DEVICE_ID 0x744b 144 #define VENDOR_ID 0x1022 145 146 /* L4 Chip Name */ 147 #define DEVICE_CHIPNAME "Memory_Map_L7 AMDIDC" 148 149 /* Error Status Registers */ 150 #define MIB_OFFSET 0x28 151 152 /* 153 * MIB counter definitions 154 */ 155 #define RcvMissPkts 0x00 156 #define RcvOctets 0x01 157 #define RcvBroadCastPkts 0x02 158 #define RcvMultiCastPkts 0x03 159 #define RcvUndersizePkts 0x04 160 #define RcvOversizePkts 0x05 161 #define RcvFragments 0x06 162 #define RcvJabbers 0x07 163 #define RcvUniCastPkts 0x08 164 #define RcvAlignmentErrors 0x09 165 #define RcvFCSErrors 0x0a 166 #define RcvGoodOctets 0x0b 167 #define RcvMACCtrl 0x0c 168 #define RcvFlowCtrl 0x0d 169 #define RcvPkts64Octets 0x0e 170 #define RcvPkts65to127Octets 0x0f 171 #define RcvPkts128to255Octets 0x10 172 #define RcvPkts256to511Octets 0x11 173 #define RcvPkts512to1023Octets 0x12 174 #define RcvPkts1024to1518Octets 0x13 175 #define RcvUnsupportedOpcode 0x14 176 #define RcvSymbolErrors 0x15 177 #define RcvDropPktsRing0 0x16 178 179 #define XmtUnderrunPkts 0x20 180 #define XmtOctets 0x21 181 #define XmtPackets 0x22 182 #define XmtBroadCastPkts 0x23 183 #define XmtMultiCastPkts 0x24 184 #define XmtCollisions 0x25 185 #define XmtUniCastPkts 0x26 186 #define XmtOneCollision 0x27 187 #define XmtMultipleCollision 0x28 188 #define XmtDeferredTransmit 0x29 189 #define XmtLateCollision 0x2a 190 #define XmtExcessiveDefer 0x2b 191 #define XmtLossCarrier 0x2c 192 #define XmtExcessiveCollision 0x2d 193 #define XmtBackPressure 0x2e 194 #define XmtFlowCtrl 0x2f 195 #define XmtPkts64Octets 0x30 196 #define XmtPkts65to127Octets 0x31 197 #define XmtPkts128to255Octets 0x32 198 #define XmtPkts256to511Octets 0x33 199 #define XmtPkts512to1023Octets 0x34 200 #define XmtPkts1024to1518Octets 0x35 201 #define XmtOversizePkts 0x36 202 203 /* Link Status */ 204 #define SPEED_MASK 0x0380 /* B9 .. B7 */ 205 #define SPEED_100Mbps 0x0180 206 #define SPEED_10Mbps 0x0100 207 208 209 /* PMR (Pattern Match RAM) */ 210 #define MAX_ALLOWED_PATTERNS 8 211 #define MAX_PATTERNS 1024 212 #define ALL_MULTI B16_MASK 213 #define ONLY_MULTI B15_MASK 214 215 #define B31_MASK 0x80000000 216 #define B30_MASK 0x40000000 217 #define B29_MASK 0x20000000 218 #define B28_MASK 0x10000000 219 #define B27_MASK 0x08000000 220 #define B26_MASK 0x04000000 221 #define B25_MASK 0x02000000 222 #define B24_MASK 0x01000000 223 #define B23_MASK 0x00800000 224 #define B22_MASK 0x00400000 225 #define B21_MASK 0x00200000 226 #define B20_MASK 0x00100000 227 #define B19_MASK 0x00080000 228 #define B18_MASK 0x00040000 229 #define B17_MASK 0x00020000 230 #define B16_MASK 0x00010000 231 232 #define B15_MASK 0x8000 233 #define B14_MASK 0x4000 234 #define B13_MASK 0x2000 235 #define B12_MASK 0x1000 236 #define B11_MASK 0x0800 237 #define B10_MASK 0x0400 238 #define B9_MASK 0x0200 239 #define B8_MASK 0x0100 240 #define B7_MASK 0x0080 241 #define B6_MASK 0x0040 242 #define B5_MASK 0x0020 243 #define B4_MASK 0x0010 244 #define B3_MASK 0x0008 245 #define B2_MASK 0x0004 246 #define B1_MASK 0x0002 247 #define B0_MASK 0x0001 248 249 /* PCI register offset */ 250 /* required by odl in getting the Memory Base Address */ 251 #define MEMBASE_MASK 0xFFFFF000 252 #define PCI_CAP_ID_REG_OFFSET 0x34 253 #define PCI_PMC_REG_OFFSET 0x36 254 #define PCI_PMCSR_REG_OFFSET 0x38 255 #define MIB_OFFSET 0x28 256 #define STAT_ASF 0x00 /* 32bit register */ 257 258 #define FORCED_PHY_MASK 0xFF07 259 260 /* Offset of Drifrent Registers */ 261 #define AP_VALUE 0x98 /* 32bit register */ 262 #define AUTOPOLL0 0x88 /* 16bit register */ 263 #define AUTOPOLL1 0x8A /* 16bit register */ 264 #define AUTOPOLL2 0x8C /* 16bit register */ 265 #define AUTOPOLL3 0x8E /* 16bit register */ 266 #define AUTOPOLL4 0x90 /* 16bit register */ 267 #define AUTOPOLL5 0x92 /* 16bit register */ 268 /* Receive Ring Base Address Registers . */ 269 #define RCV_RING_BASE_ADDR0 0x120 /* 64bit register */ 270 /* Transmit Ring Base Address */ 271 #define XMT_RING_BASE_ADDR0 0x100 /* 64bit register */ 272 #define XMT_RING_BASE_ADDR1 0x108 /* 64bit register */ 273 #define XMT_RING_BASE_ADDR2 0x110 /* 64bit register */ 274 #define XMT_RING_BASE_ADDR3 0x118 /* 64bit register */ 275 /* CAM ADDRESS */ 276 #define CAM_ADDR 0x1A0 /* 16bit register */ 277 #define CAM_DATA 0x198 /* 64bit register */ 278 /* CHIP ID */ 279 #define CHIPID 0x004 /* 32bit register */ 280 /* COMMAND STYLE REGISTERS */ 281 #define CMD0 0x48 /* 32bit register */ 282 #define CMD2 0x50 /* 32bit register */ 283 #define CMD3 0x54 /* 32bit register */ 284 #define CMD7 0x64 /* 32bit register */ 285 /* CONTRIOL REGISTER */ 286 #define CTRL1 0x6C /* 32bit register */ 287 #define CTRL2 0x70 /* 32bit register */ 288 /* DELAY INTERRUPT REGISTER */ 289 #define DLY_INT_A 0xA8 /* 32bit register */ 290 #define DLY_INT_B 0xAC /* 32bit register */ 291 /* FLOW CONTROL REGISTER */ 292 #define FLOW_CONTROL 0xC8 /* 32bit register */ 293 /* INTER FRAME SPACING */ 294 #define IFS 0x18E /* 16bit register */ 295 #define IFS1 0x18C /* 8bit register */ 296 /* INTERRUPT REGISTER */ 297 #define INT0 0x38 /* 32bit register */ 298 #define INTEN0 0x40 /* 32bit register */ 299 /* LOGICAL ADDRESS */ 300 #define LADRF1 0x168 /* 64bit register */ 301 /* MIB ADDRESS REGISTER */ 302 #define MIB_ADDR 0x14 /* 16bit register */ 303 #define MIB_DATA 0x10 /* 32bit register */ 304 /* MAC ADDRESS */ 305 #define PADR 0x160 /* 48bit register */ 306 /* PHY ADDRESS */ 307 #define PHY_ACCESS 0xD0 /* 32bit register */ 308 /* PATTERN REGISTER */ 309 #define PMAT0 0x190 /* 32bit register */ 310 #define PMAT1 0x194 /* 32bit register */ 311 /* RECEIVE RING LENGTH OFFSET */ 312 #define RCV_RING_LEN0 0x150 /* 16bit register */ 313 /* SRAM BOUNDARY */ 314 #define SRAM_BOUNDARY 0x17A /* 16bit register */ 315 #define SRAM_SIZE 0x178 /* 16bit register */ 316 /* STATUS REGISTER */ 317 #define STAT0 0x30 /* 32bit register */ 318 #define STVAL 0xD8 /* 32bit register */ 319 #define TEST0 0x1A8 /* 32bit register */ 320 #define XMT_RING_LEN0 0x140 /* 16bit register */ 321 #define XMT_RING_LEN1 0x144 /* 16bit register */ 322 #define XMT_RING_LEN2 0x148 /* 16bit register */ 323 #define XMT_RING_LEN3 0x14C /* 16bit register */ 324 #define XMT_RING_LIMIT 0x7C /* 32bit register */ 325 326 327 328 #define RCV_RING_LEN1 0x154 /* 16bit register */ 329 #define RCV_RING_LEN2 0x158 /* 16bit register */ 330 #define RCV_RING_LEN3 0x15C /* 16bit register */ 331 #define FFC_THRESH 0xCC /* 32bit register */ 332 #define RCV_RING_BASE_ADDR1 0x128 /* 64bit register */ 333 #define RCV_RING_BASE_ADDR2 0x130 /* 64bit register */ 334 #define RCV_RING_BASE_ADDR3 0x138 /* 64bit register */ 335 #define RCV_RING_CFG 0x78 /* 16bit register */ 336 #define PCS_ANEG 0x9C /* 32bit register */ 337 #define PCS_RCFG 0xA0 /* 32bit register */ 338 #define PCS_XCFG 0xA4 /* 32bit register */ 339 #define DFC_INDEX2 0xB8 /* 16bit register */ 340 #define DFC_INDEX3 0xBA /* 16bit register */ 341 #define DFC_INDEX0 0xBC /* 16bit register */ 342 #define DFC_INDEX1 0xBE /* 16bit register */ 343 #define DFC_THRESH2 0xC0 /* 16bit register */ 344 #define DFC_THRESH3 0xC2 /* 16bit register */ 345 #define DFC_THRESH0 0xC4 /* 16bit register */ 346 #define DFC_THRESH1 0xC6 /* 16bit register */ 347 #define PAUSE_CNT 0xDE /* 32bit register */ 348 #define LED0 0xE0 /* 16bit register */ 349 #define LED1 0xE2 /* 16bit register */ 350 #define LED2 0xE4 /* 16bit register */ 351 #define LED3 0xE6 /* 16bit register */ 352 353 354 #define EEPROM_ACC 0x17C /* 16bit register */ 355 356 357 /* Register Bit Definitions */ 358 /* STAT_ASF 0x00, 32bit register */ 359 #define ASF_INIT_DONE B1_MASK 360 #define ASF_INIT_PRESENT B0_MASK 361 362 /* MIB_ADDR 0x14, 16bit register */ 363 #define MIB_CMD_ACTIVE B15_MASK 364 #define MIB_RD_CMD B13_MASK 365 #define MIB_CLEAR B12_MASK 366 #define MIB_ADDRESS 0x0000003F /* 5:0 */ 367 368 /* QOS_ADDR 0x1C, 16bit register */ 369 #define QOS_CMD_ACTIVE B15_MASK 370 #define QOS_WR_CMD B14_MASK 371 #define QOS_RD_CMD B13_MASK 372 #define QOS_ADDRESS 0x0000001F /* 4:0 */ 373 374 /* STAT0 0x30, 32bit register */ 375 #define PAUSE_PEND B14_MASK 376 #define PAUSING B13_MASK 377 #define PMAT_DET B12_MASK 378 #define MP_DET B11_MASK 379 #define LC_DET B10_MASK 380 #define SPEED_MASK 0x0380 /* 9:7 */ 381 #define FULL_DPLX B6_MASK 382 #define LINK_STAT B5_MASK 383 #define AUTONEG_COMPLETE B4_MASK 384 /* #define MIIPD B3_MASK */ 385 #define RX_SUSPENDED B2_MASK 386 #define TX_SUSPENDED B1_MASK 387 #define RUNNING B0_MASK 388 389 390 /* INTEN0 0x40, 32bit register */ 391 392 #define VAL3 B31_MASK 393 #define VAL2 B23_MASK 394 #define VAL1 B15_MASK 395 #define VAL0 B7_MASK 396 397 /* VAL3 */ 398 #define PSCINTEN B28_MASK 399 #define LCINTEN B27_MASK 400 #define APINT5EN B26_MASK 401 #define APINT4EN B25_MASK 402 #define APINT3EN B24_MASK 403 404 /* VAL2 */ 405 #define APINT2EN B22_MASK 406 #define APINT1EN B21_MASK 407 #define APINT0EN B20_MASK 408 #define MIIPDTINTEN B19_MASK 409 #define MCCIINTEN B18_MASK 410 #define MCCINTEN B17_MASK 411 #define MREINTEN B16_MASK 412 413 /* VAL1 */ 414 #define SPNDINTEN B14_MASK 415 #define MPINTEN B13_MASK 416 #define SINTEN B12_MASK 417 #define TINTEN3 B11_MASK 418 #define TINTEN2 B10_MASK 419 #define TINTEN1 B9_MASK 420 #define TINTEN0 B8_MASK 421 422 /* VAL0 */ 423 #define STINTEN B4_MASK 424 #define RINTEN3 B3_MASK 425 #define RINTEN2 B2_MASK 426 #define RINTEN1 B1_MASK 427 #define RINTEN0 B0_MASK 428 429 /* CMD0 0x48, 32bit register */ 430 /* VAL2 */ 431 #define RDMD3 B19_MASK 432 #define RDMD2 B18_MASK 433 #define RDMD1 B17_MASK 434 #define RDMD0 B16_MASK 435 436 /* VAL1 */ 437 #define TDMD3 B11_MASK 438 #define TDMD2 B10_MASK 439 #define TDMD1 B9_MASK 440 #define TDMD0 B8_MASK 441 442 /* VAL0 */ 443 #define UINTCMD B6_MASK 444 #define RX_FAST_SPND B5_MASK 445 #define TX_FAST_SPND B4_MASK 446 #define RX_SPND B3_MASK 447 #define TX_SPND B2_MASK 448 #define INTREN B1_MASK 449 #define RUN B0_MASK 450 451 /* CMD2 0x50, 32bit register */ 452 /* VAL3 */ 453 #define CONDUIT_MODE B29_MASK 454 #define PREF_QTAG B28_MASK 455 #define ALT_PRI_OK B27_MASK 456 457 /* VAL2 */ 458 #define CAM_ENABLE B22_MASK 459 #define QOS_ENABLE B21_MASK 460 #define HASH_ENABLE B20_MASK 461 #define RPA B19_MASK 462 #define DRCVPA B18_MASK 463 #define DRCVBC B17_MASK 464 #define PROM B16_MASK 465 466 /* VAL1 */ 467 #define ASTRIP_RCV B13_MASK 468 #define CMD2_RCV_DROP0 B12_MASK 469 #define EMBA B11_MASK 470 #define DXMT2PD B10_MASK 471 #define LTINTEN B9_MASK 472 #define DXMTFCS B8_MASK 473 474 /* VAL0 */ 475 #define APAD_XMT B6_MASK 476 #define DRTY B5_MASK 477 #define INLOOP B4_MASK 478 #define EXLOOP B3_MASK 479 #define REX_RTRY B2_MASK 480 #define REX_UFLO B1_MASK 481 #define REX_LCOL B0_MASK 482 483 /* CMD3 0x54, 32bit register */ 484 485 /* VAL3 */ 486 #define ASF_INIT_DONE_ALIAS B29_MASK 487 488 /* VAL2 */ 489 #define JUMBO B21_MASK 490 #define VSIZE B20_MASK 491 #define VLONLY B19_MASK 492 #define VL_TAG_DEL B18_MASK 493 494 /* VAL1 */ 495 #define EN_PMGR B14_MASK 496 #define INTLEVEL B13_MASK 497 #define FORCE_FULL_DUPLEX B12_MASK 498 #define FORCE_LINK_STATUS B11_MASK 499 #define APEP B10_MASK 500 #define MPPLBA B9_MASK 501 502 /* VAL0 */ 503 #define RESET_PHY_PULSE B2_MASK 504 #define RESET_PHY B1_MASK 505 #define PHY_RST_POL B0_MASK 506 507 /* CMD7 0x64, 32bit register */ 508 /* VAL0 */ 509 #define PMAT_SAVE_MATCH B4_MASK 510 #define PMAT_MODE B3_MASK 511 #define MPEN_SW B1_MASK 512 #define LCMODE_SW B0_MASK 513 514 /* CTRL0 0x68, 32bit register */ 515 #define PHY_SEL 0x03000000 /* 25:24 */ 516 #define RESET_PHY_WIDTH 0x00FF0000 /* 23:16 */ 517 #define BSWP_REGS B10_MASK 518 #define BSWP_DESC B9_MASK 519 #define BSWP_DATA B8_MASK 520 #define CACHE_ALIGN B4_MASK 521 #define BURST_LIMIT 0x0000000F /* 3:0 */ 522 523 /* CTRL1 0x6C, 32bit register */ 524 #define SLOTMOD_MASK 0x03000000 /* 25:24 */ 525 #define XMTSP_MASK 0x300 /* 17:16 */ 526 #define XMTSP_128 0x200 527 #define XMTSP_64 0x100 528 529 /* CTRL2 0x70, 32bit register */ 530 #define FS_MASK 0x00070000 /* 18:16 */ 531 #define FMDC_MASK 0x00000300 /* 9:8 */ 532 #define XPHYRST B7_MASK 533 #define XPHYANE B6_MASK 534 #define XPHYFD B5_MASK 535 #define XPHYSP_100 B3_MASK /* 4:3, 100 Mbps */ 536 #define APDW_MASK 0x00000007 /* 2:0 */ 537 538 /* RCV_RING_CFG 0x78, 16bit register */ 539 #define RCV_DROP3 B11_MASK 540 #define RCV_DROP2 B10_MASK 541 #define RCV_DROP1 B9_MASK 542 #define RCV_DROP0 B8_MASK 543 #define RCV_RING_DEFAULT 0x0030 /* 5:4 */ 544 #define RCV_RING3_EN B3_MASK 545 #define RCV_RING2_EN B2_MASK 546 #define RCV_RING1_EN B1_MASK 547 #define RCV_RING0_EN B0_MASK 548 549 /* XMT_RING_LIMIT 0x7C, 32bit register */ 550 #define XMT_RING2_LIMIT 0x00FF0000 /* 23:16 */ 551 #define XMT_RING1_LIMIT 0x0000FF00 /* 15:8 */ 552 #define XMT_RING0_LIMIT 0x000000FF /* 7:0 */ 553 554 /* AUTOPOLL0 0x88, 16bit register */ 555 #define AP_REG0_EN B15_MASK 556 #define AP_REG0_ADDR_MASK 0x1F00 /* 12:8 */ 557 #define AP_PHY0_ADDR_MASK 0x001F /* 4:0 */ 558 559 /* AUTOPOLL1 0x8A, 16bit register */ 560 #define AP_REG1_EN B15_MASK 561 #define AP_REG1_ADDR_MASK 0x1F00 /* 12:8 */ 562 #define AP_PRE_SUP1 B6_MASK 563 #define AP_PHY1_DFLT B5_MASK 564 #define AP_PHY1_ADDR_MASK 0x001F /* 4:0 */ 565 566 /* AUTOPOLL2 0x8C, 16bit register */ 567 #define AP_REG2_EN B15_MASK 568 #define AP_REG2_ADDR_MASK 0x1F00 /* 12:8 */ 569 #define AP_PRE_SUP2 B6_MASK 570 #define AP_PHY2_DFLT B5_MASK 571 #define AP_PHY2_ADDR_MASK 0x001F /* 4:0 */ 572 573 /* AUTOPOLL3 0x8E, 16bit register */ 574 #define AP_REG3_EN B15_MASK 575 #define AP_REG3_ADDR_MASK 0x1F00 /* 12:8 */ 576 #define AP_PRE_SUP3 B6_MASK 577 #define AP_PHY3_DFLT B5_MASK 578 #define AP_PHY3_ADDR_MASK 0x001F /* 4:0 */ 579 580 /* AUTOPOLL4 0x90, 16bit register */ 581 #define AP_REG4_EN B15_MASK 582 #define AP_REG4_ADDR_MASK 0x1F00 /* 12:8 */ 583 #define AP_PRE_SUP4 B6_MASK 584 #define AP_PHY4_DFLT B5_MASK 585 #define AP_PHY4_ADDR_MASK 0x001F /* 4:0 */ 586 587 /* AUTOPOLL5 0x92, 16bit register */ 588 #define AP_REG5_EN B15_MASK 589 #define AP_REG5_ADDR_MASK 0x1F00 /* 12:8 */ 590 #define AP_PRE_SUP5 B6_MASK 591 #define AP_PHY5_DFLT B5_MASK 592 #define AP_PHY5_ADDR_MASK 0x001F /* 4:0 */ 593 594 /* AP_VALUE 0x98, 32bit ragister */ 595 #define AP_VAL_ACTIVE B31_MASK 596 #define AP_VAL_RD_CMD B29_MASK 597 #define AP_ADDR 0x00070000 /* 18:16 */ 598 #define AP_VAL 0x0000FFFF /* 15:0 */ 599 600 /* PCS_ANEG 0x9C, 32bit register */ 601 #define SYNC_LOST B10_MASK 602 #define IMATCH B9_MASK 603 #define CMATCH B8_MASK 604 #define PCS_AN_IDLE B1_MASK 605 #define PCS_AN_CFG B0_MASK 606 607 /* DLY_INT_A 0xA8, 32bit register */ 608 #define DLY_INT_A_R3 B31_MASK 609 #define DLY_INT_A_R2 B30_MASK 610 #define DLY_INT_A_R1 B29_MASK 611 #define DLY_INT_A_R0 B28_MASK 612 #define DLY_INT_A_T3 B27_MASK 613 #define DLY_INT_A_T2 B26_MASK 614 #define DLY_INT_A_T1 B25_MASK 615 #define DLY_INT_A_T0 B24_MASK 616 #define EVENT_COUNT_A 0x00FF0000 /* 20:16 */ 617 #define MAX_DELAY_TIME_A 0x000007FF /* 10:0 */ 618 619 /* DLY_INT_B 0xAC, 32bit register */ 620 #define DLY_INT_B_R3 B31_MASK 621 #define DLY_INT_B_R2 B30_MASK 622 #define DLY_INT_B_R1 B29_MASK 623 #define DLY_INT_B_R0 B28_MASK 624 #define DLY_INT_B_T3 B27_MASK 625 #define DLY_INT_B_T2 B26_MASK 626 #define DLY_INT_B_T1 B25_MASK 627 #define DLY_INT_B_T0 B24_MASK 628 #define EVENT_COUNT_B 0x00FF0000 /* 20:16 */ 629 #define MAX_DELAY_TIME_B 0x000007FF /* 10:0 */ 630 631 /* DFC_THRESH2 0xC0, 16bit register */ 632 #define DFC_THRESH2_HIGH 0xFF00 /* 15:8 */ 633 #define DFC_THRESH2_LOW 0x00FF /* 7:0 */ 634 635 /* DFC_THRESH3 0xC2, 16bit register */ 636 #define DFC_THRESH3_HIGH 0xFF00 /* 15:8 */ 637 #define DFC_THRESH3_LOW 0x00FF /* 7:0 */ 638 639 /* DFC_THRESH0 0xC4, 16bit register */ 640 #define DFC_THRESH0_HIGH 0xFF00 /* 15:8 */ 641 #define DFC_THRESH0_LOW 0x00FF /* 7:0 */ 642 643 /* DFC_THRESH1 0xC6, 16bit register */ 644 #define DFC_THRESH1_HIGH 0xFF00 /* 15:8 */ 645 #define DFC_THRESH1_LOW 0x00FF /* 7:0 */ 646 647 /* FLOW_CONTROL 0xC8, 32bit register */ 648 #define PAUSE_LEN_CHG B30_MASK 649 #define FFC_EN B28_MASK 650 #define DFC_RING3_EN B27_MASK 651 #define DFC_RING2_EN B26_MASK 652 #define DFC_RING1_EN B25_MASK 653 #define DFC_RING0_EN B24_MASK 654 #define FIXP_CONGEST B21_MASK 655 #define NAPA B20_MASK 656 #define NPA B19_MASK 657 #define FIXP B18_MASK 658 #define FCPEN B17_MASK 659 #define FCCMD B16_MASK 660 #define PAUSE_LEN 0x0000FFFF /* 15:0 */ 661 662 /* FFC THRESH 0xCC, 32bit register */ 663 #define FFC_HIGH 0xFFFF0000 /* 31:16 */ 664 #define FFC_LOW 0x0000FFFF /* 15:0 */ 665 666 /* PHY_ACCESS 0xD0, 32bit register */ 667 #define PHY_CMD_ACTIVE B31_MASK 668 #define PHY_WR_CMD B30_MASK 669 #define PHY_RD_CMD B29_MASK 670 #define PHY_RD_ERR B28_MASK 671 #define PHY_PRE_SUP B27_MASK 672 #define PHY_ADDR 0x03E00000 /* 25:21 */ 673 #define PHY_REG_ADDR 0x001F0000 /* 20:16 */ 674 #define PHY_DATA 0x0000FFFF /* 15:0 */ 675 #define PHY_ADDR_SHIFT 21 676 #define PHY_REG_ADDR_SHIFT 16 677 678 #define PHY_MAX_RETRY 30 679 680 681 /* EEPROM_ACC 0x17C, 16bit register */ 682 #define PVALID B15_MASK 683 #define PREAD B14_MASK 684 #define EEDET B13_MASK 685 #define EEN B4_MASK 686 #define ECS B2_MASK 687 #define EESK B1_MASK 688 #define EDI_EDO B0_MASK 689 690 /* PMAT0 0x190, 32bit register */ 691 #define PMR_ACTIVE B31_MASK 692 #define PMR_WR_CMD B30_MASK 693 #define PMR_RD_CMD B29_MASK 694 #define PMR_BANK B28_MASK 695 #define PMR_ADDR 0x007F0000 /* 22:16 */ 696 #define PMR_B4 0x000000FF /* 15:0 */ 697 698 /* PMAT1 0x194, 32bit register */ 699 #define PMR_B3 0xFF000000 /* 31:24 */ 700 #define PMR_B2 0x00FF0000 /* 23:16 */ 701 #define PMR_B1 0x0000FF00 /* 15:8 */ 702 #define PMR_B0 0x000000FF /* 7:0 */ 703 704 /* CAMDATA 0x198, 16bit register */ 705 #define CAM_DATA_MASK 0x000000FFFFFFFFFFFF 706 707 /* CAM_ADDR 0x1A0, 16bit register */ 708 #define CAM_CMD_ACTIVE B15_MASK 709 #define CAM_WR_CMD B14_MASK 710 #define CAM_RD_CMD B13_MASK 711 #define CAM_CLEAR B12_MASK 712 #define CAM_ADDRESS 0x001F 713 714 /* INT0 0x38, 32bit register */ 715 #define INTR B31_MASK 716 #define LCINT B27_MASK 717 #define TINT0 B8_MASK 718 #define STINT B4_MASK 719 #define RINT0 B0_MASK 720 721 /* TEST0 0x1A8, 32bit register */ 722 723 /* VAL1 */ 724 #define MFSM_RESET B10_MASK 725 #define BFD_SCALE_DOWN B9_MASK 726 727 /* VAL0 */ 728 #define LEDCNTTST B5_MASK 729 #define RTYTST_RANGEN B2_MASK 730 #define RTYTST_SLOT B1_MASK 731 #define SERRLEVEL B0_MASK 732 733 #define CABLE_CHK_TIME 100 734 735 #define PCI_IOMAP_BASE_REG 0x00 736 #define PCI_MEM_BASE_REG 0x10 737 738 #define XPHYFD B5_MASK 739 #define XPHYSP B3_MASK /* 4:3 */ 740 741 #define TX_RATE 0x1 742 #define RX_RATE 0x2 743 #define RX_BYTES 0xb 744 #define TX_BYTES 0xc 745 746 #define LOW_COALESC 1 747 #define MEDIUM_COALESC 2 748 #define HIGH_COALESC 3 749 #define NO_COALESC 4 750 751 #define CLIENT 0x1 752 #define SERVER 0x2 753 #define DISABLE 0x3 754 #define PCI_OPT 0x4 755 756 #define MULTICAST_BITMAP_ARRAY_SIZE 64 757 758 #define PHY_AUTO_NEGOTIATION 0 759 #define PHY_FORCE_HD_100 1 /* HD: Half Duplex */ 760 #define PHY_FORCE_FD_100 2 /* FD: Full Duplex */ 761 #define PHY_FORCE_HD_10 3 762 #define PHY_FORCE_FD_10 4 763 764 struct tx_desc { 765 unsigned int Tx_BCNT :16; /* Buffer Byte Count */ 766 unsigned int Tx_RES4 :6; /* RESVERD 6 bits */ 767 /* 768 * This bit causes the transmission of the corresponding frame to be 769 * aborted. If the transmitter has not started sending the frame at the 770 * time that the descriptor 771 */ 772 unsigned int KILL :1; 773 unsigned int Tx_RES3 :1; /* RESVERD 1 bits */ 774 /* End Of packet to indicates the last Buffer */ 775 unsigned int Tx_EOP :1; 776 unsigned int Tx_SOP :1; /* Defer to Transmit */ 777 unsigned int Tx_RES2 :2; 778 unsigned int Tx_LTINT :1; /* Start of packet for the Buffer */ 779 /* 780 * ADD_FCS dynamically controls the generation of FCS on a frame by 781 * frame basis. 782 */ 783 unsigned int Tx_ADD_FCS :1; 784 unsigned int Tx_RES1 :1; /* Reserved Location */ 785 unsigned int Tx_OWN :1; /* Own Bit for the Transmit */ 786 unsigned int TCI :16; /* VLAN Tag Control Command. */ 787 unsigned int TCC :2; /* Tag Control Information. */ 788 unsigned int Tx_RES0 :14; /* Resvered Location */ 789 /* 790 * TBADR[31:0] Transmit Buffer Address. This field contains the address 791 * of the Transmit buffer that is associated with this descriptor 792 */ 793 unsigned int Tx_Base_Addr :32; 794 unsigned int Tx_USPACE :32; /* User Space */ 795 }; 796 797 /* Receive Descriptor For the L7 */ 798 struct rx_desc { 799 800 /* User Reserved amar - Its just reservered. */ 801 unsigned int Rx_USPACE :32; 802 /* 803 * Message Byte Count is the number of bytes of the received message 804 * written 805 */ 806 unsigned int Rx_MCNT :16; 807 unsigned int TCI :16; 808 /* 809 * Buffer Byte Count is the length of the buffer pointed to by this 810 * descriptor 811 */ 812 unsigned int Rx_BCNT :16; 813 unsigned int Rx_RES1 :2; /* Reserved Location */ 814 /* 815 * VLAN Tag Type. Indicates what type of VLAN tag, if any, is included 816 * in the received 817 */ 818 unsigned int TT :2; 819 /* 820 * Broadcast Address Match is set by the Am79C976 controller when it 821 * accepts the reveice buffer 822 */ 823 unsigned int Rx_BAM :1; 824 /* 825 * Logical Address Filter Match is set by the Am79C976 controller 826 * to the Receive Buffer 827 */ 828 unsigned int Rx_LAFM :1; 829 /* Physical Address Match is set by the Am79C976 controller */ 830 unsigned int Rx_PAM :1; 831 unsigned int Rx_RES0 :1; /* Resvered Location */ 832 /* End Of packet to indicates the last Buffer */ 833 unsigned int Rx_EOP :1; 834 unsigned int Rx_SOP :1; /* Start of packet for the Buffer */ 835 unsigned int Rx_BUFF :1; /* Reserved location */ 836 /* 837 * CRC indicates that the receiver has detected a CRC (FCS) error on the 838 * incoming frame. 839 */ 840 unsigned int Rx_CRC :1; 841 /* 842 * Overflow error indicates that the receiver has lost all or part of 843 * the incoming frame. 844 */ 845 unsigned int Rx_OFLO :1; 846 unsigned int Rx_FRAM :1; /* Framing Error */ 847 unsigned int Rx_ERR :1; /* Error is Set By the Controller */ 848 unsigned int Rx_OWN :1; /* Own Bit of Descriptor */ 849 /* 850 * RBADR[31:0] Receive Buffer Address. This field contains the address 851 * of the receive buffer that is associated with this descriptor. 852 */ 853 unsigned int Rx_Base_Addr:32; 854 }; 855 856 857 /* Initialization Block (SSIZE32 = 1) */ 858 struct init_block { 859 unsigned int MODE :16; /* Mode */ 860 unsigned int RES1 :4; /* Reserved Location */ 861 /* Receive software structure is defined for 16 bit */ 862 unsigned int RLEN :4; 863 unsigned int RES2 :4; /* Reserved bits */ 864 /* Transmit software structure is defined for the 16 bit */ 865 unsigned int TLEN :4; 866 unsigned int PADDR0 :8; 867 unsigned int PADDR1 :8; 868 unsigned int PADDR2 :8; 869 unsigned int PADDR3 :8; 870 unsigned int PADDR4 :8; 871 unsigned int PADDR5 :8; 872 unsigned int RES3 :16; 873 unsigned char LADRF[8]; 874 /* RDRA indicate where the receive descriptor ring begins */ 875 unsigned int RDRA :32; 876 /* TDRA indicate where the transmit descriptor ring begins */ 877 unsigned int TDRA :32; 878 }; 879 880 /* MDL Physical and Normal Structure */ 881 struct mdl { 882 ULONG Io_Address; 883 ULONG Mem_Address; 884 885 volatile int CSR; 886 volatile int CardStatus; 887 888 /* PMR (Pattern Match RAM) */ 889 /* 890 * An array to store the indexes of each of the patterns in 891 * Pattern List. 892 */ 893 unsigned int *PMR_PtrList; 894 /* An array of pattern controls and pattern data bytes */ 895 unsigned char *PatternList; 896 unsigned int *PatternLength; 897 int EnableMulticast; 898 /* The begining of the free area in the PatternList array */ 899 unsigned short PatternList_FreeIndex; 900 /* The total number of patterns present in the PMR */ 901 unsigned short TotalPatterns; 902 unsigned short PatternEnableBit; 903 904 unsigned char Mac[6]; 905 unsigned char TEMP_MAC[6]; 906 unsigned int FLAGS; 907 unsigned char TempLADRF[8]; 908 909 ULONG Speed; 910 ULONG FullDuplex; 911 912 struct init_block *init_blk; 913 914 int tmpPtrArray[8]; 915 916 int MulticastBitMapArray[MULTICAST_BITMAP_ARRAY_SIZE]; 917 int External_Phy; 918 unsigned int phy_id; 919 920 /* For interrupt delay */ 921 /* Unit is 10 us. Its value must < 0x800 (2^11) */ 922 unsigned int rx_intrcoalesc_time; 923 /* Its value must < 32 (2^5) */ 924 unsigned int rx_intrcoalesc_events; 925 unsigned int tx_intrcoalesc_time; 926 unsigned int tx_intrcoalesc_events; 927 int IntrCoalescFlag; 928 929 int RxRingLenBits; 930 int TxRingLenBits; 931 int TxRingSize; 932 int RxRingSize; 933 934 int IpgValue; 935 }; 936 937 struct Rx_Buf_Desc { 938 struct rx_desc *descriptor; 939 long *USpaceMap; 940 }; 941 942 struct nonphysical 943 { 944 /* Tx descriptors queue */ 945 struct tx_desc *TxDescQRead; /* The next ring entry to be freed */ 946 struct tx_desc *TxDescQWrite; /* The next free ring entry */ 947 struct tx_desc *TxDescQStart; /* The start of the ring entries */ 948 struct tx_desc *TxDescQEnd; /* The end of the ring entries */ 949 950 /* struct Rx_Buf_Desc * queue */ 951 struct Rx_Buf_Desc *RxBufDescQRead; 952 struct Rx_Buf_Desc *RxBufDescQStart; 953 struct Rx_Buf_Desc *RxBufDescQEnd; 954 955 }; 956 957 struct mil 958 { 959 /* 960 * 1) For memory allocation and free 961 */ 962 963 /* 964 * Tx_desc: address of all tx descriptors block 965 * Tx_desc_pa: physical address of Tx_desc 966 */ 967 struct tx_desc *Tx_desc; 968 unsigned int Tx_desc_pa; 969 /* Original address, because Tx_desc needs 16 bytes alignment */ 970 ULONG Tx_desc_original; 971 972 struct rx_desc *Rx_desc; 973 unsigned int Rx_desc_pa; 974 /* Original address, because Rx_desc needs 16 bytes alignment */ 975 ULONG Rx_desc_original; 976 977 long *USpaceMapArray; /* Queue of struct rxBufInfo * */ 978 979 /* 980 * 2) For descriptor queue/buffer queue operation 981 */ 982 struct nonphysical *pNonphysical; 983 984 /* 985 * 3) Parameters 986 */ 987 int RxRingSize; 988 int TxRingSize; 989 int RxBufSize; 990 991 /* 992 * 4) Other 993 */ 994 int tx_reschedule; 995 char *name; 996 }; 997 998 struct LayerPointers 999 { 1000 struct odl *pOdl; 1001 struct mil *pMil; 1002 struct mdl *pMdl; 1003 1004 int instance; 1005 int attach_progress; 1006 int run; /* B_TRUE on plumb; B_FALSE on unplumb */ 1007 }; 1008 1009 /* MIL Function Prototypes. */ 1010 1011 /* 1012 * Initialisation of MIL data structures and External Interface Function 1013 * Pointers. 1014 */ 1015 void milInitGlbds(struct LayerPointers *); 1016 1017 void milInitRxQ(struct LayerPointers *); 1018 1019 void milResetTxQ(struct LayerPointers *); 1020 1021 void milFreeResources(struct LayerPointers *, ULONG *); 1022 1023 void milRequestResources(ULONG *); 1024 void milSetResources(struct LayerPointers *, ULONG *); 1025 1026 /* Open Functions. */ 1027 void mdlOpen(struct LayerPointers *); 1028 1029 void mdlHWReset(struct LayerPointers *); 1030 1031 /* Multicast */ 1032 void mdlDeleteMulticastAddress(struct LayerPointers *, UCHAR *); 1033 void mdlAddMulticastAddress(struct LayerPointers *, UCHAR *); 1034 1035 /* Transmit/Receive Interface provided by MDL */ 1036 void mdlTransmit(struct LayerPointers *); 1037 void mdlReceive(struct LayerPointers *); 1038 1039 unsigned int mdlReadMib(struct LayerPointers *, char); 1040 1041 /* Read Link Status */ 1042 int mdlReadLink(struct LayerPointers *); 1043 1044 /* Interrupt Handling */ 1045 unsigned int mdlReadInterrupt(struct LayerPointers *); 1046 1047 void mdlEnableInterrupt(struct LayerPointers *); 1048 void mdlDisableInterrupt(struct LayerPointers *); 1049 1050 void mdlGetActiveMediaInfo(struct LayerPointers *); 1051 1052 void mdlStartChip(struct LayerPointers *); 1053 void mdlStopChip(struct LayerPointers *); 1054 1055 void mdlGetMacAddress(struct LayerPointers *, unsigned char *); 1056 void mdlSetMacAddress(struct LayerPointers *, unsigned char *); 1057 1058 void mdlAddMulticastAddresses(struct LayerPointers *, int, unsigned char *); 1059 1060 void mdlSetPromiscuous(struct LayerPointers *); 1061 void mdlDisablePromiscuous(struct LayerPointers *); 1062 1063 void mdlSendPause(struct LayerPointers *); 1064 1065 void SetIntrCoalesc(struct LayerPointers *, boolean_t); 1066 void mdlPHYAutoNegotiation(struct LayerPointers *, unsigned int); 1067 void mdlRxFastSuspend(struct LayerPointers *); 1068 void mdlRxFastSuspendClear(struct LayerPointers *); 1069 1070 /* Externs */ 1071 1072 /* ODL functions */ 1073 extern void amd8111s_reset(struct LayerPointers *); 1074 extern unsigned char READ_REG8(struct LayerPointers *, long); 1075 extern void WRITE_REG8(struct LayerPointers *, long, int); 1076 extern int READ_REG16(struct LayerPointers *, long); 1077 extern void WRITE_REG16(struct LayerPointers *, long, int); 1078 extern long READ_REG32(struct LayerPointers *, long); 1079 extern void WRITE_REG32(struct LayerPointers *, long, int); 1080 extern void WRITE_REG64(struct LayerPointers *, long, char *); 1081 1082 #endif /* AMD8111S_HW_H */ 1083