1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License, Version 1.0 only 6 * (the "License"). You may not use this file except in compliance 7 * with the License. 8 * 9 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 10 * or http://www.opensolaris.org/os/licensing. 11 * See the License for the specific language governing permissions 12 * and limitations under the License. 13 * 14 * When distributing Covered Code, include this CDDL HEADER in each 15 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 16 * If applicable, add the following below this CDDL HEADER, with the 17 * fields enclosed by brackets "[]" replaced with your own identifying 18 * information: Portions Copyright [yyyy] [name of copyright owner] 19 * 20 * CDDL HEADER END 21 */ 22/* 23 * Copyright 2005 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27/* 28 * Copyright (c) 1990, 1991 UNIX System Laboratories, Inc. 29 * Copyright (c) 1984, 1986, 1987, 1988, 1989, 1990 AT&T 30 * All Rights Reserved 31 */ 32 33#pragma ident "%Z%%M% %I% %E% SMI" 34 35/* 36 * General assembly language routines. 37 * It is the intent of this file to contain routines that are 38 * independent of the specific kernel architecture, and those that are 39 * common across kernel architectures. 40 * As architectures diverge, and implementations of specific 41 * architecture-dependent routines change, the routines should be moved 42 * from this file into the respective ../`arch -k`/subr.s file. 43 */ 44 45#include <sys/asm_linkage.h> 46#include <sys/asm_misc.h> 47#include <sys/panic.h> 48#include <sys/ontrap.h> 49#include <sys/regset.h> 50#include <sys/privregs.h> 51#include <sys/reboot.h> 52#include <sys/psw.h> 53#include <sys/x86_archext.h> 54 55#if defined(__lint) 56#include <sys/types.h> 57#include <sys/systm.h> 58#include <sys/thread.h> 59#include <sys/archsystm.h> 60#include <sys/byteorder.h> 61#include <sys/dtrace.h> 62#else /* __lint */ 63#include "assym.h" 64#endif /* __lint */ 65#include <sys/dditypes.h> 66 67/* 68 * on_fault() 69 * Catch lofault faults. Like setjmp except it returns one 70 * if code following causes uncorrectable fault. Turned off 71 * by calling no_fault(). 72 */ 73 74#if defined(__lint) 75 76/* ARGSUSED */ 77int 78on_fault(label_t *ljb) 79{ return (0); } 80 81void 82no_fault(void) 83{} 84 85#else /* __lint */ 86 87#if defined(__amd64) 88 89 ENTRY(on_fault) 90 movq %gs:CPU_THREAD, %rsi 91 leaq catch_fault(%rip), %rdx 92 movq %rdi, T_ONFAULT(%rsi) /* jumpbuf in t_onfault */ 93 movq %rdx, T_LOFAULT(%rsi) /* catch_fault in t_lofault */ 94 jmp setjmp /* let setjmp do the rest */ 95 96catch_fault: 97 movq %gs:CPU_THREAD, %rsi 98 movq T_ONFAULT(%rsi), %rdi /* address of save area */ 99 xorl %eax, %eax 100 movq %rax, T_ONFAULT(%rsi) /* turn off onfault */ 101 movq %rax, T_LOFAULT(%rsi) /* turn off lofault */ 102 jmp longjmp /* let longjmp do the rest */ 103 SET_SIZE(on_fault) 104 105 ENTRY(no_fault) 106 movq %gs:CPU_THREAD, %rsi 107 xorl %eax, %eax 108 movq %rax, T_ONFAULT(%rsi) /* turn off onfault */ 109 movq %rax, T_LOFAULT(%rsi) /* turn off lofault */ 110 ret 111 SET_SIZE(no_fault) 112 113#elif defined(__i386) 114 115 ENTRY(on_fault) 116 movl %gs:CPU_THREAD, %edx 117 movl 4(%esp), %eax /* jumpbuf address */ 118 leal catch_fault, %ecx 119 movl %eax, T_ONFAULT(%edx) /* jumpbuf in t_onfault */ 120 movl %ecx, T_LOFAULT(%edx) /* catch_fault in t_lofault */ 121 jmp setjmp /* let setjmp do the rest */ 122 123catch_fault: 124 movl %gs:CPU_THREAD, %edx 125 xorl %eax, %eax 126 movl T_ONFAULT(%edx), %ecx /* address of save area */ 127 movl %eax, T_ONFAULT(%edx) /* turn off onfault */ 128 movl %eax, T_LOFAULT(%edx) /* turn off lofault */ 129 pushl %ecx 130 call longjmp /* let longjmp do the rest */ 131 SET_SIZE(on_fault) 132 133 ENTRY(no_fault) 134 movl %gs:CPU_THREAD, %edx 135 xorl %eax, %eax 136 movl %eax, T_ONFAULT(%edx) /* turn off onfault */ 137 movl %eax, T_LOFAULT(%edx) /* turn off lofault */ 138 ret 139 SET_SIZE(no_fault) 140 141#endif /* __i386 */ 142#endif /* __lint */ 143 144/* 145 * Default trampoline code for on_trap() (see <sys/ontrap.h>). We just 146 * do a longjmp(&curthread->t_ontrap->ot_jmpbuf) if this is ever called. 147 */ 148 149#if defined(lint) 150 151void 152on_trap_trampoline(void) 153{} 154 155#else /* __lint */ 156 157#if defined(__amd64) 158 159 ENTRY(on_trap_trampoline) 160 movq %gs:CPU_THREAD, %rsi 161 movq T_ONTRAP(%rsi), %rdi 162 addq $OT_JMPBUF, %rdi 163 jmp longjmp 164 SET_SIZE(on_trap_trampoline) 165 166#elif defined(__i386) 167 168 ENTRY(on_trap_trampoline) 169 movl %gs:CPU_THREAD, %eax 170 movl T_ONTRAP(%eax), %eax 171 addl $OT_JMPBUF, %eax 172 pushl %eax 173 call longjmp 174 SET_SIZE(on_trap_trampoline) 175 176#endif /* __i386 */ 177#endif /* __lint */ 178 179/* 180 * Push a new element on to the t_ontrap stack. Refer to <sys/ontrap.h> for 181 * more information about the on_trap() mechanism. If the on_trap_data is the 182 * same as the topmost stack element, we just modify that element. 183 */ 184#if defined(lint) 185 186/*ARGSUSED*/ 187int 188on_trap(on_trap_data_t *otp, uint_t prot) 189{ return (0); } 190 191#else /* __lint */ 192 193#if defined(__amd64) 194 195 ENTRY(on_trap) 196 movw %si, OT_PROT(%rdi) /* ot_prot = prot */ 197 movw $0, OT_TRAP(%rdi) /* ot_trap = 0 */ 198 leaq on_trap_trampoline(%rip), %rdx /* rdx = &on_trap_trampoline */ 199 movq %rdx, OT_TRAMPOLINE(%rdi) /* ot_trampoline = rdx */ 200 xorl %ecx, %ecx 201 movq %rcx, OT_HANDLE(%rdi) /* ot_handle = NULL */ 202 movq %rcx, OT_PAD1(%rdi) /* ot_pad1 = NULL */ 203 movq %gs:CPU_THREAD, %rdx /* rdx = curthread */ 204 movq T_ONTRAP(%rdx), %rcx /* rcx = curthread->t_ontrap */ 205 cmpq %rdi, %rcx /* if (otp == %rcx) */ 206 je 0f /* don't modify t_ontrap */ 207 208 movq %rcx, OT_PREV(%rdi) /* ot_prev = t_ontrap */ 209 movq %rdi, T_ONTRAP(%rdx) /* curthread->t_ontrap = otp */ 210 2110: addq $OT_JMPBUF, %rdi /* &ot_jmpbuf */ 212 jmp setjmp 213 SET_SIZE(on_trap) 214 215#elif defined(__i386) 216 217 ENTRY(on_trap) 218 movl 4(%esp), %eax /* %eax = otp */ 219 movl 8(%esp), %edx /* %edx = prot */ 220 221 movw %dx, OT_PROT(%eax) /* ot_prot = prot */ 222 movw $0, OT_TRAP(%eax) /* ot_trap = 0 */ 223 leal on_trap_trampoline, %edx /* %edx = &on_trap_trampoline */ 224 movl %edx, OT_TRAMPOLINE(%eax) /* ot_trampoline = %edx */ 225 movl $0, OT_HANDLE(%eax) /* ot_handle = NULL */ 226 movl $0, OT_PAD1(%eax) /* ot_pad1 = NULL */ 227 movl %gs:CPU_THREAD, %edx /* %edx = curthread */ 228 movl T_ONTRAP(%edx), %ecx /* %ecx = curthread->t_ontrap */ 229 cmpl %eax, %ecx /* if (otp == %ecx) */ 230 je 0f /* don't modify t_ontrap */ 231 232 movl %ecx, OT_PREV(%eax) /* ot_prev = t_ontrap */ 233 movl %eax, T_ONTRAP(%edx) /* curthread->t_ontrap = otp */ 234 2350: addl $OT_JMPBUF, %eax /* %eax = &ot_jmpbuf */ 236 movl %eax, 4(%esp) /* put %eax back on the stack */ 237 jmp setjmp /* let setjmp do the rest */ 238 SET_SIZE(on_trap) 239 240#endif /* __i386 */ 241#endif /* __lint */ 242 243/* 244 * Setjmp and longjmp implement non-local gotos using state vectors 245 * type label_t. 246 */ 247 248#if defined(__lint) 249 250/* ARGSUSED */ 251int 252setjmp(label_t *lp) 253{ return (0); } 254 255/* ARGSUSED */ 256void 257longjmp(label_t *lp) 258{} 259 260#else /* __lint */ 261 262#if LABEL_PC != 0 263#error LABEL_PC MUST be defined as 0 for setjmp/longjmp to work as coded 264#endif /* LABEL_PC != 0 */ 265 266#if defined(__amd64) 267 268 ENTRY(setjmp) 269 movq %rsp, LABEL_SP(%rdi) 270 movq %rbp, LABEL_RBP(%rdi) 271 movq %rbx, LABEL_RBX(%rdi) 272 movq %r12, LABEL_R12(%rdi) 273 movq %r13, LABEL_R13(%rdi) 274 movq %r14, LABEL_R14(%rdi) 275 movq %r15, LABEL_R15(%rdi) 276 movq (%rsp), %rdx /* return address */ 277 movq %rdx, (%rdi) /* LABEL_PC is 0 */ 278 xorl %eax, %eax /* return 0 */ 279 ret 280 SET_SIZE(setjmp) 281 282 ENTRY(longjmp) 283 movq LABEL_SP(%rdi), %rsp 284 movq LABEL_RBP(%rdi), %rbp 285 movq LABEL_RBX(%rdi), %rbx 286 movq LABEL_R12(%rdi), %r12 287 movq LABEL_R13(%rdi), %r13 288 movq LABEL_R14(%rdi), %r14 289 movq LABEL_R15(%rdi), %r15 290 movq (%rdi), %rdx /* return address; LABEL_PC is 0 */ 291 movq %rdx, (%rsp) 292 xorl %eax, %eax 293 incl %eax /* return 1 */ 294 ret 295 SET_SIZE(longjmp) 296 297#elif defined(__i386) 298 299 ENTRY(setjmp) 300 movl 4(%esp), %edx /* address of save area */ 301 movl %ebp, LABEL_EBP(%edx) 302 movl %ebx, LABEL_EBX(%edx) 303 movl %esi, LABEL_ESI(%edx) 304 movl %edi, LABEL_EDI(%edx) 305 movl %esp, 4(%edx) 306 movl (%esp), %ecx /* %eip (return address) */ 307 movl %ecx, (%edx) /* LABEL_PC is 0 */ 308 subl %eax, %eax /* return 0 */ 309 ret 310 SET_SIZE(setjmp) 311 312 ENTRY(longjmp) 313 movl 4(%esp), %edx /* address of save area */ 314 movl LABEL_EBP(%edx), %ebp 315 movl LABEL_EBX(%edx), %ebx 316 movl LABEL_ESI(%edx), %esi 317 movl LABEL_EDI(%edx), %edi 318 movl 4(%edx), %esp 319 movl (%edx), %ecx /* %eip (return addr); LABEL_PC is 0 */ 320 movl $1, %eax 321 addl $4, %esp /* pop ret adr */ 322 jmp *%ecx /* indirect */ 323 SET_SIZE(longjmp) 324 325#endif /* __i386 */ 326#endif /* __lint */ 327 328/* 329 * if a() calls b() calls caller(), 330 * caller() returns return address in a(). 331 * (Note: We assume a() and b() are C routines which do the normal entry/exit 332 * sequence.) 333 */ 334 335#if defined(__lint) 336 337caddr_t 338caller(void) 339{ return (0); } 340 341#else /* __lint */ 342 343#if defined(__amd64) 344 345 ENTRY(caller) 346 movq 8(%rbp), %rax /* b()'s return pc, in a() */ 347 ret 348 SET_SIZE(caller) 349 350#elif defined(__i386) 351 352 ENTRY(caller) 353 movl 4(%ebp), %eax /* b()'s return pc, in a() */ 354 ret 355 SET_SIZE(caller) 356 357#endif /* __i386 */ 358#endif /* __lint */ 359 360/* 361 * if a() calls callee(), callee() returns the 362 * return address in a(); 363 */ 364 365#if defined(__lint) 366 367caddr_t 368callee(void) 369{ return (0); } 370 371#else /* __lint */ 372 373#if defined(__amd64) 374 375 ENTRY(callee) 376 movq (%rsp), %rax /* callee()'s return pc, in a() */ 377 ret 378 SET_SIZE(callee) 379 380#elif defined(__i386) 381 382 ENTRY(callee) 383 movl (%esp), %eax /* callee()'s return pc, in a() */ 384 ret 385 SET_SIZE(callee) 386 387#endif /* __i386 */ 388#endif /* __lint */ 389 390/* 391 * return the current frame pointer 392 */ 393 394#if defined(__lint) 395 396greg_t 397getfp(void) 398{ return (0); } 399 400#else /* __lint */ 401 402#if defined(__amd64) 403 404 ENTRY(getfp) 405 movq %rbp, %rax 406 ret 407 SET_SIZE(getfp) 408 409#elif defined(__i386) 410 411 ENTRY(getfp) 412 movl %ebp, %eax 413 ret 414 SET_SIZE(getfp) 415 416#endif /* __i386 */ 417#endif /* __lint */ 418 419/* 420 * Invalidate a single page table entry in the TLB 421 */ 422 423#if defined(__lint) 424 425/* ARGSUSED */ 426void 427mmu_tlbflush_entry(caddr_t m) 428{} 429 430#else /* __lint */ 431 432#if defined(__amd64) 433 434 ENTRY(mmu_tlbflush_entry) 435 invlpg (%rdi) 436 ret 437 SET_SIZE(mmu_tlbflush_entry) 438 439#elif defined(__i386) 440 441 ENTRY(mmu_tlbflush_entry) 442 movl 4(%esp), %eax 443 invlpg (%eax) 444 ret 445 SET_SIZE(mmu_tlbflush_entry) 446 447#endif /* __i386 */ 448#endif /* __lint */ 449 450 451/* 452 * Get/Set the value of various control registers 453 */ 454 455#if defined(__lint) 456 457ulong_t 458getcr0(void) 459{ return (0); } 460 461/* ARGSUSED */ 462void 463setcr0(ulong_t value) 464{} 465 466ulong_t 467getcr2(void) 468{ return (0); } 469 470ulong_t 471getcr3(void) 472{ return (0); } 473 474/* ARGSUSED */ 475void 476setcr3(ulong_t val) 477{} 478 479void 480reload_cr3(void) 481{} 482 483ulong_t 484getcr4(void) 485{ return (0); } 486 487/* ARGSUSED */ 488void 489setcr4(ulong_t val) 490{} 491 492#if defined(__amd64) 493 494ulong_t 495getcr8(void) 496{ return (0); } 497 498/* ARGSUSED */ 499void 500setcr8(ulong_t val) 501{} 502 503#endif /* __amd64 */ 504 505#else /* __lint */ 506 507#if defined(__amd64) 508 509 ENTRY(getcr0) 510 movq %cr0, %rax 511 ret 512 SET_SIZE(getcr0) 513 514 ENTRY(setcr0) 515 movq %rdi, %cr0 516 ret 517 SET_SIZE(setcr0) 518 519 ENTRY(getcr2) 520 movq %cr2, %rax 521 ret 522 SET_SIZE(getcr2) 523 524 ENTRY(getcr3) 525 movq %cr3, %rax 526 ret 527 SET_SIZE(getcr3) 528 529 ENTRY(setcr3) 530 movq %rdi, %cr3 531 ret 532 SET_SIZE(setcr3) 533 534 ENTRY(reload_cr3) 535 movq %cr3, %rdi 536 movq %rdi, %cr3 537 ret 538 SET_SIZE(reload_cr3) 539 540 ENTRY(getcr4) 541 movq %cr4, %rax 542 ret 543 SET_SIZE(getcr4) 544 545 ENTRY(setcr4) 546 movq %rdi, %cr4 547 ret 548 SET_SIZE(setcr4) 549 550 ENTRY(getcr8) 551 movq %cr8, %rax 552 ret 553 SET_SIZE(getcr8) 554 555 ENTRY(setcr8) 556 movq %rdi, %cr8 557 ret 558 SET_SIZE(setcr8) 559 560#elif defined(__i386) 561 562 ENTRY(getcr0) 563 movl %cr0, %eax 564 ret 565 SET_SIZE(getcr0) 566 567 ENTRY(setcr0) 568 movl 4(%esp), %eax 569 movl %eax, %cr0 570 ret 571 SET_SIZE(setcr0) 572 573 ENTRY(getcr2) 574 movl %cr2, %eax 575 ret 576 SET_SIZE(getcr2) 577 578 ENTRY(getcr3) 579 movl %cr3, %eax 580 ret 581 SET_SIZE(getcr3) 582 583 ENTRY(setcr3) 584 movl 4(%esp), %eax 585 movl %eax, %cr3 586 ret 587 SET_SIZE(setcr3) 588 589 ENTRY(reload_cr3) 590 movl %cr3, %eax 591 movl %eax, %cr3 592 ret 593 SET_SIZE(reload_cr3) 594 595 ENTRY(getcr4) 596 movl %cr4, %eax 597 ret 598 SET_SIZE(getcr4) 599 600 ENTRY(setcr4) 601 movl 4(%esp), %eax 602 movl %eax, %cr4 603 ret 604 SET_SIZE(setcr4) 605 606#endif /* __i386 */ 607#endif /* __lint */ 608 609#if defined(__lint) 610 611/*ARGSUSED*/ 612uint32_t 613__cpuid_insn(uint32_t eax, uint32_t *ebxp, uint32_t *ecxp, uint32_t *edxp) 614{ return (0); } 615 616#else /* __lint */ 617 618#if defined(__amd64) 619 620 ENTRY(__cpuid_insn) 621 movq %rbx, %r11 622 movq %rdx, %r8 /* r8 = ecxp */ 623 movq %rcx, %r9 /* r9 = edxp */ 624 movl %edi, %eax 625 cpuid 626 movl %ebx, (%rsi) 627 movl %ecx, (%r8) 628 movl %edx, (%r9) 629 movq %r11, %rbx 630 ret 631 SET_SIZE(__cpuid_insn) 632 633#elif defined(__i386) 634 635 ENTRY(__cpuid_insn) 636 pushl %ebp 637 movl %esp, %ebp 638 pushl %ebx 639 movl 8(%ebp), %eax 640 cpuid 641 pushl %eax 642 movl 0x0c(%ebp), %eax 643 movl %ebx, (%eax) 644 movl 0x10(%ebp), %eax 645 movl %ecx, (%eax) 646 movl 0x14(%ebp), %eax 647 movl %edx, (%eax) 648 popl %eax 649 popl %ebx 650 popl %ebp 651 ret 652 SET_SIZE(__cpuid_insn) 653 654#endif /* __i386 */ 655#endif /* __lint */ 656 657/* 658 * Insert entryp after predp in a doubly linked list. 659 */ 660 661#if defined(__lint) 662 663/*ARGSUSED*/ 664void 665_insque(caddr_t entryp, caddr_t predp) 666{} 667 668#else /* __lint */ 669 670#if defined(__amd64) 671 672 ENTRY(_insque) 673 movq (%rsi), %rax /* predp->forw */ 674 movq %rsi, CPTRSIZE(%rdi) /* entryp->back = predp */ 675 movq %rax, (%rdi) /* entryp->forw = predp->forw */ 676 movq %rdi, (%rsi) /* predp->forw = entryp */ 677 movq %rdi, CPTRSIZE(%rax) /* predp->forw->back = entryp */ 678 ret 679 SET_SIZE(_insque) 680 681#elif defined(__i386) 682 683 ENTRY(_insque) 684 movl 8(%esp), %edx 685 movl 4(%esp), %ecx 686 movl (%edx), %eax /* predp->forw */ 687 movl %edx, CPTRSIZE(%ecx) /* entryp->back = predp */ 688 movl %eax, (%ecx) /* entryp->forw = predp->forw */ 689 movl %ecx, (%edx) /* predp->forw = entryp */ 690 movl %ecx, CPTRSIZE(%eax) /* predp->forw->back = entryp */ 691 ret 692 SET_SIZE(_insque) 693 694#endif /* __i386 */ 695#endif /* __lint */ 696 697/* 698 * Remove entryp from a doubly linked list 699 */ 700 701#if defined(__lint) 702 703/*ARGSUSED*/ 704void 705_remque(caddr_t entryp) 706{} 707 708#else /* __lint */ 709 710#if defined(__amd64) 711 712 ENTRY(_remque) 713 movq (%rdi), %rax /* entry->forw */ 714 movq CPTRSIZE(%rdi), %rdx /* entry->back */ 715 movq %rax, (%rdx) /* entry->back->forw = entry->forw */ 716 movq %rdx, CPTRSIZE(%rax) /* entry->forw->back = entry->back */ 717 ret 718 SET_SIZE(_remque) 719 720#elif defined(__i386) 721 722 ENTRY(_remque) 723 movl 4(%esp), %ecx 724 movl (%ecx), %eax /* entry->forw */ 725 movl CPTRSIZE(%ecx), %edx /* entry->back */ 726 movl %eax, (%edx) /* entry->back->forw = entry->forw */ 727 movl %edx, CPTRSIZE(%eax) /* entry->forw->back = entry->back */ 728 ret 729 SET_SIZE(_remque) 730 731#endif /* __i386 */ 732#endif /* __lint */ 733 734/* 735 * Returns the number of 736 * non-NULL bytes in string argument. 737 */ 738 739#if defined(__lint) 740 741/* ARGSUSED */ 742size_t 743strlen(const char *str) 744{ return (0); } 745 746#else /* __lint */ 747 748#if defined(__amd64) 749 750/* 751 * This is close to a simple transliteration of a C version of this 752 * routine. We should either just -make- this be a C version, or 753 * justify having it in assembler by making it significantly faster. 754 * 755 * size_t 756 * strlen(const char *s) 757 * { 758 * const char *s0; 759 * #if defined(DEBUG) 760 * if ((uintptr_t)s < KERNELBASE) 761 * panic(.str_panic_msg); 762 * #endif 763 * for (s0 = s; *s; s++) 764 * ; 765 * return (s - s0); 766 * } 767 */ 768 769 ENTRY(strlen) 770#ifdef DEBUG 771 movq kernelbase(%rip), %rax 772 cmpq %rax, %rdi 773 jae str_valid 774 pushq %rbp 775 movq %rsp, %rbp 776 leaq .str_panic_msg(%rip), %rdi 777 xorl %eax, %eax 778 call panic 779#endif /* DEBUG */ 780str_valid: 781 cmpb $0, (%rdi) 782 movq %rdi, %rax 783 je .null_found 784 .align 4 785.strlen_loop: 786 incq %rdi 787 cmpb $0, (%rdi) 788 jne .strlen_loop 789.null_found: 790 subq %rax, %rdi 791 movq %rdi, %rax 792 ret 793 SET_SIZE(strlen) 794 795#elif defined(__i386) 796 797 ENTRY(strlen) 798#ifdef DEBUG 799 movl kernelbase, %eax 800 cmpl %eax, 4(%esp) 801 jae str_valid 802 pushl %ebp 803 movl %esp, %ebp 804 pushl $.str_panic_msg 805 call panic 806#endif /* DEBUG */ 807 808str_valid: 809 movl 4(%esp), %eax /* %eax = string address */ 810 testl $3, %eax /* if %eax not word aligned */ 811 jnz .not_word_aligned /* goto .not_word_aligned */ 812 .align 4 813.word_aligned: 814 movl (%eax), %edx /* move 1 word from (%eax) to %edx */ 815 movl $0x7f7f7f7f, %ecx 816 andl %edx, %ecx /* %ecx = %edx & 0x7f7f7f7f */ 817 addl $4, %eax /* next word */ 818 addl $0x7f7f7f7f, %ecx /* %ecx += 0x7f7f7f7f */ 819 orl %edx, %ecx /* %ecx |= %edx */ 820 andl $0x80808080, %ecx /* %ecx &= 0x80808080 */ 821 cmpl $0x80808080, %ecx /* if no null byte in this word */ 822 je .word_aligned /* goto .word_aligned */ 823 subl $4, %eax /* post-incremented */ 824.not_word_aligned: 825 cmpb $0, (%eax) /* if a byte in (%eax) is null */ 826 je .null_found /* goto .null_found */ 827 incl %eax /* next byte */ 828 testl $3, %eax /* if %eax not word aligned */ 829 jnz .not_word_aligned /* goto .not_word_aligned */ 830 jmp .word_aligned /* goto .word_aligned */ 831 .align 4 832.null_found: 833 subl 4(%esp), %eax /* %eax -= string address */ 834 ret 835 SET_SIZE(strlen) 836 837#endif /* __i386 */ 838 839#ifdef DEBUG 840 .text 841.str_panic_msg: 842 .string "strlen: argument below kernelbase" 843#endif /* DEBUG */ 844 845#endif /* __lint */ 846 847 /* 848 * Berkley 4.3 introduced symbolically named interrupt levels 849 * as a way deal with priority in a machine independent fashion. 850 * Numbered priorities are machine specific, and should be 851 * discouraged where possible. 852 * 853 * Note, for the machine specific priorities there are 854 * examples listed for devices that use a particular priority. 855 * It should not be construed that all devices of that 856 * type should be at that priority. It is currently were 857 * the current devices fit into the priority scheme based 858 * upon time criticalness. 859 * 860 * The underlying assumption of these assignments is that 861 * IPL 10 is the highest level from which a device 862 * routine can call wakeup. Devices that interrupt from higher 863 * levels are restricted in what they can do. If they need 864 * kernels services they should schedule a routine at a lower 865 * level (via software interrupt) to do the required 866 * processing. 867 * 868 * Examples of this higher usage: 869 * Level Usage 870 * 14 Profiling clock (and PROM uart polling clock) 871 * 12 Serial ports 872 * 873 * The serial ports request lower level processing on level 6. 874 * 875 * Also, almost all splN routines (where N is a number or a 876 * mnemonic) will do a RAISE(), on the assumption that they are 877 * never used to lower our priority. 878 * The exceptions are: 879 * spl8() Because you can't be above 15 to begin with! 880 * splzs() Because this is used at boot time to lower our 881 * priority, to allow the PROM to poll the uart. 882 * spl0() Used to lower priority to 0. 883 */ 884 885#if defined(__lint) 886 887int spl0(void) { return (0); } 888int spl6(void) { return (0); } 889int spl7(void) { return (0); } 890int spl8(void) { return (0); } 891int splhigh(void) { return (0); } 892int splhi(void) { return (0); } 893int splzs(void) { return (0); } 894 895#else /* __lint */ 896 897/* reg = cpu->cpu_m.cpu_pri; */ 898#define GETIPL_NOGS(reg, cpup) \ 899 movl CPU_PRI(cpup), reg; 900 901/* cpu->cpu_m.cpu_pri; */ 902#define SETIPL_NOGS(val, cpup) \ 903 movl val, CPU_PRI(cpup); 904 905/* reg = cpu->cpu_m.cpu_pri; */ 906#define GETIPL(reg) \ 907 movl %gs:CPU_PRI, reg; 908 909/* cpu->cpu_m.cpu_pri; */ 910#define SETIPL(val) \ 911 movl val, %gs:CPU_PRI; 912 913/* 914 * Macro to raise processor priority level. 915 * Avoid dropping processor priority if already at high level. 916 * Also avoid going below CPU->cpu_base_spl, which could've just been set by 917 * a higher-level interrupt thread that just blocked. 918 */ 919#if defined(__amd64) 920 921#define RAISE(level) \ 922 cli; \ 923 LOADCPU(%rcx); \ 924 movl $/**/level, %edi;\ 925 GETIPL_NOGS(%eax, %rcx);\ 926 cmpl %eax, %edi; \ 927 jg spl; \ 928 jmp setsplhisti 929 930#elif defined(__i386) 931 932#define RAISE(level) \ 933 cli; \ 934 LOADCPU(%ecx); \ 935 movl $/**/level, %edx;\ 936 GETIPL_NOGS(%eax, %ecx);\ 937 cmpl %eax, %edx; \ 938 jg spl; \ 939 jmp setsplhisti 940 941#endif /* __i386 */ 942 943/* 944 * Macro to set the priority to a specified level. 945 * Avoid dropping the priority below CPU->cpu_base_spl. 946 */ 947#if defined(__amd64) 948 949#define SETPRI(level) \ 950 cli; \ 951 LOADCPU(%rcx); \ 952 movl $/**/level, %edi; \ 953 jmp spl 954 955#elif defined(__i386) 956 957#define SETPRI(level) \ 958 cli; \ 959 LOADCPU(%ecx); \ 960 movl $/**/level, %edx; \ 961 jmp spl 962 963#endif /* __i386 */ 964 965 /* locks out all interrupts, including memory errors */ 966 ENTRY(spl8) 967 SETPRI(15) 968 SET_SIZE(spl8) 969 970 /* just below the level that profiling runs */ 971 ENTRY(spl7) 972 RAISE(13) 973 SET_SIZE(spl7) 974 975 /* sun specific - highest priority onboard serial i/o asy ports */ 976 ENTRY(splzs) 977 SETPRI(12) /* Can't be a RAISE, as it's used to lower us */ 978 SET_SIZE(splzs) 979 980 /* 981 * should lock out clocks and all interrupts, 982 * as you can see, there are exceptions 983 */ 984 985#if defined(__amd64) 986 987 .align 16 988 ENTRY(splhi) 989 ALTENTRY(splhigh) 990 ALTENTRY(spl6) 991 ALTENTRY(i_ddi_splhigh) 992 cli 993 LOADCPU(%rcx) 994 movl $DISP_LEVEL, %edi 995 movl CPU_PRI(%rcx), %eax 996 cmpl %eax, %edi 997 jle setsplhisti 998 SETIPL_NOGS(%edi, %rcx) 999 /* 1000 * If we aren't using cr8 to control ipl then we patch this 1001 * with a jump to slow_setsplhi 1002 */ 1003 ALTENTRY(setsplhi_patch) 1004 movq CPU_PRI_DATA(%rcx), %r11 /* get pri data ptr */ 1005 movzb (%r11, %rdi, 1), %rdx /* get apic mask for this ipl */ 1006 movq %rdx, %cr8 /* set new apic priority */ 1007 /* 1008 * enable interrupts 1009 */ 1010setsplhisti: 1011 nop /* patch this to a sti when a proper setspl routine appears */ 1012 ret 1013 1014 ALTENTRY(slow_setsplhi) 1015 pushq %rbp 1016 movq %rsp, %rbp 1017 subq $16, %rsp 1018 movl %eax, -4(%rbp) /* save old ipl */ 1019 call *setspl(%rip) 1020 movl -4(%rbp), %eax /* return old ipl */ 1021 leave 1022 jmp setsplhisti 1023 1024 SET_SIZE(i_ddi_splhigh) 1025 SET_SIZE(spl6) 1026 SET_SIZE(splhigh) 1027 SET_SIZE(splhi) 1028 1029#elif defined(__i386) 1030 1031 .align 16 1032 ENTRY(splhi) 1033 ALTENTRY(splhigh) 1034 ALTENTRY(spl6) 1035 ALTENTRY(i_ddi_splhigh) 1036 cli 1037 LOADCPU(%ecx) 1038 movl $DISP_LEVEL, %edx 1039 movl CPU_PRI(%ecx), %eax 1040 cmpl %eax, %edx 1041 jle setsplhisti 1042 SETIPL_NOGS(%edx, %ecx) /* set new ipl */ 1043 1044 pushl %eax /* save old ipl */ 1045 pushl %edx /* pass new ipl */ 1046 call *setspl 1047 popl %ecx /* dummy pop */ 1048 popl %eax /* return old ipl */ 1049 /* 1050 * enable interrupts 1051 * 1052 * (we patch this to an sti once a proper setspl routine 1053 * is installed) 1054 */ 1055setsplhisti: 1056 nop /* patch this to a sti when a proper setspl routine appears */ 1057 ret 1058 SET_SIZE(i_ddi_splhigh) 1059 SET_SIZE(spl6) 1060 SET_SIZE(splhigh) 1061 SET_SIZE(splhi) 1062 1063#endif /* __i386 */ 1064 1065 /* allow all interrupts */ 1066 ENTRY(spl0) 1067 SETPRI(0) 1068 SET_SIZE(spl0) 1069 1070#endif /* __lint */ 1071 1072/* 1073 * splr is like splx but will only raise the priority and never drop it 1074 */ 1075#if defined(__lint) 1076 1077/* ARGSUSED */ 1078int 1079splr(int level) 1080{ return (0); } 1081 1082#else /* __lint */ 1083 1084#if defined(__amd64) 1085 1086 ENTRY(splr) 1087 cli 1088 LOADCPU(%rcx) 1089 GETIPL_NOGS(%eax, %rcx) 1090 cmpl %eax, %edi /* if new level > current level */ 1091 jg spl /* then set ipl to new level */ 1092splr_setsti: 1093 nop /* patch this to a sti when a proper setspl routine appears */ 1094 ret /* else return the current level */ 1095 SET_SIZE(splr) 1096 1097#elif defined(__i386) 1098 1099 ENTRY(splr) 1100 cli 1101 LOADCPU(%ecx) 1102 movl 4(%esp), %edx /* get new spl level */ 1103 GETIPL_NOGS(%eax, %ecx) 1104 cmpl %eax, %edx /* if new level > current level */ 1105 jg spl /* then set ipl to new level */ 1106splr_setsti: 1107 nop /* patch this to a sti when a proper setspl routine appears */ 1108 ret /* else return the current level */ 1109 SET_SIZE(splr) 1110 1111#endif /* __i386 */ 1112#endif /* __lint */ 1113 1114 1115 1116/* 1117 * splx - set PIL back to that indicated by the level passed as an argument, 1118 * or to the CPU's base priority, whichever is higher. 1119 * Needs to be fall through to spl to save cycles. 1120 * Algorithm for spl: 1121 * 1122 * turn off interrupts 1123 * 1124 * if (CPU->cpu_base_spl > newipl) 1125 * newipl = CPU->cpu_base_spl; 1126 * oldipl = CPU->cpu_pridata->c_ipl; 1127 * CPU->cpu_pridata->c_ipl = newipl; 1128 * 1129 * /indirectly call function to set spl values (usually setpicmasks) 1130 * setspl(); // load new masks into pics 1131 * 1132 * Be careful not to set priority lower than CPU->cpu_base_pri, 1133 * even though it seems we're raising the priority, it could be set 1134 * higher at any time by an interrupt routine, so we must block interrupts 1135 * and look at CPU->cpu_base_pri 1136 */ 1137#if defined(__lint) 1138 1139/* ARGSUSED */ 1140void 1141splx(int level) 1142{} 1143 1144#else /* __lint */ 1145 1146#if defined(__amd64) 1147 1148 ENTRY(splx) 1149 ALTENTRY(i_ddi_splx) 1150 cli /* disable interrupts */ 1151 LOADCPU(%rcx) 1152 /*FALLTHRU*/ 1153 .align 4 1154spl: 1155 /* 1156 * New priority level is in %edi, cpu struct pointer is in %rcx 1157 */ 1158 GETIPL_NOGS(%eax, %rcx) /* get current ipl */ 1159 cmpl %edi, CPU_BASE_SPL(%rcx) /* if (base spl > new ipl) */ 1160 ja set_to_base_spl /* then use base_spl */ 1161 1162setprilev: 1163 SETIPL_NOGS(%edi, %rcx) /* set new ipl */ 1164 /* 1165 * If we aren't using cr8 to control ipl then we patch this 1166 * with a jump to slow_spl 1167 */ 1168 ALTENTRY(spl_patch) 1169 movq CPU_PRI_DATA(%rcx), %r11 /* get pri data ptr */ 1170 movzb (%r11, %rdi, 1), %rdx /* get apic mask for this ipl */ 1171 movq %rdx, %cr8 /* set new apic priority */ 1172 xorl %edx, %edx 1173 bsrl CPU_SOFTINFO(%rcx), %edx /* fls(cpu->cpu_softinfo.st_pending) */ 1174 cmpl %edi, %edx /* new ipl vs. st_pending */ 1175 jle setsplsti 1176 1177 pushq %rbp 1178 movq %rsp, %rbp 1179 /* stack now 16-byte aligned */ 1180 pushq %rax /* save old spl */ 1181 pushq %rdi /* save new ipl too */ 1182 jmp fakesoftint 1183 1184setsplsti: 1185 nop /* patch this to a sti when a proper setspl routine appears */ 1186 ret 1187 1188 ALTENTRY(slow_spl) 1189 pushq %rbp 1190 movq %rsp, %rbp 1191 /* stack now 16-byte aligned */ 1192 1193 pushq %rax /* save old spl */ 1194 pushq %rdi /* save new ipl too */ 1195 1196 call *setspl(%rip) 1197 1198 LOADCPU(%rcx) 1199 movl CPU_SOFTINFO(%rcx), %eax 1200 orl %eax, %eax 1201 jz slow_setsplsti 1202 1203 bsrl %eax, %edx /* fls(cpu->cpu_softinfo.st_pending) */ 1204 cmpl 0(%rsp), %edx /* new ipl vs. st_pending */ 1205 jg fakesoftint 1206 1207 ALTENTRY(fakesoftint_return) 1208 /* 1209 * enable interrupts 1210 */ 1211slow_setsplsti: 1212 nop /* patch this to a sti when a proper setspl routine appears */ 1213 popq %rdi 1214 popq %rax /* return old ipl */ 1215 leave 1216 ret 1217 SET_SIZE(fakesoftint_return) 1218 1219set_to_base_spl: 1220 movl CPU_BASE_SPL(%rcx), %edi 1221 jmp setprilev 1222 SET_SIZE(spl) 1223 SET_SIZE(i_ddi_splx) 1224 SET_SIZE(splx) 1225 1226#elif defined(__i386) 1227 1228 ENTRY(splx) 1229 ALTENTRY(i_ddi_splx) 1230 cli /* disable interrupts */ 1231 LOADCPU(%ecx) 1232 movl 4(%esp), %edx /* get new spl level */ 1233 /*FALLTHRU*/ 1234 1235 .align 4 1236 ALTENTRY(spl) 1237 /* 1238 * New priority level is in %edx 1239 * (doing this early to avoid an AGI in the next instruction) 1240 */ 1241 GETIPL_NOGS(%eax, %ecx) /* get current ipl */ 1242 cmpl %edx, CPU_BASE_SPL(%ecx) /* if ( base spl > new ipl) */ 1243 ja set_to_base_spl /* then use base_spl */ 1244 1245setprilev: 1246 SETIPL_NOGS(%edx, %ecx) /* set new ipl */ 1247 1248 pushl %eax /* save old ipl */ 1249 pushl %edx /* pass new ipl */ 1250 call *setspl 1251 1252 LOADCPU(%ecx) 1253 movl CPU_SOFTINFO(%ecx), %eax 1254 orl %eax, %eax 1255 jz setsplsti 1256 1257 /* 1258 * Before dashing off, check that setsplsti has been patched. 1259 */ 1260 cmpl $NOP_INSTR, setsplsti 1261 je setsplsti 1262 1263 bsrl %eax, %edx 1264 cmpl 0(%esp), %edx 1265 jg fakesoftint 1266 1267 ALTENTRY(fakesoftint_return) 1268 /* 1269 * enable interrupts 1270 */ 1271setsplsti: 1272 nop /* patch this to a sti when a proper setspl routine appears */ 1273 popl %eax 1274 popl %eax / return old ipl 1275 ret 1276 SET_SIZE(fakesoftint_return) 1277 1278set_to_base_spl: 1279 movl CPU_BASE_SPL(%ecx), %edx 1280 jmp setprilev 1281 SET_SIZE(spl) 1282 SET_SIZE(i_ddi_splx) 1283 SET_SIZE(splx) 1284 1285#endif /* __i386 */ 1286#endif /* __lint */ 1287 1288#if defined(__lint) 1289 1290void 1291install_spl(void) 1292{} 1293 1294#else /* __lint */ 1295 1296#if defined(__amd64) 1297 1298 ENTRY_NP(install_spl) 1299 movq %cr0, %rax 1300 movq %rax, %rdx 1301 movl $_BITNOT(CR0_WP), %ecx 1302 movslq %ecx, %rcx 1303 andq %rcx, %rax /* we don't want to take a fault */ 1304 movq %rax, %cr0 1305 jmp 1f 13061: movb $STI_INSTR, setsplsti(%rip) 1307 movb $STI_INSTR, slow_setsplsti(%rip) 1308 movb $STI_INSTR, setsplhisti(%rip) 1309 movb $STI_INSTR, splr_setsti(%rip) 1310 testl $1, intpri_use_cr8(%rip) /* are using %cr8 ? */ 1311 jz 2f /* no, go patch more */ 1312 movq %rdx, %cr0 1313 ret 13142: 1315 /* 1316 * Patch spl functions to use slow spl method 1317 */ 1318 leaq setsplhi_patch(%rip), %rdi /* get patch point addr */ 1319 leaq slow_setsplhi(%rip), %rax /* jmp target */ 1320 subq %rdi, %rax /* calculate jmp distance */ 1321 subq $2, %rax /* minus size of jmp instr */ 1322 shlq $8, %rax /* construct jmp instr */ 1323 addq $JMP_INSTR, %rax 1324 movw %ax, setsplhi_patch(%rip) /* patch in the jmp */ 1325 leaq spl_patch(%rip), %rdi /* get patch point addr */ 1326 leaq slow_spl(%rip), %rax /* jmp target */ 1327 subq %rdi, %rax /* calculate jmp distance */ 1328 subq $2, %rax /* minus size of jmp instr */ 1329 shlq $8, %rax /* construct jmp instr */ 1330 addq $JMP_INSTR, %rax 1331 movw %ax, spl_patch(%rip) /* patch in the jmp */ 1332 /* 1333 * Ensure %cr8 is zero since we aren't using it 1334 */ 1335 xorl %eax, %eax 1336 movq %rax, %cr8 1337 movq %rdx, %cr0 1338 ret 1339 SET_SIZE(install_spl) 1340 1341#elif defined(__i386) 1342 1343 ENTRY_NP(install_spl) 1344 movl %cr0, %eax 1345 movl %eax, %edx 1346 andl $_BITNOT(CR0_WP), %eax /* we don't want to take a fault */ 1347 movl %eax, %cr0 1348 jmp 1f 13491: movb $STI_INSTR, setsplsti 1350 movb $STI_INSTR, setsplhisti 1351 movb $STI_INSTR, splr_setsti 1352 movl %edx, %cr0 1353 ret 1354 SET_SIZE(install_spl) 1355 1356#endif /* __i386 */ 1357#endif /* __lint */ 1358 1359 1360/* 1361 * Get current processor interrupt level 1362 */ 1363 1364#if defined(__lint) 1365 1366int 1367getpil(void) 1368{ return (0); } 1369 1370#else /* __lint */ 1371 1372#if defined(__amd64) 1373 1374 ENTRY(getpil) 1375 GETIPL(%eax) /* priority level into %eax */ 1376 ret 1377 SET_SIZE(getpil) 1378 1379#elif defined(__i386) 1380 1381 ENTRY(getpil) 1382 GETIPL(%eax) /* priority level into %eax */ 1383 ret 1384 SET_SIZE(getpil) 1385 1386#endif /* __i386 */ 1387#endif /* __lint */ 1388 1389#if defined(__i386) 1390 1391/* 1392 * Read and write the %gs register 1393 */ 1394 1395#if defined(__lint) 1396 1397/*ARGSUSED*/ 1398uint16_t 1399getgs(void) 1400{ return (0); } 1401 1402/*ARGSUSED*/ 1403void 1404setgs(uint16_t sel) 1405{} 1406 1407#else /* __lint */ 1408 1409 ENTRY(getgs) 1410 clr %eax 1411 movw %gs, %ax 1412 ret 1413 SET_SIZE(getgs) 1414 1415 ENTRY(setgs) 1416 movw 4(%esp), %gs 1417 ret 1418 SET_SIZE(setgs) 1419 1420#endif /* __lint */ 1421#endif /* __i386 */ 1422 1423#if defined(__lint) 1424 1425void 1426pc_reset(void) 1427{} 1428 1429#else /* __lint */ 1430 1431 ENTRY(pc_reset) 1432 movw $0x64, %dx 1433 movb $0xfe, %al 1434 outb (%dx) 1435 hlt 1436 /*NOTREACHED*/ 1437 SET_SIZE(pc_reset) 1438 1439#endif /* __lint */ 1440 1441/* 1442 * C callable in and out routines 1443 */ 1444 1445#if defined(__lint) 1446 1447/* ARGSUSED */ 1448void 1449outl(int port_address, uint32_t val) 1450{} 1451 1452#else /* __lint */ 1453 1454#if defined(__amd64) 1455 1456 ENTRY(outl) 1457 movw %di, %dx 1458 movl %esi, %eax 1459 outl (%dx) 1460 ret 1461 SET_SIZE(outl) 1462 1463#elif defined(__i386) 1464 1465 .set PORT, 4 1466 .set VAL, 8 1467 1468 ENTRY(outl) 1469 movw PORT(%esp), %dx 1470 movl VAL(%esp), %eax 1471 outl (%dx) 1472 ret 1473 SET_SIZE(outl) 1474 1475#endif /* __i386 */ 1476#endif /* __lint */ 1477 1478#if defined(__lint) 1479 1480/* ARGSUSED */ 1481void 1482outw(int port_address, uint16_t val) 1483{} 1484 1485#else /* __lint */ 1486 1487#if defined(__amd64) 1488 1489 ENTRY(outw) 1490 movw %di, %dx 1491 movw %si, %ax 1492 D16 outl (%dx) /* XX64 why not outw? */ 1493 ret 1494 SET_SIZE(outw) 1495 1496#elif defined(__i386) 1497 1498 ENTRY(outw) 1499 movw PORT(%esp), %dx 1500 movw VAL(%esp), %ax 1501 D16 outl (%dx) 1502 ret 1503 SET_SIZE(outw) 1504 1505#endif /* __i386 */ 1506#endif /* __lint */ 1507 1508#if defined(__lint) 1509 1510/* ARGSUSED */ 1511void 1512outb(int port_address, uint8_t val) 1513{} 1514 1515#else /* __lint */ 1516 1517#if defined(__amd64) 1518 1519 ENTRY(outb) 1520 movw %di, %dx 1521 movb %sil, %al 1522 outb (%dx) 1523 ret 1524 SET_SIZE(outb) 1525 1526#elif defined(__i386) 1527 1528 ENTRY(outb) 1529 movw PORT(%esp), %dx 1530 movb VAL(%esp), %al 1531 outb (%dx) 1532 ret 1533 SET_SIZE(outb) 1534 1535#endif /* __i386 */ 1536#endif /* __lint */ 1537 1538#if defined(__lint) 1539 1540/* ARGSUSED */ 1541uint32_t 1542inl(int port_address) 1543{ return (0); } 1544 1545#else /* __lint */ 1546 1547#if defined(__amd64) 1548 1549 ENTRY(inl) 1550 xorl %eax, %eax 1551 movw %di, %dx 1552 inl (%dx) 1553 ret 1554 SET_SIZE(inl) 1555 1556#elif defined(__i386) 1557 1558 ENTRY(inl) 1559 movw PORT(%esp), %dx 1560 inl (%dx) 1561 ret 1562 SET_SIZE(inl) 1563 1564#endif /* __i386 */ 1565#endif /* __lint */ 1566 1567#if defined(__lint) 1568 1569/* ARGSUSED */ 1570uint16_t 1571inw(int port_address) 1572{ return (0); } 1573 1574#else /* __lint */ 1575 1576#if defined(__amd64) 1577 1578 ENTRY(inw) 1579 xorl %eax, %eax 1580 movw %di, %dx 1581 D16 inl (%dx) 1582 ret 1583 SET_SIZE(inw) 1584 1585#elif defined(__i386) 1586 1587 ENTRY(inw) 1588 subl %eax, %eax 1589 movw PORT(%esp), %dx 1590 D16 inl (%dx) 1591 ret 1592 SET_SIZE(inw) 1593 1594#endif /* __i386 */ 1595#endif /* __lint */ 1596 1597 1598#if defined(__lint) 1599 1600/* ARGSUSED */ 1601uint8_t 1602inb(int port_address) 1603{ return (0); } 1604 1605#else /* __lint */ 1606 1607#if defined(__amd64) 1608 1609 ENTRY(inb) 1610 xorl %eax, %eax 1611 movw %di, %dx 1612 inb (%dx) 1613 ret 1614 SET_SIZE(inb) 1615 1616#elif defined(__i386) 1617 1618 ENTRY(inb) 1619 subl %eax, %eax 1620 movw PORT(%esp), %dx 1621 inb (%dx) 1622 ret 1623 SET_SIZE(inb) 1624 1625#endif /* __i386 */ 1626#endif /* __lint */ 1627 1628 1629#if defined(__lint) 1630 1631/* ARGSUSED */ 1632void 1633repoutsw(int port, uint16_t *addr, int cnt) 1634{} 1635 1636#else /* __lint */ 1637 1638#if defined(__amd64) 1639 1640 ENTRY(repoutsw) 1641 movl %edx, %ecx 1642 movw %di, %dx 1643 rep 1644 D16 outsl 1645 ret 1646 SET_SIZE(repoutsw) 1647 1648#elif defined(__i386) 1649 1650 /* 1651 * The arguments and saved registers are on the stack in the 1652 * following order: 1653 * | cnt | +16 1654 * | *addr | +12 1655 * | port | +8 1656 * | eip | +4 1657 * | esi | <-- %esp 1658 * If additional values are pushed onto the stack, make sure 1659 * to adjust the following constants accordingly. 1660 */ 1661 .set PORT, 8 1662 .set ADDR, 12 1663 .set COUNT, 16 1664 1665 ENTRY(repoutsw) 1666 pushl %esi 1667 movl PORT(%esp), %edx 1668 movl ADDR(%esp), %esi 1669 movl COUNT(%esp), %ecx 1670 rep 1671 D16 outsl 1672 popl %esi 1673 ret 1674 SET_SIZE(repoutsw) 1675 1676#endif /* __i386 */ 1677#endif /* __lint */ 1678 1679 1680#if defined(__lint) 1681 1682/* ARGSUSED */ 1683void 1684repinsw(int port_addr, uint16_t *addr, int cnt) 1685{} 1686 1687#else /* __lint */ 1688 1689#if defined(__amd64) 1690 1691 ENTRY(repinsw) 1692 movl %edx, %ecx 1693 movw %di, %dx 1694 rep 1695 D16 insl 1696 ret 1697 SET_SIZE(repinsw) 1698 1699#elif defined(__i386) 1700 1701 ENTRY(repinsw) 1702 pushl %edi 1703 movl PORT(%esp), %edx 1704 movl ADDR(%esp), %edi 1705 movl COUNT(%esp), %ecx 1706 rep 1707 D16 insl 1708 popl %edi 1709 ret 1710 SET_SIZE(repinsw) 1711 1712#endif /* __i386 */ 1713#endif /* __lint */ 1714 1715 1716#if defined(__lint) 1717 1718/* ARGSUSED */ 1719void 1720repinsb(int port, uint8_t *addr, int count) 1721{} 1722 1723#else /* __lint */ 1724 1725#if defined(__amd64) 1726 1727 ENTRY(repinsb) 1728 movl %edx, %ecx 1729 movw %di, %dx 1730 movq %rsi, %rdi 1731 rep 1732 insb 1733 ret 1734 SET_SIZE(repinsb) 1735 1736#elif defined(__i386) 1737 1738 /* 1739 * The arguments and saved registers are on the stack in the 1740 * following order: 1741 * | cnt | +16 1742 * | *addr | +12 1743 * | port | +8 1744 * | eip | +4 1745 * | esi | <-- %esp 1746 * If additional values are pushed onto the stack, make sure 1747 * to adjust the following constants accordingly. 1748 */ 1749 .set IO_PORT, 8 1750 .set IO_ADDR, 12 1751 .set IO_COUNT, 16 1752 1753 ENTRY(repinsb) 1754 pushl %edi 1755 movl IO_ADDR(%esp), %edi 1756 movl IO_COUNT(%esp), %ecx 1757 movl IO_PORT(%esp), %edx 1758 rep 1759 insb 1760 popl %edi 1761 ret 1762 SET_SIZE(repinsb) 1763 1764#endif /* __i386 */ 1765#endif /* __lint */ 1766 1767 1768/* 1769 * Input a stream of 32-bit words. 1770 * NOTE: count is a DWORD count. 1771 */ 1772#if defined(__lint) 1773 1774/* ARGSUSED */ 1775void 1776repinsd(int port, uint32_t *addr, int count) 1777{} 1778 1779#else /* __lint */ 1780 1781#if defined(__amd64) 1782 1783 ENTRY(repinsd) 1784 movl %edx, %ecx 1785 movw %di, %dx 1786 movq %rsi, %rdi 1787 rep 1788 insl 1789 ret 1790 SET_SIZE(repinsd) 1791 1792#elif defined(__i386) 1793 1794 ENTRY(repinsd) 1795 pushl %edi 1796 movl IO_ADDR(%esp), %edi 1797 movl IO_COUNT(%esp), %ecx 1798 movl IO_PORT(%esp), %edx 1799 rep 1800 insl 1801 popl %edi 1802 ret 1803 SET_SIZE(repinsd) 1804 1805#endif /* __i386 */ 1806#endif /* __lint */ 1807 1808/* 1809 * Output a stream of bytes 1810 * NOTE: count is a byte count 1811 */ 1812#if defined(__lint) 1813 1814/* ARGSUSED */ 1815void 1816repoutsb(int port, uint8_t *addr, int count) 1817{} 1818 1819#else /* __lint */ 1820 1821#if defined(__amd64) 1822 1823 ENTRY(repoutsb) 1824 movl %edx, %ecx 1825 movw %di, %dx 1826 rep 1827 outsb 1828 ret 1829 SET_SIZE(repoutsb) 1830 1831#elif defined(__i386) 1832 1833 ENTRY(repoutsb) 1834 pushl %esi 1835 movl IO_ADDR(%esp), %esi 1836 movl IO_COUNT(%esp), %ecx 1837 movl IO_PORT(%esp), %edx 1838 rep 1839 outsb 1840 popl %esi 1841 ret 1842 SET_SIZE(repoutsb) 1843 1844#endif /* __i386 */ 1845#endif /* __lint */ 1846 1847/* 1848 * Output a stream of 32-bit words 1849 * NOTE: count is a DWORD count 1850 */ 1851#if defined(__lint) 1852 1853/* ARGSUSED */ 1854void 1855repoutsd(int port, uint32_t *addr, int count) 1856{} 1857 1858#else /* __lint */ 1859 1860#if defined(__amd64) 1861 1862 ENTRY(repoutsd) 1863 movl %edx, %ecx 1864 movw %di, %dx 1865 rep 1866 outsl 1867 ret 1868 SET_SIZE(repoutsd) 1869 1870#elif defined(__i386) 1871 1872 ENTRY(repoutsd) 1873 pushl %esi 1874 movl IO_ADDR(%esp), %esi 1875 movl IO_COUNT(%esp), %ecx 1876 movl IO_PORT(%esp), %edx 1877 rep 1878 outsl 1879 popl %esi 1880 ret 1881 SET_SIZE(repoutsd) 1882 1883#endif /* __i386 */ 1884#endif /* __lint */ 1885 1886/* 1887 * void int20(void) 1888 */ 1889 1890#if defined(__lint) 1891 1892void 1893int20(void) 1894{} 1895 1896#else /* __lint */ 1897 1898 ENTRY(int20) 1899 movl boothowto, %eax 1900 andl $RB_DEBUG, %eax 1901 jz 1f 1902 1903 int $20 19041: 1905 ret 1906 SET_SIZE(int20) 1907 1908#endif /* __lint */ 1909 1910#if defined(__lint) 1911 1912/* ARGSUSED */ 1913int 1914scanc(size_t size, uchar_t *cp, uchar_t *table, uchar_t mask) 1915{ return (0); } 1916 1917#else /* __lint */ 1918 1919#if defined(__amd64) 1920 1921 ENTRY(scanc) 1922 /* rdi == size */ 1923 /* rsi == cp */ 1924 /* rdx == table */ 1925 /* rcx == mask */ 1926 addq %rsi, %rdi /* end = &cp[size] */ 1927.scanloop: 1928 cmpq %rdi, %rsi /* while (cp < end */ 1929 jnb .scandone 1930 movzbq (%rsi), %r8 /* %r8 = *cp */ 1931 incq %rsi /* cp++ */ 1932 testb %cl, (%r8, %rdx) 1933 jz .scanloop /* && (table[*cp] & mask) == 0) */ 1934 decq %rsi /* (fix post-increment) */ 1935.scandone: 1936 movl %edi, %eax 1937 subl %esi, %eax /* return (end - cp) */ 1938 ret 1939 SET_SIZE(scanc) 1940 1941#elif defined(__i386) 1942 1943 ENTRY(scanc) 1944 pushl %edi 1945 pushl %esi 1946 movb 24(%esp), %cl /* mask = %cl */ 1947 movl 16(%esp), %esi /* cp = %esi */ 1948 movl 20(%esp), %edx /* table = %edx */ 1949 movl %esi, %edi 1950 addl 12(%esp), %edi /* end = &cp[size]; */ 1951.scanloop: 1952 cmpl %edi, %esi /* while (cp < end */ 1953 jnb .scandone 1954 movzbl (%esi), %eax /* %al = *cp */ 1955 incl %esi /* cp++ */ 1956 movb (%edx, %eax), %al /* %al = table[*cp] */ 1957 testb %al, %cl 1958 jz .scanloop /* && (table[*cp] & mask) == 0) */ 1959 dec %esi /* post-incremented */ 1960.scandone: 1961 movl %edi, %eax 1962 subl %esi, %eax /* return (end - cp) */ 1963 popl %esi 1964 popl %edi 1965 ret 1966 SET_SIZE(scanc) 1967 1968#endif /* __i386 */ 1969#endif /* __lint */ 1970 1971/* 1972 * Replacement functions for ones that are normally inlined. 1973 * In addition to the copy in i86.il, they are defined here just in case. 1974 */ 1975 1976#if defined(__lint) 1977 1978int 1979intr_clear(void) 1980{ return 0; } 1981 1982int 1983clear_int_flag(void) 1984{ return 0; } 1985 1986#else /* __lint */ 1987 1988#if defined(__amd64) 1989 1990 ENTRY(intr_clear) 1991 ENTRY(clear_int_flag) 1992 pushfq 1993 cli 1994 popq %rax 1995 ret 1996 SET_SIZE(clear_int_flag) 1997 SET_SIZE(intr_clear) 1998 1999#elif defined(__i386) 2000 2001 ENTRY(intr_clear) 2002 ENTRY(clear_int_flag) 2003 pushfl 2004 cli 2005 popl %eax 2006 ret 2007 SET_SIZE(clear_int_flag) 2008 SET_SIZE(intr_clear) 2009 2010#endif /* __i386 */ 2011#endif /* __lint */ 2012 2013#if defined(__lint) 2014 2015struct cpu * 2016curcpup(void) 2017{ return 0; } 2018 2019#else /* __lint */ 2020 2021#if defined(__amd64) 2022 2023 ENTRY(curcpup) 2024 movq %gs:CPU_SELF, %rax 2025 ret 2026 SET_SIZE(curcpup) 2027 2028#elif defined(__i386) 2029 2030 ENTRY(curcpup) 2031 movl %gs:CPU_SELF, %eax 2032 ret 2033 SET_SIZE(curcpup) 2034 2035#endif /* __i386 */ 2036#endif /* __lint */ 2037 2038#if defined(__lint) 2039 2040/* ARGSUSED */ 2041uint32_t 2042htonl(uint32_t i) 2043{ return (0); } 2044 2045/* ARGSUSED */ 2046uint32_t 2047ntohl(uint32_t i) 2048{ return (0); } 2049 2050#else /* __lint */ 2051 2052#if defined(__amd64) 2053 2054 /* XX64 there must be shorter sequences for this */ 2055 ENTRY(htonl) 2056 ALTENTRY(ntohl) 2057 movl %edi, %eax 2058 bswap %eax 2059 ret 2060 SET_SIZE(ntohl) 2061 SET_SIZE(htonl) 2062 2063#elif defined(__i386) 2064 2065 ENTRY(htonl) 2066 ALTENTRY(ntohl) 2067 movl 4(%esp), %eax 2068 bswap %eax 2069 ret 2070 SET_SIZE(ntohl) 2071 SET_SIZE(htonl) 2072 2073#endif /* __i386 */ 2074#endif /* __lint */ 2075 2076#if defined(__lint) 2077 2078/* ARGSUSED */ 2079uint16_t 2080htons(uint16_t i) 2081{ return (0); } 2082 2083/* ARGSUSED */ 2084uint16_t 2085ntohs(uint16_t i) 2086{ return (0); } 2087 2088 2089#else /* __lint */ 2090 2091#if defined(__amd64) 2092 2093 /* XX64 there must be better sequences for this */ 2094 ENTRY(htons) 2095 ALTENTRY(ntohs) 2096 movl %edi, %eax 2097 bswap %eax 2098 shrl $16, %eax 2099 ret 2100 SET_SIZE(ntohs) 2101 SET_SIZE(htons) 2102 2103#elif defined(__i386) 2104 2105 ENTRY(htons) 2106 ALTENTRY(ntohs) 2107 movl 4(%esp), %eax 2108 bswap %eax 2109 shrl $16, %eax 2110 ret 2111 SET_SIZE(ntohs) 2112 SET_SIZE(htons) 2113 2114#endif /* __i386 */ 2115#endif /* __lint */ 2116 2117 2118#if defined(__lint) 2119 2120/* ARGSUSED */ 2121void 2122intr_restore(uint_t i) 2123{ return; } 2124 2125/* ARGSUSED */ 2126void 2127restore_int_flag(int i) 2128{ return; } 2129 2130#else /* __lint */ 2131 2132#if defined(__amd64) 2133 2134 ENTRY(intr_restore) 2135 ENTRY(restore_int_flag) 2136 pushq %rdi 2137 popfq 2138 ret 2139 SET_SIZE(restore_int_flag) 2140 SET_SIZE(intr_restore) 2141 2142#elif defined(__i386) 2143 2144 ENTRY(intr_restore) 2145 ENTRY(restore_int_flag) 2146 pushl 4(%esp) 2147 popfl 2148 ret 2149 SET_SIZE(restore_int_flag) 2150 SET_SIZE(intr_restore) 2151 2152#endif /* __i386 */ 2153#endif /* __lint */ 2154 2155#if defined(__lint) 2156 2157void 2158sti(void) 2159{} 2160 2161#else /* __lint */ 2162 2163 ENTRY(sti) 2164 sti 2165 ret 2166 SET_SIZE(sti) 2167 2168#endif /* __lint */ 2169 2170#if defined(__lint) 2171 2172dtrace_icookie_t 2173dtrace_interrupt_disable(void) 2174{ return (0); } 2175 2176#else /* __lint */ 2177 2178#if defined(__amd64) 2179 2180 ENTRY(dtrace_interrupt_disable) 2181 pushfq 2182 popq %rax 2183 cli 2184 ret 2185 SET_SIZE(dtrace_interrupt_disable) 2186 2187#elif defined(__i386) 2188 2189 ENTRY(dtrace_interrupt_disable) 2190 pushfl 2191 popl %eax 2192 cli 2193 ret 2194 SET_SIZE(dtrace_interrupt_disable) 2195 2196#endif /* __i386 */ 2197#endif /* __lint */ 2198 2199#if defined(__lint) 2200 2201/*ARGSUSED*/ 2202void 2203dtrace_interrupt_enable(dtrace_icookie_t cookie) 2204{} 2205 2206#else /* __lint */ 2207 2208#if defined(__amd64) 2209 2210 ENTRY(dtrace_interrupt_enable) 2211 pushq %rdi 2212 popfq 2213 ret 2214 SET_SIZE(dtrace_interrupt_enable) 2215 2216#elif defined(__i386) 2217 2218 ENTRY(dtrace_interrupt_enable) 2219 movl 4(%esp), %eax 2220 pushl %eax 2221 popfl 2222 ret 2223 SET_SIZE(dtrace_interrupt_enable) 2224 2225#endif /* __i386 */ 2226#endif /* __lint */ 2227 2228 2229#if defined(lint) 2230 2231void 2232dtrace_membar_producer(void) 2233{} 2234 2235void 2236dtrace_membar_consumer(void) 2237{} 2238 2239#else /* __lint */ 2240 2241 ENTRY(dtrace_membar_producer) 2242 ret 2243 SET_SIZE(dtrace_membar_producer) 2244 2245 ENTRY(dtrace_membar_consumer) 2246 ret 2247 SET_SIZE(dtrace_membar_consumer) 2248 2249#endif /* __lint */ 2250 2251#if defined(__lint) 2252 2253kthread_id_t 2254threadp(void) 2255{ return ((kthread_id_t)0); } 2256 2257#else /* __lint */ 2258 2259#if defined(__amd64) 2260 2261 ENTRY(threadp) 2262 movq %gs:CPU_THREAD, %rax 2263 ret 2264 SET_SIZE(threadp) 2265 2266#elif defined(__i386) 2267 2268 ENTRY(threadp) 2269 movl %gs:CPU_THREAD, %eax 2270 ret 2271 SET_SIZE(threadp) 2272 2273#endif /* __i386 */ 2274#endif /* __lint */ 2275 2276/* 2277 * Checksum routine for Internet Protocol Headers 2278 */ 2279 2280#if defined(__lint) 2281 2282/* ARGSUSED */ 2283unsigned int 2284ip_ocsum( 2285 ushort_t *address, /* ptr to 1st message buffer */ 2286 int halfword_count, /* length of data */ 2287 unsigned int sum) /* partial checksum */ 2288{ 2289 int i; 2290 unsigned int psum = 0; /* partial sum */ 2291 2292 for (i = 0; i < halfword_count; i++, address++) { 2293 psum += *address; 2294 } 2295 2296 while ((psum >> 16) != 0) { 2297 psum = (psum & 0xffff) + (psum >> 16); 2298 } 2299 2300 psum += sum; 2301 2302 while ((psum >> 16) != 0) { 2303 psum = (psum & 0xffff) + (psum >> 16); 2304 } 2305 2306 return (psum); 2307} 2308 2309#else /* __lint */ 2310 2311#if defined(__amd64) 2312 2313 ENTRY(ip_ocsum) 2314 pushq %rbp 2315 movq %rsp, %rbp 2316#ifdef DEBUG 2317 movq kernelbase(%rip), %rax 2318 cmpq %rax, %rdi 2319 jnb 1f 2320 xorl %eax, %eax 2321 movq %rdi, %rsi 2322 leaq .ip_ocsum_panic_msg(%rip), %rdi 2323 call panic 2324 /*NOTREACHED*/ 2325.ip_ocsum_panic_msg: 2326 .string "ip_ocsum: address 0x%p below kernelbase\n" 23271: 2328#endif 2329 movl %esi, %ecx /* halfword_count */ 2330 movq %rdi, %rsi /* address */ 2331 /* partial sum in %edx */ 2332 xorl %eax, %eax 2333 testl %ecx, %ecx 2334 jz .ip_ocsum_done 2335 testq $3, %rsi 2336 jnz .ip_csum_notaligned 2337.ip_csum_aligned: /* XX64 opportunities for 8-byte operations? */ 2338.next_iter: 2339 /* XX64 opportunities for prefetch? */ 2340 /* XX64 compute csum with 64 bit quantities? */ 2341 subl $32, %ecx 2342 jl .less_than_32 2343 2344 addl 0(%rsi), %edx 2345.only60: 2346 adcl 4(%rsi), %eax 2347.only56: 2348 adcl 8(%rsi), %edx 2349.only52: 2350 adcl 12(%rsi), %eax 2351.only48: 2352 adcl 16(%rsi), %edx 2353.only44: 2354 adcl 20(%rsi), %eax 2355.only40: 2356 adcl 24(%rsi), %edx 2357.only36: 2358 adcl 28(%rsi), %eax 2359.only32: 2360 adcl 32(%rsi), %edx 2361.only28: 2362 adcl 36(%rsi), %eax 2363.only24: 2364 adcl 40(%rsi), %edx 2365.only20: 2366 adcl 44(%rsi), %eax 2367.only16: 2368 adcl 48(%rsi), %edx 2369.only12: 2370 adcl 52(%rsi), %eax 2371.only8: 2372 adcl 56(%rsi), %edx 2373.only4: 2374 adcl 60(%rsi), %eax /* could be adding -1 and -1 with a carry */ 2375.only0: 2376 adcl $0, %eax /* could be adding -1 in eax with a carry */ 2377 adcl $0, %eax 2378 2379 addq $64, %rsi 2380 testl %ecx, %ecx 2381 jnz .next_iter 2382 2383.ip_ocsum_done: 2384 addl %eax, %edx 2385 adcl $0, %edx 2386 movl %edx, %eax /* form a 16 bit checksum by */ 2387 shrl $16, %eax /* adding two halves of 32 bit checksum */ 2388 addw %dx, %ax 2389 adcw $0, %ax 2390 andl $0xffff, %eax 2391 leave 2392 ret 2393 2394.ip_csum_notaligned: 2395 xorl %edi, %edi 2396 movw (%rsi), %di 2397 addl %edi, %edx 2398 adcl $0, %edx 2399 addq $2, %rsi 2400 decl %ecx 2401 jmp .ip_csum_aligned 2402 2403.less_than_32: 2404 addl $32, %ecx 2405 testl $1, %ecx 2406 jz .size_aligned 2407 andl $0xfe, %ecx 2408 movzwl (%rsi, %rcx, 2), %edi 2409 addl %edi, %edx 2410 adcl $0, %edx 2411.size_aligned: 2412 movl %ecx, %edi 2413 shrl $1, %ecx 2414 shl $1, %edi 2415 subq $64, %rdi 2416 addq %rdi, %rsi 2417 leaq .ip_ocsum_jmptbl(%rip), %rdi 2418 leaq (%rdi, %rcx, 8), %rdi 2419 xorl %ecx, %ecx 2420 clc 2421 jmp *(%rdi) 2422 2423 .align 8 2424.ip_ocsum_jmptbl: 2425 .quad .only0, .only4, .only8, .only12, .only16, .only20 2426 .quad .only24, .only28, .only32, .only36, .only40, .only44 2427 .quad .only48, .only52, .only56, .only60 2428 SET_SIZE(ip_ocsum) 2429 2430#elif defined(__i386) 2431 2432 ENTRY(ip_ocsum) 2433 pushl %ebp 2434 movl %esp, %ebp 2435 pushl %ebx 2436 pushl %esi 2437 pushl %edi 2438 movl 12(%ebp), %ecx /* count of half words */ 2439 movl 16(%ebp), %edx /* partial checksum */ 2440 movl 8(%ebp), %esi 2441 xorl %eax, %eax 2442 testl %ecx, %ecx 2443 jz .ip_ocsum_done 2444 2445 testl $3, %esi 2446 jnz .ip_csum_notaligned 2447.ip_csum_aligned: 2448.next_iter: 2449 subl $32, %ecx 2450 jl .less_than_32 2451 2452 addl 0(%esi), %edx 2453.only60: 2454 adcl 4(%esi), %eax 2455.only56: 2456 adcl 8(%esi), %edx 2457.only52: 2458 adcl 12(%esi), %eax 2459.only48: 2460 adcl 16(%esi), %edx 2461.only44: 2462 adcl 20(%esi), %eax 2463.only40: 2464 adcl 24(%esi), %edx 2465.only36: 2466 adcl 28(%esi), %eax 2467.only32: 2468 adcl 32(%esi), %edx 2469.only28: 2470 adcl 36(%esi), %eax 2471.only24: 2472 adcl 40(%esi), %edx 2473.only20: 2474 adcl 44(%esi), %eax 2475.only16: 2476 adcl 48(%esi), %edx 2477.only12: 2478 adcl 52(%esi), %eax 2479.only8: 2480 adcl 56(%esi), %edx 2481.only4: 2482 adcl 60(%esi), %eax /* We could be adding -1 and -1 with a carry */ 2483.only0: 2484 adcl $0, %eax /* we could be adding -1 in eax with a carry */ 2485 adcl $0, %eax 2486 2487 addl $64, %esi 2488 andl %ecx, %ecx 2489 jnz .next_iter 2490 2491.ip_ocsum_done: 2492 addl %eax, %edx 2493 adcl $0, %edx 2494 movl %edx, %eax /* form a 16 bit checksum by */ 2495 shrl $16, %eax /* adding two halves of 32 bit checksum */ 2496 addw %dx, %ax 2497 adcw $0, %ax 2498 andl $0xffff, %eax 2499 popl %edi /* restore registers */ 2500 popl %esi 2501 popl %ebx 2502 leave 2503 ret 2504 2505.ip_csum_notaligned: 2506 xorl %edi, %edi 2507 movw (%esi), %di 2508 addl %edi, %edx 2509 adcl $0, %edx 2510 addl $2, %esi 2511 decl %ecx 2512 jmp .ip_csum_aligned 2513 2514.less_than_32: 2515 addl $32, %ecx 2516 testl $1, %ecx 2517 jz .size_aligned 2518 andl $0xfe, %ecx 2519 movzwl (%esi, %ecx, 2), %edi 2520 addl %edi, %edx 2521 adcl $0, %edx 2522.size_aligned: 2523 movl %ecx, %edi 2524 shrl $1, %ecx 2525 shl $1, %edi 2526 subl $64, %edi 2527 addl %edi, %esi 2528 movl $.ip_ocsum_jmptbl, %edi 2529 lea (%edi, %ecx, 4), %edi 2530 xorl %ecx, %ecx 2531 clc 2532 jmp *(%edi) 2533 SET_SIZE(ip_ocsum) 2534 2535 .data 2536 .align 4 2537 2538.ip_ocsum_jmptbl: 2539 .long .only0, .only4, .only8, .only12, .only16, .only20 2540 .long .only24, .only28, .only32, .only36, .only40, .only44 2541 .long .only48, .only52, .only56, .only60 2542 2543 2544#endif /* __i386 */ 2545#endif /* __lint */ 2546 2547/* 2548 * multiply two long numbers and yield a u_longlong_t result, callable from C. 2549 * Provided to manipulate hrtime_t values. 2550 */ 2551#if defined(__lint) 2552 2553/* result = a * b; */ 2554 2555/* ARGSUSED */ 2556unsigned long long 2557mul32(uint_t a, uint_t b) 2558{ return (0); } 2559 2560#else /* __lint */ 2561 2562#if defined(__amd64) 2563 2564 ENTRY(mul32) 2565 xorl %edx, %edx /* XX64 joe, paranoia? */ 2566 movl %edi, %eax 2567 mull %esi 2568 shlq $32, %rdx 2569 orq %rdx, %rax 2570 ret 2571 SET_SIZE(mul32) 2572 2573#elif defined(__i386) 2574 2575 ENTRY(mul32) 2576 movl 8(%esp), %eax 2577 movl 4(%esp), %ecx 2578 mull %ecx 2579 ret 2580 SET_SIZE(mul32) 2581 2582#endif /* __i386 */ 2583#endif /* __lint */ 2584 2585#if defined(notused) 2586#if defined(__lint) 2587/* ARGSUSED */ 2588void 2589load_pte64(uint64_t *pte, uint64_t pte_value) 2590{} 2591#else /* __lint */ 2592 .globl load_pte64 2593load_pte64: 2594 movl 4(%esp), %eax 2595 movl 8(%esp), %ecx 2596 movl 12(%esp), %edx 2597 movl %edx, 4(%eax) 2598 movl %ecx, (%eax) 2599 ret 2600#endif /* __lint */ 2601#endif /* notused */ 2602 2603#if defined(__lint) 2604 2605/*ARGSUSED*/ 2606void 2607scan_memory(caddr_t addr, size_t size) 2608{} 2609 2610#else /* __lint */ 2611 2612#if defined(__amd64) 2613 2614 ENTRY(scan_memory) 2615 shrq $3, %rsi /* convert %rsi from byte to quadword count */ 2616 jz .scanm_done 2617 movq %rsi, %rcx /* move count into rep control register */ 2618 movq %rdi, %rsi /* move addr into lodsq control reg. */ 2619 rep lodsq /* scan the memory range */ 2620.scanm_done: 2621 ret 2622 SET_SIZE(scan_memory) 2623 2624#elif defined(__i386) 2625 2626 ENTRY(scan_memory) 2627 pushl %ecx 2628 pushl %esi 2629 movl 16(%esp), %ecx /* move 2nd arg into rep control register */ 2630 shrl $2, %ecx /* convert from byte count to word count */ 2631 jz .scanm_done 2632 movl 12(%esp), %esi /* move 1st arg into lodsw control register */ 2633 .byte 0xf3 /* rep prefix. lame assembler. sigh. */ 2634 lodsl 2635.scanm_done: 2636 popl %esi 2637 popl %ecx 2638 ret 2639 SET_SIZE(scan_memory) 2640 2641#endif /* __i386 */ 2642#endif /* __lint */ 2643 2644 2645#if defined(__lint) 2646 2647/*ARGSUSED */ 2648int 2649lowbit(ulong_t i) 2650{ return (0); } 2651 2652#else /* __lint */ 2653 2654#if defined(__amd64) 2655 2656 ENTRY(lowbit) 2657 movl $-1, %eax 2658 bsfq %rdi, %rax 2659 incl %eax 2660 ret 2661 SET_SIZE(lowbit) 2662 2663#elif defined(__i386) 2664 2665 ENTRY(lowbit) 2666 movl $-1, %eax 2667 bsfl 4(%esp), %eax 2668 incl %eax 2669 ret 2670 SET_SIZE(lowbit) 2671 2672#endif /* __i386 */ 2673#endif /* __lint */ 2674 2675#if defined(__lint) 2676 2677/*ARGSUSED*/ 2678int 2679highbit(ulong_t i) 2680{ return (0); } 2681 2682#else /* __lint */ 2683 2684#if defined(__amd64) 2685 2686 ENTRY(highbit) 2687 movl $-1, %eax 2688 bsrq %rdi, %rax 2689 incl %eax 2690 ret 2691 SET_SIZE(highbit) 2692 2693#elif defined(__i386) 2694 2695 ENTRY(highbit) 2696 movl $-1, %eax 2697 bsrl 4(%esp), %eax 2698 incl %eax 2699 ret 2700 SET_SIZE(highbit) 2701 2702#endif /* __i386 */ 2703#endif /* __lint */ 2704 2705#if defined(__lint) 2706 2707/*ARGSUSED*/ 2708uint64_t 2709rdmsr(uint_t r, uint64_t *mtr) 2710{ return (0); } 2711 2712/*ARGSUSED*/ 2713void 2714wrmsr(uint_t r, const uint64_t *mtr) 2715{} 2716 2717void 2718invalidate_cache(void) 2719{} 2720 2721#else /* __lint */ 2722 2723#if defined(__amd64) 2724 2725 ENTRY(rdmsr) 2726 movl %edi, %ecx 2727 rdmsr 2728 movl %eax, (%rsi) 2729 movl %edx, 4(%rsi) 2730 shlq $32, %rdx 2731 orq %rdx, %rax 2732 ret 2733 SET_SIZE(rdmsr) 2734 2735 ENTRY(wrmsr) 2736 movl (%rsi), %eax 2737 movl 4(%rsi), %edx 2738 movl %edi, %ecx 2739 wrmsr 2740 ret 2741 SET_SIZE(wrmsr) 2742 2743#elif defined(__i386) 2744 2745 ENTRY(rdmsr) 2746 movl 4(%esp), %ecx 2747 rdmsr 2748 movl 8(%esp), %ecx 2749 movl %eax, (%ecx) 2750 movl %edx, 4(%ecx) 2751 ret 2752 SET_SIZE(rdmsr) 2753 2754 ENTRY(wrmsr) 2755 movl 8(%esp), %ecx 2756 movl (%ecx), %eax 2757 movl 4(%ecx), %edx 2758 movl 4(%esp), %ecx 2759 wrmsr 2760 ret 2761 SET_SIZE(wrmsr) 2762 2763#endif /* __i386 */ 2764 2765 ENTRY(invalidate_cache) 2766 wbinvd 2767 ret 2768 SET_SIZE(invalidate_cache) 2769 2770#endif /* __lint */ 2771 2772#if defined(__lint) 2773 2774/*ARGSUSED*/ 2775void getcregs(struct cregs *crp) 2776{} 2777 2778#else /* __lint */ 2779 2780#if defined(__amd64) 2781 2782#define GETMSR(r, off, d) \ 2783 movl $r, %ecx; \ 2784 rdmsr; \ 2785 movl %eax, off(d); \ 2786 movl %edx, off+4(d) 2787 2788 ENTRY_NP(getcregs) 2789 xorl %eax, %eax 2790 movq %rax, CREG_GDT+8(%rdi) 2791 sgdt CREG_GDT(%rdi) /* 10 bytes */ 2792 movq %rax, CREG_IDT+8(%rdi) 2793 sidt CREG_IDT(%rdi) /* 10 bytes */ 2794 movq %rax, CREG_LDT(%rdi) 2795 sldt CREG_LDT(%rdi) /* 2 bytes */ 2796 movq %rax, CREG_TASKR(%rdi) 2797 str CREG_TASKR(%rdi) /* 2 bytes */ 2798 movq %cr0, %rax 2799 movq %rax, CREG_CR0(%rdi) /* cr0 */ 2800 movq %cr2, %rax 2801 movq %rax, CREG_CR2(%rdi) /* cr2 */ 2802 movq %cr3, %rax 2803 movq %rax, CREG_CR3(%rdi) /* cr3 */ 2804 movq %cr4, %rax 2805 movq %rax, CREG_CR8(%rdi) /* cr4 */ 2806 movq %cr8, %rax 2807 movq %rax, CREG_CR8(%rdi) /* cr8 */ 2808 GETMSR(MSR_AMD_KGSBASE, CREG_KGSBASE, %rdi) 2809 GETMSR(MSR_AMD_EFER, CREG_EFER, %rdi) 2810 SET_SIZE(getcregs) 2811 2812#undef GETMSR 2813 2814#elif defined(__i386) 2815 2816 ENTRY_NP(getcregs) 2817 movl 4(%esp), %edx 2818 movw $0, CREG_GDT+6(%edx) 2819 movw $0, CREG_IDT+6(%edx) 2820 sgdt CREG_GDT(%edx) /* gdt */ 2821 sidt CREG_IDT(%edx) /* idt */ 2822 sldt CREG_LDT(%edx) /* ldt */ 2823 str CREG_TASKR(%edx) /* task */ 2824 movl %cr0, %eax 2825 movl %eax, CREG_CR0(%edx) /* cr0 */ 2826 movl %cr2, %eax 2827 movl %eax, CREG_CR2(%edx) /* cr2 */ 2828 movl %cr3, %eax 2829 movl %eax, CREG_CR3(%edx) /* cr3 */ 2830 testl $X86_LARGEPAGE, x86_feature 2831 jz .nocr4 2832 movl %cr4, %eax 2833 movl %eax, CREG_CR4(%edx) /* cr4 */ 2834 jmp .skip 2835.nocr4: 2836 movl $0, CREG_CR4(%edx) 2837.skip: 2838 ret 2839 SET_SIZE(getcregs) 2840 2841#endif /* __i386 */ 2842#endif /* __lint */ 2843 2844 2845/* 2846 * A panic trigger is a word which is updated atomically and can only be set 2847 * once. We atomically store 0xDEFACEDD and load the old value. If the 2848 * previous value was 0, we succeed and return 1; otherwise return 0. 2849 * This allows a partially corrupt trigger to still trigger correctly. DTrace 2850 * has its own version of this function to allow it to panic correctly from 2851 * probe context. 2852 */ 2853#if defined(__lint) 2854 2855/*ARGSUSED*/ 2856int 2857panic_trigger(int *tp) 2858{ return (0); } 2859 2860/*ARGSUSED*/ 2861int 2862dtrace_panic_trigger(int *tp) 2863{ return (0); } 2864 2865#else /* __lint */ 2866 2867#if defined(__amd64) 2868 2869 ENTRY_NP(panic_trigger) 2870 xorl %eax, %eax 2871 movl $0xdefacedd, %edx 2872 lock 2873 xchgl %edx, (%rdi) 2874 cmpl $0, %edx 2875 je 0f 2876 movl $0, %eax 2877 ret 28780: movl $1, %eax 2879 ret 2880 SET_SIZE(panic_trigger) 2881 2882 ENTRY_NP(dtrace_panic_trigger) 2883 xorl %eax, %eax 2884 movl $0xdefacedd, %edx 2885 lock 2886 xchgl %edx, (%rdi) 2887 cmpl $0, %edx 2888 je 0f 2889 movl $0, %eax 2890 ret 28910: movl $1, %eax 2892 ret 2893 SET_SIZE(dtrace_panic_trigger) 2894 2895#elif defined(__i386) 2896 2897 ENTRY_NP(panic_trigger) 2898 movl 4(%esp), %edx / %edx = address of trigger 2899 movl $0xdefacedd, %eax / %eax = 0xdefacedd 2900 lock / assert lock 2901 xchgl %eax, (%edx) / exchange %eax and the trigger 2902 cmpl $0, %eax / if (%eax == 0x0) 2903 je 0f / return (1); 2904 movl $0, %eax / else 2905 ret / return (0); 29060: movl $1, %eax 2907 ret 2908 SET_SIZE(panic_trigger) 2909 2910 ENTRY_NP(dtrace_panic_trigger) 2911 movl 4(%esp), %edx / %edx = address of trigger 2912 movl $0xdefacedd, %eax / %eax = 0xdefacedd 2913 lock / assert lock 2914 xchgl %eax, (%edx) / exchange %eax and the trigger 2915 cmpl $0, %eax / if (%eax == 0x0) 2916 je 0f / return (1); 2917 movl $0, %eax / else 2918 ret / return (0); 29190: movl $1, %eax 2920 ret 2921 SET_SIZE(dtrace_panic_trigger) 2922 2923#endif /* __i386 */ 2924#endif /* __lint */ 2925 2926/* 2927 * The panic() and cmn_err() functions invoke vpanic() as a common entry point 2928 * into the panic code implemented in panicsys(). vpanic() is responsible 2929 * for passing through the format string and arguments, and constructing a 2930 * regs structure on the stack into which it saves the current register 2931 * values. If we are not dying due to a fatal trap, these registers will 2932 * then be preserved in panicbuf as the current processor state. Before 2933 * invoking panicsys(), vpanic() activates the first panic trigger (see 2934 * common/os/panic.c) and switches to the panic_stack if successful. Note that 2935 * DTrace takes a slightly different panic path if it must panic from probe 2936 * context. Instead of calling panic, it calls into dtrace_vpanic(), which 2937 * sets up the initial stack as vpanic does, calls dtrace_panic_trigger(), and 2938 * branches back into vpanic(). 2939 */ 2940#if defined(__lint) 2941 2942/*ARGSUSED*/ 2943void 2944vpanic(const char *format, va_list alist) 2945{} 2946 2947/*ARGSUSED*/ 2948void 2949dtrace_vpanic(const char *format, va_list alist) 2950{} 2951 2952#else /* __lint */ 2953 2954#if defined(__amd64) 2955 2956 ENTRY_NP(vpanic) /* Initial stack layout: */ 2957 2958 pushq %rbp /* | %rip | 0x60 */ 2959 movq %rsp, %rbp /* | %rbp | 0x58 */ 2960 pushfq /* | rfl | 0x50 */ 2961 pushq %r11 /* | %r11 | 0x48 */ 2962 pushq %r10 /* | %r10 | 0x40 */ 2963 pushq %rbx /* | %rbx | 0x38 */ 2964 pushq %rax /* | %rax | 0x30 */ 2965 pushq %r9 /* | %r9 | 0x28 */ 2966 pushq %r8 /* | %r8 | 0x20 */ 2967 pushq %rcx /* | %rcx | 0x18 */ 2968 pushq %rdx /* | %rdx | 0x10 */ 2969 pushq %rsi /* | %rsi | 0x8 alist */ 2970 pushq %rdi /* | %rdi | 0x0 format */ 2971 2972 movq %rsp, %rbx /* %rbx = current %rsp */ 2973 2974 leaq panic_quiesce(%rip), %rdi /* %rdi = &panic_quiesce */ 2975 call panic_trigger /* %eax = panic_trigger() */ 2976 2977vpanic_common: 2978 cmpl $0, %eax 2979 je 0f 2980 2981 /* 2982 * If panic_trigger() was successful, we are the first to initiate a 2983 * panic: we now switch to the reserved panic_stack before continuing. 2984 */ 2985 leaq panic_stack(%rip), %rsp 2986 addq $PANICSTKSIZE, %rsp 29870: subq $REGSIZE, %rsp 2988 /* 2989 * Now that we've got everything set up, store the register values as 2990 * they were when we entered vpanic() to the designated location in 2991 * the regs structure we allocated on the stack. 2992 */ 2993 movq 0x0(%rbx), %rcx 2994 movq %rcx, REGOFF_RDI(%rsp) 2995 movq 0x8(%rbx), %rcx 2996 movq %rcx, REGOFF_RSI(%rsp) 2997 movq 0x10(%rbx), %rcx 2998 movq %rcx, REGOFF_RDX(%rsp) 2999 movq 0x18(%rbx), %rcx 3000 movq %rcx, REGOFF_RCX(%rsp) 3001 movq 0x20(%rbx), %rcx 3002 3003 movq %rcx, REGOFF_R8(%rsp) 3004 movq 0x28(%rbx), %rcx 3005 movq %rcx, REGOFF_R9(%rsp) 3006 movq 0x30(%rbx), %rcx 3007 movq %rcx, REGOFF_RAX(%rsp) 3008 movq 0x38(%rbx), %rcx 3009 movq %rbx, REGOFF_RBX(%rsp) 3010 movq 0x58(%rbx), %rcx 3011 3012 movq %rcx, REGOFF_RBP(%rsp) 3013 movq 0x40(%rbx), %rcx 3014 movq %rcx, REGOFF_R10(%rsp) 3015 movq 0x48(%rbx), %rcx 3016 movq %rcx, REGOFF_R11(%rsp) 3017 movq %r12, REGOFF_R12(%rsp) 3018 3019 movq %r13, REGOFF_R13(%rsp) 3020 movq %r14, REGOFF_R14(%rsp) 3021 movq %r15, REGOFF_R15(%rsp) 3022 3023 movl $MSR_AMD_FSBASE, %ecx 3024 rdmsr 3025 movl %eax, REGOFF_FSBASE(%rsp) 3026 movl %edx, REGOFF_FSBASE+4(%rsp) 3027 3028 movl $MSR_AMD_GSBASE, %ecx 3029 rdmsr 3030 movl %eax, REGOFF_GSBASE(%rsp) 3031 movl %edx, REGOFF_GSBASE+4(%rsp) 3032 3033 xorl %ecx, %ecx 3034 movw %ds, %cx 3035 movq %rcx, REGOFF_DS(%rsp) 3036 movw %es, %cx 3037 movq %rcx, REGOFF_ES(%rsp) 3038 movw %fs, %cx 3039 movq %rcx, REGOFF_FS(%rsp) 3040 movw %gs, %cx 3041 movq %rcx, REGOFF_GS(%rsp) 3042 3043 movq $0, REGOFF_TRAPNO(%rsp) 3044 3045 movq $0, REGOFF_ERR(%rsp) 3046 leaq vpanic(%rip), %rcx 3047 movq %rcx, REGOFF_RIP(%rsp) 3048 movw %cs, %cx 3049 movzwq %cx, %rcx 3050 movq %rcx, REGOFF_CS(%rsp) 3051 movq 0x50(%rbx), %rcx 3052 movq %rcx, REGOFF_RFL(%rsp) 3053 movq %rbx, %rcx 3054 addq $0x60, %rcx 3055 movq %rcx, REGOFF_RSP(%rsp) 3056 movw %ss, %cx 3057 movzwq %cx, %rcx 3058 movq %rcx, REGOFF_SS(%rsp) 3059 3060 /* 3061 * panicsys(format, alist, rp, on_panic_stack) 3062 */ 3063 movq REGOFF_RDI(%rsp), %rdi /* format */ 3064 movq REGOFF_RSI(%rsp), %rsi /* alist */ 3065 movq %rsp, %rdx /* struct regs */ 3066 movl %eax, %ecx /* on_panic_stack */ 3067 call panicsys 3068 addq $REGSIZE, %rsp 3069 popq %rdi 3070 popq %rsi 3071 popq %rdx 3072 popq %rcx 3073 popq %r8 3074 popq %r9 3075 popq %rax 3076 popq %rbx 3077 popq %r10 3078 popq %r11 3079 popfq 3080 leave 3081 ret 3082 SET_SIZE(vpanic) 3083 3084 ENTRY_NP(dtrace_vpanic) /* Initial stack layout: */ 3085 3086 pushq %rbp /* | %rip | 0x60 */ 3087 movq %rsp, %rbp /* | %rbp | 0x58 */ 3088 pushfq /* | rfl | 0x50 */ 3089 pushq %r11 /* | %r11 | 0x48 */ 3090 pushq %r10 /* | %r10 | 0x40 */ 3091 pushq %rbx /* | %rbx | 0x38 */ 3092 pushq %rax /* | %rax | 0x30 */ 3093 pushq %r9 /* | %r9 | 0x28 */ 3094 pushq %r8 /* | %r8 | 0x20 */ 3095 pushq %rcx /* | %rcx | 0x18 */ 3096 pushq %rdx /* | %rdx | 0x10 */ 3097 pushq %rsi /* | %rsi | 0x8 alist */ 3098 pushq %rdi /* | %rdi | 0x0 format */ 3099 3100 movq %rsp, %rbx /* %rbx = current %rsp */ 3101 3102 leaq panic_quiesce(%rip), %rdi /* %rdi = &panic_quiesce */ 3103 call dtrace_panic_trigger /* %eax = dtrace_panic_trigger() */ 3104 jmp vpanic_common 3105 3106 SET_SIZE(dtrace_vpanic) 3107 3108#elif defined(__i386) 3109 3110 ENTRY_NP(vpanic) / Initial stack layout: 3111 3112 pushl %ebp / | %eip | 20 3113 movl %esp, %ebp / | %ebp | 16 3114 pushl %eax / | %eax | 12 3115 pushl %ebx / | %ebx | 8 3116 pushl %ecx / | %ecx | 4 3117 pushl %edx / | %edx | 0 3118 3119 movl %esp, %ebx / %ebx = current stack pointer 3120 3121 lea panic_quiesce, %eax / %eax = &panic_quiesce 3122 pushl %eax / push &panic_quiesce 3123 call panic_trigger / %eax = panic_trigger() 3124 addl $4, %esp / reset stack pointer 3125 3126vpanic_common: 3127 cmpl $0, %eax / if (%eax == 0) 3128 je 0f / goto 0f; 3129 3130 /* 3131 * If panic_trigger() was successful, we are the first to initiate a 3132 * panic: we now switch to the reserved panic_stack before continuing. 3133 */ 3134 lea panic_stack, %esp / %esp = panic_stack 3135 addl $PANICSTKSIZE, %esp / %esp += PANICSTKSIZE 3136 31370: subl $REGSIZE, %esp / allocate struct regs 3138 3139 /* 3140 * Now that we've got everything set up, store the register values as 3141 * they were when we entered vpanic() to the designated location in 3142 * the regs structure we allocated on the stack. 3143 */ 3144#if !defined(__GNUC_AS__) 3145 movw %gs, %edx 3146 movl %edx, REGOFF_GS(%esp) 3147 movw %fs, %edx 3148 movl %edx, REGOFF_FS(%esp) 3149 movw %es, %edx 3150 movl %edx, REGOFF_ES(%esp) 3151 movw %ds, %edx 3152 movl %edx, REGOFF_DS(%esp) 3153#else /* __GNUC_AS__ */ 3154 mov %gs, %edx 3155 mov %edx, REGOFF_GS(%esp) 3156 mov %fs, %edx 3157 mov %edx, REGOFF_FS(%esp) 3158 mov %es, %edx 3159 mov %edx, REGOFF_ES(%esp) 3160 mov %ds, %edx 3161 mov %edx, REGOFF_DS(%esp) 3162#endif /* __GNUC_AS__ */ 3163 movl %edi, REGOFF_EDI(%esp) 3164 movl %esi, REGOFF_ESI(%esp) 3165 movl 16(%ebx), %ecx 3166 movl %ecx, REGOFF_EBP(%esp) 3167 movl %ebx, %ecx 3168 addl $20, %ecx 3169 movl %ecx, REGOFF_ESP(%esp) 3170 movl 8(%ebx), %ecx 3171 movl %ecx, REGOFF_EBX(%esp) 3172 movl 0(%ebx), %ecx 3173 movl %ecx, REGOFF_EDX(%esp) 3174 movl 4(%ebx), %ecx 3175 movl %ecx, REGOFF_ECX(%esp) 3176 movl 12(%ebx), %ecx 3177 movl %ecx, REGOFF_EAX(%esp) 3178 movl $0, REGOFF_TRAPNO(%esp) 3179 movl $0, REGOFF_ERR(%esp) 3180 lea vpanic, %ecx 3181 movl %ecx, REGOFF_EIP(%esp) 3182#if !defined(__GNUC_AS__) 3183 movw %cs, %edx 3184#else /* __GNUC_AS__ */ 3185 mov %cs, %edx 3186#endif /* __GNUC_AS__ */ 3187 movl %edx, REGOFF_CS(%esp) 3188 pushfl 3189 popl %ecx 3190 movl %ecx, REGOFF_EFL(%esp) 3191 movl $0, REGOFF_UESP(%esp) 3192#if !defined(__GNUC_AS__) 3193 movw %ss, %edx 3194#else /* __GNUC_AS__ */ 3195 mov %ss, %edx 3196#endif /* __GNUC_AS__ */ 3197 movl %edx, REGOFF_SS(%esp) 3198 3199 movl %esp, %ecx / %ecx = ®s 3200 pushl %eax / push on_panic_stack 3201 pushl %ecx / push ®s 3202 movl 12(%ebp), %ecx / %ecx = alist 3203 pushl %ecx / push alist 3204 movl 8(%ebp), %ecx / %ecx = format 3205 pushl %ecx / push format 3206 call panicsys / panicsys(); 3207 addl $16, %esp / pop arguments 3208 3209 addl $REGSIZE, %esp 3210 popl %edx 3211 popl %ecx 3212 popl %ebx 3213 popl %eax 3214 leave 3215 ret 3216 SET_SIZE(vpanic) 3217 3218 ENTRY_NP(dtrace_vpanic) / Initial stack layout: 3219 3220 pushl %ebp / | %eip | 20 3221 movl %esp, %ebp / | %ebp | 16 3222 pushl %eax / | %eax | 12 3223 pushl %ebx / | %ebx | 8 3224 pushl %ecx / | %ecx | 4 3225 pushl %edx / | %edx | 0 3226 3227 movl %esp, %ebx / %ebx = current stack pointer 3228 3229 lea panic_quiesce, %eax / %eax = &panic_quiesce 3230 pushl %eax / push &panic_quiesce 3231 call dtrace_panic_trigger / %eax = dtrace_panic_trigger() 3232 addl $4, %esp / reset stack pointer 3233 jmp vpanic_common / jump back to common code 3234 3235 SET_SIZE(dtrace_vpanic) 3236 3237#endif /* __i386 */ 3238#endif /* __lint */ 3239 3240#if defined(__lint) 3241 3242void 3243hres_tick(void) 3244{} 3245 3246int64_t timedelta; 3247hrtime_t hres_last_tick; 3248timestruc_t hrestime; 3249int64_t hrestime_adj; 3250volatile int hres_lock; 3251uint_t nsec_scale; 3252hrtime_t hrtime_base; 3253 3254#else /* __lint */ 3255 3256 DGDEF3(hrestime, _MUL(2, CLONGSIZE), 8) 3257 .NWORD 0, 0 3258 3259 DGDEF3(hrestime_adj, 8, 8) 3260 .long 0, 0 3261 3262 DGDEF3(hres_last_tick, 8, 8) 3263 .long 0, 0 3264 3265 DGDEF3(timedelta, 8, 8) 3266 .long 0, 0 3267 3268 DGDEF3(hres_lock, 4, 8) 3269 .long 0 3270 3271 /* 3272 * initialized to a non zero value to make pc_gethrtime() 3273 * work correctly even before clock is initialized 3274 */ 3275 DGDEF3(hrtime_base, 8, 8) 3276 .long _MUL(NSEC_PER_CLOCK_TICK, 6), 0 3277 3278 DGDEF3(adj_shift, 4, 4) 3279 .long ADJ_SHIFT 3280 3281#if defined(__amd64) 3282 3283 ENTRY_NP(hres_tick) 3284 pushq %rbp 3285 movq %rsp, %rbp 3286 3287 /* 3288 * We need to call *gethrtimef before picking up CLOCK_LOCK (obviously, 3289 * hres_last_tick can only be modified while holding CLOCK_LOCK). 3290 * At worst, performing this now instead of under CLOCK_LOCK may 3291 * introduce some jitter in pc_gethrestime(). 3292 */ 3293 call *gethrtimef(%rip) 3294 movq %rax, %r8 3295 3296 leaq hres_lock(%rip), %rax 3297 movb $-1, %dl 3298.CL1: 3299 xchgb %dl, (%rax) 3300 testb %dl, %dl 3301 jz .CL3 /* got it */ 3302.CL2: 3303 cmpb $0, (%rax) /* possible to get lock? */ 3304 pause 3305 jne .CL2 3306 jmp .CL1 /* yes, try again */ 3307.CL3: 3308 /* 3309 * compute the interval since last time hres_tick was called 3310 * and adjust hrtime_base and hrestime accordingly 3311 * hrtime_base is an 8 byte value (in nsec), hrestime is 3312 * a timestruc_t (sec, nsec) 3313 */ 3314 leaq hres_last_tick(%rip), %rax 3315 movq %r8, %r11 3316 subq (%rax), %r8 3317 addq %r8, hrtime_base(%rip) /* add interval to hrtime_base */ 3318 addq %r8, hrestime+8(%rip) /* add interval to hrestime.tv_nsec */ 3319 /* 3320 * Now that we have CLOCK_LOCK, we can update hres_last_tick 3321 */ 3322 movq %r11, (%rax) 3323 3324 call __adj_hrestime 3325 3326 /* 3327 * release the hres_lock 3328 */ 3329 incl hres_lock(%rip) 3330 leave 3331 ret 3332 SET_SIZE(hres_tick) 3333 3334#elif defined(__i386) 3335 3336 ENTRY_NP(hres_tick) 3337 pushl %ebp 3338 movl %esp, %ebp 3339 pushl %esi 3340 pushl %ebx 3341 3342 /* 3343 * We need to call *gethrtimef before picking up CLOCK_LOCK (obviously, 3344 * hres_last_tick can only be modified while holding CLOCK_LOCK). 3345 * At worst, performing this now instead of under CLOCK_LOCK may 3346 * introduce some jitter in pc_gethrestime(). 3347 */ 3348 call *gethrtimef 3349 movl %eax, %ebx 3350 movl %edx, %esi 3351 3352 movl $hres_lock, %eax 3353 movl $-1, %edx 3354.CL1: 3355 xchgb %dl, (%eax) 3356 testb %dl, %dl 3357 jz .CL3 / got it 3358.CL2: 3359 cmpb $0, (%eax) / possible to get lock? 3360 pause 3361 jne .CL2 3362 jmp .CL1 / yes, try again 3363.CL3: 3364 /* 3365 * compute the interval since last time hres_tick was called 3366 * and adjust hrtime_base and hrestime accordingly 3367 * hrtime_base is an 8 byte value (in nsec), hrestime is 3368 * timestruc_t (sec, nsec) 3369 */ 3370 3371 lea hres_last_tick, %eax 3372 3373 movl %ebx, %edx 3374 movl %esi, %ecx 3375 3376 subl (%eax), %edx 3377 sbbl 4(%eax), %ecx 3378 3379 addl %edx, hrtime_base / add interval to hrtime_base 3380 adcl %ecx, hrtime_base+4 3381 3382 addl %edx, hrestime+4 / add interval to hrestime.tv_nsec 3383 3384 / 3385 / Now that we have CLOCK_LOCK, we can update hres_last_tick. 3386 / 3387 movl %ebx, (%eax) 3388 movl %esi, 4(%eax) 3389 3390 / get hrestime at this moment. used as base for pc_gethrestime 3391 / 3392 / Apply adjustment, if any 3393 / 3394 / #define HRES_ADJ (NSEC_PER_CLOCK_TICK >> ADJ_SHIFT) 3395 / (max_hres_adj) 3396 / 3397 / void 3398 / adj_hrestime() 3399 / { 3400 / long long adj; 3401 / 3402 / if (hrestime_adj == 0) 3403 / adj = 0; 3404 / else if (hrestime_adj > 0) { 3405 / if (hrestime_adj < HRES_ADJ) 3406 / adj = hrestime_adj; 3407 / else 3408 / adj = HRES_ADJ; 3409 / } 3410 / else { 3411 / if (hrestime_adj < -(HRES_ADJ)) 3412 / adj = -(HRES_ADJ); 3413 / else 3414 / adj = hrestime_adj; 3415 / } 3416 / 3417 / timedelta -= adj; 3418 / hrestime_adj = timedelta; 3419 / hrestime.tv_nsec += adj; 3420 / 3421 / while (hrestime.tv_nsec >= NANOSEC) { 3422 / one_sec++; 3423 / hrestime.tv_sec++; 3424 / hrestime.tv_nsec -= NANOSEC; 3425 / } 3426 / } 3427__adj_hrestime: 3428 movl hrestime_adj, %esi / if (hrestime_adj == 0) 3429 movl hrestime_adj+4, %edx 3430 andl %esi, %esi 3431 jne .CL4 / no 3432 andl %edx, %edx 3433 jne .CL4 / no 3434 subl %ecx, %ecx / yes, adj = 0; 3435 subl %edx, %edx 3436 jmp .CL5 3437.CL4: 3438 subl %ecx, %ecx 3439 subl %eax, %eax 3440 subl %esi, %ecx 3441 sbbl %edx, %eax 3442 andl %eax, %eax / if (hrestime_adj > 0) 3443 jge .CL6 3444 3445 / In the following comments, HRES_ADJ is used, while in the code 3446 / max_hres_adj is used. 3447 / 3448 / The test for "hrestime_adj < HRES_ADJ" is complicated because 3449 / hrestime_adj is 64-bits, while HRES_ADJ is 32-bits. We rely 3450 / on the logical equivalence of: 3451 / 3452 / !(hrestime_adj < HRES_ADJ) 3453 / 3454 / and the two step sequence: 3455 / 3456 / (HRES_ADJ - lsw(hrestime_adj)) generates a Borrow/Carry 3457 / 3458 / which computes whether or not the least significant 32-bits 3459 / of hrestime_adj is greater than HRES_ADJ, followed by: 3460 / 3461 / Previous Borrow/Carry + -1 + msw(hrestime_adj) generates a Carry 3462 / 3463 / which generates a carry whenever step 1 is true or the most 3464 / significant long of the longlong hrestime_adj is non-zero. 3465 3466 movl max_hres_adj, %ecx / hrestime_adj is positive 3467 subl %esi, %ecx 3468 movl %edx, %eax 3469 adcl $-1, %eax 3470 jnc .CL7 3471 movl max_hres_adj, %ecx / adj = HRES_ADJ; 3472 subl %edx, %edx 3473 jmp .CL5 3474 3475 / The following computation is similar to the one above. 3476 / 3477 / The test for "hrestime_adj < -(HRES_ADJ)" is complicated because 3478 / hrestime_adj is 64-bits, while HRES_ADJ is 32-bits. We rely 3479 / on the logical equivalence of: 3480 / 3481 / (hrestime_adj > -HRES_ADJ) 3482 / 3483 / and the two step sequence: 3484 / 3485 / (HRES_ADJ + lsw(hrestime_adj)) generates a Carry 3486 / 3487 / which means the least significant 32-bits of hrestime_adj is 3488 / greater than -HRES_ADJ, followed by: 3489 / 3490 / Previous Carry + 0 + msw(hrestime_adj) generates a Carry 3491 / 3492 / which generates a carry only when step 1 is true and the most 3493 / significant long of the longlong hrestime_adj is -1. 3494 3495.CL6: / hrestime_adj is negative 3496 movl %esi, %ecx 3497 addl max_hres_adj, %ecx 3498 movl %edx, %eax 3499 adcl $0, %eax 3500 jc .CL7 3501 xor %ecx, %ecx 3502 subl max_hres_adj, %ecx / adj = -(HRES_ADJ); 3503 movl $-1, %edx 3504 jmp .CL5 3505.CL7: 3506 movl %esi, %ecx / adj = hrestime_adj; 3507.CL5: 3508 movl timedelta, %esi 3509 subl %ecx, %esi 3510 movl timedelta+4, %eax 3511 sbbl %edx, %eax 3512 movl %esi, timedelta 3513 movl %eax, timedelta+4 / timedelta -= adj; 3514 movl %esi, hrestime_adj 3515 movl %eax, hrestime_adj+4 / hrestime_adj = timedelta; 3516 addl hrestime+4, %ecx 3517 3518 movl %ecx, %eax / eax = tv_nsec 35191: 3520 cmpl $NANOSEC, %eax / if ((unsigned long)tv_nsec >= NANOSEC) 3521 jb .CL8 / no 3522 incl one_sec / yes, one_sec++; 3523 incl hrestime / hrestime.tv_sec++; 3524 addl $-NANOSEC, %eax / tv_nsec -= NANOSEC 3525 jmp 1b / check for more seconds 3526 3527.CL8: 3528 movl %eax, hrestime+4 / store final into hrestime.tv_nsec 3529 incl hres_lock / release the hres_lock 3530 3531 popl %ebx 3532 popl %esi 3533 leave 3534 ret 3535 SET_SIZE(hres_tick) 3536 3537#endif /* __i386 */ 3538#endif /* __lint */ 3539 3540/* 3541 * void prefetch_smap_w(void *) 3542 * 3543 * Prefetch ahead within a linear list of smap structures. 3544 * Not implemented for ia32. Stub for compatibility. 3545 */ 3546 3547#if defined(__lint) 3548 3549/*ARGSUSED*/ 3550void prefetch_smap_w(void *smp) 3551{} 3552 3553#else /* __lint */ 3554 3555 ENTRY(prefetch_smap_w) 3556 ret 3557 SET_SIZE(prefetch_smap_w) 3558 3559#endif /* __lint */ 3560 3561/* 3562 * prefetch_page_r(page_t *) 3563 * issue prefetch instructions for a page_t 3564 */ 3565#if defined(__lint) 3566 3567/*ARGSUSED*/ 3568void 3569prefetch_page_r(void *pp) 3570{} 3571 3572#else /* __lint */ 3573 3574 ENTRY(prefetch_page_r) 3575 ret 3576 SET_SIZE(prefetch_page_r) 3577 3578#endif /* __lint */ 3579 3580#if defined(__lint) 3581 3582/*ARGSUSED*/ 3583int 3584bcmp(const void *s1, const void *s2, size_t count) 3585{ return (0); } 3586 3587#else /* __lint */ 3588 3589#if defined(__amd64) 3590 3591 ENTRY(bcmp) 3592 pushq %rbp 3593 movq %rsp, %rbp 3594#ifdef DEBUG 3595 movq kernelbase(%rip), %r11 3596 cmpq %r11, %rdi 3597 jb 0f 3598 cmpq %r11, %rsi 3599 jnb 1f 36000: leaq .bcmp_panic_msg(%rip), %rdi 3601 xorl %eax, %eax 3602 call panic 36031: 3604#endif /* DEBUG */ 3605 call memcmp 3606 testl %eax, %eax 3607 setne %dl 3608 leave 3609 movzbl %dl, %eax 3610 ret 3611 SET_SIZE(bcmp) 3612 3613#elif defined(__i386) 3614 3615#define ARG_S1 8 3616#define ARG_S2 12 3617#define ARG_LENGTH 16 3618 3619 ENTRY(bcmp) 3620#ifdef DEBUG 3621 pushl %ebp 3622 movl %esp, %ebp 3623 movl kernelbase, %eax 3624 cmpl %eax, ARG_S1(%ebp) 3625 jb 0f 3626 cmpl %eax, ARG_S2(%ebp) 3627 jnb 1f 36280: pushl $.bcmp_panic_msg 3629 call panic 36301: popl %ebp 3631#endif /* DEBUG */ 3632 3633 pushl %edi / save register variable 3634 movl ARG_S1(%esp), %eax / %eax = address of string 1 3635 movl ARG_S2(%esp), %ecx / %ecx = address of string 2 3636 cmpl %eax, %ecx / if the same string 3637 je .equal / goto .equal 3638 movl ARG_LENGTH(%esp), %edi / %edi = length in bytes 3639 cmpl $4, %edi / if %edi < 4 3640 jb .byte_check / goto .byte_check 3641 .align 4 3642.word_loop: 3643 movl (%ecx), %edx / move 1 word from (%ecx) to %edx 3644 leal -4(%edi), %edi / %edi -= 4 3645 cmpl (%eax), %edx / compare 1 word from (%eax) with %edx 3646 jne .word_not_equal / if not equal, goto .word_not_equal 3647 leal 4(%ecx), %ecx / %ecx += 4 (next word) 3648 leal 4(%eax), %eax / %eax += 4 (next word) 3649 cmpl $4, %edi / if %edi >= 4 3650 jae .word_loop / goto .word_loop 3651.byte_check: 3652 cmpl $0, %edi / if %edi == 0 3653 je .equal / goto .equal 3654 jmp .byte_loop / goto .byte_loop (checks in bytes) 3655.word_not_equal: 3656 leal 4(%edi), %edi / %edi += 4 (post-decremented) 3657 .align 4 3658.byte_loop: 3659 movb (%ecx), %dl / move 1 byte from (%ecx) to %dl 3660 cmpb %dl, (%eax) / compare %dl with 1 byte from (%eax) 3661 jne .not_equal / if not equal, goto .not_equal 3662 incl %ecx / %ecx++ (next byte) 3663 incl %eax / %eax++ (next byte) 3664 decl %edi / %edi-- 3665 jnz .byte_loop / if not zero, goto .byte_loop 3666.equal: 3667 xorl %eax, %eax / %eax = 0 3668 popl %edi / restore register variable 3669 ret / return (NULL) 3670 .align 4 3671.not_equal: 3672 movl $1, %eax / return 1 3673 popl %edi / restore register variable 3674 ret / return (NULL) 3675 SET_SIZE(bcmp) 3676 3677#endif /* __i386 */ 3678 3679#ifdef DEBUG 3680 .text 3681.bcmp_panic_msg: 3682 .string "bcmp: arguments below kernelbase" 3683#endif /* DEBUG */ 3684 3685#endif /* __lint */ 3686