1*c0da6274SZhi-Jun Robin Fu /* 2*c0da6274SZhi-Jun Robin Fu * CDDL HEADER START 3*c0da6274SZhi-Jun Robin Fu * 4*c0da6274SZhi-Jun Robin Fu * The contents of this file are subject to the terms of the 5*c0da6274SZhi-Jun Robin Fu * Common Development and Distribution License (the "License"). 6*c0da6274SZhi-Jun Robin Fu * You may not use this file except in compliance with the License. 7*c0da6274SZhi-Jun Robin Fu * 8*c0da6274SZhi-Jun Robin Fu * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9*c0da6274SZhi-Jun Robin Fu * or http://www.opensolaris.org/os/licensing. 10*c0da6274SZhi-Jun Robin Fu * See the License for the specific language governing permissions 11*c0da6274SZhi-Jun Robin Fu * and limitations under the License. 12*c0da6274SZhi-Jun Robin Fu * 13*c0da6274SZhi-Jun Robin Fu * When distributing Covered Code, include this CDDL HEADER in each 14*c0da6274SZhi-Jun Robin Fu * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15*c0da6274SZhi-Jun Robin Fu * If applicable, add the following below this CDDL HEADER, with the 16*c0da6274SZhi-Jun Robin Fu * fields enclosed by brackets "[]" replaced with your own identifying 17*c0da6274SZhi-Jun Robin Fu * information: Portions Copyright [yyyy] [name of copyright owner] 18*c0da6274SZhi-Jun Robin Fu * 19*c0da6274SZhi-Jun Robin Fu * CDDL HEADER END 20*c0da6274SZhi-Jun Robin Fu */ 21*c0da6274SZhi-Jun Robin Fu /* 22*c0da6274SZhi-Jun Robin Fu * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23*c0da6274SZhi-Jun Robin Fu * Use is subject to license terms. 24*c0da6274SZhi-Jun Robin Fu */ 25*c0da6274SZhi-Jun Robin Fu 26*c0da6274SZhi-Jun Robin Fu #ifndef _SYS_PCI_CFGACC_X86_H 27*c0da6274SZhi-Jun Robin Fu #define _SYS_PCI_CFGACC_X86_H 28*c0da6274SZhi-Jun Robin Fu 29*c0da6274SZhi-Jun Robin Fu #ifdef __cplusplus 30*c0da6274SZhi-Jun Robin Fu extern "C" { 31*c0da6274SZhi-Jun Robin Fu #endif 32*c0da6274SZhi-Jun Robin Fu 33*c0da6274SZhi-Jun Robin Fu /* AMD's northbridges vendor-id and device-ids */ 34*c0da6274SZhi-Jun Robin Fu #define AMD_NTBRDIGE_VID 0x1022 /* AMD vendor-id */ 35*c0da6274SZhi-Jun Robin Fu #define AMD_HT_NTBRIDGE_DID 0x1100 /* HT Configuration */ 36*c0da6274SZhi-Jun Robin Fu #define AMD_AM_NTBRIDGE_DID 0x1101 /* Address Map */ 37*c0da6274SZhi-Jun Robin Fu #define AMD_DC_NTBRIDGE_DID 0x1102 /* DRAM Controller */ 38*c0da6274SZhi-Jun Robin Fu #define AMD_MC_NTBRIDGE_DID 0x1103 /* Misc Controller */ 39*c0da6274SZhi-Jun Robin Fu #define AMD_K10_NTBRIDGE_DID_0 0x1200 40*c0da6274SZhi-Jun Robin Fu #define AMD_K10_NTBRIDGE_DID_1 0x1201 41*c0da6274SZhi-Jun Robin Fu #define AMD_K10_NTBRIDGE_DID_2 0x1202 42*c0da6274SZhi-Jun Robin Fu #define AMD_K10_NTBRIDGE_DID_3 0x1203 43*c0da6274SZhi-Jun Robin Fu #define AMD_K10_NTBRIDGE_DID_4 0x1204 44*c0da6274SZhi-Jun Robin Fu 45*c0da6274SZhi-Jun Robin Fu /* AMD's 8132 chipset vendor-id and device-ids */ 46*c0da6274SZhi-Jun Robin Fu #define AMD_8132_BRIDGE_DID 0x7458 /* 8132 PCI-X bridge */ 47*c0da6274SZhi-Jun Robin Fu #define AMD_8132_IOAPIC_DID 0x7459 /* 8132 IO APIC */ 48*c0da6274SZhi-Jun Robin Fu 49*c0da6274SZhi-Jun Robin Fu /* 50*c0da6274SZhi-Jun Robin Fu * Check if the given device is an AMD northbridge 51*c0da6274SZhi-Jun Robin Fu */ 52*c0da6274SZhi-Jun Robin Fu #define IS_BAD_AMD_NTBRIDGE(vid, did) \ 53*c0da6274SZhi-Jun Robin Fu (((vid) == AMD_NTBRDIGE_VID) && \ 54*c0da6274SZhi-Jun Robin Fu (((did) == AMD_HT_NTBRIDGE_DID) || \ 55*c0da6274SZhi-Jun Robin Fu ((did) == AMD_AM_NTBRIDGE_DID) || \ 56*c0da6274SZhi-Jun Robin Fu ((did) == AMD_DC_NTBRIDGE_DID) || \ 57*c0da6274SZhi-Jun Robin Fu ((did) == AMD_MC_NTBRIDGE_DID))) 58*c0da6274SZhi-Jun Robin Fu 59*c0da6274SZhi-Jun Robin Fu #define IS_K10_AMD_NTBRIDGE(vid, did) \ 60*c0da6274SZhi-Jun Robin Fu (((vid) == AMD_NTBRDIGE_VID) && \ 61*c0da6274SZhi-Jun Robin Fu (((did) == AMD_K10_NTBRIDGE_DID_0) || \ 62*c0da6274SZhi-Jun Robin Fu ((did) == AMD_K10_NTBRIDGE_DID_1) || \ 63*c0da6274SZhi-Jun Robin Fu ((did) == AMD_K10_NTBRIDGE_DID_2) || \ 64*c0da6274SZhi-Jun Robin Fu ((did) == AMD_K10_NTBRIDGE_DID_3) || \ 65*c0da6274SZhi-Jun Robin Fu ((did) == AMD_K10_NTBRIDGE_DID_4))) 66*c0da6274SZhi-Jun Robin Fu 67*c0da6274SZhi-Jun Robin Fu #define IS_AMD_8132_CHIP(vid, did) \ 68*c0da6274SZhi-Jun Robin Fu (((vid) == AMD_NTBRDIGE_VID) && \ 69*c0da6274SZhi-Jun Robin Fu (((did) == AMD_8132_BRIDGE_DID)) || \ 70*c0da6274SZhi-Jun Robin Fu (((did) == AMD_8132_IOAPIC_DID))) 71*c0da6274SZhi-Jun Robin Fu 72*c0da6274SZhi-Jun Robin Fu #define MSR_AMD_NB_MMIO_CFG_BADDR 0xc0010058 73*c0da6274SZhi-Jun Robin Fu #define AMD_MMIO_CFG_BADDR_ADDR_MASK 0xFFFFFFF00000ULL 74*c0da6274SZhi-Jun Robin Fu #define AMD_MMIO_CFG_BADDR_ENA_MASK 0x000000000001ULL 75*c0da6274SZhi-Jun Robin Fu #define AMD_MMIO_CFG_BADDR_ENA_ON 0x000000000001ULL 76*c0da6274SZhi-Jun Robin Fu #define AMD_MMIO_CFG_BADDR_ENA_OFF 0x000000000000ULL 77*c0da6274SZhi-Jun Robin Fu 78*c0da6274SZhi-Jun Robin Fu #ifdef __cplusplus 79*c0da6274SZhi-Jun Robin Fu } 80*c0da6274SZhi-Jun Robin Fu #endif 81*c0da6274SZhi-Jun Robin Fu 82*c0da6274SZhi-Jun Robin Fu #endif /* _SYS_PCI_CFGACC_X86_H */ 83