xref: /titanic_44/usr/src/uts/i86pc/sys/machcpuvar.h (revision 5e2844d4e1d6321400668cbd30b2ccd36887492f)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #ifndef	_SYS_MACHCPUVAR_H
27 #define	_SYS_MACHCPUVAR_H
28 
29 #ifdef	__cplusplus
30 extern "C" {
31 #endif
32 
33 #include <sys/inttypes.h>
34 #include <sys/xc_levels.h>
35 #include <sys/tss.h>
36 #include <sys/segments.h>
37 #include <sys/rm_platter.h>
38 #include <sys/avintr.h>
39 #include <sys/pte.h>
40 
41 #ifndef	_ASM
42 /*
43  * On a virtualized platform a virtual cpu may not be actually
44  * on a physical cpu, especially in situations where a configuration has
45  * more vcpus than pcpus.  This function tells us (if it's able) if the
46  * specified vcpu is currently running on a pcpu.  Note if it is not
47  * known or not able to determine, it will return the unknown state.
48  */
49 #define	VCPU_STATE_UNKNOWN	0
50 #define	VCPU_ON_PCPU		1
51 #define	VCPU_NOT_ON_PCPU	2
52 
53 extern int vcpu_on_pcpu(processorid_t);
54 
55 /*
56  * Machine specific fields of the cpu struct
57  * defined in common/sys/cpuvar.h.
58  *
59  * Note:  This is kinda kludgy but seems to be the best
60  * of our alternatives.
61  */
62 typedef void *cpu_pri_lev_t;
63 
64 struct cpuid_info;
65 struct cpu_ucode_info;
66 
67 /*
68  * A note about the hypervisor affinity bits: a one bit in the affinity mask
69  * means the corresponding event channel is allowed to be serviced
70  * by this cpu.
71  */
72 struct xen_evt_data {
73 	ulong_t		pending_sel[PIL_MAX + 1]; /* event array selectors */
74 	ulong_t		pending_evts[PIL_MAX + 1][sizeof (ulong_t) * 8];
75 	ulong_t		evt_affinity[sizeof (ulong_t) * 8]; /* service on cpu */
76 };
77 
78 struct	machcpu {
79 	/* define all the x_call stuff */
80 	volatile int	xc_pend[X_CALL_LEVELS];
81 	volatile int	xc_wait[X_CALL_LEVELS];
82 	volatile int	xc_ack[X_CALL_LEVELS];
83 	volatile int	xc_state[X_CALL_LEVELS];
84 	volatile int	xc_retval[X_CALL_LEVELS];
85 
86 	int		mcpu_nodeid;		/* node-id */
87 	int		mcpu_pri;		/* CPU priority */
88 	cpu_pri_lev_t	mcpu_pri_data;		/* ptr to machine dependent */
89 						/* data for setting priority */
90 						/* level */
91 
92 	struct hat	*mcpu_current_hat; /* cpu's current hat */
93 
94 	struct hat_cpu_info	*mcpu_hat_info;
95 
96 	volatile ulong_t	mcpu_tlb_info;
97 
98 	/* i86 hardware table addresses that cannot be shared */
99 
100 	user_desc_t	*mcpu_gdt;	/* GDT */
101 	gate_desc_t	*mcpu_idt;	/* current IDT */
102 
103 	struct tss	*mcpu_tss;	/* TSS */
104 
105 	kmutex_t	mcpu_ppaddr_mutex;
106 	caddr_t		mcpu_caddr1;	/* per cpu CADDR1 */
107 	caddr_t		mcpu_caddr2;	/* per cpu CADDR2 */
108 	uint64_t	mcpu_caddr1pte;
109 	uint64_t	mcpu_caddr2pte;
110 
111 	struct softint	mcpu_softinfo;
112 	uint64_t	pil_high_start[HIGH_LEVELS];
113 	uint64_t	intrstat[PIL_MAX + 1][2];
114 
115 	struct cpuid_info	 *mcpu_cpi;
116 
117 #if defined(__amd64)
118 	greg_t	mcpu_rtmp_rsp;		/* syscall: temporary %rsp stash */
119 	greg_t	mcpu_rtmp_r15;		/* syscall: temporary %r15 stash */
120 #endif
121 
122 	struct vcpu_info *mcpu_vcpu_info;
123 	uint64_t	mcpu_gdtpa;	/* hypervisor: GDT physical address */
124 
125 	uint16_t mcpu_intr_pending;	/* hypervisor: pending intrpt levels */
126 	struct xen_evt_data *mcpu_evt_pend; /* hypervisor: pending events */
127 
128 	volatile uint32_t *mcpu_mwait;	/* MONITOR/MWAIT buffer */
129 	void (*mcpu_idle_cpu)(void);	/* idle function */
130 	uint16_t mcpu_idle_type;	/* CPU next idle type */
131 	uint16_t max_cstates;		/* supported max cstates */
132 	uint32_t curr_cstate;		/* current cstate */
133 
134 	struct cpu_ucode_info	*mcpu_ucode_info;
135 
136 	void		*mcpu_pm_mach_state;
137 };
138 
139 #define	NINTR_THREADS	(LOCK_LEVEL-1)	/* number of interrupt threads */
140 #define	MWAIT_HALTED	(1)		/* mcpu_mwait set when halting */
141 #define	MWAIT_RUNNING	(0)		/* mcpu_mwait set to wakeup */
142 #define	MWAIT_WAKEUP_IPI	(2)	/* need IPI to wakeup */
143 #define	MWAIT_WAKEUP(cpu)	(*((cpu)->cpu_m.mcpu_mwait) = MWAIT_RUNNING)
144 
145 #endif	/* _ASM */
146 
147 /* Please DON'T add any more of this namespace-poisoning sewage here */
148 
149 #define	cpu_nodeid cpu_m.mcpu_nodeid
150 #define	cpu_pri cpu_m.mcpu_pri
151 #define	cpu_pri_data cpu_m.mcpu_pri_data
152 #define	cpu_current_hat cpu_m.mcpu_current_hat
153 #define	cpu_hat_info cpu_m.mcpu_hat_info
154 #define	cpu_ppaddr_mutex cpu_m.mcpu_ppaddr_mutex
155 #define	cpu_gdt cpu_m.mcpu_gdt
156 #define	cpu_idt cpu_m.mcpu_idt
157 #define	cpu_tss cpu_m.mcpu_tss
158 #define	cpu_ldt cpu_m.mcpu_ldt
159 #define	cpu_caddr1 cpu_m.mcpu_caddr1
160 #define	cpu_caddr2 cpu_m.mcpu_caddr2
161 #define	cpu_softinfo cpu_m.mcpu_softinfo
162 #define	cpu_caddr1pte cpu_m.mcpu_caddr1pte
163 #define	cpu_caddr2pte cpu_m.mcpu_caddr2pte
164 
165 #ifdef	__cplusplus
166 }
167 #endif
168 
169 #endif	/* _SYS_MACHCPUVAR_H */
170