1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #ifndef _SYS_APIC_APIC_H 27 #define _SYS_APIC_APIC_H 28 29 #pragma ident "%Z%%M% %I% %E% SMI" 30 31 #include <sys/psm_types.h> 32 #include <sys/avintr.h> 33 #include <sys/pci.h> 34 35 #ifdef __cplusplus 36 extern "C" { 37 #endif 38 39 #include <sys/psm_common.h> 40 41 #define APIC_PCPLUSMP_NAME "pcplusmp" 42 43 #define APIC_IO_ADDR 0xfec00000 44 #define APIC_LOCAL_ADDR 0xfee00000 45 #define APIC_IO_MEMLEN 0xf 46 #define APIC_LOCAL_MEMLEN 0xfffff 47 48 /* Local Unit ID register */ 49 #define APIC_LID_REG 0x8 50 51 /* I/o Unit Version Register */ 52 #define APIC_VERS_REG 0xc 53 54 /* Task Priority register */ 55 #define APIC_TASK_REG 0x20 56 57 /* EOI register */ 58 #define APIC_EOI_REG 0x2c 59 60 /* Remote Read register */ 61 #define APIC_REMOTE_READ 0x30 62 63 /* Logical Destination register */ 64 #define APIC_DEST_REG 0x34 65 66 /* Destination Format rgister */ 67 #define APIC_FORMAT_REG 0x38 68 69 /* Spurious Interrupt Vector register */ 70 #define APIC_SPUR_INT_REG 0x3c 71 72 /* Error Status Register */ 73 #define APIC_ERROR_STATUS 0xa0 74 75 /* Interrupt Command registers */ 76 #define APIC_INT_CMD1 0xc0 77 #define APIC_INT_CMD2 0xc4 78 79 /* Timer Vector Table register */ 80 #define APIC_LOCAL_TIMER 0xc8 81 82 /* Local Interrupt Vector registers */ 83 #define APIC_PCINT_VECT 0xd0 84 #define APIC_INT_VECT0 0xd4 85 #define APIC_INT_VECT1 0xd8 86 #define APIC_ERR_VECT 0xdc 87 88 /* IPL for performance counter interrupts */ 89 #define APIC_PCINT_IPL 0xe 90 #define APIC_LVT_MASK 0x10000 /* Mask bit (16) in LVT */ 91 92 /* Initial Count register */ 93 #define APIC_INIT_COUNT 0xe0 94 95 /* Current Count Register */ 96 #define APIC_CURR_COUNT 0xe4 97 #define APIC_CURR_ADD 0x39 /* used for remote read command */ 98 #define CURR_COUNT_OFFSET (sizeof (int32_t) * APIC_CURR_COUNT) 99 100 /* Divider Configuration Register */ 101 #define APIC_DIVIDE_REG 0xf8 102 103 /* IRR register */ 104 #define APIC_IRR_REG 0x80 105 106 /* ISR register */ 107 #define APIC_ISR_REG 0x40 108 109 #define APIC_IO_REG 0x0 110 #define APIC_IO_DATA 0x4 111 112 /* Bit offset of APIC ID in LID_REG, INT_CMD and in DEST_REG */ 113 #define APIC_ID_BIT_OFFSET 24 114 #define APIC_ICR_ID_BIT_OFFSET 24 115 #define APIC_LDR_ID_BIT_OFFSET 24 116 117 /* 118 * Choose between flat and clustered models by writing the following to the 119 * FORMAT_REG. 82489 DX documentation seemed to suggest that writing 0 will 120 * disable logical destination mode. 121 * Does not seem to be in the docs for local APICs on the processors. 122 */ 123 #define APIC_FLAT_MODEL 0xFFFFFFFFUL 124 #define APIC_CLUSTER_MODEL 0x0FFFFFFF 125 126 /* 127 * The commands which follow are window selectors written to APIC_IO_REG 128 * before data can be read/written from/to APIC_IO_DATA 129 */ 130 131 #define APIC_ID_CMD 0x0 132 #define APIC_VERS_CMD 0x1 133 #define APIC_RDT_CMD 0x10 134 #define APIC_RDT_CMD2 0x11 135 136 #define APIC_INTEGRATED_VERS 0x10 /* 0x10 & above indicates integrated */ 137 #define IOAPIC_VER_82489DX 0x01 /* Version ID: 82489DX External APIC */ 138 139 #define APIC_INT_SPURIOUS -1 140 141 #define APIC_IMCR_P1 0x22 /* int mode conf register port 1 */ 142 #define APIC_IMCR_P2 0x23 /* int mode conf register port 2 */ 143 #define APIC_IMCR_SELECT 0x70 /* select imcr by writing into P1 */ 144 #define APIC_IMCR_PIC 0x0 /* selects PIC mode (8259-> BSP) */ 145 #define APIC_IMCR_APIC 0x1 /* selects APIC mode (8259->APIC) */ 146 147 #define APIC_CT_VECT 0x4ac /* conf table vector */ 148 #define APIC_CT_SIZE 1024 /* conf table size */ 149 150 #define APIC_ID 'MPAT' /* conf table signature */ 151 152 #define VENID_AMD 0x1022 153 #define DEVID_8131_IOAPIC 0x7451 154 #define DEVID_8132_IOAPIC 0x7459 155 156 #define IOAPICS_NODE_NAME "ioapics" 157 #define IOAPICS_CHILD_NAME "ioapic" 158 #define IOAPICS_DEV_TYPE "ioapic" 159 #define IOAPICS_PROP_VENID "vendor-id" 160 #define IOAPICS_PROP_DEVID "device-id" 161 162 #define IS_CLASS_IOAPIC(b, s, p) \ 163 ((b) == PCI_CLASS_PERIPH && (s) == PCI_PERIPH_PIC && \ 164 ((p) == PCI_PERIPH_PIC_IF_IO_APIC || \ 165 (p) == PCI_PERIPH_PIC_IF_IOX_APIC)) 166 167 168 /* 169 * MP floating pointer structure defined in Intel MP Spec 1.1 170 */ 171 struct apic_mpfps_hdr { 172 uint32_t mpfps_sig; /* _MP_ (0x5F4D505F) */ 173 uint32_t mpfps_mpct_paddr; /* paddr of MP configuration tbl */ 174 uchar_t mpfps_length; /* in paragraph (16-bytes units) */ 175 uchar_t mpfps_spec_rev; /* version number of MP spec */ 176 uchar_t mpfps_checksum; /* checksum of complete structure */ 177 uchar_t mpfps_featinfo1; /* mp feature info bytes 1 */ 178 uchar_t mpfps_featinfo2; /* mp feature info bytes 2 */ 179 uchar_t mpfps_featinfo3; /* mp feature info bytes 3 */ 180 uchar_t mpfps_featinfo4; /* mp feature info bytes 4 */ 181 uchar_t mpfps_featinfo5; /* mp feature info bytes 5 */ 182 }; 183 184 #define MPFPS_FEATINFO2_IMCRP 0x80 /* IMCRP presence bit */ 185 186 #define APIC_MPS_OEM_ID_LEN 8 187 #define APIC_MPS_PROD_ID_LEN 12 188 189 struct apic_mp_cnf_hdr { 190 uint_t mpcnf_sig; 191 192 uint_t mpcnf_tbl_length: 16, 193 mpcnf_spec: 8, 194 mpcnf_cksum: 8; 195 196 char mpcnf_oem_str[APIC_MPS_OEM_ID_LEN]; 197 198 char mpcnf_prod_str[APIC_MPS_PROD_ID_LEN]; 199 200 uint_t mpcnf_oem_ptr; 201 202 uint_t mpcnf_oem_tbl_size: 16, 203 mpcnf_entry_cnt: 16; 204 205 uint_t mpcnf_local_apic; 206 207 uint_t mpcnf_resv; 208 }; 209 210 struct apic_procent { 211 uint_t proc_entry: 8, 212 proc_apicid: 8, 213 proc_version: 8, 214 proc_cpuflags: 8; 215 216 uint_t proc_stepping: 4, 217 proc_model: 4, 218 proc_family: 4, 219 proc_type: 2, /* undocumented feature */ 220 proc_resv1: 18; 221 222 uint_t proc_feature; 223 224 uint_t proc_resv2; 225 226 uint_t proc_resv3; 227 }; 228 229 /* 230 * proc_cpuflags definitions 231 */ 232 #define CPUFLAGS_EN 1 /* if not set, this processor is unusable */ 233 #define CPUFLAGS_BP 2 /* set if this is the bootstrap processor */ 234 235 236 struct apic_bus { 237 uchar_t bus_entry; 238 uchar_t bus_id; 239 ushort_t bus_str1; 240 uint_t bus_str2; 241 }; 242 243 struct apic_io_entry { 244 uint_t io_entry: 8, 245 io_apicid: 8, 246 io_version: 8, 247 io_flags: 8; 248 249 uint_t io_apic_addr; 250 }; 251 252 #define IOAPIC_FLAGS_EN 0x01 /* this I/O apic is enable or not */ 253 254 #define MAX_IO_APIC 32 /* maximum # of IOAPICs supported */ 255 256 struct apic_io_intr { 257 uint_t intr_entry: 8, 258 intr_type: 8, 259 intr_po: 2, 260 intr_el: 2, 261 intr_resv: 12; 262 263 uint_t intr_busid: 8, 264 intr_irq: 8, 265 intr_destid: 8, 266 intr_destintin: 8; 267 }; 268 269 /* 270 * intr_type definitions 271 */ 272 #define IO_INTR_INT 0x00 273 #define IO_INTR_NMI 0x01 274 #define IO_INTR_SMI 0x02 275 #define IO_INTR_EXTINT 0x03 276 277 /* 278 * destination APIC ID 279 */ 280 #define INTR_ALL_APIC 0xff 281 282 283 /* local vector table */ 284 #define AV_MASK 0x10000 285 286 /* interrupt command register 32-63 */ 287 #define AV_TOALL 0x7fffffff 288 #define AV_HIGH_ORDER 0x40000000 289 #define AV_IM_OFF 0x40000000 290 291 /* interrupt command register 0-31 */ 292 #define AV_FIXED 0x000 293 #define AV_LOPRI 0x100 294 #define AV_REMOTE 0x300 295 #define AV_NMI 0x400 296 #define AV_RESET 0x500 297 #define AV_STARTUP 0x600 298 #define AV_EXTINT 0x700 299 300 #define AV_PDEST 0x000 301 #define AV_LDEST 0x800 302 303 /* IO & Local APIC Bit Definitions */ 304 #define RDT_VECTOR(x) ((uchar_t)((x) & 0xFF)) 305 #define AV_PENDING 0x1000 306 #define AV_ACTIVE_LOW 0x2000 /* only for integrated APIC */ 307 #define AV_REMOTE_IRR 0x4000 /* IOAPIC RDT-specific */ 308 #define AV_LEVEL 0x8000 309 #define AV_DEASSERT AV_LEVEL 310 #define AV_ASSERT 0xc000 311 312 #define AV_READ_PENDING 0x10000 313 #define AV_REMOTE_STATUS 0x20000 /* 1 = valid, 0 = invalid */ 314 315 #define AV_SH_SELF 0x40000 /* Short hand for self */ 316 #define AV_SH_ALL_INCSELF 0x80000 /* All processors */ 317 #define AV_SH_ALL_EXCSELF 0xc0000 /* All excluding self */ 318 /* spurious interrupt vector register */ 319 #define AV_UNIT_ENABLE 0x100 320 321 /* timer vector table */ 322 #define AV_TIME 0x20000 /* Set timer mode to periodic */ 323 324 #define APIC_MAXVAL 0xffffffffUL 325 #define APIC_TIME_MIN 0x5000 326 #define APIC_TIME_COUNT 0x4000 327 328 /* 329 * Range of the low byte value in apic_tick before starting calibration 330 */ 331 #define APIC_LB_MIN 0x60 332 #define APIC_LB_MAX 0xe0 333 334 #define APIC_MAX_VECTOR 255 335 #define APIC_RESV_VECT 0x00 336 #define APIC_RESV_IRQ 0xfe 337 #define APIC_BASE_VECT 0x20 /* This will come in as interrupt 0 */ 338 #define APIC_AVAIL_VECTOR (APIC_MAX_VECTOR+1-APIC_BASE_VECT) 339 #define APIC_VECTOR_PER_IPL 0x10 /* # of vectors before PRI changes */ 340 #define APIC_VECTOR(ipl) (apic_ipltopri[ipl] | APIC_RESV_VECT) 341 #define APIC_VECTOR_MASK 0x0f 342 #define APIC_HI_PRI_VECTS 2 /* vects reserved for hi pri reqs */ 343 #define APIC_IPL_MASK 0xf0 344 #define APIC_IPL_SHIFT 4 /* >> to get ipl part of vector */ 345 #define APIC_FIRST_FREE_IRQ 0x10 346 #define APIC_MAX_ISA_IRQ 15 347 #define APIC_IPL0 0x0f /* let IDLE_IPL be the lowest */ 348 #define APIC_IDLE_IPL 0x00 349 350 #define APIC_MASK_ALL 0xf0 /* Mask all interrupts */ 351 352 /* spurious interrupt vector */ 353 #define APIC_SPUR_INTR 0xFF 354 355 /* special or reserve vectors */ 356 #define APIC_CHECK_RESERVE_VECTORS(v) \ 357 (((v) == T_FASTTRAP) || ((v) == APIC_SPUR_INTR) || \ 358 ((v) == T_SYSCALLINT) || ((v) == T_DTRACE_RET) || ((v) == T_INT80)) 359 360 /* cmos shutdown code for BIOS */ 361 #define BIOS_SHUTDOWN 0x0a 362 363 /* define the entry types for BIOS information tables as defined in PC+MP */ 364 #define APIC_CPU_ENTRY 0 365 #define APIC_BUS_ENTRY 1 366 #define APIC_IO_ENTRY 2 367 #define APIC_IO_INTR_ENTRY 3 368 #define APIC_LOCAL_INTR_ENTRY 4 369 #define APIC_MPTBL_ADDR (639 * 1024) 370 /* 371 * The MP Floating Point structure could be in 1st 1KB of EBDA or last KB 372 * of system base memory or in ROM between 0xF0000 and 0xFFFFF 373 */ 374 #define MPFPS_RAM_WIN_LEN 1024 375 #define MPFPS_ROM_WIN_START (uint32_t)0xf0000 376 #define MPFPS_ROM_WIN_LEN 0x10000 377 378 #define EISA_LEVEL_CNTL 0x4D0 379 380 /* definitions for apic_irq_table */ 381 #define FREE_INDEX (short)-1 /* empty slot */ 382 #define RESERVE_INDEX (short)-2 /* ipi, softintr, clkintr */ 383 #define ACPI_INDEX (short)-3 /* ACPI */ 384 #define MSI_INDEX (short)-4 /* MSI */ 385 #define MSIX_INDEX (short)-5 /* MSI-X */ 386 #define DEFAULT_INDEX (short)0x7FFF 387 /* biggest positive no. to avoid conflict with actual index */ 388 389 #define APIC_IS_MSI_OR_MSIX_INDEX(index) \ 390 ((index) == MSI_INDEX || (index) == MSIX_INDEX) 391 392 /* 393 * definitions for MSI Address 394 */ 395 #define MSI_ADDR_HDR APIC_LOCAL_ADDR 396 #define MSI_ADDR_DEST_SHIFT 12 /* Destination CPU's apic id */ 397 #define MSI_ADDR_RH_FIXED 0x0 /* Redirection Hint Fixed */ 398 #define MSI_ADDR_RH_LOPRI 0x1 /* Redirection Hint Lowest priority */ 399 #define MSI_ADDR_RH_SHIFT 3 400 #define MSI_ADDR_DM_PHYSICAL 0x0 /* Physical Destination Mode */ 401 #define MSI_ADDR_DM_LOGICAL 0x1 /* Logical Destination Mode */ 402 #define MSI_ADDR_DM_SHIFT 2 403 404 /* 405 * definitions for MSI Data 406 */ 407 #define MSI_DATA_DELIVERY_FIXED 0x0 /* Fixed delivery */ 408 #define MSI_DATA_DELIVERY_LOPRI 0x1 /* Lowest priority delivery */ 409 #define MSI_DATA_DELIVERY_SMI 0x2 410 #define MSI_DATA_DELIVERY_NMI 0x4 411 #define MSI_DATA_DELIVERY_INIT 0x5 412 #define MSI_DATA_DELIVERY_EXTINT 0x7 413 #define MSI_DATA_DELIVERY_SHIFT 8 414 #define MSI_DATA_TM_EDGE 0x0 /* MSI is edge sensitive */ 415 #define MSI_DATA_TM_LEVEL 0x1 /* level sensitive */ 416 #define MSI_DATA_TM_SHIFT 15 417 #define MSI_DATA_LEVEL_DEASSERT 0x0 418 #define MSI_DATA_LEVEL_ASSERT 0x1 /* Edge always assert */ 419 #define MSI_DATA_LEVEL_SHIFT 14 420 421 /* 422 * use to define each irq setup by the apic 423 */ 424 typedef struct apic_irq { 425 short airq_mps_intr_index; /* index into mps interrupt entries */ 426 /* table */ 427 uchar_t airq_intin_no; 428 uchar_t airq_ioapicindex; 429 dev_info_t *airq_dip; /* device corresponding to this interrupt */ 430 /* 431 * IRQ could be shared (in H/W) in which case dip & major will be 432 * for the one that was last added at this level. We cannot keep a 433 * linked list as delspl does not tell us which device has just 434 * been unloaded. For most servers where we are worried about 435 * performance, interrupt should not be shared & should not be 436 * a problem. This does not cause any correctness issue - dip is 437 * used only as an optimisation to avoid going thru all the tables 438 * in translate IRQ (which is always called twice due to brokenness 439 * in the way IPLs are determined for devices). major is used only 440 * to bind interrupts corresponding to the same device on the same 441 * CPU. Not finding major will just cause it to be potentially bound 442 * to another CPU. 443 */ 444 major_t airq_major; /* major number corresponding to the device */ 445 ushort_t airq_rdt_entry; /* level, polarity & trig mode */ 446 uchar_t airq_cpu; /* Which CPU are we bound to ? */ 447 uchar_t airq_temp_cpu; /* Could be diff from cpu due to disable_intr */ 448 uchar_t airq_vector; /* Vector chosen for this irq */ 449 uchar_t airq_share; /* number of interrupts at this irq */ 450 uchar_t airq_share_id; /* id to identify source from irqno */ 451 uchar_t airq_ipl; /* The ipl at which this is handled */ 452 iflag_t airq_iflag; /* interrupt flag */ 453 uchar_t airq_origirq; /* original irq passed in */ 454 uint_t airq_busy; /* How frequently did clock find */ 455 /* us in this */ 456 struct apic_irq *airq_next; /* chain of shared intpts */ 457 } apic_irq_t; 458 459 #define IRQ_USER_BOUND 0x80 /* user requested bind if set in airq_cpu */ 460 #define IRQ_UNBOUND (uchar_t)-1 /* set in airq_cpu and airq_temp_cpu */ 461 #define IRQ_UNINIT (uchar_t)-2 /* in airq_temp_cpu till addspl called */ 462 463 /* Macros to help deal with shared interrupts */ 464 #define VIRTIRQ(irqno, share_id) ((irqno) | ((share_id) << 8)) 465 #define IRQINDEX(irq) ((irq) & 0xFF) /* Mask to get irq from virtual irq */ 466 467 typedef struct apic_cpus_info { 468 uchar_t aci_local_id; 469 uchar_t aci_local_ver; 470 uchar_t aci_status; 471 uchar_t aci_redistribute; /* Selected for redistribution */ 472 uint_t aci_busy; /* Number of ticks we were in ISR */ 473 uint_t aci_spur_cnt; /* # of spurious intpts on this cpu */ 474 uint_t aci_ISR_in_progress; /* big enough to hold 1 << MAXIPL */ 475 uchar_t aci_curipl; /* IPL of current ISR */ 476 uchar_t aci_current[MAXIPL]; /* Current IRQ at each IPL */ 477 uint32_t aci_bound; /* # of user requested binds ? */ 478 uint32_t aci_temp_bound; /* # of non user IRQ binds */ 479 uchar_t aci_idle; /* The CPU is idle */ 480 /* 481 * fill to make sure each struct is in seperate cache line. 482 * Or atleast that ISR_in_progress/curipl is not shared with something 483 * that is read/written heavily by another CPU. 484 * Given kmem_alloc guarantees alignment to 8 bytes, having 8 485 * bytes on each side will isolate us in a 16 byte cache line. 486 */ 487 } apic_cpus_info_t; 488 489 #define APIC_CPU_ONLINE 1 490 #define APIC_CPU_INTR_ENABLE 2 491 492 /* 493 * Various poweroff methods and ports & bits for them 494 */ 495 #define APIC_POWEROFF_NONE 0 496 #define APIC_POWEROFF_VIA_RTC 1 497 #define APIC_POWEROFF_VIA_ASPEN_BMC 2 498 #define APIC_POWEROFF_VIA_SITKA_BMC 3 499 500 /* For RTC */ 501 #define RTC_REGA 0x0a 502 #define PFR_REG 0x4a /* extended control register */ 503 #define PAB_CBIT 0x08 504 #define WF_FLAG 0x02 505 #define KS_FLAG 0x01 506 #define EXT_BANK 0x10 507 508 /* For Aspen/Drake BMC */ 509 510 #define CC_SMS_GET_STATUS 0x40 511 #define CC_SMS_WR_START 0x41 512 #define CC_SMS_WR_NEXT 0x42 513 #define CC_SMS_WR_END 0x43 514 515 #define MISMIC_DATA_REGISTER 0x0ca9 516 #define MISMIC_CNTL_REGISTER 0x0caa 517 #define MISMIC_FLAG_REGISTER 0x0cab 518 519 #define MISMIC_BUSY_MASK 0x01 520 521 /* For Sitka/Cabrillo BMC */ 522 523 #define SMS_GET_STATUS 0x60 524 #define SMS_WRITE_START 0x61 525 #define SMS_WRITE_END 0x62 526 527 #define SMS_DATA_REGISTER 0x0ca2 528 #define SMS_STATUS_REGISTER 0x0ca3 529 #define SMS_COMMAND_REGISTER 0x0ca3 530 531 #define SMS_IBF_MASK 0x02 532 #define SMS_STATE_MASK 0xc0 533 534 #define SMS_IDLE_STATE 0x00 535 #define SMS_READ_STATE 0x40 536 #define SMS_WRITE_STATE 0x80 537 #define SMS_ERROR_STATE 0xc0 538 539 extern uint32_t ioapic_read(int ioapic_ix, uint32_t reg); 540 extern void ioapic_write(int ioapic_ix, uint32_t reg, uint32_t value); 541 542 /* Macros for reading/writing the IOAPIC RDT entries */ 543 #define READ_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin) \ 544 ioapic_read(ioapic_ix, APIC_RDT_CMD + (2 * (ipin))) 545 546 #define READ_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin) \ 547 ioapic_read(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin))) 548 549 #define WRITE_IOAPIC_RDT_ENTRY_LOW_DWORD(ioapic_ix, ipin, value) \ 550 ioapic_write(ioapic_ix, APIC_RDT_CMD + (2 * (ipin)), value) 551 552 #define WRITE_IOAPIC_RDT_ENTRY_HIGH_DWORD(ioapic_ix, ipin, value) \ 553 ioapic_write(ioapic_ix, APIC_RDT_CMD2 + (2 * (ipin)), value) 554 555 /* Used by PSM_INTR_OP_GET_INTR to return device information. */ 556 typedef struct { 557 uint16_t avgi_req_flags; /* request flags - to kernel */ 558 uint8_t avgi_num_devs; /* # devs on this ino - from kernel */ 559 uint8_t avgi_vector; /* vector */ 560 uint32_t avgi_cpu_id; /* cpu of interrupt - from kernel */ 561 dev_info_t **avgi_dip_list; /* kmem_alloc'ed list of dev_infos. */ 562 /* Contains num_devs elements. */ 563 } apic_get_intr_t; 564 565 /* Masks for avgi_req_flags. */ 566 #define PSMGI_REQ_CPUID 0x1 /* Request CPU ID */ 567 #define PSMGI_REQ_NUM_DEVS 0x2 /* Request num of devices on vector */ 568 #define PSMGI_REQ_VECTOR 0x4 569 #define PSMGI_REQ_GET_DEVS 0x8 /* Request device list */ 570 #define PSMGI_REQ_ALL 0xf /* Request everything */ 571 572 /* Other flags */ 573 #define PSMGI_INTRBY_VEC 0 /* Vec passed. xlate to IRQ needed */ 574 #define PSMGI_INTRBY_IRQ 0x8000 /* IRQ passed. no xlate needed */ 575 #define PSMGI_INTRBY_FLAGS 0x8000 /* Mask for this flag */ 576 577 /* 578 * Use scaled-fixed-point arithmetic to calculate apic ticks. 579 * Round when dividing (by adding half of divisor to dividend) 580 * for one extra bit of precision. 581 */ 582 583 #define SF (1ULL<<20) /* Scaling Factor: scale by 2^20 */ 584 #define APIC_TICKS_TO_NSECS(ticks) ((((int64_t)(ticks) * SF) + \ 585 apic_ticks_per_SFnsecs / 2) / \ 586 apic_ticks_per_SFnsecs); 587 #define APIC_NSECS_TO_TICKS(nsecs) (((int64_t)(nsecs) * \ 588 apic_ticks_per_SFnsecs + (SF/2)) / SF) 589 590 extern int apic_verbose; 591 592 /* Flag definitions for apic_verbose */ 593 #define APIC_VERBOSE_IOAPIC_FLAG 0x00000001 594 #define APIC_VERBOSE_IRQ_FLAG 0x00000002 595 #define APIC_VERBOSE_POWEROFF_FLAG 0x00000004 596 #define APIC_VERBOSE_POWEROFF_PAUSE_FLAG 0x00000008 597 598 599 #define APIC_VERBOSE_IOAPIC(fmt) \ 600 if (apic_verbose & APIC_VERBOSE_IOAPIC_FLAG) \ 601 cmn_err fmt; 602 603 #define APIC_VERBOSE_IRQ(fmt) \ 604 if (apic_verbose & APIC_VERBOSE_IRQ_FLAG) \ 605 cmn_err fmt; 606 607 #define APIC_VERBOSE_POWEROFF(fmt) \ 608 if (apic_verbose & APIC_VERBOSE_POWEROFF_FLAG) \ 609 prom_printf fmt; 610 611 #ifdef DEBUG 612 #define DENT 0x0001 613 extern int apic_debug; 614 /* 615 * set apic_restrict_vector to the # of vectors we want to allow per range 616 * useful in testing shared interrupt logic by setting it to 2 or 3 617 */ 618 extern int apic_restrict_vector; 619 620 #define APIC_DEBUG_MSGBUFSIZE 2048 621 extern int apic_debug_msgbuf[]; 622 extern int apic_debug_msgbufindex; 623 624 /* 625 * Put "int" info into debug buffer. No MP consistency, but light weight. 626 * Good enough for most debugging. 627 */ 628 #define APIC_DEBUG_BUF_PUT(x) \ 629 apic_debug_msgbuf[apic_debug_msgbufindex++] = x; \ 630 if (apic_debug_msgbufindex >= (APIC_DEBUG_MSGBUFSIZE - NCPU)) \ 631 apic_debug_msgbufindex = 0; 632 633 #endif /* DEBUG */ 634 635 extern int apic_error; 636 /* values which apic_error can take. Not catastrophic, but may help debug */ 637 #define APIC_ERR_BOOT_EOI 0x1 638 #define APIC_ERR_GET_IPIVECT_FAIL 0x2 639 #define APIC_ERR_INVALID_INDEX 0x4 640 #define APIC_ERR_MARK_VECTOR_FAIL 0x8 641 #define APIC_ERR_APIC_ERROR 0x40000000 642 #define APIC_ERR_NMI 0x80000000 643 644 /* 645 * ACPI definitions 646 */ 647 /* _PIC method arguments */ 648 #define ACPI_PIC_MODE 0 649 #define ACPI_APIC_MODE 1 650 651 /* APIC error flags we care about */ 652 #define APIC_SEND_CS_ERROR 0x01 653 #define APIC_RECV_CS_ERROR 0x02 654 #define APIC_CS_ERRORS (APIC_SEND_CS_ERROR|APIC_RECV_CS_ERROR) 655 656 /* Maximum number of times to retry reprogramming at apic_intr_exit time */ 657 #define APIC_REPROGRAM_MAX_TRIES 10000 658 659 /* Parameter to ioapic_init_intr(): Should ioapic ints be masked? */ 660 #define IOAPIC_MASK 1 661 #define IOAPIC_NOMASK 0 662 663 #define INTR_ROUND_ROBIN_WITH_AFFINITY 0 664 #define INTR_ROUND_ROBIN 1 665 #define INTR_LOWEST_PRIORITY 2 666 667 668 669 struct ioapic_reprogram_data { 670 boolean_t done; 671 apic_irq_t *irqp; 672 /* The CPU to which the int will be bound */ 673 int bindcpu; 674 /* # times the reprogram timeout was called */ 675 unsigned tries; 676 }; 677 678 /* The irq # is implicit in the array index: */ 679 extern struct ioapic_reprogram_data apic_reprogram_info[]; 680 681 extern void apic_intr_exit(int ipl, int irq); 682 extern int apic_probe_common(); 683 extern void apic_init_common(); 684 extern void ioapic_init_intr(); 685 extern void ioapic_disable_redirection(); 686 extern int apic_addspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 687 extern int apic_delspl_common(int irqno, int ipl, int min_ipl, int max_ipl); 688 extern void apic_cleanup_busy(); 689 extern void apic_intr_redistribute(); 690 extern uchar_t apic_xlate_vector(uchar_t vector); 691 extern uchar_t apic_allocate_vector(int ipl, int irq, int pri); 692 extern void apic_free_vector(uchar_t vector); 693 extern int apic_allocate_irq(int irq); 694 extern uchar_t apic_bind_intr(dev_info_t *dip, int irq, uchar_t ioapicid, 695 uchar_t intin); 696 extern int apic_rebind(apic_irq_t *irq_ptr, int bind_cpu, 697 struct ioapic_reprogram_data *drep); 698 extern int apic_rebind_all(apic_irq_t *irq_ptr, int bind_cpu); 699 extern int apic_introp_xlate(dev_info_t *dip, struct intrspec *ispec, int type); 700 extern int apic_intr_ops(dev_info_t *dip, ddi_intr_handle_impl_t *hdlp, 701 psm_intr_op_t intr_op, int *result); 702 extern int apic_state(psm_state_request_t *); 703 extern boolean_t apic_cpu_in_range(int cpu); 704 extern int apic_check_msi_support(); 705 extern apic_irq_t *apic_find_irq(dev_info_t *dip, struct intrspec *ispec, 706 int type); 707 extern int apic_navail_vector(dev_info_t *dip, int pri); 708 extern int apic_alloc_msi_vectors(dev_info_t *dip, int inum, int count, 709 int pri, int behavior); 710 extern int apic_alloc_msix_vectors(dev_info_t *dip, int inum, int count, 711 int pri, int behavior); 712 extern void apic_free_vectors(dev_info_t *dip, int inum, int count, int pri, 713 int type); 714 extern int apic_get_vector_intr_info(int vecirq, 715 apic_get_intr_t *intr_params_p); 716 extern uchar_t apic_find_multi_vectors(int pri, int count); 717 extern int apic_setup_io_intr(void *p, int irq, boolean_t deferred); 718 extern uint32_t *mapin_apic(uint32_t addr, size_t len, int flags); 719 extern uint32_t *mapin_ioapic(uint32_t addr, size_t len, int flags); 720 extern void mapout_apic(caddr_t addr, size_t len); 721 extern void mapout_ioapic(caddr_t addr, size_t len); 722 extern uchar_t apic_modify_vector(uchar_t vector, int irq); 723 extern void apic_pci_msi_unconfigure(dev_info_t *rdip, int type, int inum); 724 extern void apic_pci_msi_disable_mode(dev_info_t *rdip, int type); 725 extern void apic_pci_msi_enable_mode(dev_info_t *rdip, int type, int inum); 726 extern void apic_pci_msi_enable_vector(dev_info_t *dip, int type, int inum, 727 int vector, int count, int target_apic_id); 728 extern char *apic_get_apic_type(); 729 extern uint16_t apic_get_apic_version(); 730 731 extern volatile uint32_t *apicadr; /* virtual addr of local APIC */ 732 extern int apic_forceload; 733 extern apic_cpus_info_t *apic_cpus; 734 #ifdef _MACHDEP 735 extern cpuset_t apic_cpumask; 736 #endif 737 extern uint_t apic_picinit_called; 738 extern uchar_t apic_ipltopri[MAXIPL+1]; 739 extern uchar_t apic_vector_to_irq[APIC_MAX_VECTOR+1]; 740 extern int apic_max_device_irq; 741 extern int apic_min_device_irq; 742 extern apic_irq_t *apic_irq_table[APIC_MAX_VECTOR+1]; 743 extern volatile uint32_t *apicioadr[MAX_IO_APIC]; 744 extern uchar_t apic_io_id[MAX_IO_APIC]; 745 extern lock_t apic_ioapic_lock; 746 extern uint32_t apic_physaddr[MAX_IO_APIC]; 747 extern kmutex_t airq_mutex; 748 extern int apic_first_avail_irq; 749 extern uchar_t apic_vectortoipl[APIC_AVAIL_VECTOR / APIC_VECTOR_PER_IPL]; 750 extern int apic_imcrp; 751 extern int apic_revector_pending; 752 extern char apic_level_intr[APIC_MAX_VECTOR+1]; 753 extern uchar_t apic_resv_vector[MAXIPL+1]; 754 extern int apic_sample_factor_redistribution; 755 extern int apic_int_busy_mark; 756 extern int apic_int_free_mark; 757 extern int apic_diff_for_redistribution; 758 extern int apic_poweroff_method; 759 extern int apic_enable_acpi; 760 extern int apic_nproc; 761 extern int apic_next_bind_cpu; 762 extern int apic_redistribute_sample_interval; 763 extern int apic_multi_msi_enable; 764 extern int apic_multi_msi_max; 765 extern int apic_msix_max; 766 extern int apic_sci_vect; 767 extern uchar_t apic_ipls[]; 768 769 770 #ifdef __cplusplus 771 } 772 #endif 773 774 #endif /* _SYS_APIC_APIC_H */ 775