xref: /titanic_44/usr/src/uts/i86pc/os/pci_cfgspace.c (revision 0db3240d392634cfff2f95fb6da34b56b8dc574f)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 
22 /*
23  * Copyright 2010 Sun Microsystems, Inc.  All rights reserved.
24  * Use is subject to license terms.
25  */
26 
27 /*
28  * PCI configuration space access routines
29  */
30 
31 #include <sys/systm.h>
32 #include <sys/psw.h>
33 #include <sys/bootconf.h>
34 #include <sys/reboot.h>
35 #include <sys/pci_impl.h>
36 #include <sys/pci_cfgspace.h>
37 #include <sys/pci_cfgspace_impl.h>
38 #include <sys/pci_cfgacc.h>
39 #if defined(__xpv)
40 #include <sys/hypervisor.h>
41 #endif
42 
43 #if defined(__xpv)
44 int pci_max_nbus = 0xFE;
45 #endif
46 int pci_bios_cfg_type = PCI_MECHANISM_UNKNOWN;
47 int pci_bios_maxbus;
48 int pci_bios_mech;
49 int pci_bios_vers;
50 
51 /*
52  * These two variables can be used to force a configuration mechanism or
53  * to force which function is used to probe for the presence of the PCI bus.
54  */
55 int	PCI_CFG_TYPE = 0;
56 int	PCI_PROBE_TYPE = 0;
57 
58 /*
59  * No valid mcfg_mem_base by default, and accessing pci config space
60  * in mem-mapped way is disabled.
61  */
62 uint64_t mcfg_mem_base = 0;
63 uint8_t mcfg_bus_start = 0;
64 uint8_t mcfg_bus_end = 0xff;
65 
66 /*
67  * These function pointers lead to the actual implementation routines
68  * for configuration space access.  Normally they lead to either the
69  * pci_mech1_* or pci_mech2_* routines, but they can also lead to
70  * routines that work around chipset bugs.
71  * These functions are accessing pci config space via I/O way.
72  * Pci_cfgacc_get/put functions shoul be used as more common interfaces,
73  * which also provide accessing pci config space via mem-mapped way.
74  */
75 uint8_t (*pci_getb_func)(int bus, int dev, int func, int reg);
76 uint16_t (*pci_getw_func)(int bus, int dev, int func, int reg);
77 uint32_t (*pci_getl_func)(int bus, int dev, int func, int reg);
78 void (*pci_putb_func)(int bus, int dev, int func, int reg, uint8_t val);
79 void (*pci_putw_func)(int bus, int dev, int func, int reg, uint16_t val);
80 void (*pci_putl_func)(int bus, int dev, int func, int reg, uint32_t val);
81 
82 extern void (*pci_cfgacc_acc_p)(pci_cfgacc_req_t *req);
83 
84 /*
85  * Internal routines
86  */
87 static int pci_check(void);
88 
89 #if !defined(__xpv)
90 static int pci_check_bios(void);
91 static int pci_get_cfg_type(void);
92 #endif
93 
94 /* for legacy io-based config space access */
95 kmutex_t pcicfg_mutex;
96 
97 /* for mmio-based config space access */
98 kmutex_t pcicfg_mmio_mutex;
99 
100 /* ..except Orion and Neptune, which have to have their own */
101 kmutex_t pcicfg_chipset_mutex;
102 
103 void
104 pci_cfgspace_init(void)
105 {
106 	mutex_init(&pcicfg_mutex, NULL, MUTEX_SPIN,
107 	    (ddi_iblock_cookie_t)ipltospl(15));
108 	mutex_init(&pcicfg_mmio_mutex, NULL, MUTEX_SPIN,
109 	    (ddi_iblock_cookie_t)ipltospl(DISP_LEVEL));
110 	mutex_init(&pcicfg_chipset_mutex, NULL, MUTEX_SPIN,
111 	    (ddi_iblock_cookie_t)ipltospl(15));
112 	if (!pci_check()) {
113 		mutex_destroy(&pcicfg_mutex);
114 		mutex_destroy(&pcicfg_mmio_mutex);
115 		mutex_destroy(&pcicfg_chipset_mutex);
116 	}
117 }
118 
119 /*
120  * This code determines if this system supports PCI/PCIE and which
121  * type of configuration access method is used
122  */
123 static int
124 pci_check(void)
125 {
126 	uint64_t ecfginfo[4];
127 
128 	/*
129 	 * Only do this once.  NB:  If this is not a PCI system, and we
130 	 * get called twice, we can't detect it and will probably die
131 	 * horribly when we try to ask the BIOS whether PCI is present.
132 	 * This code is safe *ONLY* during system startup when the
133 	 * BIOS is still available.
134 	 */
135 	if (pci_bios_cfg_type != PCI_MECHANISM_UNKNOWN)
136 		return (TRUE);
137 
138 #if defined(__xpv)
139 	/*
140 	 * only support PCI config mechanism 1 in i86xpv. This should be fine
141 	 * since the other ones are workarounds for old broken H/W which won't
142 	 * be supported in i86xpv anyway.
143 	 */
144 	if (DOMAIN_IS_INITDOMAIN(xen_info)) {
145 		pci_bios_cfg_type = PCI_MECHANISM_1;
146 		pci_getb_func = pci_mech1_getb;
147 		pci_getw_func = pci_mech1_getw;
148 		pci_getl_func = pci_mech1_getl;
149 		pci_putb_func = pci_mech1_putb;
150 		pci_putw_func = pci_mech1_putw;
151 		pci_putl_func = pci_mech1_putl;
152 
153 		/*
154 		 * Since we can't get the BIOS info in i86xpv, we will do an
155 		 * exhaustive search of all PCI buses. We have to do this until
156 		 * we start using the PCI information in ACPI.
157 		 */
158 		pci_bios_maxbus = pci_max_nbus;
159 	}
160 #else /* !__xpv */
161 
162 	pci_bios_cfg_type = pci_check_bios();
163 
164 	if (pci_bios_cfg_type == PCI_MECHANISM_NONE)
165 		pci_bios_cfg_type = PCI_MECHANISM_1;	/* default to mech 1 */
166 
167 	switch (pci_get_cfg_type()) {
168 	case PCI_MECHANISM_1:
169 		if (pci_is_broken_orion()) {
170 			pci_getb_func = pci_orion_getb;
171 			pci_getw_func = pci_orion_getw;
172 			pci_getl_func = pci_orion_getl;
173 			pci_putb_func = pci_orion_putb;
174 			pci_putw_func = pci_orion_putw;
175 			pci_putl_func = pci_orion_putl;
176 		} else {
177 			pci_getb_func = pci_mech1_getb;
178 			pci_getw_func = pci_mech1_getw;
179 			pci_getl_func = pci_mech1_getl;
180 			pci_putb_func = pci_mech1_putb;
181 			pci_putw_func = pci_mech1_putw;
182 			pci_putl_func = pci_mech1_putl;
183 		}
184 		break;
185 
186 	case PCI_MECHANISM_2:
187 		if (pci_check_neptune()) {
188 			/*
189 			 * The BIOS for some systems with the Intel
190 			 * Neptune chipset seem to default to #2 even
191 			 * though the chipset can do #1.  Override
192 			 * the BIOS so that MP systems will work
193 			 * correctly.
194 			 */
195 
196 			pci_getb_func = pci_neptune_getb;
197 			pci_getw_func = pci_neptune_getw;
198 			pci_getl_func = pci_neptune_getl;
199 			pci_putb_func = pci_neptune_putb;
200 			pci_putw_func = pci_neptune_putw;
201 			pci_putl_func = pci_neptune_putl;
202 		} else {
203 			pci_getb_func = pci_mech2_getb;
204 			pci_getw_func = pci_mech2_getw;
205 			pci_getl_func = pci_mech2_getl;
206 			pci_putb_func = pci_mech2_putb;
207 			pci_putw_func = pci_mech2_putw;
208 			pci_putl_func = pci_mech2_putl;
209 		}
210 		break;
211 
212 	default:
213 		return (FALSE);
214 	}
215 #endif /* __xpv */
216 
217 	/*
218 	 * Try to get a valid mcfg_mem_base in early boot
219 	 * If failed, leave mem-mapped pci config space accessing disabled
220 	 * until pci boot code (pci_autoconfig) makes sure this is a PCIE
221 	 * platform.
222 	 */
223 	if (do_bsys_getprop(NULL, MCFG_PROPNAME, ecfginfo) != -1) {
224 		mcfg_mem_base = ecfginfo[0];
225 		mcfg_bus_start = ecfginfo[2];
226 		mcfg_bus_end = ecfginfo[3];
227 	}
228 
229 	/* See pci_cfgacc.c */
230 	pci_cfgacc_acc_p = pci_cfgacc_acc;
231 
232 	return (TRUE);
233 }
234 
235 #if !defined(__xpv)
236 
237 static int
238 pci_check_bios(void)
239 {
240 	struct bop_regs regs;
241 	uint32_t	carryflag;
242 	uint16_t	ax, dx;
243 
244 	bzero(&regs, sizeof (regs));
245 	regs.eax.word.ax = (PCI_FUNCTION_ID << 8) | PCI_BIOS_PRESENT;
246 
247 	BOP_DOINT(bootops, 0x1a, &regs);
248 	carryflag = regs.eflags & PS_C;
249 	ax = regs.eax.word.ax;
250 	dx = regs.edx.word.dx;
251 
252 	/* the carry flag must not be set */
253 	if (carryflag != 0)
254 		return (PCI_MECHANISM_NONE);
255 
256 	if (dx != ('P' | 'C'<<8))
257 		return (PCI_MECHANISM_NONE);
258 
259 	/* ah (the high byte of ax) must be zero */
260 	if ((ax & 0xff00) != 0)
261 		return (PCI_MECHANISM_NONE);
262 
263 	pci_bios_mech = (ax & 0x3);
264 	pci_bios_vers = regs.ebx.word.bx;
265 	pci_bios_maxbus = (regs.ecx.word.cx & 0xff);
266 
267 	switch (pci_bios_mech) {
268 	default:	/* ?!? */
269 	case 0:		/* supports neither? */
270 		return (PCI_MECHANISM_NONE);
271 
272 	case 1:
273 	case 3:		/* supports both */
274 		return (PCI_MECHANISM_1);
275 
276 	case 2:
277 		return (PCI_MECHANISM_2);
278 	}
279 }
280 
281 static int
282 pci_get_cfg_type(void)
283 {
284 	/* Check to see if the config mechanism has been set in /etc/system */
285 	switch (PCI_CFG_TYPE) {
286 	default:
287 	case 0:
288 		break;
289 	case 1:
290 		return (PCI_MECHANISM_1);
291 	case 2:
292 		return (PCI_MECHANISM_2);
293 	case -1:
294 		return (PCI_MECHANISM_NONE);
295 	}
296 
297 	/* call one of the PCI detection algorithms */
298 	switch (PCI_PROBE_TYPE) {
299 	default:
300 	case 0:
301 		/* From pci_check() and pci_check_bios() */
302 		return (pci_bios_cfg_type);
303 	case -1:
304 		return (PCI_MECHANISM_NONE);
305 	}
306 }
307 
308 #endif	/* __xpv */
309