1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22 /* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27 #pragma ident "%Z%%M% %I% %E% SMI" 28 29 #include <sys/types.h> 30 #include <sys/thread.h> 31 #include <sys/cpuvar.h> 32 #include <sys/t_lock.h> 33 #include <sys/param.h> 34 #include <sys/proc.h> 35 #include <sys/disp.h> 36 #include <sys/class.h> 37 #include <sys/cmn_err.h> 38 #include <sys/debug.h> 39 #include <sys/asm_linkage.h> 40 #include <sys/x_call.h> 41 #include <sys/systm.h> 42 #include <sys/var.h> 43 #include <sys/vtrace.h> 44 #include <vm/hat.h> 45 #include <vm/as.h> 46 #include <vm/seg_kmem.h> 47 #include <vm/seg_kp.h> 48 #include <sys/segments.h> 49 #include <sys/kmem.h> 50 #include <sys/stack.h> 51 #include <sys/smp_impldefs.h> 52 #include <sys/x86_archext.h> 53 #include <sys/machsystm.h> 54 #include <sys/traptrace.h> 55 #include <sys/clock.h> 56 #include <sys/cpc_impl.h> 57 #include <sys/pg.h> 58 #include <sys/cmt.h> 59 #include <sys/dtrace.h> 60 #include <sys/archsystm.h> 61 #include <sys/fp.h> 62 #include <sys/reboot.h> 63 #include <sys/kdi_machimpl.h> 64 #include <vm/hat_i86.h> 65 #include <sys/memnode.h> 66 #include <sys/pci_cfgspace.h> 67 #include <sys/mach_mmu.h> 68 #include <sys/sysmacros.h> 69 #include <sys/cpu_module.h> 70 71 struct cpu cpus[1]; /* CPU data */ 72 struct cpu *cpu[NCPU] = {&cpus[0]}; /* pointers to all CPUs */ 73 cpu_core_t cpu_core[NCPU]; /* cpu_core structures */ 74 75 /* 76 * Useful for disabling MP bring-up on a MP capable system. 77 */ 78 int use_mp = 1; 79 80 /* 81 * to be set by a PSM to indicate what cpus 82 * are sitting around on the system. 83 */ 84 cpuset_t mp_cpus; 85 86 /* 87 * This variable is used by the hat layer to decide whether or not 88 * critical sections are needed to prevent race conditions. For sun4m, 89 * this variable is set once enough MP initialization has been done in 90 * order to allow cross calls. 91 */ 92 int flushes_require_xcalls; 93 cpuset_t cpu_ready_set = 1; 94 95 static void mp_startup(void); 96 97 static void cpu_sep_enable(void); 98 static void cpu_sep_disable(void); 99 static void cpu_asysc_enable(void); 100 static void cpu_asysc_disable(void); 101 102 extern int tsc_gethrtime_enable; 103 104 /* 105 * Init CPU info - get CPU type info for processor_info system call. 106 */ 107 void 108 init_cpu_info(struct cpu *cp) 109 { 110 processor_info_t *pi = &cp->cpu_type_info; 111 char buf[CPU_IDSTRLEN]; 112 113 /* 114 * Get clock-frequency property for the CPU. 115 */ 116 pi->pi_clock = cpu_freq; 117 118 (void) strcpy(pi->pi_processor_type, "i386"); 119 if (fpu_exists) 120 (void) strcpy(pi->pi_fputypes, "i387 compatible"); 121 122 (void) cpuid_getidstr(cp, buf, sizeof (buf)); 123 124 cp->cpu_idstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 125 (void) strcpy(cp->cpu_idstr, buf); 126 127 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_idstr); 128 129 (void) cpuid_getbrandstr(cp, buf, sizeof (buf)); 130 cp->cpu_brandstr = kmem_alloc(strlen(buf) + 1, KM_SLEEP); 131 (void) strcpy(cp->cpu_brandstr, buf); 132 133 cmn_err(CE_CONT, "?cpu%d: %s\n", cp->cpu_id, cp->cpu_brandstr); 134 } 135 136 /* 137 * Configure syscall support on this CPU. 138 */ 139 /*ARGSUSED*/ 140 static void 141 init_cpu_syscall(struct cpu *cp) 142 { 143 kpreempt_disable(); 144 145 #if defined(__amd64) 146 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) { 147 148 #if !defined(__lint) 149 /* 150 * The syscall instruction imposes a certain ordering on 151 * segment selectors, so we double-check that ordering 152 * here. 153 */ 154 ASSERT(KDS_SEL == KCS_SEL + 8); 155 ASSERT(UDS_SEL == U32CS_SEL + 8); 156 ASSERT(UCS_SEL == U32CS_SEL + 16); 157 #endif 158 /* 159 * Turn syscall/sysret extensions on. 160 */ 161 cpu_asysc_enable(); 162 163 /* 164 * Program the magic registers .. 165 */ 166 wrmsr(MSR_AMD_STAR, 167 ((uint64_t)(U32CS_SEL << 16 | KCS_SEL)) << 32); 168 wrmsr(MSR_AMD_LSTAR, (uint64_t)(uintptr_t)sys_syscall); 169 wrmsr(MSR_AMD_CSTAR, (uint64_t)(uintptr_t)sys_syscall32); 170 171 /* 172 * This list of flags is masked off the incoming 173 * %rfl when we enter the kernel. 174 */ 175 wrmsr(MSR_AMD_SFMASK, (uint64_t)(uintptr_t)(PS_IE | PS_T)); 176 } 177 #endif 178 179 /* 180 * On 32-bit kernels, we use sysenter/sysexit because it's too 181 * hard to use syscall/sysret, and it is more portable anyway. 182 * 183 * On 64-bit kernels on Nocona machines, the 32-bit syscall 184 * variant isn't available to 32-bit applications, but sysenter is. 185 */ 186 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) { 187 188 #if !defined(__lint) 189 /* 190 * The sysenter instruction imposes a certain ordering on 191 * segment selectors, so we double-check that ordering 192 * here. See "sysenter" in Intel document 245471-012, "IA-32 193 * Intel Architecture Software Developer's Manual Volume 2: 194 * Instruction Set Reference" 195 */ 196 ASSERT(KDS_SEL == KCS_SEL + 8); 197 198 ASSERT32(UCS_SEL == ((KCS_SEL + 16) | 3)); 199 ASSERT32(UDS_SEL == UCS_SEL + 8); 200 201 ASSERT64(U32CS_SEL == ((KCS_SEL + 16) | 3)); 202 ASSERT64(UDS_SEL == U32CS_SEL + 8); 203 #endif 204 205 cpu_sep_enable(); 206 207 /* 208 * resume() sets this value to the base of the threads stack 209 * via a context handler. 210 */ 211 wrmsr(MSR_INTC_SEP_ESP, 0); 212 wrmsr(MSR_INTC_SEP_EIP, (uint64_t)(uintptr_t)sys_sysenter); 213 } 214 215 kpreempt_enable(); 216 } 217 218 /* 219 * Multiprocessor initialization. 220 * 221 * Allocate and initialize the cpu structure, TRAPTRACE buffer, and the 222 * startup and idle threads for the specified CPU. 223 */ 224 struct cpu * 225 mp_startup_init(int cpun) 226 { 227 struct cpu *cp; 228 kthread_id_t tp; 229 caddr_t sp; 230 proc_t *procp; 231 extern void idle(); 232 233 #ifdef TRAPTRACE 234 trap_trace_ctl_t *ttc = &trap_trace_ctl[cpun]; 235 #endif 236 237 ASSERT(cpun < NCPU && cpu[cpun] == NULL); 238 239 cp = kmem_zalloc(sizeof (*cp), KM_SLEEP); 240 if (x86_feature & X86_MWAIT) 241 cp->cpu_m.mcpu_mwait = mach_alloc_mwait(CPU); 242 243 procp = curthread->t_procp; 244 245 mutex_enter(&cpu_lock); 246 /* 247 * Initialize the dispatcher first. 248 */ 249 disp_cpu_init(cp); 250 mutex_exit(&cpu_lock); 251 252 cpu_vm_data_init(cp); 253 254 /* 255 * Allocate and initialize the startup thread for this CPU. 256 * Interrupt and process switch stacks get allocated later 257 * when the CPU starts running. 258 */ 259 tp = thread_create(NULL, 0, NULL, NULL, 0, procp, 260 TS_STOPPED, maxclsyspri); 261 262 /* 263 * Set state to TS_ONPROC since this thread will start running 264 * as soon as the CPU comes online. 265 * 266 * All the other fields of the thread structure are setup by 267 * thread_create(). 268 */ 269 THREAD_ONPROC(tp, cp); 270 tp->t_preempt = 1; 271 tp->t_bound_cpu = cp; 272 tp->t_affinitycnt = 1; 273 tp->t_cpu = cp; 274 tp->t_disp_queue = cp->cpu_disp; 275 276 /* 277 * Setup thread to start in mp_startup. 278 */ 279 sp = tp->t_stk; 280 tp->t_pc = (uintptr_t)mp_startup; 281 tp->t_sp = (uintptr_t)(sp - MINFRAME); 282 #if defined(__amd64) 283 tp->t_sp -= STACK_ENTRY_ALIGN; /* fake a call */ 284 #endif 285 286 cp->cpu_id = cpun; 287 cp->cpu_self = cp; 288 cp->cpu_thread = tp; 289 cp->cpu_lwp = NULL; 290 cp->cpu_dispthread = tp; 291 cp->cpu_dispatch_pri = DISP_PRIO(tp); 292 293 /* 294 * cpu_base_spl must be set explicitly here to prevent any blocking 295 * operations in mp_startup from causing the spl of the cpu to drop 296 * to 0 (allowing device interrupts before we're ready) in resume(). 297 * cpu_base_spl MUST remain at LOCK_LEVEL until the cpu is CPU_READY. 298 * As an extra bit of security on DEBUG kernels, this is enforced with 299 * an assertion in mp_startup() -- before cpu_base_spl is set to its 300 * proper value. 301 */ 302 cp->cpu_base_spl = ipltospl(LOCK_LEVEL); 303 304 /* 305 * Now, initialize per-CPU idle thread for this CPU. 306 */ 307 tp = thread_create(NULL, PAGESIZE, idle, NULL, 0, procp, TS_ONPROC, -1); 308 309 cp->cpu_idle_thread = tp; 310 311 tp->t_preempt = 1; 312 tp->t_bound_cpu = cp; 313 tp->t_affinitycnt = 1; 314 tp->t_cpu = cp; 315 tp->t_disp_queue = cp->cpu_disp; 316 317 /* 318 * Bootstrap the CPU's PG data 319 */ 320 pg_cpu_bootstrap(cp); 321 322 /* 323 * Perform CPC initialization on the new CPU. 324 */ 325 kcpc_hw_init(cp); 326 327 /* 328 * Allocate virtual addresses for cpu_caddr1 and cpu_caddr2 329 * for each CPU. 330 */ 331 setup_vaddr_for_ppcopy(cp); 332 333 /* 334 * Allocate page for new GDT and initialize from current GDT. 335 */ 336 #if !defined(__lint) 337 ASSERT((sizeof (*cp->cpu_gdt) * NGDT) <= PAGESIZE); 338 #endif 339 cp->cpu_m.mcpu_gdt = kmem_zalloc(PAGESIZE, KM_SLEEP); 340 bcopy(CPU->cpu_m.mcpu_gdt, cp->cpu_m.mcpu_gdt, 341 (sizeof (*cp->cpu_m.mcpu_gdt) * NGDT)); 342 343 #if defined(__i386) 344 /* 345 * setup kernel %gs. 346 */ 347 set_usegd(&cp->cpu_gdt[GDT_GS], cp, sizeof (struct cpu) -1, SDT_MEMRWA, 348 SEL_KPL, 0, 1); 349 #endif 350 351 /* 352 * If we have more than one node, each cpu gets a copy of IDT 353 * local to its node. If this is a Pentium box, we use cpu 0's 354 * IDT. cpu 0's IDT has been made read-only to workaround the 355 * cmpxchgl register bug 356 */ 357 if (system_hardware.hd_nodes && x86_type != X86_TYPE_P5) { 358 struct machcpu *mcpu = &cp->cpu_m; 359 360 mcpu->mcpu_idt = kmem_alloc(sizeof (idt0), KM_SLEEP); 361 bcopy(idt0, mcpu->mcpu_idt, sizeof (idt0)); 362 } else { 363 cp->cpu_m.mcpu_idt = CPU->cpu_m.mcpu_idt; 364 } 365 366 /* 367 * Get interrupt priority data from cpu 0. 368 */ 369 cp->cpu_pri_data = CPU->cpu_pri_data; 370 371 /* 372 * alloc space for cpuid info 373 */ 374 cpuid_alloc_space(cp); 375 376 /* 377 * alloc space for ucode_info 378 */ 379 ucode_alloc_space(cp); 380 381 hat_cpu_online(cp); 382 383 #ifdef TRAPTRACE 384 /* 385 * If this is a TRAPTRACE kernel, allocate TRAPTRACE buffers 386 */ 387 ttc->ttc_first = (uintptr_t)kmem_zalloc(trap_trace_bufsize, KM_SLEEP); 388 ttc->ttc_next = ttc->ttc_first; 389 ttc->ttc_limit = ttc->ttc_first + trap_trace_bufsize; 390 #endif 391 /* 392 * Record that we have another CPU. 393 */ 394 mutex_enter(&cpu_lock); 395 /* 396 * Initialize the interrupt threads for this CPU 397 */ 398 cpu_intr_alloc(cp, NINTR_THREADS); 399 /* 400 * Add CPU to list of available CPUs. It'll be on the active list 401 * after mp_startup(). 402 */ 403 cpu_add_unit(cp); 404 mutex_exit(&cpu_lock); 405 406 return (cp); 407 } 408 409 /* 410 * Undo what was done in mp_startup_init 411 */ 412 static void 413 mp_startup_fini(struct cpu *cp, int error) 414 { 415 mutex_enter(&cpu_lock); 416 417 /* 418 * Remove the CPU from the list of available CPUs. 419 */ 420 cpu_del_unit(cp->cpu_id); 421 422 if (error == ETIMEDOUT) { 423 /* 424 * The cpu was started, but never *seemed* to run any 425 * code in the kernel; it's probably off spinning in its 426 * own private world, though with potential references to 427 * our kmem-allocated IDTs and GDTs (for example). 428 * 429 * Worse still, it may actually wake up some time later, 430 * so rather than guess what it might or might not do, we 431 * leave the fundamental data structures intact. 432 */ 433 cp->cpu_flags = 0; 434 mutex_exit(&cpu_lock); 435 return; 436 } 437 438 /* 439 * At this point, the only threads bound to this CPU should 440 * special per-cpu threads: it's idle thread, it's pause threads, 441 * and it's interrupt threads. Clean these up. 442 */ 443 cpu_destroy_bound_threads(cp); 444 cp->cpu_idle_thread = NULL; 445 446 /* 447 * Free the interrupt stack. 448 */ 449 segkp_release(segkp, 450 cp->cpu_intr_stack - (INTR_STACK_SIZE - SA(MINFRAME))); 451 452 mutex_exit(&cpu_lock); 453 454 #ifdef TRAPTRACE 455 /* 456 * Discard the trap trace buffer 457 */ 458 { 459 trap_trace_ctl_t *ttc = &trap_trace_ctl[cp->cpu_id]; 460 461 kmem_free((void *)ttc->ttc_first, trap_trace_bufsize); 462 ttc->ttc_first = NULL; 463 } 464 #endif 465 466 hat_cpu_offline(cp); 467 468 cpuid_free_space(cp); 469 470 ucode_free_space(cp); 471 472 if (cp->cpu_m.mcpu_idt != CPU->cpu_m.mcpu_idt) 473 kmem_free(cp->cpu_m.mcpu_idt, sizeof (idt0)); 474 cp->cpu_m.mcpu_idt = NULL; 475 476 kmem_free(cp->cpu_m.mcpu_gdt, PAGESIZE); 477 cp->cpu_m.mcpu_gdt = NULL; 478 479 teardown_vaddr_for_ppcopy(cp); 480 481 kcpc_hw_fini(cp); 482 483 cp->cpu_dispthread = NULL; 484 cp->cpu_thread = NULL; /* discarded by cpu_destroy_bound_threads() */ 485 486 cpu_vm_data_destroy(cp); 487 488 mutex_enter(&cpu_lock); 489 disp_cpu_fini(cp); 490 mutex_exit(&cpu_lock); 491 492 kmem_free(cp, sizeof (*cp)); 493 } 494 495 /* 496 * Apply workarounds for known errata, and warn about those that are absent. 497 * 498 * System vendors occasionally create configurations which contain different 499 * revisions of the CPUs that are almost but not exactly the same. At the 500 * time of writing, this meant that their clock rates were the same, their 501 * feature sets were the same, but the required workaround were -not- 502 * necessarily the same. So, this routine is invoked on -every- CPU soon 503 * after starting to make sure that the resulting system contains the most 504 * pessimal set of workarounds needed to cope with *any* of the CPUs in the 505 * system. 506 * 507 * workaround_errata is invoked early in mlsetup() for CPU 0, and in 508 * mp_startup() for all slave CPUs. Slaves process workaround_errata prior 509 * to acknowledging their readiness to the master, so this routine will 510 * never be executed by multiple CPUs in parallel, thus making updates to 511 * global data safe. 512 * 513 * These workarounds are based on Rev 3.57 of the Revision Guide for 514 * AMD Athlon(tm) 64 and AMD Opteron(tm) Processors, August 2005. 515 */ 516 517 #if defined(OPTERON_ERRATUM_88) 518 int opteron_erratum_88; /* if non-zero -> at least one cpu has it */ 519 #endif 520 521 #if defined(OPTERON_ERRATUM_91) 522 int opteron_erratum_91; /* if non-zero -> at least one cpu has it */ 523 #endif 524 525 #if defined(OPTERON_ERRATUM_93) 526 int opteron_erratum_93; /* if non-zero -> at least one cpu has it */ 527 #endif 528 529 #if defined(OPTERON_ERRATUM_95) 530 int opteron_erratum_95; /* if non-zero -> at least one cpu has it */ 531 #endif 532 533 #if defined(OPTERON_ERRATUM_100) 534 int opteron_erratum_100; /* if non-zero -> at least one cpu has it */ 535 #endif 536 537 #if defined(OPTERON_ERRATUM_108) 538 int opteron_erratum_108; /* if non-zero -> at least one cpu has it */ 539 #endif 540 541 #if defined(OPTERON_ERRATUM_109) 542 int opteron_erratum_109; /* if non-zero -> at least one cpu has it */ 543 #endif 544 545 #if defined(OPTERON_ERRATUM_121) 546 int opteron_erratum_121; /* if non-zero -> at least one cpu has it */ 547 #endif 548 549 #if defined(OPTERON_ERRATUM_122) 550 int opteron_erratum_122; /* if non-zero -> at least one cpu has it */ 551 #endif 552 553 #if defined(OPTERON_ERRATUM_123) 554 int opteron_erratum_123; /* if non-zero -> at least one cpu has it */ 555 #endif 556 557 #if defined(OPTERON_ERRATUM_131) 558 int opteron_erratum_131; /* if non-zero -> at least one cpu has it */ 559 #endif 560 561 #if defined(OPTERON_WORKAROUND_6336786) 562 int opteron_workaround_6336786; /* non-zero -> WA relevant and applied */ 563 int opteron_workaround_6336786_UP = 0; /* Not needed for UP */ 564 #endif 565 566 #if defined(OPTERON_WORKAROUND_6323525) 567 int opteron_workaround_6323525; /* if non-zero -> at least one cpu has it */ 568 #endif 569 570 static void 571 workaround_warning(cpu_t *cp, uint_t erratum) 572 { 573 cmn_err(CE_WARN, "cpu%d: no workaround for erratum %u", 574 cp->cpu_id, erratum); 575 } 576 577 static void 578 workaround_applied(uint_t erratum) 579 { 580 if (erratum > 1000000) 581 cmn_err(CE_CONT, "?workaround applied for cpu issue #%d\n", 582 erratum); 583 else 584 cmn_err(CE_CONT, "?workaround applied for cpu erratum #%d\n", 585 erratum); 586 } 587 588 static void 589 msr_warning(cpu_t *cp, const char *rw, uint_t msr, int error) 590 { 591 cmn_err(CE_WARN, "cpu%d: couldn't %smsr 0x%x, error %d", 592 cp->cpu_id, rw, msr, error); 593 } 594 595 uint_t 596 workaround_errata(struct cpu *cpu) 597 { 598 uint_t missing = 0; 599 600 ASSERT(cpu == CPU); 601 602 /*LINTED*/ 603 if (cpuid_opteron_erratum(cpu, 88) > 0) { 604 /* 605 * SWAPGS May Fail To Read Correct GS Base 606 */ 607 #if defined(OPTERON_ERRATUM_88) 608 /* 609 * The workaround is an mfence in the relevant assembler code 610 */ 611 opteron_erratum_88++; 612 #else 613 workaround_warning(cpu, 88); 614 missing++; 615 #endif 616 } 617 618 if (cpuid_opteron_erratum(cpu, 91) > 0) { 619 /* 620 * Software Prefetches May Report A Page Fault 621 */ 622 #if defined(OPTERON_ERRATUM_91) 623 /* 624 * fix is in trap.c 625 */ 626 opteron_erratum_91++; 627 #else 628 workaround_warning(cpu, 91); 629 missing++; 630 #endif 631 } 632 633 if (cpuid_opteron_erratum(cpu, 93) > 0) { 634 /* 635 * RSM Auto-Halt Restart Returns to Incorrect RIP 636 */ 637 #if defined(OPTERON_ERRATUM_93) 638 /* 639 * fix is in trap.c 640 */ 641 opteron_erratum_93++; 642 #else 643 workaround_warning(cpu, 93); 644 missing++; 645 #endif 646 } 647 648 /*LINTED*/ 649 if (cpuid_opteron_erratum(cpu, 95) > 0) { 650 /* 651 * RET Instruction May Return to Incorrect EIP 652 */ 653 #if defined(OPTERON_ERRATUM_95) 654 #if defined(_LP64) 655 /* 656 * Workaround this by ensuring that 32-bit user code and 657 * 64-bit kernel code never occupy the same address 658 * range mod 4G. 659 */ 660 if (_userlimit32 > 0xc0000000ul) 661 *(uintptr_t *)&_userlimit32 = 0xc0000000ul; 662 663 /*LINTED*/ 664 ASSERT((uint32_t)COREHEAP_BASE == 0xc0000000u); 665 opteron_erratum_95++; 666 #endif /* _LP64 */ 667 #else 668 workaround_warning(cpu, 95); 669 missing++; 670 #endif 671 } 672 673 if (cpuid_opteron_erratum(cpu, 100) > 0) { 674 /* 675 * Compatibility Mode Branches Transfer to Illegal Address 676 */ 677 #if defined(OPTERON_ERRATUM_100) 678 /* 679 * fix is in trap.c 680 */ 681 opteron_erratum_100++; 682 #else 683 workaround_warning(cpu, 100); 684 missing++; 685 #endif 686 } 687 688 /*LINTED*/ 689 if (cpuid_opteron_erratum(cpu, 108) > 0) { 690 /* 691 * CPUID Instruction May Return Incorrect Model Number In 692 * Some Processors 693 */ 694 #if defined(OPTERON_ERRATUM_108) 695 /* 696 * (Our cpuid-handling code corrects the model number on 697 * those processors) 698 */ 699 #else 700 workaround_warning(cpu, 108); 701 missing++; 702 #endif 703 } 704 705 /*LINTED*/ 706 if (cpuid_opteron_erratum(cpu, 109) > 0) do { 707 /* 708 * Certain Reverse REP MOVS May Produce Unpredictable Behaviour 709 */ 710 #if defined(OPTERON_ERRATUM_109) 711 /* 712 * The "workaround" is to print a warning to upgrade the BIOS 713 */ 714 uint64_t value; 715 const uint_t msr = MSR_AMD_PATCHLEVEL; 716 int err; 717 718 if ((err = checked_rdmsr(msr, &value)) != 0) { 719 msr_warning(cpu, "rd", msr, err); 720 workaround_warning(cpu, 109); 721 missing++; 722 } 723 if (value == 0) 724 opteron_erratum_109++; 725 #else 726 workaround_warning(cpu, 109); 727 missing++; 728 #endif 729 /*CONSTANTCONDITION*/ 730 } while (0); 731 732 /*LINTED*/ 733 if (cpuid_opteron_erratum(cpu, 121) > 0) { 734 /* 735 * Sequential Execution Across Non_Canonical Boundary Caused 736 * Processor Hang 737 */ 738 #if defined(OPTERON_ERRATUM_121) 739 #if defined(_LP64) 740 /* 741 * Erratum 121 is only present in long (64 bit) mode. 742 * Workaround is to include the page immediately before the 743 * va hole to eliminate the possibility of system hangs due to 744 * sequential execution across the va hole boundary. 745 */ 746 if (opteron_erratum_121) 747 opteron_erratum_121++; 748 else { 749 if (hole_start) { 750 hole_start -= PAGESIZE; 751 } else { 752 /* 753 * hole_start not yet initialized by 754 * mmu_init. Initialize hole_start 755 * with value to be subtracted. 756 */ 757 hole_start = PAGESIZE; 758 } 759 opteron_erratum_121++; 760 } 761 #endif /* _LP64 */ 762 #else 763 workaround_warning(cpu, 121); 764 missing++; 765 #endif 766 } 767 768 /*LINTED*/ 769 if (cpuid_opteron_erratum(cpu, 122) > 0) do { 770 /* 771 * TLB Flush Filter May Cause Coherency Problem in 772 * Multiprocessor Systems 773 */ 774 #if defined(OPTERON_ERRATUM_122) 775 uint64_t value; 776 const uint_t msr = MSR_AMD_HWCR; 777 int error; 778 779 /* 780 * Erratum 122 is only present in MP configurations (multi-core 781 * or multi-processor). 782 */ 783 if (!opteron_erratum_122 && lgrp_plat_node_cnt == 1 && 784 cpuid_get_ncpu_per_chip(cpu) == 1) 785 break; 786 787 /* disable TLB Flush Filter */ 788 789 if ((error = checked_rdmsr(msr, &value)) != 0) { 790 msr_warning(cpu, "rd", msr, error); 791 workaround_warning(cpu, 122); 792 missing++; 793 } else { 794 value |= (uint64_t)AMD_HWCR_FFDIS; 795 if ((error = checked_wrmsr(msr, value)) != 0) { 796 msr_warning(cpu, "wr", msr, error); 797 workaround_warning(cpu, 122); 798 missing++; 799 } 800 } 801 opteron_erratum_122++; 802 #else 803 workaround_warning(cpu, 122); 804 missing++; 805 #endif 806 /*CONSTANTCONDITION*/ 807 } while (0); 808 809 /*LINTED*/ 810 if (cpuid_opteron_erratum(cpu, 123) > 0) do { 811 /* 812 * Bypassed Reads May Cause Data Corruption of System Hang in 813 * Dual Core Processors 814 */ 815 #if defined(OPTERON_ERRATUM_123) 816 uint64_t value; 817 const uint_t msr = MSR_AMD_PATCHLEVEL; 818 int err; 819 820 /* 821 * Erratum 123 applies only to multi-core cpus. 822 */ 823 if (cpuid_get_ncpu_per_chip(cpu) < 2) 824 break; 825 826 /* 827 * The "workaround" is to print a warning to upgrade the BIOS 828 */ 829 if ((err = checked_rdmsr(msr, &value)) != 0) { 830 msr_warning(cpu, "rd", msr, err); 831 workaround_warning(cpu, 123); 832 missing++; 833 } 834 if (value == 0) 835 opteron_erratum_123++; 836 #else 837 workaround_warning(cpu, 123); 838 missing++; 839 840 #endif 841 /*CONSTANTCONDITION*/ 842 } while (0); 843 844 /*LINTED*/ 845 if (cpuid_opteron_erratum(cpu, 131) > 0) do { 846 /* 847 * Multiprocessor Systems with Four or More Cores May Deadlock 848 * Waiting for a Probe Response 849 */ 850 #if defined(OPTERON_ERRATUM_131) 851 uint64_t nbcfg; 852 const uint_t msr = MSR_AMD_NB_CFG; 853 const uint64_t wabits = 854 AMD_NB_CFG_SRQ_HEARTBEAT | AMD_NB_CFG_SRQ_SPR; 855 int error; 856 857 /* 858 * Erratum 131 applies to any system with four or more cores. 859 */ 860 if (opteron_erratum_131) 861 break; 862 863 if (lgrp_plat_node_cnt * cpuid_get_ncpu_per_chip(cpu) < 4) 864 break; 865 866 /* 867 * Print a warning if neither of the workarounds for 868 * erratum 131 is present. 869 */ 870 if ((error = checked_rdmsr(msr, &nbcfg)) != 0) { 871 msr_warning(cpu, "rd", msr, error); 872 workaround_warning(cpu, 131); 873 missing++; 874 } else if ((nbcfg & wabits) == 0) { 875 opteron_erratum_131++; 876 } else { 877 /* cannot have both workarounds set */ 878 ASSERT((nbcfg & wabits) != wabits); 879 } 880 #else 881 workaround_warning(cpu, 131); 882 missing++; 883 #endif 884 /*CONSTANTCONDITION*/ 885 } while (0); 886 887 /* 888 * This isn't really an erratum, but for convenience the 889 * detection/workaround code lives here and in cpuid_opteron_erratum. 890 */ 891 if (cpuid_opteron_erratum(cpu, 6336786) > 0) { 892 #if defined(OPTERON_WORKAROUND_6336786) 893 /* 894 * Disable C1-Clock ramping on multi-core/multi-processor 895 * K8 platforms to guard against TSC drift. 896 */ 897 if (opteron_workaround_6336786) { 898 opteron_workaround_6336786++; 899 } else if ((lgrp_plat_node_cnt * 900 cpuid_get_ncpu_per_chip(cpu) > 1) || 901 opteron_workaround_6336786_UP) { 902 int node; 903 uint8_t data; 904 905 for (node = 0; node < lgrp_plat_node_cnt; node++) { 906 /* 907 * Clear PMM7[1:0] (function 3, offset 0x87) 908 * Northbridge device is the node id + 24. 909 */ 910 data = pci_getb_func(0, node + 24, 3, 0x87); 911 data &= 0xFC; 912 pci_putb_func(0, node + 24, 3, 0x87, data); 913 } 914 opteron_workaround_6336786++; 915 } 916 #else 917 workaround_warning(cpu, 6336786); 918 missing++; 919 #endif 920 } 921 922 /*LINTED*/ 923 /* 924 * Mutex primitives don't work as expected. 925 */ 926 if (cpuid_opteron_erratum(cpu, 6323525) > 0) { 927 #if defined(OPTERON_WORKAROUND_6323525) 928 /* 929 * This problem only occurs with 2 or more cores. If bit in 930 * MSR_BU_CFG set, then not applicable. The workaround 931 * is to patch the semaphone routines with the lfence 932 * instruction to provide necessary load memory barrier with 933 * possible subsequent read-modify-write ops. 934 * 935 * It is too early in boot to call the patch routine so 936 * set erratum variable to be done in startup_end(). 937 */ 938 if (opteron_workaround_6323525) { 939 opteron_workaround_6323525++; 940 } else if ((x86_feature & X86_SSE2) && ((lgrp_plat_node_cnt * 941 cpuid_get_ncpu_per_chip(cpu)) > 1)) { 942 if ((xrdmsr(MSR_BU_CFG) & 0x02) == 0) 943 opteron_workaround_6323525++; 944 } 945 #else 946 workaround_warning(cpu, 6323525); 947 missing++; 948 #endif 949 } 950 951 return (missing); 952 } 953 954 void 955 workaround_errata_end() 956 { 957 #if defined(OPTERON_ERRATUM_88) 958 if (opteron_erratum_88) 959 workaround_applied(88); 960 #endif 961 #if defined(OPTERON_ERRATUM_91) 962 if (opteron_erratum_91) 963 workaround_applied(91); 964 #endif 965 #if defined(OPTERON_ERRATUM_93) 966 if (opteron_erratum_93) 967 workaround_applied(93); 968 #endif 969 #if defined(OPTERON_ERRATUM_95) 970 if (opteron_erratum_95) 971 workaround_applied(95); 972 #endif 973 #if defined(OPTERON_ERRATUM_100) 974 if (opteron_erratum_100) 975 workaround_applied(100); 976 #endif 977 #if defined(OPTERON_ERRATUM_108) 978 if (opteron_erratum_108) 979 workaround_applied(108); 980 #endif 981 #if defined(OPTERON_ERRATUM_109) 982 if (opteron_erratum_109) { 983 cmn_err(CE_WARN, 984 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 985 " processor\nerratum 109 was not detected; updating your" 986 " system's BIOS to a version\ncontaining this" 987 " microcode patch is HIGHLY recommended or erroneous" 988 " system\noperation may occur.\n"); 989 } 990 #endif 991 #if defined(OPTERON_ERRATUM_121) 992 if (opteron_erratum_121) 993 workaround_applied(121); 994 #endif 995 #if defined(OPTERON_ERRATUM_122) 996 if (opteron_erratum_122) 997 workaround_applied(122); 998 #endif 999 #if defined(OPTERON_ERRATUM_123) 1000 if (opteron_erratum_123) { 1001 cmn_err(CE_WARN, 1002 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1003 " processor\nerratum 123 was not detected; updating your" 1004 " system's BIOS to a version\ncontaining this" 1005 " microcode patch is HIGHLY recommended or erroneous" 1006 " system\noperation may occur.\n"); 1007 } 1008 #endif 1009 #if defined(OPTERON_ERRATUM_131) 1010 if (opteron_erratum_131) { 1011 cmn_err(CE_WARN, 1012 "BIOS microcode patch for AMD Athlon(tm) 64/Opteron(tm)" 1013 " processor\nerratum 131 was not detected; updating your" 1014 " system's BIOS to a version\ncontaining this" 1015 " microcode patch is HIGHLY recommended or erroneous" 1016 " system\noperation may occur.\n"); 1017 } 1018 #endif 1019 #if defined(OPTERON_WORKAROUND_6336786) 1020 if (opteron_workaround_6336786) 1021 workaround_applied(6336786); 1022 #endif 1023 #if defined(OPTERON_WORKAROUND_6323525) 1024 if (opteron_workaround_6323525) 1025 workaround_applied(6323525); 1026 #endif 1027 } 1028 1029 static cpuset_t procset; 1030 1031 /* 1032 * Start a single cpu, assuming that the kernel context is available 1033 * to successfully start another cpu. 1034 * 1035 * (For example, real mode code is mapped into the right place 1036 * in memory and is ready to be run.) 1037 */ 1038 int 1039 start_cpu(processorid_t who) 1040 { 1041 void *ctx; 1042 cpu_t *cp; 1043 int delays; 1044 int error = 0; 1045 1046 ASSERT(who != 0); 1047 1048 /* 1049 * Check if there's at least a Mbyte of kmem available 1050 * before attempting to start the cpu. 1051 */ 1052 if (kmem_avail() < 1024 * 1024) { 1053 /* 1054 * Kick off a reap in case that helps us with 1055 * later attempts .. 1056 */ 1057 kmem_reap(); 1058 return (ENOMEM); 1059 } 1060 1061 cp = mp_startup_init(who); 1062 if ((ctx = mach_cpucontext_alloc(cp)) == NULL || 1063 (error = mach_cpu_start(cp, ctx)) != 0) { 1064 1065 /* 1066 * Something went wrong before we even started it 1067 */ 1068 if (ctx) 1069 cmn_err(CE_WARN, 1070 "cpu%d: failed to start error %d", 1071 cp->cpu_id, error); 1072 else 1073 cmn_err(CE_WARN, 1074 "cpu%d: failed to allocate context", cp->cpu_id); 1075 1076 if (ctx) 1077 mach_cpucontext_free(cp, ctx, error); 1078 else 1079 error = EAGAIN; /* hmm. */ 1080 mp_startup_fini(cp, error); 1081 return (error); 1082 } 1083 1084 for (delays = 0; !CPU_IN_SET(procset, who); delays++) { 1085 if (delays == 500) { 1086 /* 1087 * After five seconds, things are probably looking 1088 * a bit bleak - explain the hang. 1089 */ 1090 cmn_err(CE_NOTE, "cpu%d: started, " 1091 "but not running in the kernel yet", who); 1092 } else if (delays > 2000) { 1093 /* 1094 * We waited at least 20 seconds, bail .. 1095 */ 1096 error = ETIMEDOUT; 1097 cmn_err(CE_WARN, "cpu%d: timed out", who); 1098 mach_cpucontext_free(cp, ctx, error); 1099 mp_startup_fini(cp, error); 1100 return (error); 1101 } 1102 1103 /* 1104 * wait at least 10ms, then check again.. 1105 */ 1106 delay(USEC_TO_TICK_ROUNDUP(10000)); 1107 } 1108 1109 mach_cpucontext_free(cp, ctx, 0); 1110 1111 if (tsc_gethrtime_enable) 1112 tsc_sync_master(who); 1113 1114 if (dtrace_cpu_init != NULL) { 1115 /* 1116 * DTrace CPU initialization expects cpu_lock to be held. 1117 */ 1118 mutex_enter(&cpu_lock); 1119 (*dtrace_cpu_init)(who); 1120 mutex_exit(&cpu_lock); 1121 } 1122 1123 while (!CPU_IN_SET(cpu_ready_set, who)) 1124 delay(1); 1125 1126 return (0); 1127 } 1128 1129 1130 /*ARGSUSED*/ 1131 void 1132 start_other_cpus(int cprboot) 1133 { 1134 uint_t who; 1135 uint_t skipped = 0; 1136 uint_t bootcpuid = 0; 1137 1138 /* 1139 * Initialize our own cpu_info. 1140 */ 1141 init_cpu_info(CPU); 1142 1143 /* 1144 * Initialize our syscall handlers 1145 */ 1146 init_cpu_syscall(CPU); 1147 1148 /* 1149 * Take the boot cpu out of the mp_cpus set because we know 1150 * it's already running. Add it to the cpu_ready_set for 1151 * precisely the same reason. 1152 */ 1153 CPUSET_DEL(mp_cpus, bootcpuid); 1154 CPUSET_ADD(cpu_ready_set, bootcpuid); 1155 1156 /* 1157 * if only 1 cpu or not using MP, skip the rest of this 1158 */ 1159 if (CPUSET_ISNULL(mp_cpus) || use_mp == 0) { 1160 if (use_mp == 0) 1161 cmn_err(CE_CONT, "?***** Not in MP mode\n"); 1162 goto done; 1163 } 1164 1165 /* 1166 * perform such initialization as is needed 1167 * to be able to take CPUs on- and off-line. 1168 */ 1169 cpu_pause_init(); 1170 1171 xc_init(); /* initialize processor crosscalls */ 1172 1173 if (mach_cpucontext_init() != 0) 1174 goto done; 1175 1176 flushes_require_xcalls = 1; 1177 1178 /* 1179 * We lock our affinity to the master CPU to ensure that all slave CPUs 1180 * do their TSC syncs with the same CPU. 1181 */ 1182 affinity_set(CPU_CURRENT); 1183 1184 for (who = 0; who < NCPU; who++) { 1185 1186 if (!CPU_IN_SET(mp_cpus, who)) 1187 continue; 1188 ASSERT(who != bootcpuid); 1189 if (ncpus >= max_ncpus) { 1190 skipped = who; 1191 continue; 1192 } 1193 if (start_cpu(who) != 0) 1194 CPUSET_DEL(mp_cpus, who); 1195 } 1196 1197 /* Free the space allocated to hold the microcode file */ 1198 ucode_free(); 1199 1200 affinity_clear(); 1201 1202 if (skipped) { 1203 cmn_err(CE_NOTE, 1204 "System detected %d cpus, but " 1205 "only %d cpu(s) were enabled during boot.", 1206 skipped + 1, ncpus); 1207 cmn_err(CE_NOTE, 1208 "Use \"boot-ncpus\" parameter to enable more CPU(s). " 1209 "See eeprom(1M)."); 1210 } 1211 1212 done: 1213 workaround_errata_end(); 1214 mach_cpucontext_fini(); 1215 1216 cmi_post_mpstartup(); 1217 } 1218 1219 /* 1220 * Dummy functions - no i86pc platforms support dynamic cpu allocation. 1221 */ 1222 /*ARGSUSED*/ 1223 int 1224 mp_cpu_configure(int cpuid) 1225 { 1226 return (ENOTSUP); /* not supported */ 1227 } 1228 1229 /*ARGSUSED*/ 1230 int 1231 mp_cpu_unconfigure(int cpuid) 1232 { 1233 return (ENOTSUP); /* not supported */ 1234 } 1235 1236 /* 1237 * Startup function for 'other' CPUs (besides boot cpu). 1238 * Called from real_mode_start. 1239 * 1240 * WARNING: until CPU_READY is set, mp_startup and routines called by 1241 * mp_startup should not call routines (e.g. kmem_free) that could call 1242 * hat_unload which requires CPU_READY to be set. 1243 */ 1244 void 1245 mp_startup(void) 1246 { 1247 struct cpu *cp = CPU; 1248 uint_t new_x86_feature; 1249 1250 /* 1251 * We need to get TSC on this proc synced (i.e., any delta 1252 * from cpu0 accounted for) as soon as we can, because many 1253 * many things use gethrtime/pc_gethrestime, including 1254 * interrupts, cmn_err, etc. 1255 */ 1256 1257 /* Let cpu0 continue into tsc_sync_master() */ 1258 CPUSET_ATOMIC_ADD(procset, cp->cpu_id); 1259 1260 if (tsc_gethrtime_enable) 1261 tsc_sync_slave(); 1262 1263 /* 1264 * Once this was done from assembly, but it's safer here; if 1265 * it blocks, we need to be able to swtch() to and from, and 1266 * since we get here by calling t_pc, we need to do that call 1267 * before swtch() overwrites it. 1268 */ 1269 1270 (void) (*ap_mlsetup)(); 1271 1272 new_x86_feature = cpuid_pass1(cp); 1273 1274 /* 1275 * We need to Sync MTRR with cpu0's MTRR. We have to do 1276 * this with interrupts disabled. 1277 */ 1278 if (x86_feature & X86_MTRR) 1279 mtrr_sync(); 1280 1281 /* 1282 * Set up TSC_AUX to contain the cpuid for this processor 1283 * for the rdtscp instruction. 1284 */ 1285 if (x86_feature & X86_TSCP) 1286 (void) wrmsr(MSR_AMD_TSCAUX, cp->cpu_id); 1287 1288 /* 1289 * Initialize this CPU's syscall handlers 1290 */ 1291 init_cpu_syscall(cp); 1292 1293 /* 1294 * Enable interrupts with spl set to LOCK_LEVEL. LOCK_LEVEL is the 1295 * highest level at which a routine is permitted to block on 1296 * an adaptive mutex (allows for cpu poke interrupt in case 1297 * the cpu is blocked on a mutex and halts). Setting LOCK_LEVEL blocks 1298 * device interrupts that may end up in the hat layer issuing cross 1299 * calls before CPU_READY is set. 1300 */ 1301 splx(ipltospl(LOCK_LEVEL)); 1302 sti(); 1303 1304 /* 1305 * Do a sanity check to make sure this new CPU is a sane thing 1306 * to add to the collection of processors running this system. 1307 * 1308 * XXX Clearly this needs to get more sophisticated, if x86 1309 * systems start to get built out of heterogenous CPUs; as is 1310 * likely to happen once the number of processors in a configuration 1311 * gets large enough. 1312 */ 1313 if ((x86_feature & new_x86_feature) != x86_feature) { 1314 cmn_err(CE_CONT, "?cpu%d: %b\n", 1315 cp->cpu_id, new_x86_feature, FMT_X86_FEATURE); 1316 cmn_err(CE_WARN, "cpu%d feature mismatch", cp->cpu_id); 1317 } 1318 1319 /* 1320 * We do not support cpus with mixed monitor/mwait support if the 1321 * boot cpu supports monitor/mwait. 1322 */ 1323 if ((x86_feature & ~new_x86_feature) & X86_MWAIT) 1324 panic("unsupported mixed cpu monitor/mwait support detected"); 1325 1326 /* 1327 * We could be more sophisticated here, and just mark the CPU 1328 * as "faulted" but at this point we'll opt for the easier 1329 * answer of dieing horribly. Provided the boot cpu is ok, 1330 * the system can be recovered by booting with use_mp set to zero. 1331 */ 1332 if (workaround_errata(cp) != 0) 1333 panic("critical workaround(s) missing for cpu%d", cp->cpu_id); 1334 1335 cpuid_pass2(cp); 1336 cpuid_pass3(cp); 1337 (void) cpuid_pass4(cp); 1338 1339 init_cpu_info(cp); 1340 1341 mutex_enter(&cpu_lock); 1342 /* 1343 * Processor group initialization for this CPU is dependent on the 1344 * cpuid probing, which must be done in the context of the current 1345 * CPU. 1346 */ 1347 pghw_physid_create(cp); 1348 pg_cpu_init(cp); 1349 pg_cmt_cpu_startup(cp); 1350 1351 cp->cpu_flags |= CPU_RUNNING | CPU_READY | CPU_ENABLE | CPU_EXISTS; 1352 cpu_add_active(cp); 1353 1354 if (dtrace_cpu_init != NULL) { 1355 (*dtrace_cpu_init)(cp->cpu_id); 1356 } 1357 1358 /* 1359 * Fill out cpu_ucode_info. Update microcode if necessary. 1360 */ 1361 ucode_check(cp); 1362 1363 mutex_exit(&cpu_lock); 1364 1365 /* 1366 * Enable preemption here so that contention for any locks acquired 1367 * later in mp_startup may be preempted if the thread owning those 1368 * locks is continously executing on other CPUs (for example, this 1369 * CPU must be preemptible to allow other CPUs to pause it during their 1370 * startup phases). It's safe to enable preemption here because the 1371 * CPU state is pretty-much fully constructed. 1372 */ 1373 curthread->t_preempt = 0; 1374 1375 add_cpunode2devtree(cp->cpu_id, cp->cpu_m.mcpu_cpi); 1376 1377 /* The base spl should still be at LOCK LEVEL here */ 1378 ASSERT(cp->cpu_base_spl == ipltospl(LOCK_LEVEL)); 1379 set_base_spl(); /* Restore the spl to its proper value */ 1380 1381 (void) spl0(); /* enable interrupts */ 1382 1383 /* 1384 * Set up the CPU module for this CPU. This can't be done before 1385 * this CPU is made CPU_READY, because we may (in heterogeneous systems) 1386 * need to go load another CPU module. The act of attempting to load 1387 * a module may trigger a cross-call, which will ASSERT unless this 1388 * cpu is CPU_READY. 1389 */ 1390 cmi_init(); 1391 1392 if (x86_feature & X86_MCA) 1393 cmi_mca_init(); 1394 1395 if (boothowto & RB_DEBUG) 1396 kdi_cpu_init(); 1397 1398 /* 1399 * Setting the bit in cpu_ready_set must be the last operation in 1400 * processor initialization; the boot CPU will continue to boot once 1401 * it sees this bit set for all active CPUs. 1402 */ 1403 CPUSET_ATOMIC_ADD(cpu_ready_set, cp->cpu_id); 1404 1405 /* 1406 * Because mp_startup() gets fired off after init() starts, we 1407 * can't use the '?' trick to do 'boot -v' printing - so we 1408 * always direct the 'cpu .. online' messages to the log. 1409 */ 1410 cmn_err(CE_CONT, "!cpu%d initialization complete - online\n", 1411 cp->cpu_id); 1412 1413 /* 1414 * Now we are done with the startup thread, so free it up. 1415 */ 1416 thread_exit(); 1417 panic("mp_startup: cannot return"); 1418 /*NOTREACHED*/ 1419 } 1420 1421 1422 /* 1423 * Start CPU on user request. 1424 */ 1425 /* ARGSUSED */ 1426 int 1427 mp_cpu_start(struct cpu *cp) 1428 { 1429 ASSERT(MUTEX_HELD(&cpu_lock)); 1430 return (0); 1431 } 1432 1433 /* 1434 * Stop CPU on user request. 1435 */ 1436 /* ARGSUSED */ 1437 int 1438 mp_cpu_stop(struct cpu *cp) 1439 { 1440 extern int cbe_psm_timer_mode; 1441 ASSERT(MUTEX_HELD(&cpu_lock)); 1442 1443 /* 1444 * If TIMER_PERIODIC mode is used, CPU0 is the one running it; 1445 * can't stop it. (This is true only for machines with no TSC.) 1446 */ 1447 1448 if ((cbe_psm_timer_mode == TIMER_PERIODIC) && (cp->cpu_id == 0)) 1449 return (1); 1450 1451 return (0); 1452 } 1453 1454 /* 1455 * Take the specified CPU out of participation in interrupts. 1456 */ 1457 int 1458 cpu_disable_intr(struct cpu *cp) 1459 { 1460 if (psm_disable_intr(cp->cpu_id) != DDI_SUCCESS) 1461 return (EBUSY); 1462 1463 cp->cpu_flags &= ~CPU_ENABLE; 1464 return (0); 1465 } 1466 1467 /* 1468 * Allow the specified CPU to participate in interrupts. 1469 */ 1470 void 1471 cpu_enable_intr(struct cpu *cp) 1472 { 1473 ASSERT(MUTEX_HELD(&cpu_lock)); 1474 cp->cpu_flags |= CPU_ENABLE; 1475 psm_enable_intr(cp->cpu_id); 1476 } 1477 1478 1479 1480 void 1481 mp_cpu_faulted_enter(struct cpu *cp) 1482 { 1483 cmi_faulted_enter(cp); 1484 } 1485 1486 void 1487 mp_cpu_faulted_exit(struct cpu *cp) 1488 { 1489 cmi_faulted_exit(cp); 1490 } 1491 1492 /* 1493 * The following two routines are used as context operators on threads belonging 1494 * to processes with a private LDT (see sysi86). Due to the rarity of such 1495 * processes, these routines are currently written for best code readability and 1496 * organization rather than speed. We could avoid checking x86_feature at every 1497 * context switch by installing different context ops, depending on the 1498 * x86_feature flags, at LDT creation time -- one for each combination of fast 1499 * syscall feature flags. 1500 */ 1501 1502 /*ARGSUSED*/ 1503 void 1504 cpu_fast_syscall_disable(void *arg) 1505 { 1506 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1507 cpu_sep_disable(); 1508 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1509 cpu_asysc_disable(); 1510 } 1511 1512 /*ARGSUSED*/ 1513 void 1514 cpu_fast_syscall_enable(void *arg) 1515 { 1516 if ((x86_feature & (X86_MSR | X86_SEP)) == (X86_MSR | X86_SEP)) 1517 cpu_sep_enable(); 1518 if ((x86_feature & (X86_MSR | X86_ASYSC)) == (X86_MSR | X86_ASYSC)) 1519 cpu_asysc_enable(); 1520 } 1521 1522 static void 1523 cpu_sep_enable(void) 1524 { 1525 ASSERT(x86_feature & X86_SEP); 1526 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1527 1528 wrmsr(MSR_INTC_SEP_CS, (uint64_t)(uintptr_t)KCS_SEL); 1529 } 1530 1531 static void 1532 cpu_sep_disable(void) 1533 { 1534 ASSERT(x86_feature & X86_SEP); 1535 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1536 1537 /* 1538 * Setting the SYSENTER_CS_MSR register to 0 causes software executing 1539 * the sysenter or sysexit instruction to trigger a #gp fault. 1540 */ 1541 wrmsr(MSR_INTC_SEP_CS, 0); 1542 } 1543 1544 static void 1545 cpu_asysc_enable(void) 1546 { 1547 ASSERT(x86_feature & X86_ASYSC); 1548 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1549 1550 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) | 1551 (uint64_t)(uintptr_t)AMD_EFER_SCE); 1552 } 1553 1554 static void 1555 cpu_asysc_disable(void) 1556 { 1557 ASSERT(x86_feature & X86_ASYSC); 1558 ASSERT(curthread->t_preempt || getpil() >= LOCK_LEVEL); 1559 1560 /* 1561 * Turn off the SCE (syscall enable) bit in the EFER register. Software 1562 * executing syscall or sysret with this bit off will incur a #ud trap. 1563 */ 1564 wrmsr(MSR_AMD_EFER, rdmsr(MSR_AMD_EFER) & 1565 ~((uint64_t)(uintptr_t)AMD_EFER_SCE)); 1566 } 1567