1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 #pragma ident "%Z%%M% %I% %E% SMI" 27 28 #include <sys/types.h> 29 #include <sys/sysmacros.h> 30 #include <sys/disp.h> 31 #include <sys/promif.h> 32 #include <sys/clock.h> 33 #include <sys/cpuvar.h> 34 #include <sys/stack.h> 35 #include <vm/as.h> 36 #include <vm/hat.h> 37 #include <sys/reboot.h> 38 #include <sys/avintr.h> 39 #include <sys/vtrace.h> 40 #include <sys/proc.h> 41 #include <sys/thread.h> 42 #include <sys/cpupart.h> 43 #include <sys/pset.h> 44 #include <sys/copyops.h> 45 #include <sys/pg.h> 46 #include <sys/disp.h> 47 #include <sys/debug.h> 48 #include <sys/sunddi.h> 49 #include <sys/x86_archext.h> 50 #include <sys/privregs.h> 51 #include <sys/machsystm.h> 52 #include <sys/ontrap.h> 53 #include <sys/bootconf.h> 54 #include <sys/kdi_machimpl.h> 55 #include <sys/archsystm.h> 56 #include <sys/promif.h> 57 #include <sys/bootconf.h> 58 #include <sys/kobj.h> 59 #include <sys/kobj_lex.h> 60 #include <sys/pci_cfgspace.h> 61 #ifdef __xpv 62 #include <sys/hypervisor.h> 63 #endif 64 65 /* 66 * some globals for patching the result of cpuid 67 * to solve problems w/ creative cpu vendors 68 */ 69 70 extern uint32_t cpuid_feature_ecx_include; 71 extern uint32_t cpuid_feature_ecx_exclude; 72 extern uint32_t cpuid_feature_edx_include; 73 extern uint32_t cpuid_feature_edx_exclude; 74 75 /* 76 * Dummy spl priority masks 77 */ 78 static unsigned char dummy_cpu_pri[MAXIPL + 1] = { 79 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 80 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf, 0xf 81 }; 82 83 84 static uint32_t 85 bootprop_getval(char *name) 86 { 87 char prop[32]; 88 u_longlong_t ll; 89 extern struct bootops *bootops; 90 if ((BOP_GETPROPLEN(bootops, name) > sizeof (prop)) || 91 (BOP_GETPROP(bootops, name, prop) < 0) || 92 (kobj_getvalue(prop, &ll) == -1)) 93 return (0); 94 return ((uint32_t)ll); 95 } 96 97 /* 98 * Setup routine called right before main(). Interposing this function 99 * before main() allows us to call it in a machine-independent fashion. 100 */ 101 void 102 mlsetup(struct regs *rp) 103 { 104 extern struct classfuncs sys_classfuncs; 105 extern disp_t cpu0_disp; 106 extern char t0stack[]; 107 int boot_ncpus; 108 109 ASSERT_STACK_ALIGNED(); 110 111 /* 112 * initialize cpu_self 113 */ 114 cpu[0]->cpu_self = cpu[0]; 115 116 #if defined(__xpv) 117 /* 118 * Point at the hypervisor's virtual cpu structure 119 */ 120 cpu[0]->cpu_m.mcpu_vcpu_info = &HYPERVISOR_shared_info->vcpu_info[0]; 121 #endif 122 123 /* 124 * Set up dummy cpu_pri_data values till psm spl code is 125 * installed. This allows splx() to work on amd64. 126 */ 127 128 cpu[0]->cpu_pri_data = dummy_cpu_pri; 129 130 /* 131 * check if we've got special bits to clear or set 132 * when checking cpu features 133 */ 134 135 cpuid_feature_ecx_include = 136 bootprop_getval("cpuid_feature_ecx_include"); 137 cpuid_feature_ecx_exclude = 138 bootprop_getval("cpuid_feature_ecx_exclude"); 139 cpuid_feature_edx_include = 140 bootprop_getval("cpuid_feature_edx_include"); 141 cpuid_feature_edx_exclude = 142 bootprop_getval("cpuid_feature_edx_exclude"); 143 144 /* 145 * The first lightweight pass (pass0) through the cpuid data 146 * was done in locore before mlsetup was called. Do the next 147 * pass in C code. 148 * 149 * The x86_feature bits are set here on the basis of the capabilities 150 * of the boot CPU. Note that if we choose to support CPUs that have 151 * different feature sets (at which point we would almost certainly 152 * want to set the feature bits to correspond to the feature 153 * minimum) this value may be altered. 154 */ 155 x86_feature = cpuid_pass1(cpu[0]); 156 157 /* 158 * Initialize idt0, gdt0, ldt0_default, ktss0 and dftss. 159 */ 160 init_desctbls(); 161 162 #if !defined(__xpv) 163 164 /* 165 * Patch the tsc_read routine with appropriate set of instructions, 166 * depending on the processor family and architecure, to read the 167 * time-stamp counter while ensuring no out-of-order execution. 168 * Patch it while the kernel text is still writable. 169 * 170 * Note: tsc_read is not patched for intel processors whose family 171 * is >6 and for amd whose family >f (in case they don't support rdtscp 172 * instruction, unlikely). By default tsc_read will use cpuid for 173 * serialization in such cases. The following code needs to be 174 * revisited if intel processors of family >= f retains the 175 * instruction serialization nature of mfence instruction. 176 * Note: tsc_read is not patched for x86 processors which do 177 * not support "mfence". By default tsc_read will use cpuid for 178 * serialization in such cases. 179 */ 180 if (x86_feature & X86_TSCP) 181 patch_tsc_read(X86_HAVE_TSCP); 182 else if (cpuid_getvendor(CPU) == X86_VENDOR_AMD && 183 cpuid_getfamily(CPU) <= 0xf && (x86_feature & X86_SSE2) != 0) 184 patch_tsc_read(X86_TSC_MFENCE); 185 else if (cpuid_getvendor(CPU) == X86_VENDOR_Intel && 186 cpuid_getfamily(CPU) <= 6 && (x86_feature & X86_SSE2) != 0) 187 patch_tsc_read(X86_TSC_MFENCE); 188 189 #endif /* !__xpv */ 190 191 #if defined(__i386) && !defined(__xpv) 192 /* 193 * Some i386 processors do not implement the rdtsc instruction, 194 * or at least they do not implement it correctly. Patch them to 195 * return 0. 196 */ 197 if ((x86_feature & X86_TSC) == 0) 198 patch_tsc_read(X86_NO_TSC); 199 #endif /* __i386 && !__xpv */ 200 201 #if !defined(__xpv) 202 /* XXPV what, if anything, should be dorked with here under xen? */ 203 204 /* 205 * While we're thinking about the TSC, let's set up %cr4 so that 206 * userland can issue rdtsc, and initialize the TSC_AUX value 207 * (the cpuid) for the rdtscp instruction on appropriately 208 * capable hardware. 209 */ 210 if (x86_feature & X86_TSC) 211 setcr4(getcr4() & ~CR4_TSD); 212 213 if (x86_feature & X86_TSCP) 214 (void) wrmsr(MSR_AMD_TSCAUX, 0); 215 216 if (x86_feature & X86_DE) 217 setcr4(getcr4() | CR4_DE); 218 #endif /* __xpv */ 219 220 /* 221 * initialize t0 222 */ 223 t0.t_stk = (caddr_t)rp - MINFRAME; 224 t0.t_stkbase = t0stack; 225 t0.t_pri = maxclsyspri - 3; 226 t0.t_schedflag = TS_LOAD | TS_DONT_SWAP; 227 t0.t_procp = &p0; 228 t0.t_plockp = &p0lock.pl_lock; 229 t0.t_lwp = &lwp0; 230 t0.t_forw = &t0; 231 t0.t_back = &t0; 232 t0.t_next = &t0; 233 t0.t_prev = &t0; 234 t0.t_cpu = cpu[0]; 235 t0.t_disp_queue = &cpu0_disp; 236 t0.t_bind_cpu = PBIND_NONE; 237 t0.t_bind_pset = PS_NONE; 238 t0.t_cpupart = &cp_default; 239 t0.t_clfuncs = &sys_classfuncs.thread; 240 t0.t_copyops = NULL; 241 THREAD_ONPROC(&t0, CPU); 242 243 lwp0.lwp_thread = &t0; 244 lwp0.lwp_regs = (void *)rp; 245 lwp0.lwp_procp = &p0; 246 t0.t_tid = p0.p_lwpcnt = p0.p_lwprcnt = p0.p_lwpid = 1; 247 248 p0.p_exec = NULL; 249 p0.p_stat = SRUN; 250 p0.p_flag = SSYS; 251 p0.p_tlist = &t0; 252 p0.p_stksize = 2*PAGESIZE; 253 p0.p_stkpageszc = 0; 254 p0.p_as = &kas; 255 p0.p_lockp = &p0lock; 256 p0.p_brkpageszc = 0; 257 p0.p_t1_lgrpid = LGRP_NONE; 258 p0.p_tr_lgrpid = LGRP_NONE; 259 sigorset(&p0.p_ignore, &ignoredefault); 260 261 CPU->cpu_thread = &t0; 262 bzero(&cpu0_disp, sizeof (disp_t)); 263 CPU->cpu_disp = &cpu0_disp; 264 CPU->cpu_disp->disp_cpu = CPU; 265 CPU->cpu_dispthread = &t0; 266 CPU->cpu_idle_thread = &t0; 267 CPU->cpu_flags = CPU_READY | CPU_RUNNING | CPU_EXISTS | CPU_ENABLE; 268 CPU->cpu_dispatch_pri = t0.t_pri; 269 270 CPU->cpu_id = 0; 271 272 CPU->cpu_pri = 12; /* initial PIL for the boot CPU */ 273 274 /* 275 * The kernel doesn't use LDTs unless a process explicitly requests one. 276 */ 277 p0.p_ldt_desc = null_sdesc; 278 279 /* 280 * Initialize thread/cpu microstate accounting 281 */ 282 init_mstate(&t0, LMS_SYSTEM); 283 init_cpu_mstate(CPU, CMS_SYSTEM); 284 285 /* 286 * Initialize lists of available and active CPUs. 287 */ 288 cpu_list_init(CPU); 289 290 /* 291 * Now that we have taken over the GDT, IDT and have initialized 292 * active CPU list it's time to inform kmdb if present. 293 */ 294 if (boothowto & RB_DEBUG) 295 kdi_idt_sync(); 296 297 /* 298 * If requested (boot -d) drop into kmdb. 299 * 300 * This must be done after cpu_list_init() on the 64-bit kernel 301 * since taking a trap requires that we re-compute gsbase based 302 * on the cpu list. 303 */ 304 if (boothowto & RB_DEBUGENTER) 305 kmdb_enter(); 306 307 cpu_vm_data_init(CPU); 308 309 /* lgrp_init() needs PCI config space access */ 310 #if defined(__xpv) 311 if (DOMAIN_IS_INITDOMAIN(xen_info)) 312 pci_cfgspace_init(); 313 #else 314 pci_cfgspace_init(); 315 #endif 316 317 /* 318 * Initialize the lgrp framework 319 */ 320 lgrp_init(); 321 322 rp->r_fp = 0; /* terminate kernel stack traces! */ 323 324 prom_init("kernel", (void *)NULL); 325 326 boot_ncpus = bootprop_getval("boot-ncpus"); 327 328 if (boot_ncpus <= 0 || boot_ncpus > NCPU) 329 boot_ncpus = NCPU; 330 331 max_ncpus = boot_max_ncpus = boot_ncpus; 332 333 if (boothowto & RB_HALT) { 334 prom_printf("unix: kernel halted by -h flag\n"); 335 prom_enter_mon(); 336 } 337 338 ASSERT_STACK_ALIGNED(); 339 340 #if !defined(__xpv) 341 /* 342 * Fill out cpu_ucode_info. Update microcode if necessary. 343 */ 344 ucode_check(CPU); 345 #endif 346 347 if (workaround_errata(CPU) != 0) 348 panic("critical workaround(s) missing for boot cpu"); 349 } 350