xref: /titanic_44/usr/src/uts/i86pc/os/cpupm/cpupm_amd.c (revision 0e7515250c8395f368aa45fb9acae7c4f8f8b786)
1*0e751525SEric Saxe /*
2*0e751525SEric Saxe  * CDDL HEADER START
3*0e751525SEric Saxe  *
4*0e751525SEric Saxe  * The contents of this file are subject to the terms of the
5*0e751525SEric Saxe  * Common Development and Distribution License (the "License").
6*0e751525SEric Saxe  * You may not use this file except in compliance with the License.
7*0e751525SEric Saxe  *
8*0e751525SEric Saxe  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9*0e751525SEric Saxe  * or http://www.opensolaris.org/os/licensing.
10*0e751525SEric Saxe  * See the License for the specific language governing permissions
11*0e751525SEric Saxe  * and limitations under the License.
12*0e751525SEric Saxe  *
13*0e751525SEric Saxe  * When distributing Covered Code, include this CDDL HEADER in each
14*0e751525SEric Saxe  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15*0e751525SEric Saxe  * If applicable, add the following below this CDDL HEADER, with the
16*0e751525SEric Saxe  * fields enclosed by brackets "[]" replaced with your own identifying
17*0e751525SEric Saxe  * information: Portions Copyright [yyyy] [name of copyright owner]
18*0e751525SEric Saxe  *
19*0e751525SEric Saxe  * CDDL HEADER END
20*0e751525SEric Saxe  */
21*0e751525SEric Saxe /*
22*0e751525SEric Saxe  * Copyright 2009 Sun Microsystems, Inc.  All rights reserved.
23*0e751525SEric Saxe  * Use is subject to license terms.
24*0e751525SEric Saxe  */
25*0e751525SEric Saxe 
26*0e751525SEric Saxe /*
27*0e751525SEric Saxe  * AMD specific CPU power management support.
28*0e751525SEric Saxe  */
29*0e751525SEric Saxe 
30*0e751525SEric Saxe #include <sys/x86_archext.h>
31*0e751525SEric Saxe #include <sys/cpu_acpi.h>
32*0e751525SEric Saxe #include <sys/pwrnow.h>
33*0e751525SEric Saxe 
34*0e751525SEric Saxe boolean_t
cpupm_amd_init(cpu_t * cp)35*0e751525SEric Saxe cpupm_amd_init(cpu_t *cp)
36*0e751525SEric Saxe {
37*0e751525SEric Saxe 	cpupm_mach_state_t *mach_state =
38*0e751525SEric Saxe 	    (cpupm_mach_state_t *)(cp->cpu_m.mcpu_pm_mach_state);
39*0e751525SEric Saxe 
40*0e751525SEric Saxe 	/* AMD? */
41*0e751525SEric Saxe 	if (x86_vendor != X86_VENDOR_AMD)
42*0e751525SEric Saxe 		return (B_FALSE);
43*0e751525SEric Saxe 
44*0e751525SEric Saxe 	/*
45*0e751525SEric Saxe 	 * If we support PowerNow! on this processor, then set the
46*0e751525SEric Saxe 	 * correct cma_ops for the processor.
47*0e751525SEric Saxe 	 */
48*0e751525SEric Saxe 	mach_state->ms_pstate.cma_ops = pwrnow_supported() ?
49*0e751525SEric Saxe 	    &pwrnow_ops : NULL;
50*0e751525SEric Saxe 
51*0e751525SEric Saxe 	return (B_TRUE);
52*0e751525SEric Saxe }
53