1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright (c) 2004, 2010, Oracle and/or its affiliates. All rights reserved. 23 * Copyright (c) 2011 by Delphix. All rights reserved. 24 * Copyright 2013 Nexenta Systems, Inc. All rights reserved. 25 * Copyright 2014 Josef "Jeff" Sipek <jeffpc@josefsipek.net> 26 */ 27 /* 28 * Copyright (c) 2010, Intel Corporation. 29 * All rights reserved. 30 */ 31 /* 32 * Portions Copyright 2009 Advanced Micro Devices, Inc. 33 */ 34 /* 35 * Copyright 2016 Joyent, Inc. 36 */ 37 /* 38 * Various routines to handle identification 39 * and classification of x86 processors. 40 */ 41 42 #include <sys/types.h> 43 #include <sys/archsystm.h> 44 #include <sys/x86_archext.h> 45 #include <sys/kmem.h> 46 #include <sys/systm.h> 47 #include <sys/cmn_err.h> 48 #include <sys/sunddi.h> 49 #include <sys/sunndi.h> 50 #include <sys/cpuvar.h> 51 #include <sys/processor.h> 52 #include <sys/sysmacros.h> 53 #include <sys/pg.h> 54 #include <sys/fp.h> 55 #include <sys/controlregs.h> 56 #include <sys/bitmap.h> 57 #include <sys/auxv_386.h> 58 #include <sys/memnode.h> 59 #include <sys/pci_cfgspace.h> 60 #include <sys/comm_page.h> 61 #include <sys/tsc.h> 62 63 #ifdef __xpv 64 #include <sys/hypervisor.h> 65 #else 66 #include <sys/ontrap.h> 67 #endif 68 69 /* 70 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 71 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 72 * them accordingly. For most modern processors, feature detection occurs here 73 * in pass 1. 74 * 75 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 76 * for the boot CPU and does the basic analysis that the early kernel needs. 77 * x86_featureset is set based on the return value of cpuid_pass1() of the boot 78 * CPU. 79 * 80 * Pass 1 includes: 81 * 82 * o Determining vendor/model/family/stepping and setting x86_type and 83 * x86_vendor accordingly. 84 * o Processing the feature flags returned by the cpuid instruction while 85 * applying any workarounds or tricks for the specific processor. 86 * o Mapping the feature flags into Solaris feature bits (X86_*). 87 * o Processing extended feature flags if supported by the processor, 88 * again while applying specific processor knowledge. 89 * o Determining the CMT characteristics of the system. 90 * 91 * Pass 1 is done on non-boot CPUs during their initialization and the results 92 * are used only as a meager attempt at ensuring that all processors within the 93 * system support the same features. 94 * 95 * Pass 2 of cpuid feature analysis happens just at the beginning 96 * of startup(). It just copies in and corrects the remainder 97 * of the cpuid data we depend on: standard cpuid functions that we didn't 98 * need for pass1 feature analysis, and extended cpuid functions beyond the 99 * simple feature processing done in pass1. 100 * 101 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 102 * particular kernel memory allocation has been made available. It creates a 103 * readable brand string based on the data collected in the first two passes. 104 * 105 * Pass 4 of cpuid analysis is invoked after post_startup() when all 106 * the support infrastructure for various hardware features has been 107 * initialized. It determines which processor features will be reported 108 * to userland via the aux vector. 109 * 110 * All passes are executed on all CPUs, but only the boot CPU determines what 111 * features the kernel will use. 112 * 113 * Much of the worst junk in this file is for the support of processors 114 * that didn't really implement the cpuid instruction properly. 115 * 116 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 117 * the pass numbers. Accordingly, changes to the pass code may require changes 118 * to the accessor code. 119 */ 120 121 uint_t x86_vendor = X86_VENDOR_IntelClone; 122 uint_t x86_type = X86_TYPE_OTHER; 123 uint_t x86_clflush_size = 0; 124 125 uint_t pentiumpro_bug4046376; 126 127 uchar_t x86_featureset[BT_SIZEOFMAP(NUM_X86_FEATURES)]; 128 129 static char *x86_feature_names[NUM_X86_FEATURES] = { 130 "lgpg", 131 "tsc", 132 "msr", 133 "mtrr", 134 "pge", 135 "de", 136 "cmov", 137 "mmx", 138 "mca", 139 "pae", 140 "cv8", 141 "pat", 142 "sep", 143 "sse", 144 "sse2", 145 "htt", 146 "asysc", 147 "nx", 148 "sse3", 149 "cx16", 150 "cmp", 151 "tscp", 152 "mwait", 153 "sse4a", 154 "cpuid", 155 "ssse3", 156 "sse4_1", 157 "sse4_2", 158 "1gpg", 159 "clfsh", 160 "64", 161 "aes", 162 "pclmulqdq", 163 "xsave", 164 "avx", 165 "vmx", 166 "svm", 167 "topoext", 168 "f16c", 169 "rdrand", 170 "x2apic", 171 "avx2", 172 "bmi1", 173 "bmi2", 174 "fma", 175 "smep", 176 "adx", 177 "rdseed" 178 }; 179 180 boolean_t 181 is_x86_feature(void *featureset, uint_t feature) 182 { 183 ASSERT(feature < NUM_X86_FEATURES); 184 return (BT_TEST((ulong_t *)featureset, feature)); 185 } 186 187 void 188 add_x86_feature(void *featureset, uint_t feature) 189 { 190 ASSERT(feature < NUM_X86_FEATURES); 191 BT_SET((ulong_t *)featureset, feature); 192 } 193 194 void 195 remove_x86_feature(void *featureset, uint_t feature) 196 { 197 ASSERT(feature < NUM_X86_FEATURES); 198 BT_CLEAR((ulong_t *)featureset, feature); 199 } 200 201 boolean_t 202 compare_x86_featureset(void *setA, void *setB) 203 { 204 /* 205 * We assume that the unused bits of the bitmap are always zero. 206 */ 207 if (memcmp(setA, setB, BT_SIZEOFMAP(NUM_X86_FEATURES)) == 0) { 208 return (B_TRUE); 209 } else { 210 return (B_FALSE); 211 } 212 } 213 214 void 215 print_x86_featureset(void *featureset) 216 { 217 uint_t i; 218 219 for (i = 0; i < NUM_X86_FEATURES; i++) { 220 if (is_x86_feature(featureset, i)) { 221 cmn_err(CE_CONT, "?x86_feature: %s\n", 222 x86_feature_names[i]); 223 } 224 } 225 } 226 227 static size_t xsave_state_size = 0; 228 uint64_t xsave_bv_all = (XFEATURE_LEGACY_FP | XFEATURE_SSE); 229 boolean_t xsave_force_disable = B_FALSE; 230 231 /* 232 * This is set to platform type we are running on. 233 */ 234 static int platform_type = -1; 235 236 #if !defined(__xpv) 237 /* 238 * Variable to patch if hypervisor platform detection needs to be 239 * disabled (e.g. platform_type will always be HW_NATIVE if this is 0). 240 */ 241 int enable_platform_detection = 1; 242 #endif 243 244 /* 245 * monitor/mwait info. 246 * 247 * size_actual and buf_actual are the real address and size allocated to get 248 * proper mwait_buf alignement. buf_actual and size_actual should be passed 249 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 250 * processor cache-line alignment, but this is not guarantied in the furture. 251 */ 252 struct mwait_info { 253 size_t mon_min; /* min size to avoid missed wakeups */ 254 size_t mon_max; /* size to avoid false wakeups */ 255 size_t size_actual; /* size actually allocated */ 256 void *buf_actual; /* memory actually allocated */ 257 uint32_t support; /* processor support of monitor/mwait */ 258 }; 259 260 /* 261 * xsave/xrestor info. 262 * 263 * This structure contains HW feature bits and size of the xsave save area. 264 * Note: the kernel will use the maximum size required for all hardware 265 * features. It is not optimize for potential memory savings if features at 266 * the end of the save area are not enabled. 267 */ 268 struct xsave_info { 269 uint32_t xsav_hw_features_low; /* Supported HW features */ 270 uint32_t xsav_hw_features_high; /* Supported HW features */ 271 size_t xsav_max_size; /* max size save area for HW features */ 272 size_t ymm_size; /* AVX: size of ymm save area */ 273 size_t ymm_offset; /* AVX: offset for ymm save area */ 274 }; 275 276 277 /* 278 * These constants determine how many of the elements of the 279 * cpuid we cache in the cpuid_info data structure; the 280 * remaining elements are accessible via the cpuid instruction. 281 */ 282 283 #define NMAX_CPI_STD 8 /* eax = 0 .. 7 */ 284 #define NMAX_CPI_EXTD 0x1f /* eax = 0x80000000 .. 0x8000001e */ 285 286 /* 287 * Some terminology needs to be explained: 288 * - Socket: Something that can be plugged into a motherboard. 289 * - Package: Same as socket 290 * - Chip: Same as socket. Note that AMD's documentation uses term "chip" 291 * differently: there, chip is the same as processor node (below) 292 * - Processor node: Some AMD processors have more than one 293 * "subprocessor" embedded in a package. These subprocessors (nodes) 294 * are fully-functional processors themselves with cores, caches, 295 * memory controllers, PCI configuration spaces. They are connected 296 * inside the package with Hypertransport links. On single-node 297 * processors, processor node is equivalent to chip/socket/package. 298 * - Compute Unit: Some AMD processors pair cores in "compute units" that 299 * share the FPU and the I$ and L2 caches. 300 */ 301 302 struct cpuid_info { 303 uint_t cpi_pass; /* last pass completed */ 304 /* 305 * standard function information 306 */ 307 uint_t cpi_maxeax; /* fn 0: %eax */ 308 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 309 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 310 311 uint_t cpi_family; /* fn 1: extended family */ 312 uint_t cpi_model; /* fn 1: extended model */ 313 uint_t cpi_step; /* fn 1: stepping */ 314 chipid_t cpi_chipid; /* fn 1: %ebx: Intel: chip # */ 315 /* AMD: package/socket # */ 316 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 317 int cpi_clogid; /* fn 1: %ebx: thread # */ 318 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 319 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 320 uint_t cpi_ncache; /* fn 2: number of elements */ 321 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 322 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 323 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 324 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 325 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 7 */ 326 /* 327 * extended function information 328 */ 329 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 330 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 331 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 332 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 333 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x800000XX */ 334 335 id_t cpi_coreid; /* same coreid => strands share core */ 336 int cpi_pkgcoreid; /* core number within single package */ 337 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 338 /* Intel: fn 4: %eax[31-26] */ 339 /* 340 * supported feature information 341 */ 342 uint32_t cpi_support[6]; 343 #define STD_EDX_FEATURES 0 344 #define AMD_EDX_FEATURES 1 345 #define TM_EDX_FEATURES 2 346 #define STD_ECX_FEATURES 3 347 #define AMD_ECX_FEATURES 4 348 #define STD_EBX_FEATURES 5 349 /* 350 * Synthesized information, where known. 351 */ 352 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 353 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 354 uint32_t cpi_socket; /* Chip package/socket type */ 355 356 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 357 uint32_t cpi_apicid; 358 uint_t cpi_procnodeid; /* AMD: nodeID on HT, Intel: chipid */ 359 uint_t cpi_procnodes_per_pkg; /* AMD: # of nodes in the package */ 360 /* Intel: 1 */ 361 uint_t cpi_compunitid; /* AMD: ComputeUnit ID, Intel: coreid */ 362 uint_t cpi_cores_per_compunit; /* AMD: # of cores in the ComputeUnit */ 363 364 struct xsave_info cpi_xsave; /* fn D: xsave/xrestor info */ 365 }; 366 367 368 static struct cpuid_info cpuid_info0; 369 370 /* 371 * These bit fields are defined by the Intel Application Note AP-485 372 * "Intel Processor Identification and the CPUID Instruction" 373 */ 374 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 375 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 376 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 377 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 378 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 379 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 380 381 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 382 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 383 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 384 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 385 #define CPI_FEATURES_7_0_EBX(cpi) ((cpi)->cpi_std[7].cp_ebx) 386 387 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 388 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 389 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 390 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 391 392 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 393 #define CPI_XMAXEAX_MAX 0x80000100 394 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 395 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */ 396 397 /* 398 * Function 4 (Deterministic Cache Parameters) macros 399 * Defined by Intel Application Note AP-485 400 */ 401 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 402 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 403 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 404 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 405 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 406 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 407 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8) 408 409 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 410 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 411 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 412 413 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 414 415 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 416 417 418 /* 419 * A couple of shorthand macros to identify "later" P6-family chips 420 * like the Pentium M and Core. First, the "older" P6-based stuff 421 * (loosely defined as "pre-Pentium-4"): 422 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 423 */ 424 425 #define IS_LEGACY_P6(cpi) ( \ 426 cpi->cpi_family == 6 && \ 427 (cpi->cpi_model == 1 || \ 428 cpi->cpi_model == 3 || \ 429 cpi->cpi_model == 5 || \ 430 cpi->cpi_model == 6 || \ 431 cpi->cpi_model == 7 || \ 432 cpi->cpi_model == 8 || \ 433 cpi->cpi_model == 0xA || \ 434 cpi->cpi_model == 0xB) \ 435 ) 436 437 /* A "new F6" is everything with family 6 that's not the above */ 438 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 439 440 /* Extended family/model support */ 441 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 442 cpi->cpi_family >= 0xf) 443 444 /* 445 * Info for monitor/mwait idle loop. 446 * 447 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 448 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 449 * 2006. 450 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 451 * Documentation Updates" #33633, Rev 2.05, December 2006. 452 */ 453 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 454 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 455 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 456 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 457 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 458 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 459 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 460 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 461 /* 462 * Number of sub-cstates for a given c-state. 463 */ 464 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 465 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 466 467 /* 468 * XSAVE leaf 0xD enumeration 469 */ 470 #define CPUID_LEAFD_2_YMM_OFFSET 576 471 #define CPUID_LEAFD_2_YMM_SIZE 256 472 473 /* 474 * Functions we consune from cpuid_subr.c; don't publish these in a header 475 * file to try and keep people using the expected cpuid_* interfaces. 476 */ 477 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t); 478 extern const char *_cpuid_sktstr(uint_t, uint_t, uint_t, uint_t); 479 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t); 480 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t); 481 extern uint_t _cpuid_vendorstr_to_vendorcode(char *); 482 483 /* 484 * Apply up various platform-dependent restrictions where the 485 * underlying platform restrictions mean the CPU can be marked 486 * as less capable than its cpuid instruction would imply. 487 */ 488 #if defined(__xpv) 489 static void 490 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 491 { 492 switch (eax) { 493 case 1: { 494 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ? 495 0 : CPUID_INTC_EDX_MCA; 496 cp->cp_edx &= 497 ~(mcamask | 498 CPUID_INTC_EDX_PSE | 499 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 500 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 501 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 502 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 503 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 504 break; 505 } 506 507 case 0x80000001: 508 cp->cp_edx &= 509 ~(CPUID_AMD_EDX_PSE | 510 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 511 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 512 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 513 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 514 CPUID_AMD_EDX_TSCP); 515 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 516 break; 517 default: 518 break; 519 } 520 521 switch (vendor) { 522 case X86_VENDOR_Intel: 523 switch (eax) { 524 case 4: 525 /* 526 * Zero out the (ncores-per-chip - 1) field 527 */ 528 cp->cp_eax &= 0x03fffffff; 529 break; 530 default: 531 break; 532 } 533 break; 534 case X86_VENDOR_AMD: 535 switch (eax) { 536 537 case 0x80000001: 538 cp->cp_ecx &= ~CPUID_AMD_ECX_CR8D; 539 break; 540 541 case 0x80000008: 542 /* 543 * Zero out the (ncores-per-chip - 1) field 544 */ 545 cp->cp_ecx &= 0xffffff00; 546 break; 547 default: 548 break; 549 } 550 break; 551 default: 552 break; 553 } 554 } 555 #else 556 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 557 #endif 558 559 /* 560 * Some undocumented ways of patching the results of the cpuid 561 * instruction to permit running Solaris 10 on future cpus that 562 * we don't currently support. Could be set to non-zero values 563 * via settings in eeprom. 564 */ 565 566 uint32_t cpuid_feature_ecx_include; 567 uint32_t cpuid_feature_ecx_exclude; 568 uint32_t cpuid_feature_edx_include; 569 uint32_t cpuid_feature_edx_exclude; 570 571 /* 572 * Allocate space for mcpu_cpi in the machcpu structure for all non-boot CPUs. 573 */ 574 void 575 cpuid_alloc_space(cpu_t *cpu) 576 { 577 /* 578 * By convention, cpu0 is the boot cpu, which is set up 579 * before memory allocation is available. All other cpus get 580 * their cpuid_info struct allocated here. 581 */ 582 ASSERT(cpu->cpu_id != 0); 583 ASSERT(cpu->cpu_m.mcpu_cpi == NULL); 584 cpu->cpu_m.mcpu_cpi = 585 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 586 } 587 588 void 589 cpuid_free_space(cpu_t *cpu) 590 { 591 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 592 int i; 593 594 ASSERT(cpi != NULL); 595 ASSERT(cpi != &cpuid_info0); 596 597 /* 598 * Free up any function 4 related dynamic storage 599 */ 600 for (i = 1; i < cpi->cpi_std_4_size; i++) 601 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 602 if (cpi->cpi_std_4_size > 0) 603 kmem_free(cpi->cpi_std_4, 604 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 605 606 kmem_free(cpi, sizeof (*cpi)); 607 cpu->cpu_m.mcpu_cpi = NULL; 608 } 609 610 #if !defined(__xpv) 611 /* 612 * Determine the type of the underlying platform. This is used to customize 613 * initialization of various subsystems (e.g. TSC). determine_platform() must 614 * only ever be called once to prevent two processors from seeing different 615 * values of platform_type. Must be called before cpuid_pass1(), the earliest 616 * consumer to execute (uses _cpuid_chiprev --> synth_amd_info --> get_hwenv). 617 */ 618 void 619 determine_platform(void) 620 { 621 struct cpuid_regs cp; 622 uint32_t base; 623 uint32_t regs[4]; 624 char *hvstr = (char *)regs; 625 626 ASSERT(platform_type == -1); 627 628 platform_type = HW_NATIVE; 629 630 if (!enable_platform_detection) 631 return; 632 633 /* 634 * If Hypervisor CPUID bit is set, try to determine hypervisor 635 * vendor signature, and set platform type accordingly. 636 * 637 * References: 638 * http://lkml.org/lkml/2008/10/1/246 639 * http://kb.vmware.com/kb/1009458 640 */ 641 cp.cp_eax = 0x1; 642 (void) __cpuid_insn(&cp); 643 if ((cp.cp_ecx & CPUID_INTC_ECX_HV) != 0) { 644 cp.cp_eax = 0x40000000; 645 (void) __cpuid_insn(&cp); 646 regs[0] = cp.cp_ebx; 647 regs[1] = cp.cp_ecx; 648 regs[2] = cp.cp_edx; 649 regs[3] = 0; 650 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0) { 651 platform_type = HW_XEN_HVM; 652 return; 653 } 654 if (strcmp(hvstr, HVSIG_VMWARE) == 0) { 655 platform_type = HW_VMWARE; 656 return; 657 } 658 if (strcmp(hvstr, HVSIG_KVM) == 0) { 659 platform_type = HW_KVM; 660 return; 661 } 662 if (strcmp(hvstr, HVSIG_MICROSOFT) == 0) 663 platform_type = HW_MICROSOFT; 664 } else { 665 /* 666 * Check older VMware hardware versions. VMware hypervisor is 667 * detected by performing an IN operation to VMware hypervisor 668 * port and checking that value returned in %ebx is VMware 669 * hypervisor magic value. 670 * 671 * References: http://kb.vmware.com/kb/1009458 672 */ 673 vmware_port(VMWARE_HVCMD_GETVERSION, regs); 674 if (regs[1] == VMWARE_HVMAGIC) { 675 platform_type = HW_VMWARE; 676 return; 677 } 678 } 679 680 /* 681 * Check Xen hypervisor. In a fully virtualized domain, 682 * Xen's pseudo-cpuid function returns a string representing the 683 * Xen signature in %ebx, %ecx, and %edx. %eax contains the maximum 684 * supported cpuid function. We need at least a (base + 2) leaf value 685 * to do what we want to do. Try different base values, since the 686 * hypervisor might use a different one depending on whether Hyper-V 687 * emulation is switched on by default or not. 688 */ 689 for (base = 0x40000000; base < 0x40010000; base += 0x100) { 690 cp.cp_eax = base; 691 (void) __cpuid_insn(&cp); 692 regs[0] = cp.cp_ebx; 693 regs[1] = cp.cp_ecx; 694 regs[2] = cp.cp_edx; 695 regs[3] = 0; 696 if (strcmp(hvstr, HVSIG_XEN_HVM) == 0 && 697 cp.cp_eax >= (base + 2)) { 698 platform_type &= ~HW_NATIVE; 699 platform_type |= HW_XEN_HVM; 700 return; 701 } 702 } 703 } 704 705 int 706 get_hwenv(void) 707 { 708 ASSERT(platform_type != -1); 709 return (platform_type); 710 } 711 712 int 713 is_controldom(void) 714 { 715 return (0); 716 } 717 718 #else 719 720 int 721 get_hwenv(void) 722 { 723 return (HW_XEN_PV); 724 } 725 726 int 727 is_controldom(void) 728 { 729 return (DOMAIN_IS_INITDOMAIN(xen_info)); 730 } 731 732 #endif /* __xpv */ 733 734 static void 735 cpuid_intel_getids(cpu_t *cpu, void *feature) 736 { 737 uint_t i; 738 uint_t chipid_shift = 0; 739 uint_t coreid_shift = 0; 740 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 741 742 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 743 chipid_shift++; 744 745 cpi->cpi_chipid = cpi->cpi_apicid >> chipid_shift; 746 cpi->cpi_clogid = cpi->cpi_apicid & ((1 << chipid_shift) - 1); 747 748 if (is_x86_feature(feature, X86FSET_CMP)) { 749 /* 750 * Multi-core (and possibly multi-threaded) 751 * processors. 752 */ 753 uint_t ncpu_per_core; 754 if (cpi->cpi_ncore_per_chip == 1) 755 ncpu_per_core = cpi->cpi_ncpu_per_chip; 756 else if (cpi->cpi_ncore_per_chip > 1) 757 ncpu_per_core = cpi->cpi_ncpu_per_chip / 758 cpi->cpi_ncore_per_chip; 759 /* 760 * 8bit APIC IDs on dual core Pentiums 761 * look like this: 762 * 763 * +-----------------------+------+------+ 764 * | Physical Package ID | MC | HT | 765 * +-----------------------+------+------+ 766 * <------- chipid --------> 767 * <------- coreid ---------------> 768 * <--- clogid --> 769 * <------> 770 * pkgcoreid 771 * 772 * Where the number of bits necessary to 773 * represent MC and HT fields together equals 774 * to the minimum number of bits necessary to 775 * store the value of cpi->cpi_ncpu_per_chip. 776 * Of those bits, the MC part uses the number 777 * of bits necessary to store the value of 778 * cpi->cpi_ncore_per_chip. 779 */ 780 for (i = 1; i < ncpu_per_core; i <<= 1) 781 coreid_shift++; 782 cpi->cpi_coreid = cpi->cpi_apicid >> coreid_shift; 783 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; 784 } else if (is_x86_feature(feature, X86FSET_HTT)) { 785 /* 786 * Single-core multi-threaded processors. 787 */ 788 cpi->cpi_coreid = cpi->cpi_chipid; 789 cpi->cpi_pkgcoreid = 0; 790 } 791 cpi->cpi_procnodeid = cpi->cpi_chipid; 792 cpi->cpi_compunitid = cpi->cpi_coreid; 793 } 794 795 static void 796 cpuid_amd_getids(cpu_t *cpu) 797 { 798 int i, first_half, coreidsz; 799 uint32_t nb_caps_reg; 800 uint_t node2_1; 801 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 802 struct cpuid_regs *cp; 803 804 /* 805 * AMD CMP chips currently have a single thread per core. 806 * 807 * Since no two cpus share a core we must assign a distinct coreid 808 * per cpu, and we do this by using the cpu_id. This scheme does not, 809 * however, guarantee that sibling cores of a chip will have sequential 810 * coreids starting at a multiple of the number of cores per chip - 811 * that is usually the case, but if the ACPI MADT table is presented 812 * in a different order then we need to perform a few more gymnastics 813 * for the pkgcoreid. 814 * 815 * All processors in the system have the same number of enabled 816 * cores. Cores within a processor are always numbered sequentially 817 * from 0 regardless of how many or which are disabled, and there 818 * is no way for operating system to discover the real core id when some 819 * are disabled. 820 * 821 * In family 0x15, the cores come in pairs called compute units. They 822 * share I$ and L2 caches and the FPU. Enumeration of this feature is 823 * simplified by the new topology extensions CPUID leaf, indicated by 824 * the X86 feature X86FSET_TOPOEXT. 825 */ 826 827 cpi->cpi_coreid = cpu->cpu_id; 828 cpi->cpi_compunitid = cpu->cpu_id; 829 830 if (cpi->cpi_xmaxeax >= 0x80000008) { 831 832 coreidsz = BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12); 833 834 /* 835 * In AMD parlance chip is really a node while Solaris 836 * sees chip as equivalent to socket/package. 837 */ 838 cpi->cpi_ncore_per_chip = 839 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 840 if (coreidsz == 0) { 841 /* Use legacy method */ 842 for (i = 1; i < cpi->cpi_ncore_per_chip; i <<= 1) 843 coreidsz++; 844 if (coreidsz == 0) 845 coreidsz = 1; 846 } 847 } else { 848 /* Assume single-core part */ 849 cpi->cpi_ncore_per_chip = 1; 850 coreidsz = 1; 851 } 852 853 cpi->cpi_clogid = cpi->cpi_pkgcoreid = 854 cpi->cpi_apicid & ((1<<coreidsz) - 1); 855 cpi->cpi_ncpu_per_chip = cpi->cpi_ncore_per_chip; 856 857 /* Get node ID, compute unit ID */ 858 if (is_x86_feature(x86_featureset, X86FSET_TOPOEXT) && 859 cpi->cpi_xmaxeax >= 0x8000001e) { 860 cp = &cpi->cpi_extd[0x1e]; 861 cp->cp_eax = 0x8000001e; 862 (void) __cpuid_insn(cp); 863 864 cpi->cpi_procnodes_per_pkg = BITX(cp->cp_ecx, 10, 8) + 1; 865 cpi->cpi_procnodeid = BITX(cp->cp_ecx, 7, 0); 866 cpi->cpi_cores_per_compunit = BITX(cp->cp_ebx, 15, 8) + 1; 867 cpi->cpi_compunitid = BITX(cp->cp_ebx, 7, 0) 868 + (cpi->cpi_ncore_per_chip / cpi->cpi_cores_per_compunit) 869 * (cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg); 870 } else if (cpi->cpi_family == 0xf || cpi->cpi_family >= 0x11) { 871 cpi->cpi_procnodeid = (cpi->cpi_apicid >> coreidsz) & 7; 872 } else if (cpi->cpi_family == 0x10) { 873 /* 874 * See if we are a multi-node processor. 875 * All processors in the system have the same number of nodes 876 */ 877 nb_caps_reg = pci_getl_func(0, 24, 3, 0xe8); 878 if ((cpi->cpi_model < 8) || BITX(nb_caps_reg, 29, 29) == 0) { 879 /* Single-node */ 880 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 5, 881 coreidsz); 882 } else { 883 884 /* 885 * Multi-node revision D (2 nodes per package 886 * are supported) 887 */ 888 cpi->cpi_procnodes_per_pkg = 2; 889 890 first_half = (cpi->cpi_pkgcoreid <= 891 (cpi->cpi_ncore_per_chip/2 - 1)); 892 893 if (cpi->cpi_apicid == cpi->cpi_pkgcoreid) { 894 /* We are BSP */ 895 cpi->cpi_procnodeid = (first_half ? 0 : 1); 896 } else { 897 898 /* We are AP */ 899 /* NodeId[2:1] bits to use for reading F3xe8 */ 900 node2_1 = BITX(cpi->cpi_apicid, 5, 4) << 1; 901 902 nb_caps_reg = 903 pci_getl_func(0, 24 + node2_1, 3, 0xe8); 904 905 /* 906 * Check IntNodeNum bit (31:30, but bit 31 is 907 * always 0 on dual-node processors) 908 */ 909 if (BITX(nb_caps_reg, 30, 30) == 0) 910 cpi->cpi_procnodeid = node2_1 + 911 !first_half; 912 else 913 cpi->cpi_procnodeid = node2_1 + 914 first_half; 915 } 916 } 917 } else { 918 cpi->cpi_procnodeid = 0; 919 } 920 921 cpi->cpi_chipid = 922 cpi->cpi_procnodeid / cpi->cpi_procnodes_per_pkg; 923 } 924 925 /* 926 * Setup XFeature_Enabled_Mask register. Required by xsave feature. 927 */ 928 void 929 setup_xfem(void) 930 { 931 uint64_t flags = XFEATURE_LEGACY_FP; 932 933 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE)); 934 935 if (is_x86_feature(x86_featureset, X86FSET_SSE)) 936 flags |= XFEATURE_SSE; 937 938 if (is_x86_feature(x86_featureset, X86FSET_AVX)) 939 flags |= XFEATURE_AVX; 940 941 set_xcr(XFEATURE_ENABLED_MASK, flags); 942 943 xsave_bv_all = flags; 944 } 945 946 void 947 cpuid_pass1(cpu_t *cpu, uchar_t *featureset) 948 { 949 uint32_t mask_ecx, mask_edx; 950 struct cpuid_info *cpi; 951 struct cpuid_regs *cp; 952 int xcpuid; 953 #if !defined(__xpv) 954 extern int idle_cpu_prefer_mwait; 955 #endif 956 957 /* 958 * Space statically allocated for BSP, ensure pointer is set 959 */ 960 if (cpu->cpu_id == 0) { 961 if (cpu->cpu_m.mcpu_cpi == NULL) 962 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 963 } 964 965 add_x86_feature(featureset, X86FSET_CPUID); 966 967 cpi = cpu->cpu_m.mcpu_cpi; 968 ASSERT(cpi != NULL); 969 cp = &cpi->cpi_std[0]; 970 cp->cp_eax = 0; 971 cpi->cpi_maxeax = __cpuid_insn(cp); 972 { 973 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 974 *iptr++ = cp->cp_ebx; 975 *iptr++ = cp->cp_edx; 976 *iptr++ = cp->cp_ecx; 977 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 978 } 979 980 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr); 981 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 982 983 /* 984 * Limit the range in case of weird hardware 985 */ 986 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 987 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 988 if (cpi->cpi_maxeax < 1) 989 goto pass1_done; 990 991 cp = &cpi->cpi_std[1]; 992 cp->cp_eax = 1; 993 (void) __cpuid_insn(cp); 994 995 /* 996 * Extract identifying constants for easy access. 997 */ 998 cpi->cpi_model = CPI_MODEL(cpi); 999 cpi->cpi_family = CPI_FAMILY(cpi); 1000 1001 if (cpi->cpi_family == 0xf) 1002 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 1003 1004 /* 1005 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 1006 * Intel, and presumably everyone else, uses model == 0xf, as 1007 * one would expect (max value means possible overflow). Sigh. 1008 */ 1009 1010 switch (cpi->cpi_vendor) { 1011 case X86_VENDOR_Intel: 1012 if (IS_EXTENDED_MODEL_INTEL(cpi)) 1013 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 1014 break; 1015 case X86_VENDOR_AMD: 1016 if (CPI_FAMILY(cpi) == 0xf) 1017 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 1018 break; 1019 default: 1020 if (cpi->cpi_model == 0xf) 1021 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 1022 break; 1023 } 1024 1025 cpi->cpi_step = CPI_STEP(cpi); 1026 cpi->cpi_brandid = CPI_BRANDID(cpi); 1027 1028 /* 1029 * *default* assumptions: 1030 * - believe %edx feature word 1031 * - ignore %ecx feature word 1032 * - 32-bit virtual and physical addressing 1033 */ 1034 mask_edx = 0xffffffff; 1035 mask_ecx = 0; 1036 1037 cpi->cpi_pabits = cpi->cpi_vabits = 32; 1038 1039 switch (cpi->cpi_vendor) { 1040 case X86_VENDOR_Intel: 1041 if (cpi->cpi_family == 5) 1042 x86_type = X86_TYPE_P5; 1043 else if (IS_LEGACY_P6(cpi)) { 1044 x86_type = X86_TYPE_P6; 1045 pentiumpro_bug4046376 = 1; 1046 /* 1047 * Clear the SEP bit when it was set erroneously 1048 */ 1049 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 1050 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 1051 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 1052 x86_type = X86_TYPE_P4; 1053 /* 1054 * We don't currently depend on any of the %ecx 1055 * features until Prescott, so we'll only check 1056 * this from P4 onwards. We might want to revisit 1057 * that idea later. 1058 */ 1059 mask_ecx = 0xffffffff; 1060 } else if (cpi->cpi_family > 0xf) 1061 mask_ecx = 0xffffffff; 1062 /* 1063 * We don't support MONITOR/MWAIT if leaf 5 is not available 1064 * to obtain the monitor linesize. 1065 */ 1066 if (cpi->cpi_maxeax < 5) 1067 mask_ecx &= ~CPUID_INTC_ECX_MON; 1068 break; 1069 case X86_VENDOR_IntelClone: 1070 default: 1071 break; 1072 case X86_VENDOR_AMD: 1073 #if defined(OPTERON_ERRATUM_108) 1074 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 1075 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 1076 cpi->cpi_model = 0xc; 1077 } else 1078 #endif 1079 if (cpi->cpi_family == 5) { 1080 /* 1081 * AMD K5 and K6 1082 * 1083 * These CPUs have an incomplete implementation 1084 * of MCA/MCE which we mask away. 1085 */ 1086 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 1087 1088 /* 1089 * Model 0 uses the wrong (APIC) bit 1090 * to indicate PGE. Fix it here. 1091 */ 1092 if (cpi->cpi_model == 0) { 1093 if (cp->cp_edx & 0x200) { 1094 cp->cp_edx &= ~0x200; 1095 cp->cp_edx |= CPUID_INTC_EDX_PGE; 1096 } 1097 } 1098 1099 /* 1100 * Early models had problems w/ MMX; disable. 1101 */ 1102 if (cpi->cpi_model < 6) 1103 mask_edx &= ~CPUID_INTC_EDX_MMX; 1104 } 1105 1106 /* 1107 * For newer families, SSE3 and CX16, at least, are valid; 1108 * enable all 1109 */ 1110 if (cpi->cpi_family >= 0xf) 1111 mask_ecx = 0xffffffff; 1112 /* 1113 * We don't support MONITOR/MWAIT if leaf 5 is not available 1114 * to obtain the monitor linesize. 1115 */ 1116 if (cpi->cpi_maxeax < 5) 1117 mask_ecx &= ~CPUID_INTC_ECX_MON; 1118 1119 #if !defined(__xpv) 1120 /* 1121 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 1122 * processors. AMD does not intend MWAIT to be used in the cpu 1123 * idle loop on current and future processors. 10h and future 1124 * AMD processors use more power in MWAIT than HLT. 1125 * Pre-family-10h Opterons do not have the MWAIT instruction. 1126 */ 1127 idle_cpu_prefer_mwait = 0; 1128 #endif 1129 1130 break; 1131 case X86_VENDOR_TM: 1132 /* 1133 * workaround the NT workaround in CMS 4.1 1134 */ 1135 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 1136 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 1137 cp->cp_edx |= CPUID_INTC_EDX_CX8; 1138 break; 1139 case X86_VENDOR_Centaur: 1140 /* 1141 * workaround the NT workarounds again 1142 */ 1143 if (cpi->cpi_family == 6) 1144 cp->cp_edx |= CPUID_INTC_EDX_CX8; 1145 break; 1146 case X86_VENDOR_Cyrix: 1147 /* 1148 * We rely heavily on the probing in locore 1149 * to actually figure out what parts, if any, 1150 * of the Cyrix cpuid instruction to believe. 1151 */ 1152 switch (x86_type) { 1153 case X86_TYPE_CYRIX_486: 1154 mask_edx = 0; 1155 break; 1156 case X86_TYPE_CYRIX_6x86: 1157 mask_edx = 0; 1158 break; 1159 case X86_TYPE_CYRIX_6x86L: 1160 mask_edx = 1161 CPUID_INTC_EDX_DE | 1162 CPUID_INTC_EDX_CX8; 1163 break; 1164 case X86_TYPE_CYRIX_6x86MX: 1165 mask_edx = 1166 CPUID_INTC_EDX_DE | 1167 CPUID_INTC_EDX_MSR | 1168 CPUID_INTC_EDX_CX8 | 1169 CPUID_INTC_EDX_PGE | 1170 CPUID_INTC_EDX_CMOV | 1171 CPUID_INTC_EDX_MMX; 1172 break; 1173 case X86_TYPE_CYRIX_GXm: 1174 mask_edx = 1175 CPUID_INTC_EDX_MSR | 1176 CPUID_INTC_EDX_CX8 | 1177 CPUID_INTC_EDX_CMOV | 1178 CPUID_INTC_EDX_MMX; 1179 break; 1180 case X86_TYPE_CYRIX_MediaGX: 1181 break; 1182 case X86_TYPE_CYRIX_MII: 1183 case X86_TYPE_VIA_CYRIX_III: 1184 mask_edx = 1185 CPUID_INTC_EDX_DE | 1186 CPUID_INTC_EDX_TSC | 1187 CPUID_INTC_EDX_MSR | 1188 CPUID_INTC_EDX_CX8 | 1189 CPUID_INTC_EDX_PGE | 1190 CPUID_INTC_EDX_CMOV | 1191 CPUID_INTC_EDX_MMX; 1192 break; 1193 default: 1194 break; 1195 } 1196 break; 1197 } 1198 1199 #if defined(__xpv) 1200 /* 1201 * Do not support MONITOR/MWAIT under a hypervisor 1202 */ 1203 mask_ecx &= ~CPUID_INTC_ECX_MON; 1204 /* 1205 * Do not support XSAVE under a hypervisor for now 1206 */ 1207 xsave_force_disable = B_TRUE; 1208 1209 #endif /* __xpv */ 1210 1211 if (xsave_force_disable) { 1212 mask_ecx &= ~CPUID_INTC_ECX_XSAVE; 1213 mask_ecx &= ~CPUID_INTC_ECX_AVX; 1214 mask_ecx &= ~CPUID_INTC_ECX_F16C; 1215 mask_ecx &= ~CPUID_INTC_ECX_FMA; 1216 } 1217 1218 /* 1219 * Now we've figured out the masks that determine 1220 * which bits we choose to believe, apply the masks 1221 * to the feature words, then map the kernel's view 1222 * of these feature words into its feature word. 1223 */ 1224 cp->cp_edx &= mask_edx; 1225 cp->cp_ecx &= mask_ecx; 1226 1227 /* 1228 * apply any platform restrictions (we don't call this 1229 * immediately after __cpuid_insn here, because we need the 1230 * workarounds applied above first) 1231 */ 1232 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 1233 1234 /* 1235 * In addition to ecx and edx, Intel is storing a bunch of instruction 1236 * set extensions in leaf 7's ebx. 1237 */ 1238 if (cpi->cpi_vendor == X86_VENDOR_Intel && cpi->cpi_maxeax >= 7) { 1239 struct cpuid_regs *ecp; 1240 ecp = &cpi->cpi_std[7]; 1241 ecp->cp_eax = 7; 1242 ecp->cp_ecx = 0; 1243 (void) __cpuid_insn(ecp); 1244 /* 1245 * If XSAVE has been disabled, just ignore all of the AVX 1246 * dependent flags here. 1247 */ 1248 if (xsave_force_disable) { 1249 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI1; 1250 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_BMI2; 1251 ecp->cp_ebx &= ~CPUID_INTC_EBX_7_0_AVX2; 1252 } 1253 1254 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_SMEP) 1255 add_x86_feature(featureset, X86FSET_SMEP); 1256 1257 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_RDSEED) 1258 add_x86_feature(featureset, X86FSET_RDSEED); 1259 1260 if (ecp->cp_ebx & CPUID_INTC_EBX_7_0_ADX) 1261 add_x86_feature(featureset, X86FSET_ADX); 1262 } 1263 1264 /* 1265 * fold in overrides from the "eeprom" mechanism 1266 */ 1267 cp->cp_edx |= cpuid_feature_edx_include; 1268 cp->cp_edx &= ~cpuid_feature_edx_exclude; 1269 1270 cp->cp_ecx |= cpuid_feature_ecx_include; 1271 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 1272 1273 if (cp->cp_edx & CPUID_INTC_EDX_PSE) { 1274 add_x86_feature(featureset, X86FSET_LARGEPAGE); 1275 } 1276 if (cp->cp_edx & CPUID_INTC_EDX_TSC) { 1277 add_x86_feature(featureset, X86FSET_TSC); 1278 } 1279 if (cp->cp_edx & CPUID_INTC_EDX_MSR) { 1280 add_x86_feature(featureset, X86FSET_MSR); 1281 } 1282 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) { 1283 add_x86_feature(featureset, X86FSET_MTRR); 1284 } 1285 if (cp->cp_edx & CPUID_INTC_EDX_PGE) { 1286 add_x86_feature(featureset, X86FSET_PGE); 1287 } 1288 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) { 1289 add_x86_feature(featureset, X86FSET_CMOV); 1290 } 1291 if (cp->cp_edx & CPUID_INTC_EDX_MMX) { 1292 add_x86_feature(featureset, X86FSET_MMX); 1293 } 1294 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 1295 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) { 1296 add_x86_feature(featureset, X86FSET_MCA); 1297 } 1298 if (cp->cp_edx & CPUID_INTC_EDX_PAE) { 1299 add_x86_feature(featureset, X86FSET_PAE); 1300 } 1301 if (cp->cp_edx & CPUID_INTC_EDX_CX8) { 1302 add_x86_feature(featureset, X86FSET_CX8); 1303 } 1304 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) { 1305 add_x86_feature(featureset, X86FSET_CX16); 1306 } 1307 if (cp->cp_edx & CPUID_INTC_EDX_PAT) { 1308 add_x86_feature(featureset, X86FSET_PAT); 1309 } 1310 if (cp->cp_edx & CPUID_INTC_EDX_SEP) { 1311 add_x86_feature(featureset, X86FSET_SEP); 1312 } 1313 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 1314 /* 1315 * In our implementation, fxsave/fxrstor 1316 * are prerequisites before we'll even 1317 * try and do SSE things. 1318 */ 1319 if (cp->cp_edx & CPUID_INTC_EDX_SSE) { 1320 add_x86_feature(featureset, X86FSET_SSE); 1321 } 1322 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) { 1323 add_x86_feature(featureset, X86FSET_SSE2); 1324 } 1325 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) { 1326 add_x86_feature(featureset, X86FSET_SSE3); 1327 } 1328 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) { 1329 add_x86_feature(featureset, X86FSET_SSSE3); 1330 } 1331 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) { 1332 add_x86_feature(featureset, X86FSET_SSE4_1); 1333 } 1334 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) { 1335 add_x86_feature(featureset, X86FSET_SSE4_2); 1336 } 1337 if (cp->cp_ecx & CPUID_INTC_ECX_AES) { 1338 add_x86_feature(featureset, X86FSET_AES); 1339 } 1340 if (cp->cp_ecx & CPUID_INTC_ECX_PCLMULQDQ) { 1341 add_x86_feature(featureset, X86FSET_PCLMULQDQ); 1342 } 1343 1344 if (cp->cp_ecx & CPUID_INTC_ECX_XSAVE) { 1345 add_x86_feature(featureset, X86FSET_XSAVE); 1346 1347 /* We only test AVX when there is XSAVE */ 1348 if (cp->cp_ecx & CPUID_INTC_ECX_AVX) { 1349 add_x86_feature(featureset, 1350 X86FSET_AVX); 1351 1352 /* 1353 * Intel says we can't check these without also 1354 * checking AVX. 1355 */ 1356 if (cp->cp_ecx & CPUID_INTC_ECX_F16C) 1357 add_x86_feature(featureset, 1358 X86FSET_F16C); 1359 1360 if (cp->cp_ecx & CPUID_INTC_ECX_FMA) 1361 add_x86_feature(featureset, 1362 X86FSET_FMA); 1363 1364 if (cpi->cpi_std[7].cp_ebx & 1365 CPUID_INTC_EBX_7_0_BMI1) 1366 add_x86_feature(featureset, 1367 X86FSET_BMI1); 1368 1369 if (cpi->cpi_std[7].cp_ebx & 1370 CPUID_INTC_EBX_7_0_BMI2) 1371 add_x86_feature(featureset, 1372 X86FSET_BMI2); 1373 1374 if (cpi->cpi_std[7].cp_ebx & 1375 CPUID_INTC_EBX_7_0_AVX2) 1376 add_x86_feature(featureset, 1377 X86FSET_AVX2); 1378 } 1379 } 1380 } 1381 if (cp->cp_ecx & CPUID_INTC_ECX_X2APIC) { 1382 add_x86_feature(featureset, X86FSET_X2APIC); 1383 } 1384 if (cp->cp_edx & CPUID_INTC_EDX_DE) { 1385 add_x86_feature(featureset, X86FSET_DE); 1386 } 1387 #if !defined(__xpv) 1388 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 1389 1390 /* 1391 * We require the CLFLUSH instruction for erratum workaround 1392 * to use MONITOR/MWAIT. 1393 */ 1394 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 1395 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 1396 add_x86_feature(featureset, X86FSET_MWAIT); 1397 } else { 1398 extern int idle_cpu_assert_cflush_monitor; 1399 1400 /* 1401 * All processors we are aware of which have 1402 * MONITOR/MWAIT also have CLFLUSH. 1403 */ 1404 if (idle_cpu_assert_cflush_monitor) { 1405 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) && 1406 (cp->cp_edx & CPUID_INTC_EDX_CLFSH)); 1407 } 1408 } 1409 } 1410 #endif /* __xpv */ 1411 1412 if (cp->cp_ecx & CPUID_INTC_ECX_VMX) { 1413 add_x86_feature(featureset, X86FSET_VMX); 1414 } 1415 1416 if (cp->cp_ecx & CPUID_INTC_ECX_RDRAND) 1417 add_x86_feature(featureset, X86FSET_RDRAND); 1418 1419 /* 1420 * Only need it first time, rest of the cpus would follow suit. 1421 * we only capture this for the bootcpu. 1422 */ 1423 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 1424 add_x86_feature(featureset, X86FSET_CLFSH); 1425 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8); 1426 } 1427 if (is_x86_feature(featureset, X86FSET_PAE)) 1428 cpi->cpi_pabits = 36; 1429 1430 /* 1431 * Hyperthreading configuration is slightly tricky on Intel 1432 * and pure clones, and even trickier on AMD. 1433 * 1434 * (AMD chose to set the HTT bit on their CMP processors, 1435 * even though they're not actually hyperthreaded. Thus it 1436 * takes a bit more work to figure out what's really going 1437 * on ... see the handling of the CMP_LGCY bit below) 1438 */ 1439 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 1440 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 1441 if (cpi->cpi_ncpu_per_chip > 1) 1442 add_x86_feature(featureset, X86FSET_HTT); 1443 } else { 1444 cpi->cpi_ncpu_per_chip = 1; 1445 } 1446 1447 /* 1448 * Work on the "extended" feature information, doing 1449 * some basic initialization for cpuid_pass2() 1450 */ 1451 xcpuid = 0; 1452 switch (cpi->cpi_vendor) { 1453 case X86_VENDOR_Intel: 1454 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 1455 xcpuid++; 1456 break; 1457 case X86_VENDOR_AMD: 1458 if (cpi->cpi_family > 5 || 1459 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 1460 xcpuid++; 1461 break; 1462 case X86_VENDOR_Cyrix: 1463 /* 1464 * Only these Cyrix CPUs are -known- to support 1465 * extended cpuid operations. 1466 */ 1467 if (x86_type == X86_TYPE_VIA_CYRIX_III || 1468 x86_type == X86_TYPE_CYRIX_GXm) 1469 xcpuid++; 1470 break; 1471 case X86_VENDOR_Centaur: 1472 case X86_VENDOR_TM: 1473 default: 1474 xcpuid++; 1475 break; 1476 } 1477 1478 if (xcpuid) { 1479 cp = &cpi->cpi_extd[0]; 1480 cp->cp_eax = 0x80000000; 1481 cpi->cpi_xmaxeax = __cpuid_insn(cp); 1482 } 1483 1484 if (cpi->cpi_xmaxeax & 0x80000000) { 1485 1486 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 1487 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 1488 1489 switch (cpi->cpi_vendor) { 1490 case X86_VENDOR_Intel: 1491 case X86_VENDOR_AMD: 1492 if (cpi->cpi_xmaxeax < 0x80000001) 1493 break; 1494 cp = &cpi->cpi_extd[1]; 1495 cp->cp_eax = 0x80000001; 1496 (void) __cpuid_insn(cp); 1497 1498 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1499 cpi->cpi_family == 5 && 1500 cpi->cpi_model == 6 && 1501 cpi->cpi_step == 6) { 1502 /* 1503 * K6 model 6 uses bit 10 to indicate SYSC 1504 * Later models use bit 11. Fix it here. 1505 */ 1506 if (cp->cp_edx & 0x400) { 1507 cp->cp_edx &= ~0x400; 1508 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 1509 } 1510 } 1511 1512 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 1513 1514 /* 1515 * Compute the additions to the kernel's feature word. 1516 */ 1517 if (cp->cp_edx & CPUID_AMD_EDX_NX) { 1518 add_x86_feature(featureset, X86FSET_NX); 1519 } 1520 1521 /* 1522 * Regardless whether or not we boot 64-bit, 1523 * we should have a way to identify whether 1524 * the CPU is capable of running 64-bit. 1525 */ 1526 if (cp->cp_edx & CPUID_AMD_EDX_LM) { 1527 add_x86_feature(featureset, X86FSET_64); 1528 } 1529 1530 #if defined(__amd64) 1531 /* 1 GB large page - enable only for 64 bit kernel */ 1532 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) { 1533 add_x86_feature(featureset, X86FSET_1GPG); 1534 } 1535 #endif 1536 1537 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 1538 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 1539 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) { 1540 add_x86_feature(featureset, X86FSET_SSE4A); 1541 } 1542 1543 /* 1544 * If both the HTT and CMP_LGCY bits are set, 1545 * then we're not actually HyperThreaded. Read 1546 * "AMD CPUID Specification" for more details. 1547 */ 1548 if (cpi->cpi_vendor == X86_VENDOR_AMD && 1549 is_x86_feature(featureset, X86FSET_HTT) && 1550 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 1551 remove_x86_feature(featureset, X86FSET_HTT); 1552 add_x86_feature(featureset, X86FSET_CMP); 1553 } 1554 #if defined(__amd64) 1555 /* 1556 * It's really tricky to support syscall/sysret in 1557 * the i386 kernel; we rely on sysenter/sysexit 1558 * instead. In the amd64 kernel, things are -way- 1559 * better. 1560 */ 1561 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) { 1562 add_x86_feature(featureset, X86FSET_ASYSC); 1563 } 1564 1565 /* 1566 * While we're thinking about system calls, note 1567 * that AMD processors don't support sysenter 1568 * in long mode at all, so don't try to program them. 1569 */ 1570 if (x86_vendor == X86_VENDOR_AMD) { 1571 remove_x86_feature(featureset, X86FSET_SEP); 1572 } 1573 #endif 1574 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) { 1575 add_x86_feature(featureset, X86FSET_TSCP); 1576 } 1577 1578 if (cp->cp_ecx & CPUID_AMD_ECX_SVM) { 1579 add_x86_feature(featureset, X86FSET_SVM); 1580 } 1581 1582 if (cp->cp_ecx & CPUID_AMD_ECX_TOPOEXT) { 1583 add_x86_feature(featureset, X86FSET_TOPOEXT); 1584 } 1585 break; 1586 default: 1587 break; 1588 } 1589 1590 /* 1591 * Get CPUID data about processor cores and hyperthreads. 1592 */ 1593 switch (cpi->cpi_vendor) { 1594 case X86_VENDOR_Intel: 1595 if (cpi->cpi_maxeax >= 4) { 1596 cp = &cpi->cpi_std[4]; 1597 cp->cp_eax = 4; 1598 cp->cp_ecx = 0; 1599 (void) __cpuid_insn(cp); 1600 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 1601 } 1602 /*FALLTHROUGH*/ 1603 case X86_VENDOR_AMD: 1604 if (cpi->cpi_xmaxeax < 0x80000008) 1605 break; 1606 cp = &cpi->cpi_extd[8]; 1607 cp->cp_eax = 0x80000008; 1608 (void) __cpuid_insn(cp); 1609 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 1610 1611 /* 1612 * Virtual and physical address limits from 1613 * cpuid override previously guessed values. 1614 */ 1615 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 1616 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 1617 break; 1618 default: 1619 break; 1620 } 1621 1622 /* 1623 * Derive the number of cores per chip 1624 */ 1625 switch (cpi->cpi_vendor) { 1626 case X86_VENDOR_Intel: 1627 if (cpi->cpi_maxeax < 4) { 1628 cpi->cpi_ncore_per_chip = 1; 1629 break; 1630 } else { 1631 cpi->cpi_ncore_per_chip = 1632 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 1633 } 1634 break; 1635 case X86_VENDOR_AMD: 1636 if (cpi->cpi_xmaxeax < 0x80000008) { 1637 cpi->cpi_ncore_per_chip = 1; 1638 break; 1639 } else { 1640 /* 1641 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is 1642 * 1 less than the number of physical cores on 1643 * the chip. In family 0x10 this value can 1644 * be affected by "downcoring" - it reflects 1645 * 1 less than the number of cores actually 1646 * enabled on this node. 1647 */ 1648 cpi->cpi_ncore_per_chip = 1649 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 1650 } 1651 break; 1652 default: 1653 cpi->cpi_ncore_per_chip = 1; 1654 break; 1655 } 1656 1657 /* 1658 * Get CPUID data about TSC Invariance in Deep C-State. 1659 */ 1660 switch (cpi->cpi_vendor) { 1661 case X86_VENDOR_Intel: 1662 if (cpi->cpi_maxeax >= 7) { 1663 cp = &cpi->cpi_extd[7]; 1664 cp->cp_eax = 0x80000007; 1665 cp->cp_ecx = 0; 1666 (void) __cpuid_insn(cp); 1667 } 1668 break; 1669 default: 1670 break; 1671 } 1672 } else { 1673 cpi->cpi_ncore_per_chip = 1; 1674 } 1675 1676 /* 1677 * If more than one core, then this processor is CMP. 1678 */ 1679 if (cpi->cpi_ncore_per_chip > 1) { 1680 add_x86_feature(featureset, X86FSET_CMP); 1681 } 1682 1683 /* 1684 * If the number of cores is the same as the number 1685 * of CPUs, then we cannot have HyperThreading. 1686 */ 1687 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) { 1688 remove_x86_feature(featureset, X86FSET_HTT); 1689 } 1690 1691 cpi->cpi_apicid = CPI_APIC_ID(cpi); 1692 cpi->cpi_procnodes_per_pkg = 1; 1693 cpi->cpi_cores_per_compunit = 1; 1694 if (is_x86_feature(featureset, X86FSET_HTT) == B_FALSE && 1695 is_x86_feature(featureset, X86FSET_CMP) == B_FALSE) { 1696 /* 1697 * Single-core single-threaded processors. 1698 */ 1699 cpi->cpi_chipid = -1; 1700 cpi->cpi_clogid = 0; 1701 cpi->cpi_coreid = cpu->cpu_id; 1702 cpi->cpi_pkgcoreid = 0; 1703 if (cpi->cpi_vendor == X86_VENDOR_AMD) 1704 cpi->cpi_procnodeid = BITX(cpi->cpi_apicid, 3, 0); 1705 else 1706 cpi->cpi_procnodeid = cpi->cpi_chipid; 1707 } else if (cpi->cpi_ncpu_per_chip > 1) { 1708 if (cpi->cpi_vendor == X86_VENDOR_Intel) 1709 cpuid_intel_getids(cpu, featureset); 1710 else if (cpi->cpi_vendor == X86_VENDOR_AMD) 1711 cpuid_amd_getids(cpu); 1712 else { 1713 /* 1714 * All other processors are currently 1715 * assumed to have single cores. 1716 */ 1717 cpi->cpi_coreid = cpi->cpi_chipid; 1718 cpi->cpi_pkgcoreid = 0; 1719 cpi->cpi_procnodeid = cpi->cpi_chipid; 1720 cpi->cpi_compunitid = cpi->cpi_chipid; 1721 } 1722 } 1723 1724 /* 1725 * Synthesize chip "revision" and socket type 1726 */ 1727 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family, 1728 cpi->cpi_model, cpi->cpi_step); 1729 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor, 1730 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step); 1731 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family, 1732 cpi->cpi_model, cpi->cpi_step); 1733 1734 pass1_done: 1735 cpi->cpi_pass = 1; 1736 } 1737 1738 /* 1739 * Make copies of the cpuid table entries we depend on, in 1740 * part for ease of parsing now, in part so that we have only 1741 * one place to correct any of it, in part for ease of 1742 * later export to userland, and in part so we can look at 1743 * this stuff in a crash dump. 1744 */ 1745 1746 /*ARGSUSED*/ 1747 void 1748 cpuid_pass2(cpu_t *cpu) 1749 { 1750 uint_t n, nmax; 1751 int i; 1752 struct cpuid_regs *cp; 1753 uint8_t *dp; 1754 uint32_t *iptr; 1755 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1756 1757 ASSERT(cpi->cpi_pass == 1); 1758 1759 if (cpi->cpi_maxeax < 1) 1760 goto pass2_done; 1761 1762 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1763 nmax = NMAX_CPI_STD; 1764 /* 1765 * (We already handled n == 0 and n == 1 in pass 1) 1766 */ 1767 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1768 cp->cp_eax = n; 1769 1770 /* 1771 * CPUID function 4 expects %ecx to be initialized 1772 * with an index which indicates which cache to return 1773 * information about. The OS is expected to call function 4 1774 * with %ecx set to 0, 1, 2, ... until it returns with 1775 * EAX[4:0] set to 0, which indicates there are no more 1776 * caches. 1777 * 1778 * Here, populate cpi_std[4] with the information returned by 1779 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1780 * when dynamic memory allocation becomes available. 1781 * 1782 * Note: we need to explicitly initialize %ecx here, since 1783 * function 4 may have been previously invoked. 1784 */ 1785 if (n == 4) 1786 cp->cp_ecx = 0; 1787 1788 (void) __cpuid_insn(cp); 1789 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1790 switch (n) { 1791 case 2: 1792 /* 1793 * "the lower 8 bits of the %eax register 1794 * contain a value that identifies the number 1795 * of times the cpuid [instruction] has to be 1796 * executed to obtain a complete image of the 1797 * processor's caching systems." 1798 * 1799 * How *do* they make this stuff up? 1800 */ 1801 cpi->cpi_ncache = sizeof (*cp) * 1802 BITX(cp->cp_eax, 7, 0); 1803 if (cpi->cpi_ncache == 0) 1804 break; 1805 cpi->cpi_ncache--; /* skip count byte */ 1806 1807 /* 1808 * Well, for now, rather than attempt to implement 1809 * this slightly dubious algorithm, we just look 1810 * at the first 15 .. 1811 */ 1812 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1813 cpi->cpi_ncache = sizeof (*cp) - 1; 1814 1815 dp = cpi->cpi_cacheinfo; 1816 if (BITX(cp->cp_eax, 31, 31) == 0) { 1817 uint8_t *p = (void *)&cp->cp_eax; 1818 for (i = 1; i < 4; i++) 1819 if (p[i] != 0) 1820 *dp++ = p[i]; 1821 } 1822 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1823 uint8_t *p = (void *)&cp->cp_ebx; 1824 for (i = 0; i < 4; i++) 1825 if (p[i] != 0) 1826 *dp++ = p[i]; 1827 } 1828 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1829 uint8_t *p = (void *)&cp->cp_ecx; 1830 for (i = 0; i < 4; i++) 1831 if (p[i] != 0) 1832 *dp++ = p[i]; 1833 } 1834 if (BITX(cp->cp_edx, 31, 31) == 0) { 1835 uint8_t *p = (void *)&cp->cp_edx; 1836 for (i = 0; i < 4; i++) 1837 if (p[i] != 0) 1838 *dp++ = p[i]; 1839 } 1840 break; 1841 1842 case 3: /* Processor serial number, if PSN supported */ 1843 break; 1844 1845 case 4: /* Deterministic cache parameters */ 1846 break; 1847 1848 case 5: /* Monitor/Mwait parameters */ 1849 { 1850 size_t mwait_size; 1851 1852 /* 1853 * check cpi_mwait.support which was set in cpuid_pass1 1854 */ 1855 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1856 break; 1857 1858 /* 1859 * Protect ourself from insane mwait line size. 1860 * Workaround for incomplete hardware emulator(s). 1861 */ 1862 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1863 if (mwait_size < sizeof (uint32_t) || 1864 !ISP2(mwait_size)) { 1865 #if DEBUG 1866 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1867 "size %ld", cpu->cpu_id, (long)mwait_size); 1868 #endif 1869 break; 1870 } 1871 1872 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1873 cpi->cpi_mwait.mon_max = mwait_size; 1874 if (MWAIT_EXTENSION(cpi)) { 1875 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1876 if (MWAIT_INT_ENABLE(cpi)) 1877 cpi->cpi_mwait.support |= 1878 MWAIT_ECX_INT_ENABLE; 1879 } 1880 break; 1881 } 1882 default: 1883 break; 1884 } 1885 } 1886 1887 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) { 1888 struct cpuid_regs regs; 1889 1890 cp = ®s; 1891 cp->cp_eax = 0xB; 1892 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; 1893 1894 (void) __cpuid_insn(cp); 1895 1896 /* 1897 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which 1898 * indicates that the extended topology enumeration leaf is 1899 * available. 1900 */ 1901 if (cp->cp_ebx) { 1902 uint32_t x2apic_id; 1903 uint_t coreid_shift = 0; 1904 uint_t ncpu_per_core = 1; 1905 uint_t chipid_shift = 0; 1906 uint_t ncpu_per_chip = 1; 1907 uint_t i; 1908 uint_t level; 1909 1910 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { 1911 cp->cp_eax = 0xB; 1912 cp->cp_ecx = i; 1913 1914 (void) __cpuid_insn(cp); 1915 level = CPI_CPU_LEVEL_TYPE(cp); 1916 1917 if (level == 1) { 1918 x2apic_id = cp->cp_edx; 1919 coreid_shift = BITX(cp->cp_eax, 4, 0); 1920 ncpu_per_core = BITX(cp->cp_ebx, 15, 0); 1921 } else if (level == 2) { 1922 x2apic_id = cp->cp_edx; 1923 chipid_shift = BITX(cp->cp_eax, 4, 0); 1924 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0); 1925 } 1926 } 1927 1928 cpi->cpi_apicid = x2apic_id; 1929 cpi->cpi_ncpu_per_chip = ncpu_per_chip; 1930 cpi->cpi_ncore_per_chip = ncpu_per_chip / 1931 ncpu_per_core; 1932 cpi->cpi_chipid = x2apic_id >> chipid_shift; 1933 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1); 1934 cpi->cpi_coreid = x2apic_id >> coreid_shift; 1935 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; 1936 } 1937 1938 /* Make cp NULL so that we don't stumble on others */ 1939 cp = NULL; 1940 } 1941 1942 /* 1943 * XSAVE enumeration 1944 */ 1945 if (cpi->cpi_maxeax >= 0xD) { 1946 struct cpuid_regs regs; 1947 boolean_t cpuid_d_valid = B_TRUE; 1948 1949 cp = ®s; 1950 cp->cp_eax = 0xD; 1951 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; 1952 1953 (void) __cpuid_insn(cp); 1954 1955 /* 1956 * Sanity checks for debug 1957 */ 1958 if ((cp->cp_eax & XFEATURE_LEGACY_FP) == 0 || 1959 (cp->cp_eax & XFEATURE_SSE) == 0) { 1960 cpuid_d_valid = B_FALSE; 1961 } 1962 1963 cpi->cpi_xsave.xsav_hw_features_low = cp->cp_eax; 1964 cpi->cpi_xsave.xsav_hw_features_high = cp->cp_edx; 1965 cpi->cpi_xsave.xsav_max_size = cp->cp_ecx; 1966 1967 /* 1968 * If the hw supports AVX, get the size and offset in the save 1969 * area for the ymm state. 1970 */ 1971 if (cpi->cpi_xsave.xsav_hw_features_low & XFEATURE_AVX) { 1972 cp->cp_eax = 0xD; 1973 cp->cp_ecx = 2; 1974 cp->cp_edx = cp->cp_ebx = 0; 1975 1976 (void) __cpuid_insn(cp); 1977 1978 if (cp->cp_ebx != CPUID_LEAFD_2_YMM_OFFSET || 1979 cp->cp_eax != CPUID_LEAFD_2_YMM_SIZE) { 1980 cpuid_d_valid = B_FALSE; 1981 } 1982 1983 cpi->cpi_xsave.ymm_size = cp->cp_eax; 1984 cpi->cpi_xsave.ymm_offset = cp->cp_ebx; 1985 } 1986 1987 if (is_x86_feature(x86_featureset, X86FSET_XSAVE)) { 1988 xsave_state_size = 0; 1989 } else if (cpuid_d_valid) { 1990 xsave_state_size = cpi->cpi_xsave.xsav_max_size; 1991 } else { 1992 /* Broken CPUID 0xD, probably in HVM */ 1993 cmn_err(CE_WARN, "cpu%d: CPUID.0xD returns invalid " 1994 "value: hw_low = %d, hw_high = %d, xsave_size = %d" 1995 ", ymm_size = %d, ymm_offset = %d\n", 1996 cpu->cpu_id, cpi->cpi_xsave.xsav_hw_features_low, 1997 cpi->cpi_xsave.xsav_hw_features_high, 1998 (int)cpi->cpi_xsave.xsav_max_size, 1999 (int)cpi->cpi_xsave.ymm_size, 2000 (int)cpi->cpi_xsave.ymm_offset); 2001 2002 if (xsave_state_size != 0) { 2003 /* 2004 * This must be a non-boot CPU. We cannot 2005 * continue, because boot cpu has already 2006 * enabled XSAVE. 2007 */ 2008 ASSERT(cpu->cpu_id != 0); 2009 cmn_err(CE_PANIC, "cpu%d: we have already " 2010 "enabled XSAVE on boot cpu, cannot " 2011 "continue.", cpu->cpu_id); 2012 } else { 2013 /* 2014 * If we reached here on the boot CPU, it's also 2015 * almost certain that we'll reach here on the 2016 * non-boot CPUs. When we're here on a boot CPU 2017 * we should disable the feature, on a non-boot 2018 * CPU we need to confirm that we have. 2019 */ 2020 if (cpu->cpu_id == 0) { 2021 remove_x86_feature(x86_featureset, 2022 X86FSET_XSAVE); 2023 remove_x86_feature(x86_featureset, 2024 X86FSET_AVX); 2025 remove_x86_feature(x86_featureset, 2026 X86FSET_F16C); 2027 remove_x86_feature(x86_featureset, 2028 X86FSET_BMI1); 2029 remove_x86_feature(x86_featureset, 2030 X86FSET_BMI2); 2031 remove_x86_feature(x86_featureset, 2032 X86FSET_FMA); 2033 remove_x86_feature(x86_featureset, 2034 X86FSET_AVX2); 2035 CPI_FEATURES_ECX(cpi) &= 2036 ~CPUID_INTC_ECX_XSAVE; 2037 CPI_FEATURES_ECX(cpi) &= 2038 ~CPUID_INTC_ECX_AVX; 2039 CPI_FEATURES_ECX(cpi) &= 2040 ~CPUID_INTC_ECX_F16C; 2041 CPI_FEATURES_ECX(cpi) &= 2042 ~CPUID_INTC_ECX_FMA; 2043 CPI_FEATURES_7_0_EBX(cpi) &= 2044 ~CPUID_INTC_EBX_7_0_BMI1; 2045 CPI_FEATURES_7_0_EBX(cpi) &= 2046 ~CPUID_INTC_EBX_7_0_BMI2; 2047 CPI_FEATURES_7_0_EBX(cpi) &= 2048 ~CPUID_INTC_EBX_7_0_AVX2; 2049 xsave_force_disable = B_TRUE; 2050 } else { 2051 VERIFY(is_x86_feature(x86_featureset, 2052 X86FSET_XSAVE) == B_FALSE); 2053 } 2054 } 2055 } 2056 } 2057 2058 2059 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 2060 goto pass2_done; 2061 2062 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 2063 nmax = NMAX_CPI_EXTD; 2064 /* 2065 * Copy the extended properties, fixing them as we go. 2066 * (We already handled n == 0 and n == 1 in pass 1) 2067 */ 2068 iptr = (void *)cpi->cpi_brandstr; 2069 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 2070 cp->cp_eax = 0x80000000 + n; 2071 (void) __cpuid_insn(cp); 2072 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 2073 switch (n) { 2074 case 2: 2075 case 3: 2076 case 4: 2077 /* 2078 * Extract the brand string 2079 */ 2080 *iptr++ = cp->cp_eax; 2081 *iptr++ = cp->cp_ebx; 2082 *iptr++ = cp->cp_ecx; 2083 *iptr++ = cp->cp_edx; 2084 break; 2085 case 5: 2086 switch (cpi->cpi_vendor) { 2087 case X86_VENDOR_AMD: 2088 /* 2089 * The Athlon and Duron were the first 2090 * parts to report the sizes of the 2091 * TLB for large pages. Before then, 2092 * we don't trust the data. 2093 */ 2094 if (cpi->cpi_family < 6 || 2095 (cpi->cpi_family == 6 && 2096 cpi->cpi_model < 1)) 2097 cp->cp_eax = 0; 2098 break; 2099 default: 2100 break; 2101 } 2102 break; 2103 case 6: 2104 switch (cpi->cpi_vendor) { 2105 case X86_VENDOR_AMD: 2106 /* 2107 * The Athlon and Duron were the first 2108 * AMD parts with L2 TLB's. 2109 * Before then, don't trust the data. 2110 */ 2111 if (cpi->cpi_family < 6 || 2112 cpi->cpi_family == 6 && 2113 cpi->cpi_model < 1) 2114 cp->cp_eax = cp->cp_ebx = 0; 2115 /* 2116 * AMD Duron rev A0 reports L2 2117 * cache size incorrectly as 1K 2118 * when it is really 64K 2119 */ 2120 if (cpi->cpi_family == 6 && 2121 cpi->cpi_model == 3 && 2122 cpi->cpi_step == 0) { 2123 cp->cp_ecx &= 0xffff; 2124 cp->cp_ecx |= 0x400000; 2125 } 2126 break; 2127 case X86_VENDOR_Cyrix: /* VIA C3 */ 2128 /* 2129 * VIA C3 processors are a bit messed 2130 * up w.r.t. encoding cache sizes in %ecx 2131 */ 2132 if (cpi->cpi_family != 6) 2133 break; 2134 /* 2135 * model 7 and 8 were incorrectly encoded 2136 * 2137 * xxx is model 8 really broken? 2138 */ 2139 if (cpi->cpi_model == 7 || 2140 cpi->cpi_model == 8) 2141 cp->cp_ecx = 2142 BITX(cp->cp_ecx, 31, 24) << 16 | 2143 BITX(cp->cp_ecx, 23, 16) << 12 | 2144 BITX(cp->cp_ecx, 15, 8) << 8 | 2145 BITX(cp->cp_ecx, 7, 0); 2146 /* 2147 * model 9 stepping 1 has wrong associativity 2148 */ 2149 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 2150 cp->cp_ecx |= 8 << 12; 2151 break; 2152 case X86_VENDOR_Intel: 2153 /* 2154 * Extended L2 Cache features function. 2155 * First appeared on Prescott. 2156 */ 2157 default: 2158 break; 2159 } 2160 break; 2161 default: 2162 break; 2163 } 2164 } 2165 2166 pass2_done: 2167 cpi->cpi_pass = 2; 2168 } 2169 2170 static const char * 2171 intel_cpubrand(const struct cpuid_info *cpi) 2172 { 2173 int i; 2174 2175 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) || 2176 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 2177 return ("i486"); 2178 2179 switch (cpi->cpi_family) { 2180 case 5: 2181 return ("Intel Pentium(r)"); 2182 case 6: 2183 switch (cpi->cpi_model) { 2184 uint_t celeron, xeon; 2185 const struct cpuid_regs *cp; 2186 case 0: 2187 case 1: 2188 case 2: 2189 return ("Intel Pentium(r) Pro"); 2190 case 3: 2191 case 4: 2192 return ("Intel Pentium(r) II"); 2193 case 6: 2194 return ("Intel Celeron(r)"); 2195 case 5: 2196 case 7: 2197 celeron = xeon = 0; 2198 cp = &cpi->cpi_std[2]; /* cache info */ 2199 2200 for (i = 1; i < 4; i++) { 2201 uint_t tmp; 2202 2203 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 2204 if (tmp == 0x40) 2205 celeron++; 2206 if (tmp >= 0x44 && tmp <= 0x45) 2207 xeon++; 2208 } 2209 2210 for (i = 0; i < 2; i++) { 2211 uint_t tmp; 2212 2213 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 2214 if (tmp == 0x40) 2215 celeron++; 2216 else if (tmp >= 0x44 && tmp <= 0x45) 2217 xeon++; 2218 } 2219 2220 for (i = 0; i < 4; i++) { 2221 uint_t tmp; 2222 2223 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 2224 if (tmp == 0x40) 2225 celeron++; 2226 else if (tmp >= 0x44 && tmp <= 0x45) 2227 xeon++; 2228 } 2229 2230 for (i = 0; i < 4; i++) { 2231 uint_t tmp; 2232 2233 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 2234 if (tmp == 0x40) 2235 celeron++; 2236 else if (tmp >= 0x44 && tmp <= 0x45) 2237 xeon++; 2238 } 2239 2240 if (celeron) 2241 return ("Intel Celeron(r)"); 2242 if (xeon) 2243 return (cpi->cpi_model == 5 ? 2244 "Intel Pentium(r) II Xeon(tm)" : 2245 "Intel Pentium(r) III Xeon(tm)"); 2246 return (cpi->cpi_model == 5 ? 2247 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 2248 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 2249 default: 2250 break; 2251 } 2252 default: 2253 break; 2254 } 2255 2256 /* BrandID is present if the field is nonzero */ 2257 if (cpi->cpi_brandid != 0) { 2258 static const struct { 2259 uint_t bt_bid; 2260 const char *bt_str; 2261 } brand_tbl[] = { 2262 { 0x1, "Intel(r) Celeron(r)" }, 2263 { 0x2, "Intel(r) Pentium(r) III" }, 2264 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 2265 { 0x4, "Intel(r) Pentium(r) III" }, 2266 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 2267 { 0x7, "Mobile Intel(r) Celeron(r)" }, 2268 { 0x8, "Intel(r) Pentium(r) 4" }, 2269 { 0x9, "Intel(r) Pentium(r) 4" }, 2270 { 0xa, "Intel(r) Celeron(r)" }, 2271 { 0xb, "Intel(r) Xeon(tm)" }, 2272 { 0xc, "Intel(r) Xeon(tm) MP" }, 2273 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 2274 { 0xf, "Mobile Intel(r) Celeron(r)" }, 2275 { 0x11, "Mobile Genuine Intel(r)" }, 2276 { 0x12, "Intel(r) Celeron(r) M" }, 2277 { 0x13, "Mobile Intel(r) Celeron(r)" }, 2278 { 0x14, "Intel(r) Celeron(r)" }, 2279 { 0x15, "Mobile Genuine Intel(r)" }, 2280 { 0x16, "Intel(r) Pentium(r) M" }, 2281 { 0x17, "Mobile Intel(r) Celeron(r)" } 2282 }; 2283 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 2284 uint_t sgn; 2285 2286 sgn = (cpi->cpi_family << 8) | 2287 (cpi->cpi_model << 4) | cpi->cpi_step; 2288 2289 for (i = 0; i < btblmax; i++) 2290 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 2291 break; 2292 if (i < btblmax) { 2293 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 2294 return ("Intel(r) Celeron(r)"); 2295 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 2296 return ("Intel(r) Xeon(tm) MP"); 2297 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 2298 return ("Intel(r) Xeon(tm)"); 2299 return (brand_tbl[i].bt_str); 2300 } 2301 } 2302 2303 return (NULL); 2304 } 2305 2306 static const char * 2307 amd_cpubrand(const struct cpuid_info *cpi) 2308 { 2309 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) || 2310 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 2311 return ("i486 compatible"); 2312 2313 switch (cpi->cpi_family) { 2314 case 5: 2315 switch (cpi->cpi_model) { 2316 case 0: 2317 case 1: 2318 case 2: 2319 case 3: 2320 case 4: 2321 case 5: 2322 return ("AMD-K5(r)"); 2323 case 6: 2324 case 7: 2325 return ("AMD-K6(r)"); 2326 case 8: 2327 return ("AMD-K6(r)-2"); 2328 case 9: 2329 return ("AMD-K6(r)-III"); 2330 default: 2331 return ("AMD (family 5)"); 2332 } 2333 case 6: 2334 switch (cpi->cpi_model) { 2335 case 1: 2336 return ("AMD-K7(tm)"); 2337 case 0: 2338 case 2: 2339 case 4: 2340 return ("AMD Athlon(tm)"); 2341 case 3: 2342 case 7: 2343 return ("AMD Duron(tm)"); 2344 case 6: 2345 case 8: 2346 case 10: 2347 /* 2348 * Use the L2 cache size to distinguish 2349 */ 2350 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 2351 "AMD Athlon(tm)" : "AMD Duron(tm)"); 2352 default: 2353 return ("AMD (family 6)"); 2354 } 2355 default: 2356 break; 2357 } 2358 2359 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 2360 cpi->cpi_brandid != 0) { 2361 switch (BITX(cpi->cpi_brandid, 7, 5)) { 2362 case 3: 2363 return ("AMD Opteron(tm) UP 1xx"); 2364 case 4: 2365 return ("AMD Opteron(tm) DP 2xx"); 2366 case 5: 2367 return ("AMD Opteron(tm) MP 8xx"); 2368 default: 2369 return ("AMD Opteron(tm)"); 2370 } 2371 } 2372 2373 return (NULL); 2374 } 2375 2376 static const char * 2377 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 2378 { 2379 if (!is_x86_feature(x86_featureset, X86FSET_CPUID) || 2380 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 2381 type == X86_TYPE_CYRIX_486) 2382 return ("i486 compatible"); 2383 2384 switch (type) { 2385 case X86_TYPE_CYRIX_6x86: 2386 return ("Cyrix 6x86"); 2387 case X86_TYPE_CYRIX_6x86L: 2388 return ("Cyrix 6x86L"); 2389 case X86_TYPE_CYRIX_6x86MX: 2390 return ("Cyrix 6x86MX"); 2391 case X86_TYPE_CYRIX_GXm: 2392 return ("Cyrix GXm"); 2393 case X86_TYPE_CYRIX_MediaGX: 2394 return ("Cyrix MediaGX"); 2395 case X86_TYPE_CYRIX_MII: 2396 return ("Cyrix M2"); 2397 case X86_TYPE_VIA_CYRIX_III: 2398 return ("VIA Cyrix M3"); 2399 default: 2400 /* 2401 * Have another wild guess .. 2402 */ 2403 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 2404 return ("Cyrix 5x86"); 2405 else if (cpi->cpi_family == 5) { 2406 switch (cpi->cpi_model) { 2407 case 2: 2408 return ("Cyrix 6x86"); /* Cyrix M1 */ 2409 case 4: 2410 return ("Cyrix MediaGX"); 2411 default: 2412 break; 2413 } 2414 } else if (cpi->cpi_family == 6) { 2415 switch (cpi->cpi_model) { 2416 case 0: 2417 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 2418 case 5: 2419 case 6: 2420 case 7: 2421 case 8: 2422 case 9: 2423 return ("VIA C3"); 2424 default: 2425 break; 2426 } 2427 } 2428 break; 2429 } 2430 return (NULL); 2431 } 2432 2433 /* 2434 * This only gets called in the case that the CPU extended 2435 * feature brand string (0x80000002, 0x80000003, 0x80000004) 2436 * aren't available, or contain null bytes for some reason. 2437 */ 2438 static void 2439 fabricate_brandstr(struct cpuid_info *cpi) 2440 { 2441 const char *brand = NULL; 2442 2443 switch (cpi->cpi_vendor) { 2444 case X86_VENDOR_Intel: 2445 brand = intel_cpubrand(cpi); 2446 break; 2447 case X86_VENDOR_AMD: 2448 brand = amd_cpubrand(cpi); 2449 break; 2450 case X86_VENDOR_Cyrix: 2451 brand = cyrix_cpubrand(cpi, x86_type); 2452 break; 2453 case X86_VENDOR_NexGen: 2454 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 2455 brand = "NexGen Nx586"; 2456 break; 2457 case X86_VENDOR_Centaur: 2458 if (cpi->cpi_family == 5) 2459 switch (cpi->cpi_model) { 2460 case 4: 2461 brand = "Centaur C6"; 2462 break; 2463 case 8: 2464 brand = "Centaur C2"; 2465 break; 2466 case 9: 2467 brand = "Centaur C3"; 2468 break; 2469 default: 2470 break; 2471 } 2472 break; 2473 case X86_VENDOR_Rise: 2474 if (cpi->cpi_family == 5 && 2475 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 2476 brand = "Rise mP6"; 2477 break; 2478 case X86_VENDOR_SiS: 2479 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 2480 brand = "SiS 55x"; 2481 break; 2482 case X86_VENDOR_TM: 2483 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 2484 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 2485 break; 2486 case X86_VENDOR_NSC: 2487 case X86_VENDOR_UMC: 2488 default: 2489 break; 2490 } 2491 if (brand) { 2492 (void) strcpy((char *)cpi->cpi_brandstr, brand); 2493 return; 2494 } 2495 2496 /* 2497 * If all else fails ... 2498 */ 2499 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 2500 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 2501 cpi->cpi_model, cpi->cpi_step); 2502 } 2503 2504 /* 2505 * This routine is called just after kernel memory allocation 2506 * becomes available on cpu0, and as part of mp_startup() on 2507 * the other cpus. 2508 * 2509 * Fixup the brand string, and collect any information from cpuid 2510 * that requires dynamically allocated storage to represent. 2511 */ 2512 /*ARGSUSED*/ 2513 void 2514 cpuid_pass3(cpu_t *cpu) 2515 { 2516 int i, max, shft, level, size; 2517 struct cpuid_regs regs; 2518 struct cpuid_regs *cp; 2519 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2520 2521 ASSERT(cpi->cpi_pass == 2); 2522 2523 /* 2524 * Function 4: Deterministic cache parameters 2525 * 2526 * Take this opportunity to detect the number of threads 2527 * sharing the last level cache, and construct a corresponding 2528 * cache id. The respective cpuid_info members are initialized 2529 * to the default case of "no last level cache sharing". 2530 */ 2531 cpi->cpi_ncpu_shr_last_cache = 1; 2532 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 2533 2534 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 2535 2536 /* 2537 * Find the # of elements (size) returned by fn 4, and along 2538 * the way detect last level cache sharing details. 2539 */ 2540 bzero(®s, sizeof (regs)); 2541 cp = ®s; 2542 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 2543 cp->cp_eax = 4; 2544 cp->cp_ecx = i; 2545 2546 (void) __cpuid_insn(cp); 2547 2548 if (CPI_CACHE_TYPE(cp) == 0) 2549 break; 2550 level = CPI_CACHE_LVL(cp); 2551 if (level > max) { 2552 max = level; 2553 cpi->cpi_ncpu_shr_last_cache = 2554 CPI_NTHR_SHR_CACHE(cp) + 1; 2555 } 2556 } 2557 cpi->cpi_std_4_size = size = i; 2558 2559 /* 2560 * Allocate the cpi_std_4 array. The first element 2561 * references the regs for fn 4, %ecx == 0, which 2562 * cpuid_pass2() stashed in cpi->cpi_std[4]. 2563 */ 2564 if (size > 0) { 2565 cpi->cpi_std_4 = 2566 kmem_alloc(size * sizeof (cp), KM_SLEEP); 2567 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 2568 2569 /* 2570 * Allocate storage to hold the additional regs 2571 * for function 4, %ecx == 1 .. cpi_std_4_size. 2572 * 2573 * The regs for fn 4, %ecx == 0 has already 2574 * been allocated as indicated above. 2575 */ 2576 for (i = 1; i < size; i++) { 2577 cp = cpi->cpi_std_4[i] = 2578 kmem_zalloc(sizeof (regs), KM_SLEEP); 2579 cp->cp_eax = 4; 2580 cp->cp_ecx = i; 2581 2582 (void) __cpuid_insn(cp); 2583 } 2584 } 2585 /* 2586 * Determine the number of bits needed to represent 2587 * the number of CPUs sharing the last level cache. 2588 * 2589 * Shift off that number of bits from the APIC id to 2590 * derive the cache id. 2591 */ 2592 shft = 0; 2593 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 2594 shft++; 2595 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft; 2596 } 2597 2598 /* 2599 * Now fixup the brand string 2600 */ 2601 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 2602 fabricate_brandstr(cpi); 2603 } else { 2604 2605 /* 2606 * If we successfully extracted a brand string from the cpuid 2607 * instruction, clean it up by removing leading spaces and 2608 * similar junk. 2609 */ 2610 if (cpi->cpi_brandstr[0]) { 2611 size_t maxlen = sizeof (cpi->cpi_brandstr); 2612 char *src, *dst; 2613 2614 dst = src = (char *)cpi->cpi_brandstr; 2615 src[maxlen - 1] = '\0'; 2616 /* 2617 * strip leading spaces 2618 */ 2619 while (*src == ' ') 2620 src++; 2621 /* 2622 * Remove any 'Genuine' or "Authentic" prefixes 2623 */ 2624 if (strncmp(src, "Genuine ", 8) == 0) 2625 src += 8; 2626 if (strncmp(src, "Authentic ", 10) == 0) 2627 src += 10; 2628 2629 /* 2630 * Now do an in-place copy. 2631 * Map (R) to (r) and (TM) to (tm). 2632 * The era of teletypes is long gone, and there's 2633 * -really- no need to shout. 2634 */ 2635 while (*src != '\0') { 2636 if (src[0] == '(') { 2637 if (strncmp(src + 1, "R)", 2) == 0) { 2638 (void) strncpy(dst, "(r)", 3); 2639 src += 3; 2640 dst += 3; 2641 continue; 2642 } 2643 if (strncmp(src + 1, "TM)", 3) == 0) { 2644 (void) strncpy(dst, "(tm)", 4); 2645 src += 4; 2646 dst += 4; 2647 continue; 2648 } 2649 } 2650 *dst++ = *src++; 2651 } 2652 *dst = '\0'; 2653 2654 /* 2655 * Finally, remove any trailing spaces 2656 */ 2657 while (--dst > cpi->cpi_brandstr) 2658 if (*dst == ' ') 2659 *dst = '\0'; 2660 else 2661 break; 2662 } else 2663 fabricate_brandstr(cpi); 2664 } 2665 cpi->cpi_pass = 3; 2666 } 2667 2668 /* 2669 * This routine is called out of bind_hwcap() much later in the life 2670 * of the kernel (post_startup()). The job of this routine is to resolve 2671 * the hardware feature support and kernel support for those features into 2672 * what we're actually going to tell applications via the aux vector. 2673 */ 2674 void 2675 cpuid_pass4(cpu_t *cpu, uint_t *hwcap_out) 2676 { 2677 struct cpuid_info *cpi; 2678 uint_t hwcap_flags = 0, hwcap_flags_2 = 0; 2679 2680 if (cpu == NULL) 2681 cpu = CPU; 2682 cpi = cpu->cpu_m.mcpu_cpi; 2683 2684 ASSERT(cpi->cpi_pass == 3); 2685 2686 if (cpi->cpi_maxeax >= 1) { 2687 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 2688 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 2689 uint32_t *ebx = &cpi->cpi_support[STD_EBX_FEATURES]; 2690 2691 *edx = CPI_FEATURES_EDX(cpi); 2692 *ecx = CPI_FEATURES_ECX(cpi); 2693 *ebx = CPI_FEATURES_7_0_EBX(cpi); 2694 2695 /* 2696 * [these require explicit kernel support] 2697 */ 2698 if (!is_x86_feature(x86_featureset, X86FSET_SEP)) 2699 *edx &= ~CPUID_INTC_EDX_SEP; 2700 2701 if (!is_x86_feature(x86_featureset, X86FSET_SSE)) 2702 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 2703 if (!is_x86_feature(x86_featureset, X86FSET_SSE2)) 2704 *edx &= ~CPUID_INTC_EDX_SSE2; 2705 2706 if (!is_x86_feature(x86_featureset, X86FSET_HTT)) 2707 *edx &= ~CPUID_INTC_EDX_HTT; 2708 2709 if (!is_x86_feature(x86_featureset, X86FSET_SSE3)) 2710 *ecx &= ~CPUID_INTC_ECX_SSE3; 2711 2712 if (!is_x86_feature(x86_featureset, X86FSET_SSSE3)) 2713 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2714 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_1)) 2715 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2716 if (!is_x86_feature(x86_featureset, X86FSET_SSE4_2)) 2717 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2718 if (!is_x86_feature(x86_featureset, X86FSET_AES)) 2719 *ecx &= ~CPUID_INTC_ECX_AES; 2720 if (!is_x86_feature(x86_featureset, X86FSET_PCLMULQDQ)) 2721 *ecx &= ~CPUID_INTC_ECX_PCLMULQDQ; 2722 if (!is_x86_feature(x86_featureset, X86FSET_XSAVE)) 2723 *ecx &= ~(CPUID_INTC_ECX_XSAVE | 2724 CPUID_INTC_ECX_OSXSAVE); 2725 if (!is_x86_feature(x86_featureset, X86FSET_AVX)) 2726 *ecx &= ~CPUID_INTC_ECX_AVX; 2727 if (!is_x86_feature(x86_featureset, X86FSET_F16C)) 2728 *ecx &= ~CPUID_INTC_ECX_F16C; 2729 if (!is_x86_feature(x86_featureset, X86FSET_FMA)) 2730 *ecx &= ~CPUID_INTC_ECX_FMA; 2731 if (!is_x86_feature(x86_featureset, X86FSET_BMI1)) 2732 *ebx &= ~CPUID_INTC_EBX_7_0_BMI1; 2733 if (!is_x86_feature(x86_featureset, X86FSET_BMI2)) 2734 *ebx &= ~CPUID_INTC_EBX_7_0_BMI2; 2735 if (!is_x86_feature(x86_featureset, X86FSET_AVX2)) 2736 *ebx &= ~CPUID_INTC_EBX_7_0_AVX2; 2737 if (!is_x86_feature(x86_featureset, X86FSET_RDSEED)) 2738 *ebx &= ~CPUID_INTC_EBX_7_0_RDSEED; 2739 if (!is_x86_feature(x86_featureset, X86FSET_ADX)) 2740 *ebx &= ~CPUID_INTC_EBX_7_0_ADX; 2741 2742 /* 2743 * [no explicit support required beyond x87 fp context] 2744 */ 2745 if (!fpu_exists) 2746 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2747 2748 /* 2749 * Now map the supported feature vector to things that we 2750 * think userland will care about. 2751 */ 2752 if (*edx & CPUID_INTC_EDX_SEP) 2753 hwcap_flags |= AV_386_SEP; 2754 if (*edx & CPUID_INTC_EDX_SSE) 2755 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2756 if (*edx & CPUID_INTC_EDX_SSE2) 2757 hwcap_flags |= AV_386_SSE2; 2758 if (*ecx & CPUID_INTC_ECX_SSE3) 2759 hwcap_flags |= AV_386_SSE3; 2760 if (*ecx & CPUID_INTC_ECX_SSSE3) 2761 hwcap_flags |= AV_386_SSSE3; 2762 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2763 hwcap_flags |= AV_386_SSE4_1; 2764 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2765 hwcap_flags |= AV_386_SSE4_2; 2766 if (*ecx & CPUID_INTC_ECX_MOVBE) 2767 hwcap_flags |= AV_386_MOVBE; 2768 if (*ecx & CPUID_INTC_ECX_AES) 2769 hwcap_flags |= AV_386_AES; 2770 if (*ecx & CPUID_INTC_ECX_PCLMULQDQ) 2771 hwcap_flags |= AV_386_PCLMULQDQ; 2772 if ((*ecx & CPUID_INTC_ECX_XSAVE) && 2773 (*ecx & CPUID_INTC_ECX_OSXSAVE)) { 2774 hwcap_flags |= AV_386_XSAVE; 2775 2776 if (*ecx & CPUID_INTC_ECX_AVX) { 2777 hwcap_flags |= AV_386_AVX; 2778 if (*ecx & CPUID_INTC_ECX_F16C) 2779 hwcap_flags_2 |= AV_386_2_F16C; 2780 if (*ecx & CPUID_INTC_ECX_FMA) 2781 hwcap_flags_2 |= AV_386_2_FMA; 2782 if (*ebx & CPUID_INTC_EBX_7_0_BMI1) 2783 hwcap_flags_2 |= AV_386_2_BMI1; 2784 if (*ebx & CPUID_INTC_EBX_7_0_BMI2) 2785 hwcap_flags_2 |= AV_386_2_BMI2; 2786 if (*ebx & CPUID_INTC_EBX_7_0_AVX2) 2787 hwcap_flags_2 |= AV_386_2_AVX2; 2788 } 2789 } 2790 if (*ecx & CPUID_INTC_ECX_VMX) 2791 hwcap_flags |= AV_386_VMX; 2792 if (*ecx & CPUID_INTC_ECX_POPCNT) 2793 hwcap_flags |= AV_386_POPCNT; 2794 if (*edx & CPUID_INTC_EDX_FPU) 2795 hwcap_flags |= AV_386_FPU; 2796 if (*edx & CPUID_INTC_EDX_MMX) 2797 hwcap_flags |= AV_386_MMX; 2798 2799 if (*edx & CPUID_INTC_EDX_TSC) 2800 hwcap_flags |= AV_386_TSC; 2801 if (*edx & CPUID_INTC_EDX_CX8) 2802 hwcap_flags |= AV_386_CX8; 2803 if (*edx & CPUID_INTC_EDX_CMOV) 2804 hwcap_flags |= AV_386_CMOV; 2805 if (*ecx & CPUID_INTC_ECX_CX16) 2806 hwcap_flags |= AV_386_CX16; 2807 2808 if (*ecx & CPUID_INTC_ECX_RDRAND) 2809 hwcap_flags_2 |= AV_386_2_RDRAND; 2810 if (*ebx & CPUID_INTC_EBX_7_0_ADX) 2811 hwcap_flags_2 |= AV_386_2_ADX; 2812 if (*ebx & CPUID_INTC_EBX_7_0_RDSEED) 2813 hwcap_flags_2 |= AV_386_2_RDSEED; 2814 2815 } 2816 2817 if (cpi->cpi_xmaxeax < 0x80000001) 2818 goto pass4_done; 2819 2820 switch (cpi->cpi_vendor) { 2821 struct cpuid_regs cp; 2822 uint32_t *edx, *ecx; 2823 2824 case X86_VENDOR_Intel: 2825 /* 2826 * Seems like Intel duplicated what we necessary 2827 * here to make the initial crop of 64-bit OS's work. 2828 * Hopefully, those are the only "extended" bits 2829 * they'll add. 2830 */ 2831 /*FALLTHROUGH*/ 2832 2833 case X86_VENDOR_AMD: 2834 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2835 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2836 2837 *edx = CPI_FEATURES_XTD_EDX(cpi); 2838 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2839 2840 /* 2841 * [these features require explicit kernel support] 2842 */ 2843 switch (cpi->cpi_vendor) { 2844 case X86_VENDOR_Intel: 2845 if (!is_x86_feature(x86_featureset, X86FSET_TSCP)) 2846 *edx &= ~CPUID_AMD_EDX_TSCP; 2847 break; 2848 2849 case X86_VENDOR_AMD: 2850 if (!is_x86_feature(x86_featureset, X86FSET_TSCP)) 2851 *edx &= ~CPUID_AMD_EDX_TSCP; 2852 if (!is_x86_feature(x86_featureset, X86FSET_SSE4A)) 2853 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2854 break; 2855 2856 default: 2857 break; 2858 } 2859 2860 /* 2861 * [no explicit support required beyond 2862 * x87 fp context and exception handlers] 2863 */ 2864 if (!fpu_exists) 2865 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2866 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2867 2868 if (!is_x86_feature(x86_featureset, X86FSET_NX)) 2869 *edx &= ~CPUID_AMD_EDX_NX; 2870 #if !defined(__amd64) 2871 *edx &= ~CPUID_AMD_EDX_LM; 2872 #endif 2873 /* 2874 * Now map the supported feature vector to 2875 * things that we think userland will care about. 2876 */ 2877 #if defined(__amd64) 2878 if (*edx & CPUID_AMD_EDX_SYSC) 2879 hwcap_flags |= AV_386_AMD_SYSC; 2880 #endif 2881 if (*edx & CPUID_AMD_EDX_MMXamd) 2882 hwcap_flags |= AV_386_AMD_MMX; 2883 if (*edx & CPUID_AMD_EDX_3DNow) 2884 hwcap_flags |= AV_386_AMD_3DNow; 2885 if (*edx & CPUID_AMD_EDX_3DNowx) 2886 hwcap_flags |= AV_386_AMD_3DNowx; 2887 if (*ecx & CPUID_AMD_ECX_SVM) 2888 hwcap_flags |= AV_386_AMD_SVM; 2889 2890 switch (cpi->cpi_vendor) { 2891 case X86_VENDOR_AMD: 2892 if (*edx & CPUID_AMD_EDX_TSCP) 2893 hwcap_flags |= AV_386_TSCP; 2894 if (*ecx & CPUID_AMD_ECX_AHF64) 2895 hwcap_flags |= AV_386_AHF; 2896 if (*ecx & CPUID_AMD_ECX_SSE4A) 2897 hwcap_flags |= AV_386_AMD_SSE4A; 2898 if (*ecx & CPUID_AMD_ECX_LZCNT) 2899 hwcap_flags |= AV_386_AMD_LZCNT; 2900 break; 2901 2902 case X86_VENDOR_Intel: 2903 if (*edx & CPUID_AMD_EDX_TSCP) 2904 hwcap_flags |= AV_386_TSCP; 2905 /* 2906 * Aarrgh. 2907 * Intel uses a different bit in the same word. 2908 */ 2909 if (*ecx & CPUID_INTC_ECX_AHF64) 2910 hwcap_flags |= AV_386_AHF; 2911 break; 2912 2913 default: 2914 break; 2915 } 2916 break; 2917 2918 case X86_VENDOR_TM: 2919 cp.cp_eax = 0x80860001; 2920 (void) __cpuid_insn(&cp); 2921 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2922 break; 2923 2924 default: 2925 break; 2926 } 2927 2928 pass4_done: 2929 cpi->cpi_pass = 4; 2930 if (hwcap_out != NULL) { 2931 hwcap_out[0] = hwcap_flags; 2932 hwcap_out[1] = hwcap_flags_2; 2933 } 2934 } 2935 2936 2937 /* 2938 * Simulate the cpuid instruction using the data we previously 2939 * captured about this CPU. We try our best to return the truth 2940 * about the hardware, independently of kernel support. 2941 */ 2942 uint32_t 2943 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2944 { 2945 struct cpuid_info *cpi; 2946 struct cpuid_regs *xcp; 2947 2948 if (cpu == NULL) 2949 cpu = CPU; 2950 cpi = cpu->cpu_m.mcpu_cpi; 2951 2952 ASSERT(cpuid_checkpass(cpu, 3)); 2953 2954 /* 2955 * CPUID data is cached in two separate places: cpi_std for standard 2956 * CPUID functions, and cpi_extd for extended CPUID functions. 2957 */ 2958 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2959 xcp = &cpi->cpi_std[cp->cp_eax]; 2960 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2961 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2962 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2963 else 2964 /* 2965 * The caller is asking for data from an input parameter which 2966 * the kernel has not cached. In this case we go fetch from 2967 * the hardware and return the data directly to the user. 2968 */ 2969 return (__cpuid_insn(cp)); 2970 2971 cp->cp_eax = xcp->cp_eax; 2972 cp->cp_ebx = xcp->cp_ebx; 2973 cp->cp_ecx = xcp->cp_ecx; 2974 cp->cp_edx = xcp->cp_edx; 2975 return (cp->cp_eax); 2976 } 2977 2978 int 2979 cpuid_checkpass(cpu_t *cpu, int pass) 2980 { 2981 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2982 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2983 } 2984 2985 int 2986 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2987 { 2988 ASSERT(cpuid_checkpass(cpu, 3)); 2989 2990 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2991 } 2992 2993 int 2994 cpuid_is_cmt(cpu_t *cpu) 2995 { 2996 if (cpu == NULL) 2997 cpu = CPU; 2998 2999 ASSERT(cpuid_checkpass(cpu, 1)); 3000 3001 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 3002 } 3003 3004 /* 3005 * AMD and Intel both implement the 64-bit variant of the syscall 3006 * instruction (syscallq), so if there's -any- support for syscall, 3007 * cpuid currently says "yes, we support this". 3008 * 3009 * However, Intel decided to -not- implement the 32-bit variant of the 3010 * syscall instruction, so we provide a predicate to allow our caller 3011 * to test that subtlety here. 3012 * 3013 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 3014 * even in the case where the hardware would in fact support it. 3015 */ 3016 /*ARGSUSED*/ 3017 int 3018 cpuid_syscall32_insn(cpu_t *cpu) 3019 { 3020 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 3021 3022 #if !defined(__xpv) 3023 if (cpu == NULL) 3024 cpu = CPU; 3025 3026 /*CSTYLED*/ 3027 { 3028 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3029 3030 if (cpi->cpi_vendor == X86_VENDOR_AMD && 3031 cpi->cpi_xmaxeax >= 0x80000001 && 3032 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 3033 return (1); 3034 } 3035 #endif 3036 return (0); 3037 } 3038 3039 int 3040 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 3041 { 3042 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3043 3044 static const char fmt[] = 3045 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 3046 static const char fmt_ht[] = 3047 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 3048 3049 ASSERT(cpuid_checkpass(cpu, 1)); 3050 3051 if (cpuid_is_cmt(cpu)) 3052 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 3053 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 3054 cpi->cpi_family, cpi->cpi_model, 3055 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 3056 return (snprintf(s, n, fmt, 3057 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 3058 cpi->cpi_family, cpi->cpi_model, 3059 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 3060 } 3061 3062 const char * 3063 cpuid_getvendorstr(cpu_t *cpu) 3064 { 3065 ASSERT(cpuid_checkpass(cpu, 1)); 3066 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 3067 } 3068 3069 uint_t 3070 cpuid_getvendor(cpu_t *cpu) 3071 { 3072 ASSERT(cpuid_checkpass(cpu, 1)); 3073 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 3074 } 3075 3076 uint_t 3077 cpuid_getfamily(cpu_t *cpu) 3078 { 3079 ASSERT(cpuid_checkpass(cpu, 1)); 3080 return (cpu->cpu_m.mcpu_cpi->cpi_family); 3081 } 3082 3083 uint_t 3084 cpuid_getmodel(cpu_t *cpu) 3085 { 3086 ASSERT(cpuid_checkpass(cpu, 1)); 3087 return (cpu->cpu_m.mcpu_cpi->cpi_model); 3088 } 3089 3090 uint_t 3091 cpuid_get_ncpu_per_chip(cpu_t *cpu) 3092 { 3093 ASSERT(cpuid_checkpass(cpu, 1)); 3094 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 3095 } 3096 3097 uint_t 3098 cpuid_get_ncore_per_chip(cpu_t *cpu) 3099 { 3100 ASSERT(cpuid_checkpass(cpu, 1)); 3101 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 3102 } 3103 3104 uint_t 3105 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 3106 { 3107 ASSERT(cpuid_checkpass(cpu, 2)); 3108 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 3109 } 3110 3111 id_t 3112 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 3113 { 3114 ASSERT(cpuid_checkpass(cpu, 2)); 3115 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 3116 } 3117 3118 uint_t 3119 cpuid_getstep(cpu_t *cpu) 3120 { 3121 ASSERT(cpuid_checkpass(cpu, 1)); 3122 return (cpu->cpu_m.mcpu_cpi->cpi_step); 3123 } 3124 3125 uint_t 3126 cpuid_getsig(struct cpu *cpu) 3127 { 3128 ASSERT(cpuid_checkpass(cpu, 1)); 3129 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 3130 } 3131 3132 uint32_t 3133 cpuid_getchiprev(struct cpu *cpu) 3134 { 3135 ASSERT(cpuid_checkpass(cpu, 1)); 3136 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 3137 } 3138 3139 const char * 3140 cpuid_getchiprevstr(struct cpu *cpu) 3141 { 3142 ASSERT(cpuid_checkpass(cpu, 1)); 3143 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 3144 } 3145 3146 uint32_t 3147 cpuid_getsockettype(struct cpu *cpu) 3148 { 3149 ASSERT(cpuid_checkpass(cpu, 1)); 3150 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 3151 } 3152 3153 const char * 3154 cpuid_getsocketstr(cpu_t *cpu) 3155 { 3156 static const char *socketstr = NULL; 3157 struct cpuid_info *cpi; 3158 3159 ASSERT(cpuid_checkpass(cpu, 1)); 3160 cpi = cpu->cpu_m.mcpu_cpi; 3161 3162 /* Assume that socket types are the same across the system */ 3163 if (socketstr == NULL) 3164 socketstr = _cpuid_sktstr(cpi->cpi_vendor, cpi->cpi_family, 3165 cpi->cpi_model, cpi->cpi_step); 3166 3167 3168 return (socketstr); 3169 } 3170 3171 int 3172 cpuid_get_chipid(cpu_t *cpu) 3173 { 3174 ASSERT(cpuid_checkpass(cpu, 1)); 3175 3176 if (cpuid_is_cmt(cpu)) 3177 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 3178 return (cpu->cpu_id); 3179 } 3180 3181 id_t 3182 cpuid_get_coreid(cpu_t *cpu) 3183 { 3184 ASSERT(cpuid_checkpass(cpu, 1)); 3185 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 3186 } 3187 3188 int 3189 cpuid_get_pkgcoreid(cpu_t *cpu) 3190 { 3191 ASSERT(cpuid_checkpass(cpu, 1)); 3192 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid); 3193 } 3194 3195 int 3196 cpuid_get_clogid(cpu_t *cpu) 3197 { 3198 ASSERT(cpuid_checkpass(cpu, 1)); 3199 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 3200 } 3201 3202 int 3203 cpuid_get_cacheid(cpu_t *cpu) 3204 { 3205 ASSERT(cpuid_checkpass(cpu, 1)); 3206 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 3207 } 3208 3209 uint_t 3210 cpuid_get_procnodeid(cpu_t *cpu) 3211 { 3212 ASSERT(cpuid_checkpass(cpu, 1)); 3213 return (cpu->cpu_m.mcpu_cpi->cpi_procnodeid); 3214 } 3215 3216 uint_t 3217 cpuid_get_procnodes_per_pkg(cpu_t *cpu) 3218 { 3219 ASSERT(cpuid_checkpass(cpu, 1)); 3220 return (cpu->cpu_m.mcpu_cpi->cpi_procnodes_per_pkg); 3221 } 3222 3223 uint_t 3224 cpuid_get_compunitid(cpu_t *cpu) 3225 { 3226 ASSERT(cpuid_checkpass(cpu, 1)); 3227 return (cpu->cpu_m.mcpu_cpi->cpi_compunitid); 3228 } 3229 3230 uint_t 3231 cpuid_get_cores_per_compunit(cpu_t *cpu) 3232 { 3233 ASSERT(cpuid_checkpass(cpu, 1)); 3234 return (cpu->cpu_m.mcpu_cpi->cpi_cores_per_compunit); 3235 } 3236 3237 /*ARGSUSED*/ 3238 int 3239 cpuid_have_cr8access(cpu_t *cpu) 3240 { 3241 #if defined(__amd64) 3242 return (1); 3243 #else 3244 struct cpuid_info *cpi; 3245 3246 ASSERT(cpu != NULL); 3247 cpi = cpu->cpu_m.mcpu_cpi; 3248 if (cpi->cpi_vendor == X86_VENDOR_AMD && cpi->cpi_maxeax >= 1 && 3249 (CPI_FEATURES_XTD_ECX(cpi) & CPUID_AMD_ECX_CR8D) != 0) 3250 return (1); 3251 return (0); 3252 #endif 3253 } 3254 3255 uint32_t 3256 cpuid_get_apicid(cpu_t *cpu) 3257 { 3258 ASSERT(cpuid_checkpass(cpu, 1)); 3259 if (cpu->cpu_m.mcpu_cpi->cpi_maxeax < 1) { 3260 return (UINT32_MAX); 3261 } else { 3262 return (cpu->cpu_m.mcpu_cpi->cpi_apicid); 3263 } 3264 } 3265 3266 void 3267 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 3268 { 3269 struct cpuid_info *cpi; 3270 3271 if (cpu == NULL) 3272 cpu = CPU; 3273 cpi = cpu->cpu_m.mcpu_cpi; 3274 3275 ASSERT(cpuid_checkpass(cpu, 1)); 3276 3277 if (pabits) 3278 *pabits = cpi->cpi_pabits; 3279 if (vabits) 3280 *vabits = cpi->cpi_vabits; 3281 } 3282 3283 /* 3284 * Returns the number of data TLB entries for a corresponding 3285 * pagesize. If it can't be computed, or isn't known, the 3286 * routine returns zero. If you ask about an architecturally 3287 * impossible pagesize, the routine will panic (so that the 3288 * hat implementor knows that things are inconsistent.) 3289 */ 3290 uint_t 3291 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 3292 { 3293 struct cpuid_info *cpi; 3294 uint_t dtlb_nent = 0; 3295 3296 if (cpu == NULL) 3297 cpu = CPU; 3298 cpi = cpu->cpu_m.mcpu_cpi; 3299 3300 ASSERT(cpuid_checkpass(cpu, 1)); 3301 3302 /* 3303 * Check the L2 TLB info 3304 */ 3305 if (cpi->cpi_xmaxeax >= 0x80000006) { 3306 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 3307 3308 switch (pagesize) { 3309 3310 case 4 * 1024: 3311 /* 3312 * All zero in the top 16 bits of the register 3313 * indicates a unified TLB. Size is in low 16 bits. 3314 */ 3315 if ((cp->cp_ebx & 0xffff0000) == 0) 3316 dtlb_nent = cp->cp_ebx & 0x0000ffff; 3317 else 3318 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 3319 break; 3320 3321 case 2 * 1024 * 1024: 3322 if ((cp->cp_eax & 0xffff0000) == 0) 3323 dtlb_nent = cp->cp_eax & 0x0000ffff; 3324 else 3325 dtlb_nent = BITX(cp->cp_eax, 27, 16); 3326 break; 3327 3328 default: 3329 panic("unknown L2 pagesize"); 3330 /*NOTREACHED*/ 3331 } 3332 } 3333 3334 if (dtlb_nent != 0) 3335 return (dtlb_nent); 3336 3337 /* 3338 * No L2 TLB support for this size, try L1. 3339 */ 3340 if (cpi->cpi_xmaxeax >= 0x80000005) { 3341 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 3342 3343 switch (pagesize) { 3344 case 4 * 1024: 3345 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 3346 break; 3347 case 2 * 1024 * 1024: 3348 dtlb_nent = BITX(cp->cp_eax, 23, 16); 3349 break; 3350 default: 3351 panic("unknown L1 d-TLB pagesize"); 3352 /*NOTREACHED*/ 3353 } 3354 } 3355 3356 return (dtlb_nent); 3357 } 3358 3359 /* 3360 * Return 0 if the erratum is not present or not applicable, positive 3361 * if it is, and negative if the status of the erratum is unknown. 3362 * 3363 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 3364 * Processors" #25759, Rev 3.57, August 2005 3365 */ 3366 int 3367 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 3368 { 3369 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3370 uint_t eax; 3371 3372 /* 3373 * Bail out if this CPU isn't an AMD CPU, or if it's 3374 * a legacy (32-bit) AMD CPU. 3375 */ 3376 if (cpi->cpi_vendor != X86_VENDOR_AMD || 3377 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 3378 cpi->cpi_family == 6) 3379 3380 return (0); 3381 3382 eax = cpi->cpi_std[1].cp_eax; 3383 3384 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 3385 #define SH_B3(eax) (eax == 0xf51) 3386 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 3387 3388 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 3389 3390 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 3391 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 3392 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 3393 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 3394 3395 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 3396 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 3397 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 3398 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 3399 3400 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 3401 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 3402 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 3403 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 3404 #define BH_E4(eax) (eax == 0x20fb1) 3405 #define SH_E5(eax) (eax == 0x20f42) 3406 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 3407 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 3408 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 3409 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 3410 DH_E6(eax) || JH_E6(eax)) 3411 3412 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02) 3413 #define DR_B0(eax) (eax == 0x100f20) 3414 #define DR_B1(eax) (eax == 0x100f21) 3415 #define DR_BA(eax) (eax == 0x100f2a) 3416 #define DR_B2(eax) (eax == 0x100f22) 3417 #define DR_B3(eax) (eax == 0x100f23) 3418 #define RB_C0(eax) (eax == 0x100f40) 3419 3420 switch (erratum) { 3421 case 1: 3422 return (cpi->cpi_family < 0x10); 3423 case 51: /* what does the asterisk mean? */ 3424 return (B(eax) || SH_C0(eax) || CG(eax)); 3425 case 52: 3426 return (B(eax)); 3427 case 57: 3428 return (cpi->cpi_family <= 0x11); 3429 case 58: 3430 return (B(eax)); 3431 case 60: 3432 return (cpi->cpi_family <= 0x11); 3433 case 61: 3434 case 62: 3435 case 63: 3436 case 64: 3437 case 65: 3438 case 66: 3439 case 68: 3440 case 69: 3441 case 70: 3442 case 71: 3443 return (B(eax)); 3444 case 72: 3445 return (SH_B0(eax)); 3446 case 74: 3447 return (B(eax)); 3448 case 75: 3449 return (cpi->cpi_family < 0x10); 3450 case 76: 3451 return (B(eax)); 3452 case 77: 3453 return (cpi->cpi_family <= 0x11); 3454 case 78: 3455 return (B(eax) || SH_C0(eax)); 3456 case 79: 3457 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 3458 case 80: 3459 case 81: 3460 case 82: 3461 return (B(eax)); 3462 case 83: 3463 return (B(eax) || SH_C0(eax) || CG(eax)); 3464 case 85: 3465 return (cpi->cpi_family < 0x10); 3466 case 86: 3467 return (SH_C0(eax) || CG(eax)); 3468 case 88: 3469 #if !defined(__amd64) 3470 return (0); 3471 #else 3472 return (B(eax) || SH_C0(eax)); 3473 #endif 3474 case 89: 3475 return (cpi->cpi_family < 0x10); 3476 case 90: 3477 return (B(eax) || SH_C0(eax) || CG(eax)); 3478 case 91: 3479 case 92: 3480 return (B(eax) || SH_C0(eax)); 3481 case 93: 3482 return (SH_C0(eax)); 3483 case 94: 3484 return (B(eax) || SH_C0(eax) || CG(eax)); 3485 case 95: 3486 #if !defined(__amd64) 3487 return (0); 3488 #else 3489 return (B(eax) || SH_C0(eax)); 3490 #endif 3491 case 96: 3492 return (B(eax) || SH_C0(eax) || CG(eax)); 3493 case 97: 3494 case 98: 3495 return (SH_C0(eax) || CG(eax)); 3496 case 99: 3497 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 3498 case 100: 3499 return (B(eax) || SH_C0(eax)); 3500 case 101: 3501 case 103: 3502 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 3503 case 104: 3504 return (SH_C0(eax) || CG(eax) || D0(eax)); 3505 case 105: 3506 case 106: 3507 case 107: 3508 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 3509 case 108: 3510 return (DH_CG(eax)); 3511 case 109: 3512 return (SH_C0(eax) || CG(eax) || D0(eax)); 3513 case 110: 3514 return (D0(eax) || EX(eax)); 3515 case 111: 3516 return (CG(eax)); 3517 case 112: 3518 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 3519 case 113: 3520 return (eax == 0x20fc0); 3521 case 114: 3522 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 3523 case 115: 3524 return (SH_E0(eax) || JH_E1(eax)); 3525 case 116: 3526 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 3527 case 117: 3528 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 3529 case 118: 3530 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 3531 JH_E6(eax)); 3532 case 121: 3533 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 3534 case 122: 3535 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11); 3536 case 123: 3537 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 3538 case 131: 3539 return (cpi->cpi_family < 0x10); 3540 case 6336786: 3541 /* 3542 * Test for AdvPowerMgmtInfo.TscPStateInvariant 3543 * if this is a K8 family or newer processor 3544 */ 3545 if (CPI_FAMILY(cpi) == 0xf) { 3546 struct cpuid_regs regs; 3547 regs.cp_eax = 0x80000007; 3548 (void) __cpuid_insn(®s); 3549 return (!(regs.cp_edx & 0x100)); 3550 } 3551 return (0); 3552 case 6323525: 3553 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 3554 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 3555 3556 case 6671130: 3557 /* 3558 * check for processors (pre-Shanghai) that do not provide 3559 * optimal management of 1gb ptes in its tlb. 3560 */ 3561 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4); 3562 3563 case 298: 3564 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) || 3565 DR_B2(eax) || RB_C0(eax)); 3566 3567 case 721: 3568 #if defined(__amd64) 3569 return (cpi->cpi_family == 0x10 || cpi->cpi_family == 0x12); 3570 #else 3571 return (0); 3572 #endif 3573 3574 default: 3575 return (-1); 3576 3577 } 3578 } 3579 3580 /* 3581 * Determine if specified erratum is present via OSVW (OS Visible Workaround). 3582 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate. 3583 */ 3584 int 3585 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum) 3586 { 3587 struct cpuid_info *cpi; 3588 uint_t osvwid; 3589 static int osvwfeature = -1; 3590 uint64_t osvwlength; 3591 3592 3593 cpi = cpu->cpu_m.mcpu_cpi; 3594 3595 /* confirm OSVW supported */ 3596 if (osvwfeature == -1) { 3597 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW; 3598 } else { 3599 /* assert that osvw feature setting is consistent on all cpus */ 3600 ASSERT(osvwfeature == 3601 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW)); 3602 } 3603 if (!osvwfeature) 3604 return (-1); 3605 3606 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK; 3607 3608 switch (erratum) { 3609 case 298: /* osvwid is 0 */ 3610 osvwid = 0; 3611 if (osvwlength <= (uint64_t)osvwid) { 3612 /* osvwid 0 is unknown */ 3613 return (-1); 3614 } 3615 3616 /* 3617 * Check the OSVW STATUS MSR to determine the state 3618 * of the erratum where: 3619 * 0 - fixed by HW 3620 * 1 - BIOS has applied the workaround when BIOS 3621 * workaround is available. (Or for other errata, 3622 * OS workaround is required.) 3623 * For a value of 1, caller will confirm that the 3624 * erratum 298 workaround has indeed been applied by BIOS. 3625 * 3626 * A 1 may be set in cpus that have a HW fix 3627 * in a mixed cpu system. Regarding erratum 298: 3628 * In a multiprocessor platform, the workaround above 3629 * should be applied to all processors regardless of 3630 * silicon revision when an affected processor is 3631 * present. 3632 */ 3633 3634 return (rdmsr(MSR_AMD_OSVW_STATUS + 3635 (osvwid / OSVW_ID_CNT_PER_MSR)) & 3636 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR))); 3637 3638 default: 3639 return (-1); 3640 } 3641 } 3642 3643 static const char assoc_str[] = "associativity"; 3644 static const char line_str[] = "line-size"; 3645 static const char size_str[] = "size"; 3646 3647 static void 3648 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 3649 uint32_t val) 3650 { 3651 char buf[128]; 3652 3653 /* 3654 * ndi_prop_update_int() is used because it is desirable for 3655 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 3656 */ 3657 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 3658 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 3659 } 3660 3661 /* 3662 * Intel-style cache/tlb description 3663 * 3664 * Standard cpuid level 2 gives a randomly ordered 3665 * selection of tags that index into a table that describes 3666 * cache and tlb properties. 3667 */ 3668 3669 static const char l1_icache_str[] = "l1-icache"; 3670 static const char l1_dcache_str[] = "l1-dcache"; 3671 static const char l2_cache_str[] = "l2-cache"; 3672 static const char l3_cache_str[] = "l3-cache"; 3673 static const char itlb4k_str[] = "itlb-4K"; 3674 static const char dtlb4k_str[] = "dtlb-4K"; 3675 static const char itlb2M_str[] = "itlb-2M"; 3676 static const char itlb4M_str[] = "itlb-4M"; 3677 static const char dtlb4M_str[] = "dtlb-4M"; 3678 static const char dtlb24_str[] = "dtlb0-2M-4M"; 3679 static const char itlb424_str[] = "itlb-4K-2M-4M"; 3680 static const char itlb24_str[] = "itlb-2M-4M"; 3681 static const char dtlb44_str[] = "dtlb-4K-4M"; 3682 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 3683 static const char sl2_cache_str[] = "sectored-l2-cache"; 3684 static const char itrace_str[] = "itrace-cache"; 3685 static const char sl3_cache_str[] = "sectored-l3-cache"; 3686 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; 3687 3688 static const struct cachetab { 3689 uint8_t ct_code; 3690 uint8_t ct_assoc; 3691 uint16_t ct_line_size; 3692 size_t ct_size; 3693 const char *ct_label; 3694 } intel_ctab[] = { 3695 /* 3696 * maintain descending order! 3697 * 3698 * Codes ignored - Reason 3699 * ---------------------- 3700 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache 3701 * f0H/f1H - Currently we do not interpret prefetch size by design 3702 */ 3703 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str}, 3704 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str}, 3705 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str}, 3706 { 0xde, 12, 64, 6*1024*1024, l3_cache_str}, 3707 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str}, 3708 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str}, 3709 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str}, 3710 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str}, 3711 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str}, 3712 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str}, 3713 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str}, 3714 { 0xd0, 4, 64, 512*1024, l3_cache_str}, 3715 { 0xca, 4, 0, 512, sh_l2_tlb4k_str}, 3716 { 0xc0, 4, 0, 8, dtlb44_str }, 3717 { 0xba, 4, 0, 64, dtlb4k_str }, 3718 { 0xb4, 4, 0, 256, dtlb4k_str }, 3719 { 0xb3, 4, 0, 128, dtlb4k_str }, 3720 { 0xb2, 4, 0, 64, itlb4k_str }, 3721 { 0xb0, 4, 0, 128, itlb4k_str }, 3722 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 3723 { 0x86, 4, 64, 512*1024, l2_cache_str}, 3724 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 3725 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 3726 { 0x83, 8, 32, 512*1024, l2_cache_str}, 3727 { 0x82, 8, 32, 256*1024, l2_cache_str}, 3728 { 0x80, 8, 64, 512*1024, l2_cache_str}, 3729 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 3730 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 3731 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 3732 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 3733 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 3734 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 3735 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 3736 { 0x73, 8, 0, 64*1024, itrace_str}, 3737 { 0x72, 8, 0, 32*1024, itrace_str}, 3738 { 0x71, 8, 0, 16*1024, itrace_str}, 3739 { 0x70, 8, 0, 12*1024, itrace_str}, 3740 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 3741 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 3742 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 3743 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 3744 { 0x5d, 0, 0, 256, dtlb44_str}, 3745 { 0x5c, 0, 0, 128, dtlb44_str}, 3746 { 0x5b, 0, 0, 64, dtlb44_str}, 3747 { 0x5a, 4, 0, 32, dtlb24_str}, 3748 { 0x59, 0, 0, 16, dtlb4k_str}, 3749 { 0x57, 4, 0, 16, dtlb4k_str}, 3750 { 0x56, 4, 0, 16, dtlb4M_str}, 3751 { 0x55, 0, 0, 7, itlb24_str}, 3752 { 0x52, 0, 0, 256, itlb424_str}, 3753 { 0x51, 0, 0, 128, itlb424_str}, 3754 { 0x50, 0, 0, 64, itlb424_str}, 3755 { 0x4f, 0, 0, 32, itlb4k_str}, 3756 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str}, 3757 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 3758 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 3759 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 3760 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 3761 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 3762 { 0x48, 12, 64, 3*1024*1024, l2_cache_str}, 3763 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 3764 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 3765 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 3766 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 3767 { 0x43, 4, 32, 512*1024, l2_cache_str}, 3768 { 0x42, 4, 32, 256*1024, l2_cache_str}, 3769 { 0x41, 4, 32, 128*1024, l2_cache_str}, 3770 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 3771 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 3772 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 3773 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 3774 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 3775 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 3776 { 0x30, 8, 64, 32*1024, l1_icache_str}, 3777 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 3778 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 3779 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 3780 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 3781 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 3782 { 0x0e, 6, 64, 24*1024, l1_dcache_str}, 3783 { 0x0d, 4, 32, 16*1024, l1_dcache_str}, 3784 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 3785 { 0x0b, 4, 0, 4, itlb4M_str}, 3786 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 3787 { 0x08, 4, 32, 16*1024, l1_icache_str}, 3788 { 0x06, 4, 32, 8*1024, l1_icache_str}, 3789 { 0x05, 4, 0, 32, dtlb4M_str}, 3790 { 0x04, 4, 0, 8, dtlb4M_str}, 3791 { 0x03, 4, 0, 64, dtlb4k_str}, 3792 { 0x02, 4, 0, 2, itlb4M_str}, 3793 { 0x01, 4, 0, 32, itlb4k_str}, 3794 { 0 } 3795 }; 3796 3797 static const struct cachetab cyrix_ctab[] = { 3798 { 0x70, 4, 0, 32, "tlb-4K" }, 3799 { 0x80, 4, 16, 16*1024, "l1-cache" }, 3800 { 0 } 3801 }; 3802 3803 /* 3804 * Search a cache table for a matching entry 3805 */ 3806 static const struct cachetab * 3807 find_cacheent(const struct cachetab *ct, uint_t code) 3808 { 3809 if (code != 0) { 3810 for (; ct->ct_code != 0; ct++) 3811 if (ct->ct_code <= code) 3812 break; 3813 if (ct->ct_code == code) 3814 return (ct); 3815 } 3816 return (NULL); 3817 } 3818 3819 /* 3820 * Populate cachetab entry with L2 or L3 cache-information using 3821 * cpuid function 4. This function is called from intel_walk_cacheinfo() 3822 * when descriptor 0x49 is encountered. It returns 0 if no such cache 3823 * information is found. 3824 */ 3825 static int 3826 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi) 3827 { 3828 uint32_t level, i; 3829 int ret = 0; 3830 3831 for (i = 0; i < cpi->cpi_std_4_size; i++) { 3832 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 3833 3834 if (level == 2 || level == 3) { 3835 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 3836 ct->ct_line_size = 3837 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 3838 ct->ct_size = ct->ct_assoc * 3839 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 3840 ct->ct_line_size * 3841 (cpi->cpi_std_4[i]->cp_ecx + 1); 3842 3843 if (level == 2) { 3844 ct->ct_label = l2_cache_str; 3845 } else if (level == 3) { 3846 ct->ct_label = l3_cache_str; 3847 } 3848 ret = 1; 3849 } 3850 } 3851 3852 return (ret); 3853 } 3854 3855 /* 3856 * Walk the cacheinfo descriptor, applying 'func' to every valid element 3857 * The walk is terminated if the walker returns non-zero. 3858 */ 3859 static void 3860 intel_walk_cacheinfo(struct cpuid_info *cpi, 3861 void *arg, int (*func)(void *, const struct cachetab *)) 3862 { 3863 const struct cachetab *ct; 3864 struct cachetab des_49_ct, des_b1_ct; 3865 uint8_t *dp; 3866 int i; 3867 3868 if ((dp = cpi->cpi_cacheinfo) == NULL) 3869 return; 3870 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3871 /* 3872 * For overloaded descriptor 0x49 we use cpuid function 4 3873 * if supported by the current processor, to create 3874 * cache information. 3875 * For overloaded descriptor 0xb1 we use X86_PAE flag 3876 * to disambiguate the cache information. 3877 */ 3878 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 && 3879 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) { 3880 ct = &des_49_ct; 3881 } else if (*dp == 0xb1) { 3882 des_b1_ct.ct_code = 0xb1; 3883 des_b1_ct.ct_assoc = 4; 3884 des_b1_ct.ct_line_size = 0; 3885 if (is_x86_feature(x86_featureset, X86FSET_PAE)) { 3886 des_b1_ct.ct_size = 8; 3887 des_b1_ct.ct_label = itlb2M_str; 3888 } else { 3889 des_b1_ct.ct_size = 4; 3890 des_b1_ct.ct_label = itlb4M_str; 3891 } 3892 ct = &des_b1_ct; 3893 } else { 3894 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) { 3895 continue; 3896 } 3897 } 3898 3899 if (func(arg, ct) != 0) { 3900 break; 3901 } 3902 } 3903 } 3904 3905 /* 3906 * (Like the Intel one, except for Cyrix CPUs) 3907 */ 3908 static void 3909 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 3910 void *arg, int (*func)(void *, const struct cachetab *)) 3911 { 3912 const struct cachetab *ct; 3913 uint8_t *dp; 3914 int i; 3915 3916 if ((dp = cpi->cpi_cacheinfo) == NULL) 3917 return; 3918 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3919 /* 3920 * Search Cyrix-specific descriptor table first .. 3921 */ 3922 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 3923 if (func(arg, ct) != 0) 3924 break; 3925 continue; 3926 } 3927 /* 3928 * .. else fall back to the Intel one 3929 */ 3930 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 3931 if (func(arg, ct) != 0) 3932 break; 3933 continue; 3934 } 3935 } 3936 } 3937 3938 /* 3939 * A cacheinfo walker that adds associativity, line-size, and size properties 3940 * to the devinfo node it is passed as an argument. 3941 */ 3942 static int 3943 add_cacheent_props(void *arg, const struct cachetab *ct) 3944 { 3945 dev_info_t *devi = arg; 3946 3947 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 3948 if (ct->ct_line_size != 0) 3949 add_cache_prop(devi, ct->ct_label, line_str, 3950 ct->ct_line_size); 3951 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 3952 return (0); 3953 } 3954 3955 3956 static const char fully_assoc[] = "fully-associative?"; 3957 3958 /* 3959 * AMD style cache/tlb description 3960 * 3961 * Extended functions 5 and 6 directly describe properties of 3962 * tlbs and various cache levels. 3963 */ 3964 static void 3965 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3966 { 3967 switch (assoc) { 3968 case 0: /* reserved; ignore */ 3969 break; 3970 default: 3971 add_cache_prop(devi, label, assoc_str, assoc); 3972 break; 3973 case 0xff: 3974 add_cache_prop(devi, label, fully_assoc, 1); 3975 break; 3976 } 3977 } 3978 3979 static void 3980 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3981 { 3982 if (size == 0) 3983 return; 3984 add_cache_prop(devi, label, size_str, size); 3985 add_amd_assoc(devi, label, assoc); 3986 } 3987 3988 static void 3989 add_amd_cache(dev_info_t *devi, const char *label, 3990 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3991 { 3992 if (size == 0 || line_size == 0) 3993 return; 3994 add_amd_assoc(devi, label, assoc); 3995 /* 3996 * Most AMD parts have a sectored cache. Multiple cache lines are 3997 * associated with each tag. A sector consists of all cache lines 3998 * associated with a tag. For example, the AMD K6-III has a sector 3999 * size of 2 cache lines per tag. 4000 */ 4001 if (lines_per_tag != 0) 4002 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 4003 add_cache_prop(devi, label, line_str, line_size); 4004 add_cache_prop(devi, label, size_str, size * 1024); 4005 } 4006 4007 static void 4008 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 4009 { 4010 switch (assoc) { 4011 case 0: /* off */ 4012 break; 4013 case 1: 4014 case 2: 4015 case 4: 4016 add_cache_prop(devi, label, assoc_str, assoc); 4017 break; 4018 case 6: 4019 add_cache_prop(devi, label, assoc_str, 8); 4020 break; 4021 case 8: 4022 add_cache_prop(devi, label, assoc_str, 16); 4023 break; 4024 case 0xf: 4025 add_cache_prop(devi, label, fully_assoc, 1); 4026 break; 4027 default: /* reserved; ignore */ 4028 break; 4029 } 4030 } 4031 4032 static void 4033 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 4034 { 4035 if (size == 0 || assoc == 0) 4036 return; 4037 add_amd_l2_assoc(devi, label, assoc); 4038 add_cache_prop(devi, label, size_str, size); 4039 } 4040 4041 static void 4042 add_amd_l2_cache(dev_info_t *devi, const char *label, 4043 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 4044 { 4045 if (size == 0 || assoc == 0 || line_size == 0) 4046 return; 4047 add_amd_l2_assoc(devi, label, assoc); 4048 if (lines_per_tag != 0) 4049 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 4050 add_cache_prop(devi, label, line_str, line_size); 4051 add_cache_prop(devi, label, size_str, size * 1024); 4052 } 4053 4054 static void 4055 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 4056 { 4057 struct cpuid_regs *cp; 4058 4059 if (cpi->cpi_xmaxeax < 0x80000005) 4060 return; 4061 cp = &cpi->cpi_extd[5]; 4062 4063 /* 4064 * 4M/2M L1 TLB configuration 4065 * 4066 * We report the size for 2M pages because AMD uses two 4067 * TLB entries for one 4M page. 4068 */ 4069 add_amd_tlb(devi, "dtlb-2M", 4070 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 4071 add_amd_tlb(devi, "itlb-2M", 4072 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 4073 4074 /* 4075 * 4K L1 TLB configuration 4076 */ 4077 4078 switch (cpi->cpi_vendor) { 4079 uint_t nentries; 4080 case X86_VENDOR_TM: 4081 if (cpi->cpi_family >= 5) { 4082 /* 4083 * Crusoe processors have 256 TLB entries, but 4084 * cpuid data format constrains them to only 4085 * reporting 255 of them. 4086 */ 4087 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 4088 nentries = 256; 4089 /* 4090 * Crusoe processors also have a unified TLB 4091 */ 4092 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 4093 nentries); 4094 break; 4095 } 4096 /*FALLTHROUGH*/ 4097 default: 4098 add_amd_tlb(devi, itlb4k_str, 4099 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 4100 add_amd_tlb(devi, dtlb4k_str, 4101 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 4102 break; 4103 } 4104 4105 /* 4106 * data L1 cache configuration 4107 */ 4108 4109 add_amd_cache(devi, l1_dcache_str, 4110 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 4111 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 4112 4113 /* 4114 * code L1 cache configuration 4115 */ 4116 4117 add_amd_cache(devi, l1_icache_str, 4118 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 4119 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 4120 4121 if (cpi->cpi_xmaxeax < 0x80000006) 4122 return; 4123 cp = &cpi->cpi_extd[6]; 4124 4125 /* Check for a unified L2 TLB for large pages */ 4126 4127 if (BITX(cp->cp_eax, 31, 16) == 0) 4128 add_amd_l2_tlb(devi, "l2-tlb-2M", 4129 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 4130 else { 4131 add_amd_l2_tlb(devi, "l2-dtlb-2M", 4132 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 4133 add_amd_l2_tlb(devi, "l2-itlb-2M", 4134 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 4135 } 4136 4137 /* Check for a unified L2 TLB for 4K pages */ 4138 4139 if (BITX(cp->cp_ebx, 31, 16) == 0) { 4140 add_amd_l2_tlb(devi, "l2-tlb-4K", 4141 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 4142 } else { 4143 add_amd_l2_tlb(devi, "l2-dtlb-4K", 4144 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 4145 add_amd_l2_tlb(devi, "l2-itlb-4K", 4146 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 4147 } 4148 4149 add_amd_l2_cache(devi, l2_cache_str, 4150 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 4151 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 4152 } 4153 4154 /* 4155 * There are two basic ways that the x86 world describes it cache 4156 * and tlb architecture - Intel's way and AMD's way. 4157 * 4158 * Return which flavor of cache architecture we should use 4159 */ 4160 static int 4161 x86_which_cacheinfo(struct cpuid_info *cpi) 4162 { 4163 switch (cpi->cpi_vendor) { 4164 case X86_VENDOR_Intel: 4165 if (cpi->cpi_maxeax >= 2) 4166 return (X86_VENDOR_Intel); 4167 break; 4168 case X86_VENDOR_AMD: 4169 /* 4170 * The K5 model 1 was the first part from AMD that reported 4171 * cache sizes via extended cpuid functions. 4172 */ 4173 if (cpi->cpi_family > 5 || 4174 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 4175 return (X86_VENDOR_AMD); 4176 break; 4177 case X86_VENDOR_TM: 4178 if (cpi->cpi_family >= 5) 4179 return (X86_VENDOR_AMD); 4180 /*FALLTHROUGH*/ 4181 default: 4182 /* 4183 * If they have extended CPU data for 0x80000005 4184 * then we assume they have AMD-format cache 4185 * information. 4186 * 4187 * If not, and the vendor happens to be Cyrix, 4188 * then try our-Cyrix specific handler. 4189 * 4190 * If we're not Cyrix, then assume we're using Intel's 4191 * table-driven format instead. 4192 */ 4193 if (cpi->cpi_xmaxeax >= 0x80000005) 4194 return (X86_VENDOR_AMD); 4195 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 4196 return (X86_VENDOR_Cyrix); 4197 else if (cpi->cpi_maxeax >= 2) 4198 return (X86_VENDOR_Intel); 4199 break; 4200 } 4201 return (-1); 4202 } 4203 4204 void 4205 cpuid_set_cpu_properties(void *dip, processorid_t cpu_id, 4206 struct cpuid_info *cpi) 4207 { 4208 dev_info_t *cpu_devi; 4209 int create; 4210 4211 cpu_devi = (dev_info_t *)dip; 4212 4213 /* device_type */ 4214 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 4215 "device_type", "cpu"); 4216 4217 /* reg */ 4218 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4219 "reg", cpu_id); 4220 4221 /* cpu-mhz, and clock-frequency */ 4222 if (cpu_freq > 0) { 4223 long long mul; 4224 4225 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4226 "cpu-mhz", cpu_freq); 4227 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 4228 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4229 "clock-frequency", (int)mul); 4230 } 4231 4232 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) { 4233 return; 4234 } 4235 4236 /* vendor-id */ 4237 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 4238 "vendor-id", cpi->cpi_vendorstr); 4239 4240 if (cpi->cpi_maxeax == 0) { 4241 return; 4242 } 4243 4244 /* 4245 * family, model, and step 4246 */ 4247 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4248 "family", CPI_FAMILY(cpi)); 4249 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4250 "cpu-model", CPI_MODEL(cpi)); 4251 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4252 "stepping-id", CPI_STEP(cpi)); 4253 4254 /* type */ 4255 switch (cpi->cpi_vendor) { 4256 case X86_VENDOR_Intel: 4257 create = 1; 4258 break; 4259 default: 4260 create = 0; 4261 break; 4262 } 4263 if (create) 4264 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4265 "type", CPI_TYPE(cpi)); 4266 4267 /* ext-family */ 4268 switch (cpi->cpi_vendor) { 4269 case X86_VENDOR_Intel: 4270 case X86_VENDOR_AMD: 4271 create = cpi->cpi_family >= 0xf; 4272 break; 4273 default: 4274 create = 0; 4275 break; 4276 } 4277 if (create) 4278 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4279 "ext-family", CPI_FAMILY_XTD(cpi)); 4280 4281 /* ext-model */ 4282 switch (cpi->cpi_vendor) { 4283 case X86_VENDOR_Intel: 4284 create = IS_EXTENDED_MODEL_INTEL(cpi); 4285 break; 4286 case X86_VENDOR_AMD: 4287 create = CPI_FAMILY(cpi) == 0xf; 4288 break; 4289 default: 4290 create = 0; 4291 break; 4292 } 4293 if (create) 4294 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4295 "ext-model", CPI_MODEL_XTD(cpi)); 4296 4297 /* generation */ 4298 switch (cpi->cpi_vendor) { 4299 case X86_VENDOR_AMD: 4300 /* 4301 * AMD K5 model 1 was the first part to support this 4302 */ 4303 create = cpi->cpi_xmaxeax >= 0x80000001; 4304 break; 4305 default: 4306 create = 0; 4307 break; 4308 } 4309 if (create) 4310 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4311 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 4312 4313 /* brand-id */ 4314 switch (cpi->cpi_vendor) { 4315 case X86_VENDOR_Intel: 4316 /* 4317 * brand id first appeared on Pentium III Xeon model 8, 4318 * and Celeron model 8 processors and Opteron 4319 */ 4320 create = cpi->cpi_family > 6 || 4321 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 4322 break; 4323 case X86_VENDOR_AMD: 4324 create = cpi->cpi_family >= 0xf; 4325 break; 4326 default: 4327 create = 0; 4328 break; 4329 } 4330 if (create && cpi->cpi_brandid != 0) { 4331 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4332 "brand-id", cpi->cpi_brandid); 4333 } 4334 4335 /* chunks, and apic-id */ 4336 switch (cpi->cpi_vendor) { 4337 /* 4338 * first available on Pentium IV and Opteron (K8) 4339 */ 4340 case X86_VENDOR_Intel: 4341 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 4342 break; 4343 case X86_VENDOR_AMD: 4344 create = cpi->cpi_family >= 0xf; 4345 break; 4346 default: 4347 create = 0; 4348 break; 4349 } 4350 if (create) { 4351 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4352 "chunks", CPI_CHUNKS(cpi)); 4353 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4354 "apic-id", cpi->cpi_apicid); 4355 if (cpi->cpi_chipid >= 0) { 4356 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4357 "chip#", cpi->cpi_chipid); 4358 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4359 "clog#", cpi->cpi_clogid); 4360 } 4361 } 4362 4363 /* cpuid-features */ 4364 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4365 "cpuid-features", CPI_FEATURES_EDX(cpi)); 4366 4367 4368 /* cpuid-features-ecx */ 4369 switch (cpi->cpi_vendor) { 4370 case X86_VENDOR_Intel: 4371 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 4372 break; 4373 case X86_VENDOR_AMD: 4374 create = cpi->cpi_family >= 0xf; 4375 break; 4376 default: 4377 create = 0; 4378 break; 4379 } 4380 if (create) 4381 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4382 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 4383 4384 /* ext-cpuid-features */ 4385 switch (cpi->cpi_vendor) { 4386 case X86_VENDOR_Intel: 4387 case X86_VENDOR_AMD: 4388 case X86_VENDOR_Cyrix: 4389 case X86_VENDOR_TM: 4390 case X86_VENDOR_Centaur: 4391 create = cpi->cpi_xmaxeax >= 0x80000001; 4392 break; 4393 default: 4394 create = 0; 4395 break; 4396 } 4397 if (create) { 4398 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4399 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 4400 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 4401 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 4402 } 4403 4404 /* 4405 * Brand String first appeared in Intel Pentium IV, AMD K5 4406 * model 1, and Cyrix GXm. On earlier models we try and 4407 * simulate something similar .. so this string should always 4408 * same -something- about the processor, however lame. 4409 */ 4410 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 4411 "brand-string", cpi->cpi_brandstr); 4412 4413 /* 4414 * Finally, cache and tlb information 4415 */ 4416 switch (x86_which_cacheinfo(cpi)) { 4417 case X86_VENDOR_Intel: 4418 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 4419 break; 4420 case X86_VENDOR_Cyrix: 4421 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 4422 break; 4423 case X86_VENDOR_AMD: 4424 amd_cache_info(cpi, cpu_devi); 4425 break; 4426 default: 4427 break; 4428 } 4429 } 4430 4431 struct l2info { 4432 int *l2i_csz; 4433 int *l2i_lsz; 4434 int *l2i_assoc; 4435 int l2i_ret; 4436 }; 4437 4438 /* 4439 * A cacheinfo walker that fetches the size, line-size and associativity 4440 * of the L2 cache 4441 */ 4442 static int 4443 intel_l2cinfo(void *arg, const struct cachetab *ct) 4444 { 4445 struct l2info *l2i = arg; 4446 int *ip; 4447 4448 if (ct->ct_label != l2_cache_str && 4449 ct->ct_label != sl2_cache_str) 4450 return (0); /* not an L2 -- keep walking */ 4451 4452 if ((ip = l2i->l2i_csz) != NULL) 4453 *ip = ct->ct_size; 4454 if ((ip = l2i->l2i_lsz) != NULL) 4455 *ip = ct->ct_line_size; 4456 if ((ip = l2i->l2i_assoc) != NULL) 4457 *ip = ct->ct_assoc; 4458 l2i->l2i_ret = ct->ct_size; 4459 return (1); /* was an L2 -- terminate walk */ 4460 } 4461 4462 /* 4463 * AMD L2/L3 Cache and TLB Associativity Field Definition: 4464 * 4465 * Unlike the associativity for the L1 cache and tlb where the 8 bit 4466 * value is the associativity, the associativity for the L2 cache and 4467 * tlb is encoded in the following table. The 4 bit L2 value serves as 4468 * an index into the amd_afd[] array to determine the associativity. 4469 * -1 is undefined. 0 is fully associative. 4470 */ 4471 4472 static int amd_afd[] = 4473 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 4474 4475 static void 4476 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 4477 { 4478 struct cpuid_regs *cp; 4479 uint_t size, assoc; 4480 int i; 4481 int *ip; 4482 4483 if (cpi->cpi_xmaxeax < 0x80000006) 4484 return; 4485 cp = &cpi->cpi_extd[6]; 4486 4487 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 4488 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 4489 uint_t cachesz = size * 1024; 4490 assoc = amd_afd[i]; 4491 4492 ASSERT(assoc != -1); 4493 4494 if ((ip = l2i->l2i_csz) != NULL) 4495 *ip = cachesz; 4496 if ((ip = l2i->l2i_lsz) != NULL) 4497 *ip = BITX(cp->cp_ecx, 7, 0); 4498 if ((ip = l2i->l2i_assoc) != NULL) 4499 *ip = assoc; 4500 l2i->l2i_ret = cachesz; 4501 } 4502 } 4503 4504 int 4505 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 4506 { 4507 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 4508 struct l2info __l2info, *l2i = &__l2info; 4509 4510 l2i->l2i_csz = csz; 4511 l2i->l2i_lsz = lsz; 4512 l2i->l2i_assoc = assoc; 4513 l2i->l2i_ret = -1; 4514 4515 switch (x86_which_cacheinfo(cpi)) { 4516 case X86_VENDOR_Intel: 4517 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 4518 break; 4519 case X86_VENDOR_Cyrix: 4520 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 4521 break; 4522 case X86_VENDOR_AMD: 4523 amd_l2cacheinfo(cpi, l2i); 4524 break; 4525 default: 4526 break; 4527 } 4528 return (l2i->l2i_ret); 4529 } 4530 4531 #if !defined(__xpv) 4532 4533 uint32_t * 4534 cpuid_mwait_alloc(cpu_t *cpu) 4535 { 4536 uint32_t *ret; 4537 size_t mwait_size; 4538 4539 ASSERT(cpuid_checkpass(CPU, 2)); 4540 4541 mwait_size = CPU->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 4542 if (mwait_size == 0) 4543 return (NULL); 4544 4545 /* 4546 * kmem_alloc() returns cache line size aligned data for mwait_size 4547 * allocations. mwait_size is currently cache line sized. Neither 4548 * of these implementation details are guarantied to be true in the 4549 * future. 4550 * 4551 * First try allocating mwait_size as kmem_alloc() currently returns 4552 * correctly aligned memory. If kmem_alloc() does not return 4553 * mwait_size aligned memory, then use mwait_size ROUNDUP. 4554 * 4555 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 4556 * decide to free this memory. 4557 */ 4558 ret = kmem_zalloc(mwait_size, KM_SLEEP); 4559 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 4560 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 4561 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 4562 *ret = MWAIT_RUNNING; 4563 return (ret); 4564 } else { 4565 kmem_free(ret, mwait_size); 4566 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 4567 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 4568 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 4569 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 4570 *ret = MWAIT_RUNNING; 4571 return (ret); 4572 } 4573 } 4574 4575 void 4576 cpuid_mwait_free(cpu_t *cpu) 4577 { 4578 if (cpu->cpu_m.mcpu_cpi == NULL) { 4579 return; 4580 } 4581 4582 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 4583 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 4584 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 4585 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 4586 } 4587 4588 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 4589 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 4590 } 4591 4592 void 4593 patch_tsc_read(int flag) 4594 { 4595 size_t cnt; 4596 4597 switch (flag) { 4598 case TSC_NONE: 4599 cnt = &_no_rdtsc_end - &_no_rdtsc_start; 4600 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); 4601 break; 4602 case TSC_RDTSC_MFENCE: 4603 cnt = &_tsc_mfence_end - &_tsc_mfence_start; 4604 (void) memcpy((void *)tsc_read, 4605 (void *)&_tsc_mfence_start, cnt); 4606 break; 4607 case TSC_RDTSC_LFENCE: 4608 cnt = &_tsc_lfence_end - &_tsc_lfence_start; 4609 (void) memcpy((void *)tsc_read, 4610 (void *)&_tsc_lfence_start, cnt); 4611 break; 4612 case TSC_TSCP: 4613 cnt = &_tscp_end - &_tscp_start; 4614 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); 4615 break; 4616 default: 4617 /* Bail for unexpected TSC types. (TSC_NONE covers 0) */ 4618 cmn_err(CE_PANIC, "Unrecogized TSC type: %d", flag); 4619 break; 4620 } 4621 tsc_type = flag; 4622 } 4623 4624 int 4625 cpuid_deep_cstates_supported(void) 4626 { 4627 struct cpuid_info *cpi; 4628 struct cpuid_regs regs; 4629 4630 ASSERT(cpuid_checkpass(CPU, 1)); 4631 4632 cpi = CPU->cpu_m.mcpu_cpi; 4633 4634 if (!is_x86_feature(x86_featureset, X86FSET_CPUID)) 4635 return (0); 4636 4637 switch (cpi->cpi_vendor) { 4638 case X86_VENDOR_Intel: 4639 if (cpi->cpi_xmaxeax < 0x80000007) 4640 return (0); 4641 4642 /* 4643 * TSC run at a constant rate in all ACPI C-states? 4644 */ 4645 regs.cp_eax = 0x80000007; 4646 (void) __cpuid_insn(®s); 4647 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE); 4648 4649 default: 4650 return (0); 4651 } 4652 } 4653 4654 #endif /* !__xpv */ 4655 4656 void 4657 post_startup_cpu_fixups(void) 4658 { 4659 #ifndef __xpv 4660 /* 4661 * Some AMD processors support C1E state. Entering this state will 4662 * cause the local APIC timer to stop, which we can't deal with at 4663 * this time. 4664 */ 4665 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) { 4666 on_trap_data_t otd; 4667 uint64_t reg; 4668 4669 if (!on_trap(&otd, OT_DATA_ACCESS)) { 4670 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT); 4671 /* Disable C1E state if it is enabled by BIOS */ 4672 if ((reg >> AMD_ACTONCMPHALT_SHIFT) & 4673 AMD_ACTONCMPHALT_MASK) { 4674 reg &= ~(AMD_ACTONCMPHALT_MASK << 4675 AMD_ACTONCMPHALT_SHIFT); 4676 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg); 4677 } 4678 } 4679 no_trap(); 4680 } 4681 #endif /* !__xpv */ 4682 } 4683 4684 /* 4685 * Setup necessary registers to enable XSAVE feature on this processor. 4686 * This function needs to be called early enough, so that no xsave/xrstor 4687 * ops will execute on the processor before the MSRs are properly set up. 4688 * 4689 * Current implementation has the following assumption: 4690 * - cpuid_pass1() is done, so that X86 features are known. 4691 * - fpu_probe() is done, so that fp_save_mech is chosen. 4692 */ 4693 void 4694 xsave_setup_msr(cpu_t *cpu) 4695 { 4696 ASSERT(fp_save_mech == FP_XSAVE); 4697 ASSERT(is_x86_feature(x86_featureset, X86FSET_XSAVE)); 4698 4699 /* Enable OSXSAVE in CR4. */ 4700 setcr4(getcr4() | CR4_OSXSAVE); 4701 /* 4702 * Update SW copy of ECX, so that /dev/cpu/self/cpuid will report 4703 * correct value. 4704 */ 4705 cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_ecx |= CPUID_INTC_ECX_OSXSAVE; 4706 setup_xfem(); 4707 } 4708 4709 /* 4710 * Starting with the Westmere processor the local 4711 * APIC timer will continue running in all C-states, 4712 * including the deepest C-states. 4713 */ 4714 int 4715 cpuid_arat_supported(void) 4716 { 4717 struct cpuid_info *cpi; 4718 struct cpuid_regs regs; 4719 4720 ASSERT(cpuid_checkpass(CPU, 1)); 4721 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID)); 4722 4723 cpi = CPU->cpu_m.mcpu_cpi; 4724 4725 switch (cpi->cpi_vendor) { 4726 case X86_VENDOR_Intel: 4727 /* 4728 * Always-running Local APIC Timer is 4729 * indicated by CPUID.6.EAX[2]. 4730 */ 4731 if (cpi->cpi_maxeax >= 6) { 4732 regs.cp_eax = 6; 4733 (void) cpuid_insn(NULL, ®s); 4734 return (regs.cp_eax & CPUID_CSTATE_ARAT); 4735 } else { 4736 return (0); 4737 } 4738 default: 4739 return (0); 4740 } 4741 } 4742 4743 /* 4744 * Check support for Intel ENERGY_PERF_BIAS feature 4745 */ 4746 int 4747 cpuid_iepb_supported(struct cpu *cp) 4748 { 4749 struct cpuid_info *cpi = cp->cpu_m.mcpu_cpi; 4750 struct cpuid_regs regs; 4751 4752 ASSERT(cpuid_checkpass(cp, 1)); 4753 4754 if (!(is_x86_feature(x86_featureset, X86FSET_CPUID)) || 4755 !(is_x86_feature(x86_featureset, X86FSET_MSR))) { 4756 return (0); 4757 } 4758 4759 /* 4760 * Intel ENERGY_PERF_BIAS MSR is indicated by 4761 * capability bit CPUID.6.ECX.3 4762 */ 4763 if ((cpi->cpi_vendor != X86_VENDOR_Intel) || (cpi->cpi_maxeax < 6)) 4764 return (0); 4765 4766 regs.cp_eax = 0x6; 4767 (void) cpuid_insn(NULL, ®s); 4768 return (regs.cp_ecx & CPUID_EPB_SUPPORT); 4769 } 4770 4771 /* 4772 * Check support for TSC deadline timer 4773 * 4774 * TSC deadline timer provides a superior software programming 4775 * model over local APIC timer that eliminates "time drifts". 4776 * Instead of specifying a relative time, software specifies an 4777 * absolute time as the target at which the processor should 4778 * generate a timer event. 4779 */ 4780 int 4781 cpuid_deadline_tsc_supported(void) 4782 { 4783 struct cpuid_info *cpi = CPU->cpu_m.mcpu_cpi; 4784 struct cpuid_regs regs; 4785 4786 ASSERT(cpuid_checkpass(CPU, 1)); 4787 ASSERT(is_x86_feature(x86_featureset, X86FSET_CPUID)); 4788 4789 switch (cpi->cpi_vendor) { 4790 case X86_VENDOR_Intel: 4791 if (cpi->cpi_maxeax >= 1) { 4792 regs.cp_eax = 1; 4793 (void) cpuid_insn(NULL, ®s); 4794 return (regs.cp_ecx & CPUID_DEADLINE_TSC); 4795 } else { 4796 return (0); 4797 } 4798 default: 4799 return (0); 4800 } 4801 } 4802 4803 #if defined(__amd64) && !defined(__xpv) 4804 /* 4805 * Patch in versions of bcopy for high performance Intel Nhm processors 4806 * and later... 4807 */ 4808 void 4809 patch_memops(uint_t vendor) 4810 { 4811 size_t cnt, i; 4812 caddr_t to, from; 4813 4814 if ((vendor == X86_VENDOR_Intel) && 4815 is_x86_feature(x86_featureset, X86FSET_SSE4_2)) { 4816 cnt = &bcopy_patch_end - &bcopy_patch_start; 4817 to = &bcopy_ck_size; 4818 from = &bcopy_patch_start; 4819 for (i = 0; i < cnt; i++) { 4820 *to++ = *from++; 4821 } 4822 } 4823 } 4824 #endif /* __amd64 && !__xpv */ 4825 4826 /* 4827 * This function finds the number of bits to represent the number of cores per 4828 * chip and the number of strands per core for the Intel platforms. 4829 * It re-uses the x2APIC cpuid code of the cpuid_pass2(). 4830 */ 4831 void 4832 cpuid_get_ext_topo(uint_t vendor, uint_t *core_nbits, uint_t *strand_nbits) 4833 { 4834 struct cpuid_regs regs; 4835 struct cpuid_regs *cp = ®s; 4836 4837 if (vendor != X86_VENDOR_Intel) { 4838 return; 4839 } 4840 4841 /* if the cpuid level is 0xB, extended topo is available. */ 4842 cp->cp_eax = 0; 4843 if (__cpuid_insn(cp) >= 0xB) { 4844 4845 cp->cp_eax = 0xB; 4846 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; 4847 (void) __cpuid_insn(cp); 4848 4849 /* 4850 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which 4851 * indicates that the extended topology enumeration leaf is 4852 * available. 4853 */ 4854 if (cp->cp_ebx) { 4855 uint_t coreid_shift = 0; 4856 uint_t chipid_shift = 0; 4857 uint_t i; 4858 uint_t level; 4859 4860 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { 4861 cp->cp_eax = 0xB; 4862 cp->cp_ecx = i; 4863 4864 (void) __cpuid_insn(cp); 4865 level = CPI_CPU_LEVEL_TYPE(cp); 4866 4867 if (level == 1) { 4868 /* 4869 * Thread level processor topology 4870 * Number of bits shift right APIC ID 4871 * to get the coreid. 4872 */ 4873 coreid_shift = BITX(cp->cp_eax, 4, 0); 4874 } else if (level == 2) { 4875 /* 4876 * Core level processor topology 4877 * Number of bits shift right APIC ID 4878 * to get the chipid. 4879 */ 4880 chipid_shift = BITX(cp->cp_eax, 4, 0); 4881 } 4882 } 4883 4884 if (coreid_shift > 0 && chipid_shift > coreid_shift) { 4885 *strand_nbits = coreid_shift; 4886 *core_nbits = chipid_shift - coreid_shift; 4887 } 4888 } 4889 } 4890 } 4891