xref: /titanic_44/usr/src/uts/i86pc/os/cpuid.c (revision a1e4879402b1a0a7c410577cff81f1ce31ace7af)
1 /*
2  * CDDL HEADER START
3  *
4  * The contents of this file are subject to the terms of the
5  * Common Development and Distribution License (the "License").
6  * You may not use this file except in compliance with the License.
7  *
8  * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE
9  * or http://www.opensolaris.org/os/licensing.
10  * See the License for the specific language governing permissions
11  * and limitations under the License.
12  *
13  * When distributing Covered Code, include this CDDL HEADER in each
14  * file and include the License file at usr/src/OPENSOLARIS.LICENSE.
15  * If applicable, add the following below this CDDL HEADER, with the
16  * fields enclosed by brackets "[]" replaced with your own identifying
17  * information: Portions Copyright [yyyy] [name of copyright owner]
18  *
19  * CDDL HEADER END
20  */
21 /*
22  * Copyright 2007 Sun Microsystems, Inc.  All rights reserved.
23  * Use is subject to license terms.
24  */
25 
26 #pragma ident	"%Z%%M%	%I%	%E% SMI"
27 
28 /*
29  * Various routines to handle identification
30  * and classification of x86 processors.
31  */
32 
33 #include <sys/types.h>
34 #include <sys/archsystm.h>
35 #include <sys/x86_archext.h>
36 #include <sys/kmem.h>
37 #include <sys/systm.h>
38 #include <sys/cmn_err.h>
39 #include <sys/sunddi.h>
40 #include <sys/sunndi.h>
41 #include <sys/cpuvar.h>
42 #include <sys/processor.h>
43 #include <sys/pg.h>
44 #include <sys/fp.h>
45 #include <sys/controlregs.h>
46 #include <sys/auxv_386.h>
47 #include <sys/bitmap.h>
48 #include <sys/memnode.h>
49 
50 /*
51  * Pass 0 of cpuid feature analysis happens in locore. It contains special code
52  * to recognize Cyrix processors that are not cpuid-compliant, and to deal with
53  * them accordingly. For most modern processors, feature detection occurs here
54  * in pass 1.
55  *
56  * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup()
57  * for the boot CPU and does the basic analysis that the early kernel needs.
58  * x86_feature is set based on the return value of cpuid_pass1() of the boot
59  * CPU.
60  *
61  * Pass 1 includes:
62  *
63  *	o Determining vendor/model/family/stepping and setting x86_type and
64  *	  x86_vendor accordingly.
65  *	o Processing the feature flags returned by the cpuid instruction while
66  *	  applying any workarounds or tricks for the specific processor.
67  *	o Mapping the feature flags into Solaris feature bits (X86_*).
68  *	o Processing extended feature flags if supported by the processor,
69  *	  again while applying specific processor knowledge.
70  *	o Determining the CMT characteristics of the system.
71  *
72  * Pass 1 is done on non-boot CPUs during their initialization and the results
73  * are used only as a meager attempt at ensuring that all processors within the
74  * system support the same features.
75  *
76  * Pass 2 of cpuid feature analysis happens just at the beginning
77  * of startup().  It just copies in and corrects the remainder
78  * of the cpuid data we depend on: standard cpuid functions that we didn't
79  * need for pass1 feature analysis, and extended cpuid functions beyond the
80  * simple feature processing done in pass1.
81  *
82  * Pass 3 of cpuid analysis is invoked after basic kernel services; in
83  * particular kernel memory allocation has been made available. It creates a
84  * readable brand string based on the data collected in the first two passes.
85  *
86  * Pass 4 of cpuid analysis is invoked after post_startup() when all
87  * the support infrastructure for various hardware features has been
88  * initialized. It determines which processor features will be reported
89  * to userland via the aux vector.
90  *
91  * All passes are executed on all CPUs, but only the boot CPU determines what
92  * features the kernel will use.
93  *
94  * Much of the worst junk in this file is for the support of processors
95  * that didn't really implement the cpuid instruction properly.
96  *
97  * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon,
98  * the pass numbers.  Accordingly, changes to the pass code may require changes
99  * to the accessor code.
100  */
101 
102 uint_t x86_feature = 0;
103 uint_t x86_vendor = X86_VENDOR_IntelClone;
104 uint_t x86_type = X86_TYPE_OTHER;
105 
106 uint_t pentiumpro_bug4046376;
107 uint_t pentiumpro_bug4064495;
108 
109 uint_t enable486;
110 
111 /*
112  * This set of strings are for processors rumored to support the cpuid
113  * instruction, and is used by locore.s to figure out how to set x86_vendor
114  */
115 const char CyrixInstead[] = "CyrixInstead";
116 
117 /*
118  * These constants determine how many of the elements of the
119  * cpuid we cache in the cpuid_info data structure; the
120  * remaining elements are accessible via the cpuid instruction.
121  */
122 
123 #define	NMAX_CPI_STD	6		/* eax = 0 .. 5 */
124 #define	NMAX_CPI_EXTD	9		/* eax = 0x80000000 .. 0x80000008 */
125 
126 struct cpuid_info {
127 	uint_t cpi_pass;		/* last pass completed */
128 	/*
129 	 * standard function information
130 	 */
131 	uint_t cpi_maxeax;		/* fn 0: %eax */
132 	char cpi_vendorstr[13];		/* fn 0: %ebx:%ecx:%edx */
133 	uint_t cpi_vendor;		/* enum of cpi_vendorstr */
134 
135 	uint_t cpi_family;		/* fn 1: extended family */
136 	uint_t cpi_model;		/* fn 1: extended model */
137 	uint_t cpi_step;		/* fn 1: stepping */
138 	chipid_t cpi_chipid;		/* fn 1: %ebx: chip # on ht cpus */
139 	uint_t cpi_brandid;		/* fn 1: %ebx: brand ID */
140 	int cpi_clogid;			/* fn 1: %ebx: thread # */
141 	uint_t cpi_ncpu_per_chip;	/* fn 1: %ebx: logical cpu count */
142 	uint8_t cpi_cacheinfo[16];	/* fn 2: intel-style cache desc */
143 	uint_t cpi_ncache;		/* fn 2: number of elements */
144 	struct cpuid_regs cpi_std[NMAX_CPI_STD];	/* 0 .. 5 */
145 	/*
146 	 * extended function information
147 	 */
148 	uint_t cpi_xmaxeax;		/* fn 0x80000000: %eax */
149 	char cpi_brandstr[49];		/* fn 0x8000000[234] */
150 	uint8_t cpi_pabits;		/* fn 0x80000006: %eax */
151 	uint8_t cpi_vabits;		/* fn 0x80000006: %eax */
152 	struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */
153 	id_t cpi_coreid;
154 	uint_t cpi_ncore_per_chip;	/* AMD: fn 0x80000008: %ecx[7-0] */
155 					/* Intel: fn 4: %eax[31-26] */
156 	/*
157 	 * supported feature information
158 	 */
159 	uint32_t cpi_support[5];
160 #define	STD_EDX_FEATURES	0
161 #define	AMD_EDX_FEATURES	1
162 #define	TM_EDX_FEATURES		2
163 #define	STD_ECX_FEATURES	3
164 #define	AMD_ECX_FEATURES	4
165 	/*
166 	 * Synthesized information, where known.
167 	 */
168 	uint32_t cpi_chiprev;		/* See X86_CHIPREV_* in x86_archext.h */
169 	const char *cpi_chiprevstr;	/* May be NULL if chiprev unknown */
170 	uint32_t cpi_socket;		/* Chip package/socket type */
171 };
172 
173 
174 static struct cpuid_info cpuid_info0;
175 
176 /*
177  * These bit fields are defined by the Intel Application Note AP-485
178  * "Intel Processor Identification and the CPUID Instruction"
179  */
180 #define	CPI_FAMILY_XTD(cpi)	BITX((cpi)->cpi_std[1].cp_eax, 27, 20)
181 #define	CPI_MODEL_XTD(cpi)	BITX((cpi)->cpi_std[1].cp_eax, 19, 16)
182 #define	CPI_TYPE(cpi)		BITX((cpi)->cpi_std[1].cp_eax, 13, 12)
183 #define	CPI_FAMILY(cpi)		BITX((cpi)->cpi_std[1].cp_eax, 11, 8)
184 #define	CPI_STEP(cpi)		BITX((cpi)->cpi_std[1].cp_eax, 3, 0)
185 #define	CPI_MODEL(cpi)		BITX((cpi)->cpi_std[1].cp_eax, 7, 4)
186 
187 #define	CPI_FEATURES_EDX(cpi)		((cpi)->cpi_std[1].cp_edx)
188 #define	CPI_FEATURES_ECX(cpi)		((cpi)->cpi_std[1].cp_ecx)
189 #define	CPI_FEATURES_XTD_EDX(cpi)	((cpi)->cpi_extd[1].cp_edx)
190 #define	CPI_FEATURES_XTD_ECX(cpi)	((cpi)->cpi_extd[1].cp_ecx)
191 
192 #define	CPI_BRANDID(cpi)	BITX((cpi)->cpi_std[1].cp_ebx, 7, 0)
193 #define	CPI_CHUNKS(cpi)		BITX((cpi)->cpi_std[1].cp_ebx, 15, 7)
194 #define	CPI_CPU_COUNT(cpi)	BITX((cpi)->cpi_std[1].cp_ebx, 23, 16)
195 #define	CPI_APIC_ID(cpi)	BITX((cpi)->cpi_std[1].cp_ebx, 31, 24)
196 
197 #define	CPI_MAXEAX_MAX		0x100		/* sanity control */
198 #define	CPI_XMAXEAX_MAX		0x80000100
199 
200 /*
201  * A couple of shorthand macros to identify "later" P6-family chips
202  * like the Pentium M and Core.  First, the "older" P6-based stuff
203  * (loosely defined as "pre-Pentium-4"):
204  * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon
205  */
206 
207 #define	IS_LEGACY_P6(cpi) (			\
208 	cpi->cpi_family == 6 && 		\
209 		(cpi->cpi_model == 1 ||		\
210 		cpi->cpi_model == 3 ||		\
211 		cpi->cpi_model == 5 ||		\
212 		cpi->cpi_model == 6 ||		\
213 		cpi->cpi_model == 7 ||		\
214 		cpi->cpi_model == 8 ||		\
215 		cpi->cpi_model == 0xA ||	\
216 		cpi->cpi_model == 0xB)		\
217 )
218 
219 /* A "new F6" is everything with family 6 that's not the above */
220 #define	IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi))
221 
222 /*
223  * AMD family 0xf socket types.
224  * First index is 0 for revs B thru E, 1 for F and G.
225  * Second index by (model & 0x3)
226  */
227 static uint32_t amd_skts[2][4] = {
228 	{
229 		X86_SOCKET_754,		/* 0b00 */
230 		X86_SOCKET_940,		/* 0b01 */
231 		X86_SOCKET_754,		/* 0b10 */
232 		X86_SOCKET_939		/* 0b11 */
233 	},
234 	{
235 		X86_SOCKET_S1g1,	/* 0b00 */
236 		X86_SOCKET_F1207,	/* 0b01 */
237 		X86_SOCKET_UNKNOWN,	/* 0b10 */
238 		X86_SOCKET_AM2		/* 0b11 */
239 	}
240 };
241 
242 /*
243  * Table for mapping AMD Family 0xf model/stepping combination to
244  * chip "revision" and socket type.  Only rm_family 0xf is used at the
245  * moment, but AMD family 0x10 will extend the exsiting revision names
246  * so will likely also use this table.
247  *
248  * The first member of this array that matches a given family, extended model
249  * plus model range, and stepping range will be considered a match.
250  */
251 static const struct amd_rev_mapent {
252 	uint_t rm_family;
253 	uint_t rm_modello;
254 	uint_t rm_modelhi;
255 	uint_t rm_steplo;
256 	uint_t rm_stephi;
257 	uint32_t rm_chiprev;
258 	const char *rm_chiprevstr;
259 	int rm_sktidx;
260 } amd_revmap[] = {
261 	/*
262 	 * Rev B includes model 0x4 stepping 0 and model 0x5 stepping 0 and 1.
263 	 */
264 	{ 0xf, 0x04, 0x04, 0x0, 0x0, X86_CHIPREV_AMD_F_REV_B, "B", 0 },
265 	{ 0xf, 0x05, 0x05, 0x0, 0x1, X86_CHIPREV_AMD_F_REV_B, "B", 0 },
266 	/*
267 	 * Rev C0 includes model 0x4 stepping 8 and model 0x5 stepping 8
268 	 */
269 	{ 0xf, 0x04, 0x05, 0x8, 0x8, X86_CHIPREV_AMD_F_REV_C0, "C0", 0 },
270 	/*
271 	 * Rev CG is the rest of extended model 0x0 - i.e., everything
272 	 * but the rev B and C0 combinations covered above.
273 	 */
274 	{ 0xf, 0x00, 0x0f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_CG, "CG", 0 },
275 	/*
276 	 * Rev D has extended model 0x1.
277 	 */
278 	{ 0xf, 0x10, 0x1f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_D, "D", 0 },
279 	/*
280 	 * Rev E has extended model 0x2.
281 	 * Extended model 0x3 is unused but available to grow into.
282 	 */
283 	{ 0xf, 0x20, 0x3f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_E, "E", 0 },
284 	/*
285 	 * Rev F has extended models 0x4 and 0x5.
286 	 */
287 	{ 0xf, 0x40, 0x5f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_F, "F", 1 },
288 	/*
289 	 * Rev G has extended model 0x6.
290 	 */
291 	{ 0xf, 0x60, 0x6f, 0x0, 0xf, X86_CHIPREV_AMD_F_REV_G, "G", 1 },
292 };
293 
294 static void
295 synth_amd_info(struct cpuid_info *cpi)
296 {
297 	const struct amd_rev_mapent *rmp;
298 	uint_t family, model, step;
299 	int i;
300 
301 	/*
302 	 * Currently only AMD family 0xf uses these fields.
303 	 */
304 	if (cpi->cpi_family != 0xf)
305 		return;
306 
307 	family = cpi->cpi_family;
308 	model = cpi->cpi_model;
309 	step = cpi->cpi_step;
310 
311 	for (i = 0, rmp = amd_revmap; i < sizeof (amd_revmap) / sizeof (*rmp);
312 	    i++, rmp++) {
313 		if (family == rmp->rm_family &&
314 		    model >= rmp->rm_modello && model <= rmp->rm_modelhi &&
315 		    step >= rmp->rm_steplo && step <= rmp->rm_stephi) {
316 			cpi->cpi_chiprev = rmp->rm_chiprev;
317 			cpi->cpi_chiprevstr = rmp->rm_chiprevstr;
318 			cpi->cpi_socket = amd_skts[rmp->rm_sktidx][model & 0x3];
319 			return;
320 		}
321 	}
322 }
323 
324 static void
325 synth_info(struct cpuid_info *cpi)
326 {
327 	cpi->cpi_chiprev = X86_CHIPREV_UNKNOWN;
328 	cpi->cpi_chiprevstr = "Unknown";
329 	cpi->cpi_socket = X86_SOCKET_UNKNOWN;
330 
331 	switch (cpi->cpi_vendor) {
332 	case X86_VENDOR_AMD:
333 		synth_amd_info(cpi);
334 		break;
335 
336 	default:
337 		break;
338 
339 	}
340 }
341 
342 /*
343  * Apply up various platform-dependent restrictions where the
344  * underlying platform restrictions mean the CPU can be marked
345  * as less capable than its cpuid instruction would imply.
346  */
347 
348 #define	platform_cpuid_mangle(vendor, eax, cp)	/* nothing */
349 
350 /*
351  *  Some undocumented ways of patching the results of the cpuid
352  *  instruction to permit running Solaris 10 on future cpus that
353  *  we don't currently support.  Could be set to non-zero values
354  *  via settings in eeprom.
355  */
356 
357 uint32_t cpuid_feature_ecx_include;
358 uint32_t cpuid_feature_ecx_exclude;
359 uint32_t cpuid_feature_edx_include;
360 uint32_t cpuid_feature_edx_exclude;
361 
362 void
363 cpuid_alloc_space(cpu_t *cpu)
364 {
365 	/*
366 	 * By convention, cpu0 is the boot cpu, which is set up
367 	 * before memory allocation is available.  All other cpus get
368 	 * their cpuid_info struct allocated here.
369 	 */
370 	ASSERT(cpu->cpu_id != 0);
371 	cpu->cpu_m.mcpu_cpi =
372 	    kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP);
373 }
374 
375 void
376 cpuid_free_space(cpu_t *cpu)
377 {
378 	ASSERT(cpu->cpu_id != 0);
379 	kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi));
380 }
381 
382 uint_t
383 cpuid_pass1(cpu_t *cpu)
384 {
385 	uint32_t mask_ecx, mask_edx;
386 	uint_t feature = X86_CPUID;
387 	struct cpuid_info *cpi;
388 	struct cpuid_regs *cp;
389 	int xcpuid;
390 
391 
392 	/*
393 	 * Space statically allocated for cpu0, ensure pointer is set
394 	 */
395 	if (cpu->cpu_id == 0)
396 		cpu->cpu_m.mcpu_cpi = &cpuid_info0;
397 	cpi = cpu->cpu_m.mcpu_cpi;
398 	ASSERT(cpi != NULL);
399 	cp = &cpi->cpi_std[0];
400 	cp->cp_eax = 0;
401 	cpi->cpi_maxeax = __cpuid_insn(cp);
402 	{
403 		uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr;
404 		*iptr++ = cp->cp_ebx;
405 		*iptr++ = cp->cp_edx;
406 		*iptr++ = cp->cp_ecx;
407 		*(char *)&cpi->cpi_vendorstr[12] = '\0';
408 	}
409 
410 	/*
411 	 * Map the vendor string to a type code
412 	 */
413 	if (strcmp(cpi->cpi_vendorstr, "GenuineIntel") == 0)
414 		cpi->cpi_vendor = X86_VENDOR_Intel;
415 	else if (strcmp(cpi->cpi_vendorstr, "AuthenticAMD") == 0)
416 		cpi->cpi_vendor = X86_VENDOR_AMD;
417 	else if (strcmp(cpi->cpi_vendorstr, "GenuineTMx86") == 0)
418 		cpi->cpi_vendor = X86_VENDOR_TM;
419 	else if (strcmp(cpi->cpi_vendorstr, CyrixInstead) == 0)
420 		/*
421 		 * CyrixInstead is a variable used by the Cyrix detection code
422 		 * in locore.
423 		 */
424 		cpi->cpi_vendor = X86_VENDOR_Cyrix;
425 	else if (strcmp(cpi->cpi_vendorstr, "UMC UMC UMC ") == 0)
426 		cpi->cpi_vendor = X86_VENDOR_UMC;
427 	else if (strcmp(cpi->cpi_vendorstr, "NexGenDriven") == 0)
428 		cpi->cpi_vendor = X86_VENDOR_NexGen;
429 	else if (strcmp(cpi->cpi_vendorstr, "CentaurHauls") == 0)
430 		cpi->cpi_vendor = X86_VENDOR_Centaur;
431 	else if (strcmp(cpi->cpi_vendorstr, "RiseRiseRise") == 0)
432 		cpi->cpi_vendor = X86_VENDOR_Rise;
433 	else if (strcmp(cpi->cpi_vendorstr, "SiS SiS SiS ") == 0)
434 		cpi->cpi_vendor = X86_VENDOR_SiS;
435 	else if (strcmp(cpi->cpi_vendorstr, "Geode by NSC") == 0)
436 		cpi->cpi_vendor = X86_VENDOR_NSC;
437 	else
438 		cpi->cpi_vendor = X86_VENDOR_IntelClone;
439 
440 	x86_vendor = cpi->cpi_vendor; /* for compatibility */
441 
442 	/*
443 	 * Limit the range in case of weird hardware
444 	 */
445 	if (cpi->cpi_maxeax > CPI_MAXEAX_MAX)
446 		cpi->cpi_maxeax = CPI_MAXEAX_MAX;
447 	if (cpi->cpi_maxeax < 1)
448 		goto pass1_done;
449 
450 	cp = &cpi->cpi_std[1];
451 	cp->cp_eax = 1;
452 	(void) __cpuid_insn(cp);
453 
454 	/*
455 	 * Extract identifying constants for easy access.
456 	 */
457 	cpi->cpi_model = CPI_MODEL(cpi);
458 	cpi->cpi_family = CPI_FAMILY(cpi);
459 
460 	if (cpi->cpi_family == 0xf)
461 		cpi->cpi_family += CPI_FAMILY_XTD(cpi);
462 
463 	/*
464 	 * Beware: AMD uses "extended model" iff *FAMILY* == 0xf.
465 	 * Intel, and presumably everyone else, uses model == 0xf, as
466 	 * one would expect (max value means possible overflow).  Sigh.
467 	 */
468 
469 	switch (cpi->cpi_vendor) {
470 	case X86_VENDOR_AMD:
471 		if (cpi->cpi_family == 0xf)
472 			cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
473 		break;
474 	default:
475 		if (cpi->cpi_model == 0xf)
476 			cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4;
477 		break;
478 	}
479 
480 	cpi->cpi_step = CPI_STEP(cpi);
481 	cpi->cpi_brandid = CPI_BRANDID(cpi);
482 
483 	/*
484 	 * *default* assumptions:
485 	 * - believe %edx feature word
486 	 * - ignore %ecx feature word
487 	 * - 32-bit virtual and physical addressing
488 	 */
489 	mask_edx = 0xffffffff;
490 	mask_ecx = 0;
491 
492 	cpi->cpi_pabits = cpi->cpi_vabits = 32;
493 
494 	switch (cpi->cpi_vendor) {
495 	case X86_VENDOR_Intel:
496 		if (cpi->cpi_family == 5)
497 			x86_type = X86_TYPE_P5;
498 		else if (IS_LEGACY_P6(cpi)) {
499 			x86_type = X86_TYPE_P6;
500 			pentiumpro_bug4046376 = 1;
501 			pentiumpro_bug4064495 = 1;
502 			/*
503 			 * Clear the SEP bit when it was set erroneously
504 			 */
505 			if (cpi->cpi_model < 3 && cpi->cpi_step < 3)
506 				cp->cp_edx &= ~CPUID_INTC_EDX_SEP;
507 		} else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) {
508 			x86_type = X86_TYPE_P4;
509 			/*
510 			 * We don't currently depend on any of the %ecx
511 			 * features until Prescott, so we'll only check
512 			 * this from P4 onwards.  We might want to revisit
513 			 * that idea later.
514 			 */
515 			mask_ecx = 0xffffffff;
516 		} else if (cpi->cpi_family > 0xf)
517 			mask_ecx = 0xffffffff;
518 		break;
519 	case X86_VENDOR_IntelClone:
520 	default:
521 		break;
522 	case X86_VENDOR_AMD:
523 #if defined(OPTERON_ERRATUM_108)
524 		if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) {
525 			cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0;
526 			cpi->cpi_model = 0xc;
527 		} else
528 #endif
529 		if (cpi->cpi_family == 5) {
530 			/*
531 			 * AMD K5 and K6
532 			 *
533 			 * These CPUs have an incomplete implementation
534 			 * of MCA/MCE which we mask away.
535 			 */
536 			mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA);
537 
538 			/*
539 			 * Model 0 uses the wrong (APIC) bit
540 			 * to indicate PGE.  Fix it here.
541 			 */
542 			if (cpi->cpi_model == 0) {
543 				if (cp->cp_edx & 0x200) {
544 					cp->cp_edx &= ~0x200;
545 					cp->cp_edx |= CPUID_INTC_EDX_PGE;
546 				}
547 			}
548 
549 			/*
550 			 * Early models had problems w/ MMX; disable.
551 			 */
552 			if (cpi->cpi_model < 6)
553 				mask_edx &= ~CPUID_INTC_EDX_MMX;
554 		}
555 
556 		/*
557 		 * For newer families, SSE3 and CX16, at least, are valid;
558 		 * enable all
559 		 */
560 		if (cpi->cpi_family >= 0xf)
561 			mask_ecx = 0xffffffff;
562 		break;
563 	case X86_VENDOR_TM:
564 		/*
565 		 * workaround the NT workaround in CMS 4.1
566 		 */
567 		if (cpi->cpi_family == 5 && cpi->cpi_model == 4 &&
568 		    (cpi->cpi_step == 2 || cpi->cpi_step == 3))
569 			cp->cp_edx |= CPUID_INTC_EDX_CX8;
570 		break;
571 	case X86_VENDOR_Centaur:
572 		/*
573 		 * workaround the NT workarounds again
574 		 */
575 		if (cpi->cpi_family == 6)
576 			cp->cp_edx |= CPUID_INTC_EDX_CX8;
577 		break;
578 	case X86_VENDOR_Cyrix:
579 		/*
580 		 * We rely heavily on the probing in locore
581 		 * to actually figure out what parts, if any,
582 		 * of the Cyrix cpuid instruction to believe.
583 		 */
584 		switch (x86_type) {
585 		case X86_TYPE_CYRIX_486:
586 			mask_edx = 0;
587 			break;
588 		case X86_TYPE_CYRIX_6x86:
589 			mask_edx = 0;
590 			break;
591 		case X86_TYPE_CYRIX_6x86L:
592 			mask_edx =
593 			    CPUID_INTC_EDX_DE |
594 			    CPUID_INTC_EDX_CX8;
595 			break;
596 		case X86_TYPE_CYRIX_6x86MX:
597 			mask_edx =
598 			    CPUID_INTC_EDX_DE |
599 			    CPUID_INTC_EDX_MSR |
600 			    CPUID_INTC_EDX_CX8 |
601 			    CPUID_INTC_EDX_PGE |
602 			    CPUID_INTC_EDX_CMOV |
603 			    CPUID_INTC_EDX_MMX;
604 			break;
605 		case X86_TYPE_CYRIX_GXm:
606 			mask_edx =
607 			    CPUID_INTC_EDX_MSR |
608 			    CPUID_INTC_EDX_CX8 |
609 			    CPUID_INTC_EDX_CMOV |
610 			    CPUID_INTC_EDX_MMX;
611 			break;
612 		case X86_TYPE_CYRIX_MediaGX:
613 			break;
614 		case X86_TYPE_CYRIX_MII:
615 		case X86_TYPE_VIA_CYRIX_III:
616 			mask_edx =
617 			    CPUID_INTC_EDX_DE |
618 			    CPUID_INTC_EDX_TSC |
619 			    CPUID_INTC_EDX_MSR |
620 			    CPUID_INTC_EDX_CX8 |
621 			    CPUID_INTC_EDX_PGE |
622 			    CPUID_INTC_EDX_CMOV |
623 			    CPUID_INTC_EDX_MMX;
624 			break;
625 		default:
626 			break;
627 		}
628 		break;
629 	}
630 
631 	/*
632 	 * Now we've figured out the masks that determine
633 	 * which bits we choose to believe, apply the masks
634 	 * to the feature words, then map the kernel's view
635 	 * of these feature words into its feature word.
636 	 */
637 	cp->cp_edx &= mask_edx;
638 	cp->cp_ecx &= mask_ecx;
639 
640 	/*
641 	 * apply any platform restrictions (we don't call this
642 	 * immediately after __cpuid_insn here, because we need the
643 	 * workarounds applied above first)
644 	 */
645 	platform_cpuid_mangle(cpi->cpi_vendor, 1, cp);
646 
647 	/*
648 	 * fold in overrides from the "eeprom" mechanism
649 	 */
650 	cp->cp_edx |= cpuid_feature_edx_include;
651 	cp->cp_edx &= ~cpuid_feature_edx_exclude;
652 
653 	cp->cp_ecx |= cpuid_feature_ecx_include;
654 	cp->cp_ecx &= ~cpuid_feature_ecx_exclude;
655 
656 	if (cp->cp_edx & CPUID_INTC_EDX_PSE)
657 		feature |= X86_LARGEPAGE;
658 	if (cp->cp_edx & CPUID_INTC_EDX_TSC)
659 		feature |= X86_TSC;
660 	if (cp->cp_edx & CPUID_INTC_EDX_MSR)
661 		feature |= X86_MSR;
662 	if (cp->cp_edx & CPUID_INTC_EDX_MTRR)
663 		feature |= X86_MTRR;
664 	if (cp->cp_edx & CPUID_INTC_EDX_PGE)
665 		feature |= X86_PGE;
666 	if (cp->cp_edx & CPUID_INTC_EDX_CMOV)
667 		feature |= X86_CMOV;
668 	if (cp->cp_edx & CPUID_INTC_EDX_MMX)
669 		feature |= X86_MMX;
670 	if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 &&
671 	    (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0)
672 		feature |= X86_MCA;
673 	if (cp->cp_edx & CPUID_INTC_EDX_PAE)
674 		feature |= X86_PAE;
675 	if (cp->cp_edx & CPUID_INTC_EDX_CX8)
676 		feature |= X86_CX8;
677 	if (cp->cp_ecx & CPUID_INTC_ECX_CX16)
678 		feature |= X86_CX16;
679 	if (cp->cp_edx & CPUID_INTC_EDX_PAT)
680 		feature |= X86_PAT;
681 	if (cp->cp_edx & CPUID_INTC_EDX_SEP)
682 		feature |= X86_SEP;
683 	if (cp->cp_edx & CPUID_INTC_EDX_FXSR) {
684 		/*
685 		 * In our implementation, fxsave/fxrstor
686 		 * are prerequisites before we'll even
687 		 * try and do SSE things.
688 		 */
689 		if (cp->cp_edx & CPUID_INTC_EDX_SSE)
690 			feature |= X86_SSE;
691 		if (cp->cp_edx & CPUID_INTC_EDX_SSE2)
692 			feature |= X86_SSE2;
693 		if (cp->cp_ecx & CPUID_INTC_ECX_SSE3)
694 			feature |= X86_SSE3;
695 	}
696 	if (cp->cp_edx & CPUID_INTC_EDX_DE)
697 		feature |= X86_DE;
698 
699 	if (feature & X86_PAE)
700 		cpi->cpi_pabits = 36;
701 
702 	/*
703 	 * Hyperthreading configuration is slightly tricky on Intel
704 	 * and pure clones, and even trickier on AMD.
705 	 *
706 	 * (AMD chose to set the HTT bit on their CMP processors,
707 	 * even though they're not actually hyperthreaded.  Thus it
708 	 * takes a bit more work to figure out what's really going
709 	 * on ... see the handling of the CMP_LGCY bit below)
710 	 */
711 	if (cp->cp_edx & CPUID_INTC_EDX_HTT) {
712 		cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi);
713 		if (cpi->cpi_ncpu_per_chip > 1)
714 			feature |= X86_HTT;
715 	} else {
716 		cpi->cpi_ncpu_per_chip = 1;
717 	}
718 
719 	/*
720 	 * Work on the "extended" feature information, doing
721 	 * some basic initialization for cpuid_pass2()
722 	 */
723 	xcpuid = 0;
724 	switch (cpi->cpi_vendor) {
725 	case X86_VENDOR_Intel:
726 		if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf)
727 			xcpuid++;
728 		break;
729 	case X86_VENDOR_AMD:
730 		if (cpi->cpi_family > 5 ||
731 		    (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
732 			xcpuid++;
733 		break;
734 	case X86_VENDOR_Cyrix:
735 		/*
736 		 * Only these Cyrix CPUs are -known- to support
737 		 * extended cpuid operations.
738 		 */
739 		if (x86_type == X86_TYPE_VIA_CYRIX_III ||
740 		    x86_type == X86_TYPE_CYRIX_GXm)
741 			xcpuid++;
742 		break;
743 	case X86_VENDOR_Centaur:
744 	case X86_VENDOR_TM:
745 	default:
746 		xcpuid++;
747 		break;
748 	}
749 
750 	if (xcpuid) {
751 		cp = &cpi->cpi_extd[0];
752 		cp->cp_eax = 0x80000000;
753 		cpi->cpi_xmaxeax = __cpuid_insn(cp);
754 	}
755 
756 	if (cpi->cpi_xmaxeax & 0x80000000) {
757 
758 		if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX)
759 			cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX;
760 
761 		switch (cpi->cpi_vendor) {
762 		case X86_VENDOR_Intel:
763 		case X86_VENDOR_AMD:
764 			if (cpi->cpi_xmaxeax < 0x80000001)
765 				break;
766 			cp = &cpi->cpi_extd[1];
767 			cp->cp_eax = 0x80000001;
768 			(void) __cpuid_insn(cp);
769 
770 			if (cpi->cpi_vendor == X86_VENDOR_AMD &&
771 			    cpi->cpi_family == 5 &&
772 			    cpi->cpi_model == 6 &&
773 			    cpi->cpi_step == 6) {
774 				/*
775 				 * K6 model 6 uses bit 10 to indicate SYSC
776 				 * Later models use bit 11. Fix it here.
777 				 */
778 				if (cp->cp_edx & 0x400) {
779 					cp->cp_edx &= ~0x400;
780 					cp->cp_edx |= CPUID_AMD_EDX_SYSC;
781 				}
782 			}
783 
784 			platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp);
785 
786 			/*
787 			 * Compute the additions to the kernel's feature word.
788 			 */
789 			if (cp->cp_edx & CPUID_AMD_EDX_NX)
790 				feature |= X86_NX;
791 
792 			/*
793 			 * If both the HTT and CMP_LGCY bits are set,
794 			 * then we're not actually HyperThreaded.  Read
795 			 * "AMD CPUID Specification" for more details.
796 			 */
797 			if (cpi->cpi_vendor == X86_VENDOR_AMD &&
798 			    (feature & X86_HTT) &&
799 			    (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) {
800 				feature &= ~X86_HTT;
801 				feature |= X86_CMP;
802 			}
803 #if defined(__amd64)
804 			/*
805 			 * It's really tricky to support syscall/sysret in
806 			 * the i386 kernel; we rely on sysenter/sysexit
807 			 * instead.  In the amd64 kernel, things are -way-
808 			 * better.
809 			 */
810 			if (cp->cp_edx & CPUID_AMD_EDX_SYSC)
811 				feature |= X86_ASYSC;
812 
813 			/*
814 			 * While we're thinking about system calls, note
815 			 * that AMD processors don't support sysenter
816 			 * in long mode at all, so don't try to program them.
817 			 */
818 			if (x86_vendor == X86_VENDOR_AMD)
819 				feature &= ~X86_SEP;
820 #endif
821 			if (cp->cp_edx & CPUID_AMD_EDX_TSCP)
822 				feature |= X86_TSCP;
823 			break;
824 		default:
825 			break;
826 		}
827 
828 		/*
829 		 * Get CPUID data about processor cores and hyperthreads.
830 		 */
831 		switch (cpi->cpi_vendor) {
832 		case X86_VENDOR_Intel:
833 			if (cpi->cpi_maxeax >= 4) {
834 				cp = &cpi->cpi_std[4];
835 				cp->cp_eax = 4;
836 				cp->cp_ecx = 0;
837 				(void) __cpuid_insn(cp);
838 				platform_cpuid_mangle(cpi->cpi_vendor, 4, cp);
839 			}
840 			/*FALLTHROUGH*/
841 		case X86_VENDOR_AMD:
842 			if (cpi->cpi_xmaxeax < 0x80000008)
843 				break;
844 			cp = &cpi->cpi_extd[8];
845 			cp->cp_eax = 0x80000008;
846 			(void) __cpuid_insn(cp);
847 			platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp);
848 
849 			/*
850 			 * Virtual and physical address limits from
851 			 * cpuid override previously guessed values.
852 			 */
853 			cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0);
854 			cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8);
855 			break;
856 		default:
857 			break;
858 		}
859 
860 		switch (cpi->cpi_vendor) {
861 		case X86_VENDOR_Intel:
862 			if (cpi->cpi_maxeax < 4) {
863 				cpi->cpi_ncore_per_chip = 1;
864 				break;
865 			} else {
866 				cpi->cpi_ncore_per_chip =
867 				    BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1;
868 			}
869 			break;
870 		case X86_VENDOR_AMD:
871 			if (cpi->cpi_xmaxeax < 0x80000008) {
872 				cpi->cpi_ncore_per_chip = 1;
873 				break;
874 			} else {
875 				cpi->cpi_ncore_per_chip =
876 				    BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1;
877 			}
878 			break;
879 		default:
880 			cpi->cpi_ncore_per_chip = 1;
881 			break;
882 		}
883 	}
884 
885 	/*
886 	 * If more than one core, then this processor is CMP.
887 	 */
888 	if (cpi->cpi_ncore_per_chip > 1)
889 		feature |= X86_CMP;
890 
891 	/*
892 	 * If the number of cores is the same as the number
893 	 * of CPUs, then we cannot have HyperThreading.
894 	 */
895 	if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip)
896 		feature &= ~X86_HTT;
897 
898 	if ((feature & (X86_HTT | X86_CMP)) == 0) {
899 		/*
900 		 * Single-core single-threaded processors.
901 		 */
902 		cpi->cpi_chipid = -1;
903 		cpi->cpi_clogid = 0;
904 		cpi->cpi_coreid = cpu->cpu_id;
905 	} else if (cpi->cpi_ncpu_per_chip > 1) {
906 		uint_t i;
907 		uint_t chipid_shift = 0;
908 		uint_t coreid_shift = 0;
909 		uint_t apic_id = CPI_APIC_ID(cpi);
910 
911 		for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1)
912 			chipid_shift++;
913 		cpi->cpi_chipid = apic_id >> chipid_shift;
914 		cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1);
915 
916 		if (cpi->cpi_vendor == X86_VENDOR_Intel) {
917 			if (feature & X86_CMP) {
918 				/*
919 				 * Multi-core (and possibly multi-threaded)
920 				 * processors.
921 				 */
922 				uint_t ncpu_per_core;
923 				if (cpi->cpi_ncore_per_chip == 1)
924 					ncpu_per_core = cpi->cpi_ncpu_per_chip;
925 				else if (cpi->cpi_ncore_per_chip > 1)
926 					ncpu_per_core = cpi->cpi_ncpu_per_chip /
927 					    cpi->cpi_ncore_per_chip;
928 				/*
929 				 * 8bit APIC IDs on dual core Pentiums
930 				 * look like this:
931 				 *
932 				 * +-----------------------+------+------+
933 				 * | Physical Package ID   |  MC  |  HT  |
934 				 * +-----------------------+------+------+
935 				 * <------- chipid -------->
936 				 * <------- coreid --------------->
937 				 *			   <--- clogid -->
938 				 *
939 				 * Where the number of bits necessary to
940 				 * represent MC and HT fields together equals
941 				 * to the minimum number of bits necessary to
942 				 * store the value of cpi->cpi_ncpu_per_chip.
943 				 * Of those bits, the MC part uses the number
944 				 * of bits necessary to store the value of
945 				 * cpi->cpi_ncore_per_chip.
946 				 */
947 				for (i = 1; i < ncpu_per_core; i <<= 1)
948 					coreid_shift++;
949 				cpi->cpi_coreid = apic_id >> coreid_shift;
950 			} else if (feature & X86_HTT) {
951 				/*
952 				 * Single-core multi-threaded processors.
953 				 */
954 				cpi->cpi_coreid = cpi->cpi_chipid;
955 			}
956 		} else if (cpi->cpi_vendor == X86_VENDOR_AMD) {
957 			/*
958 			 * AMD currently only has dual-core processors with
959 			 * single-threaded cores.  If they ever release
960 			 * multi-threaded processors, then this code
961 			 * will have to be updated.
962 			 */
963 			cpi->cpi_coreid = cpu->cpu_id;
964 		} else {
965 			/*
966 			 * All other processors are currently
967 			 * assumed to have single cores.
968 			 */
969 			cpi->cpi_coreid = cpi->cpi_chipid;
970 		}
971 	}
972 
973 	/*
974 	 * Synthesize chip "revision" and socket type
975 	 */
976 	synth_info(cpi);
977 
978 pass1_done:
979 	cpi->cpi_pass = 1;
980 	return (feature);
981 }
982 
983 /*
984  * Make copies of the cpuid table entries we depend on, in
985  * part for ease of parsing now, in part so that we have only
986  * one place to correct any of it, in part for ease of
987  * later export to userland, and in part so we can look at
988  * this stuff in a crash dump.
989  */
990 
991 /*ARGSUSED*/
992 void
993 cpuid_pass2(cpu_t *cpu)
994 {
995 	uint_t n, nmax;
996 	int i;
997 	struct cpuid_regs *cp;
998 	uint8_t *dp;
999 	uint32_t *iptr;
1000 	struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1001 
1002 	ASSERT(cpi->cpi_pass == 1);
1003 
1004 	if (cpi->cpi_maxeax < 1)
1005 		goto pass2_done;
1006 
1007 	if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD)
1008 		nmax = NMAX_CPI_STD;
1009 	/*
1010 	 * (We already handled n == 0 and n == 1 in pass 1)
1011 	 */
1012 	for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) {
1013 		cp->cp_eax = n;
1014 		(void) __cpuid_insn(cp);
1015 		platform_cpuid_mangle(cpi->cpi_vendor, n, cp);
1016 		switch (n) {
1017 		case 2:
1018 			/*
1019 			 * "the lower 8 bits of the %eax register
1020 			 * contain a value that identifies the number
1021 			 * of times the cpuid [instruction] has to be
1022 			 * executed to obtain a complete image of the
1023 			 * processor's caching systems."
1024 			 *
1025 			 * How *do* they make this stuff up?
1026 			 */
1027 			cpi->cpi_ncache = sizeof (*cp) *
1028 			    BITX(cp->cp_eax, 7, 0);
1029 			if (cpi->cpi_ncache == 0)
1030 				break;
1031 			cpi->cpi_ncache--;	/* skip count byte */
1032 
1033 			/*
1034 			 * Well, for now, rather than attempt to implement
1035 			 * this slightly dubious algorithm, we just look
1036 			 * at the first 15 ..
1037 			 */
1038 			if (cpi->cpi_ncache > (sizeof (*cp) - 1))
1039 				cpi->cpi_ncache = sizeof (*cp) - 1;
1040 
1041 			dp = cpi->cpi_cacheinfo;
1042 			if (BITX(cp->cp_eax, 31, 31) == 0) {
1043 				uint8_t *p = (void *)&cp->cp_eax;
1044 				for (i = 1; i < 3; i++)
1045 					if (p[i] != 0)
1046 						*dp++ = p[i];
1047 			}
1048 			if (BITX(cp->cp_ebx, 31, 31) == 0) {
1049 				uint8_t *p = (void *)&cp->cp_ebx;
1050 				for (i = 0; i < 4; i++)
1051 					if (p[i] != 0)
1052 						*dp++ = p[i];
1053 			}
1054 			if (BITX(cp->cp_ecx, 31, 31) == 0) {
1055 				uint8_t *p = (void *)&cp->cp_ecx;
1056 				for (i = 0; i < 4; i++)
1057 					if (p[i] != 0)
1058 						*dp++ = p[i];
1059 			}
1060 			if (BITX(cp->cp_edx, 31, 31) == 0) {
1061 				uint8_t *p = (void *)&cp->cp_edx;
1062 				for (i = 0; i < 4; i++)
1063 					if (p[i] != 0)
1064 						*dp++ = p[i];
1065 			}
1066 			break;
1067 		case 3:	/* Processor serial number, if PSN supported */
1068 		case 4:	/* Deterministic cache parameters */
1069 		case 5:	/* Monitor/Mwait parameters */
1070 		default:
1071 			break;
1072 		}
1073 	}
1074 
1075 	if ((cpi->cpi_xmaxeax & 0x80000000) == 0)
1076 		goto pass2_done;
1077 
1078 	if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD)
1079 		nmax = NMAX_CPI_EXTD;
1080 	/*
1081 	 * Copy the extended properties, fixing them as we go.
1082 	 * (We already handled n == 0 and n == 1 in pass 1)
1083 	 */
1084 	iptr = (void *)cpi->cpi_brandstr;
1085 	for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) {
1086 		cp->cp_eax = 0x80000000 + n;
1087 		(void) __cpuid_insn(cp);
1088 		platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp);
1089 		switch (n) {
1090 		case 2:
1091 		case 3:
1092 		case 4:
1093 			/*
1094 			 * Extract the brand string
1095 			 */
1096 			*iptr++ = cp->cp_eax;
1097 			*iptr++ = cp->cp_ebx;
1098 			*iptr++ = cp->cp_ecx;
1099 			*iptr++ = cp->cp_edx;
1100 			break;
1101 		case 5:
1102 			switch (cpi->cpi_vendor) {
1103 			case X86_VENDOR_AMD:
1104 				/*
1105 				 * The Athlon and Duron were the first
1106 				 * parts to report the sizes of the
1107 				 * TLB for large pages. Before then,
1108 				 * we don't trust the data.
1109 				 */
1110 				if (cpi->cpi_family < 6 ||
1111 				    (cpi->cpi_family == 6 &&
1112 				    cpi->cpi_model < 1))
1113 					cp->cp_eax = 0;
1114 				break;
1115 			default:
1116 				break;
1117 			}
1118 			break;
1119 		case 6:
1120 			switch (cpi->cpi_vendor) {
1121 			case X86_VENDOR_AMD:
1122 				/*
1123 				 * The Athlon and Duron were the first
1124 				 * AMD parts with L2 TLB's.
1125 				 * Before then, don't trust the data.
1126 				 */
1127 				if (cpi->cpi_family < 6 ||
1128 				    cpi->cpi_family == 6 &&
1129 				    cpi->cpi_model < 1)
1130 					cp->cp_eax = cp->cp_ebx = 0;
1131 				/*
1132 				 * AMD Duron rev A0 reports L2
1133 				 * cache size incorrectly as 1K
1134 				 * when it is really 64K
1135 				 */
1136 				if (cpi->cpi_family == 6 &&
1137 				    cpi->cpi_model == 3 &&
1138 				    cpi->cpi_step == 0) {
1139 					cp->cp_ecx &= 0xffff;
1140 					cp->cp_ecx |= 0x400000;
1141 				}
1142 				break;
1143 			case X86_VENDOR_Cyrix:	/* VIA C3 */
1144 				/*
1145 				 * VIA C3 processors are a bit messed
1146 				 * up w.r.t. encoding cache sizes in %ecx
1147 				 */
1148 				if (cpi->cpi_family != 6)
1149 					break;
1150 				/*
1151 				 * model 7 and 8 were incorrectly encoded
1152 				 *
1153 				 * xxx is model 8 really broken?
1154 				 */
1155 				if (cpi->cpi_model == 7 ||
1156 				    cpi->cpi_model == 8)
1157 					cp->cp_ecx =
1158 					    BITX(cp->cp_ecx, 31, 24) << 16 |
1159 					    BITX(cp->cp_ecx, 23, 16) << 12 |
1160 					    BITX(cp->cp_ecx, 15, 8) << 8 |
1161 					    BITX(cp->cp_ecx, 7, 0);
1162 				/*
1163 				 * model 9 stepping 1 has wrong associativity
1164 				 */
1165 				if (cpi->cpi_model == 9 && cpi->cpi_step == 1)
1166 					cp->cp_ecx |= 8 << 12;
1167 				break;
1168 			case X86_VENDOR_Intel:
1169 				/*
1170 				 * Extended L2 Cache features function.
1171 				 * First appeared on Prescott.
1172 				 */
1173 			default:
1174 				break;
1175 			}
1176 			break;
1177 		default:
1178 			break;
1179 		}
1180 	}
1181 
1182 pass2_done:
1183 	cpi->cpi_pass = 2;
1184 }
1185 
1186 static const char *
1187 intel_cpubrand(const struct cpuid_info *cpi)
1188 {
1189 	int i;
1190 
1191 	if ((x86_feature & X86_CPUID) == 0 ||
1192 	    cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
1193 		return ("i486");
1194 
1195 	switch (cpi->cpi_family) {
1196 	case 5:
1197 		return ("Intel Pentium(r)");
1198 	case 6:
1199 		switch (cpi->cpi_model) {
1200 			uint_t celeron, xeon;
1201 			const struct cpuid_regs *cp;
1202 		case 0:
1203 		case 1:
1204 		case 2:
1205 			return ("Intel Pentium(r) Pro");
1206 		case 3:
1207 		case 4:
1208 			return ("Intel Pentium(r) II");
1209 		case 6:
1210 			return ("Intel Celeron(r)");
1211 		case 5:
1212 		case 7:
1213 			celeron = xeon = 0;
1214 			cp = &cpi->cpi_std[2];	/* cache info */
1215 
1216 			for (i = 1; i < 3; i++) {
1217 				uint_t tmp;
1218 
1219 				tmp = (cp->cp_eax >> (8 * i)) & 0xff;
1220 				if (tmp == 0x40)
1221 					celeron++;
1222 				if (tmp >= 0x44 && tmp <= 0x45)
1223 					xeon++;
1224 			}
1225 
1226 			for (i = 0; i < 2; i++) {
1227 				uint_t tmp;
1228 
1229 				tmp = (cp->cp_ebx >> (8 * i)) & 0xff;
1230 				if (tmp == 0x40)
1231 					celeron++;
1232 				else if (tmp >= 0x44 && tmp <= 0x45)
1233 					xeon++;
1234 			}
1235 
1236 			for (i = 0; i < 4; i++) {
1237 				uint_t tmp;
1238 
1239 				tmp = (cp->cp_ecx >> (8 * i)) & 0xff;
1240 				if (tmp == 0x40)
1241 					celeron++;
1242 				else if (tmp >= 0x44 && tmp <= 0x45)
1243 					xeon++;
1244 			}
1245 
1246 			for (i = 0; i < 4; i++) {
1247 				uint_t tmp;
1248 
1249 				tmp = (cp->cp_edx >> (8 * i)) & 0xff;
1250 				if (tmp == 0x40)
1251 					celeron++;
1252 				else if (tmp >= 0x44 && tmp <= 0x45)
1253 					xeon++;
1254 			}
1255 
1256 			if (celeron)
1257 				return ("Intel Celeron(r)");
1258 			if (xeon)
1259 				return (cpi->cpi_model == 5 ?
1260 				    "Intel Pentium(r) II Xeon(tm)" :
1261 				    "Intel Pentium(r) III Xeon(tm)");
1262 			return (cpi->cpi_model == 5 ?
1263 			    "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" :
1264 			    "Intel Pentium(r) III or Pentium(r) III Xeon(tm)");
1265 		default:
1266 			break;
1267 		}
1268 	default:
1269 		break;
1270 	}
1271 
1272 	/* BrandID is present if the field is nonzero */
1273 	if (cpi->cpi_brandid != 0) {
1274 		static const struct {
1275 			uint_t bt_bid;
1276 			const char *bt_str;
1277 		} brand_tbl[] = {
1278 			{ 0x1,	"Intel(r) Celeron(r)" },
1279 			{ 0x2,	"Intel(r) Pentium(r) III" },
1280 			{ 0x3,	"Intel(r) Pentium(r) III Xeon(tm)" },
1281 			{ 0x4,	"Intel(r) Pentium(r) III" },
1282 			{ 0x6,	"Mobile Intel(r) Pentium(r) III" },
1283 			{ 0x7,	"Mobile Intel(r) Celeron(r)" },
1284 			{ 0x8,	"Intel(r) Pentium(r) 4" },
1285 			{ 0x9,	"Intel(r) Pentium(r) 4" },
1286 			{ 0xa,	"Intel(r) Celeron(r)" },
1287 			{ 0xb,	"Intel(r) Xeon(tm)" },
1288 			{ 0xc,	"Intel(r) Xeon(tm) MP" },
1289 			{ 0xe,	"Mobile Intel(r) Pentium(r) 4" },
1290 			{ 0xf,	"Mobile Intel(r) Celeron(r)" },
1291 			{ 0x11, "Mobile Genuine Intel(r)" },
1292 			{ 0x12, "Intel(r) Celeron(r) M" },
1293 			{ 0x13, "Mobile Intel(r) Celeron(r)" },
1294 			{ 0x14, "Intel(r) Celeron(r)" },
1295 			{ 0x15, "Mobile Genuine Intel(r)" },
1296 			{ 0x16,	"Intel(r) Pentium(r) M" },
1297 			{ 0x17, "Mobile Intel(r) Celeron(r)" }
1298 		};
1299 		uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]);
1300 		uint_t sgn;
1301 
1302 		sgn = (cpi->cpi_family << 8) |
1303 		    (cpi->cpi_model << 4) | cpi->cpi_step;
1304 
1305 		for (i = 0; i < btblmax; i++)
1306 			if (brand_tbl[i].bt_bid == cpi->cpi_brandid)
1307 				break;
1308 		if (i < btblmax) {
1309 			if (sgn == 0x6b1 && cpi->cpi_brandid == 3)
1310 				return ("Intel(r) Celeron(r)");
1311 			if (sgn < 0xf13 && cpi->cpi_brandid == 0xb)
1312 				return ("Intel(r) Xeon(tm) MP");
1313 			if (sgn < 0xf13 && cpi->cpi_brandid == 0xe)
1314 				return ("Intel(r) Xeon(tm)");
1315 			return (brand_tbl[i].bt_str);
1316 		}
1317 	}
1318 
1319 	return (NULL);
1320 }
1321 
1322 static const char *
1323 amd_cpubrand(const struct cpuid_info *cpi)
1324 {
1325 	if ((x86_feature & X86_CPUID) == 0 ||
1326 	    cpi->cpi_maxeax < 1 || cpi->cpi_family < 5)
1327 		return ("i486 compatible");
1328 
1329 	switch (cpi->cpi_family) {
1330 	case 5:
1331 		switch (cpi->cpi_model) {
1332 		case 0:
1333 		case 1:
1334 		case 2:
1335 		case 3:
1336 		case 4:
1337 		case 5:
1338 			return ("AMD-K5(r)");
1339 		case 6:
1340 		case 7:
1341 			return ("AMD-K6(r)");
1342 		case 8:
1343 			return ("AMD-K6(r)-2");
1344 		case 9:
1345 			return ("AMD-K6(r)-III");
1346 		default:
1347 			return ("AMD (family 5)");
1348 		}
1349 	case 6:
1350 		switch (cpi->cpi_model) {
1351 		case 1:
1352 			return ("AMD-K7(tm)");
1353 		case 0:
1354 		case 2:
1355 		case 4:
1356 			return ("AMD Athlon(tm)");
1357 		case 3:
1358 		case 7:
1359 			return ("AMD Duron(tm)");
1360 		case 6:
1361 		case 8:
1362 		case 10:
1363 			/*
1364 			 * Use the L2 cache size to distinguish
1365 			 */
1366 			return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ?
1367 			    "AMD Athlon(tm)" : "AMD Duron(tm)");
1368 		default:
1369 			return ("AMD (family 6)");
1370 		}
1371 	default:
1372 		break;
1373 	}
1374 
1375 	if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 &&
1376 	    cpi->cpi_brandid != 0) {
1377 		switch (BITX(cpi->cpi_brandid, 7, 5)) {
1378 		case 3:
1379 			return ("AMD Opteron(tm) UP 1xx");
1380 		case 4:
1381 			return ("AMD Opteron(tm) DP 2xx");
1382 		case 5:
1383 			return ("AMD Opteron(tm) MP 8xx");
1384 		default:
1385 			return ("AMD Opteron(tm)");
1386 		}
1387 	}
1388 
1389 	return (NULL);
1390 }
1391 
1392 static const char *
1393 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type)
1394 {
1395 	if ((x86_feature & X86_CPUID) == 0 ||
1396 	    cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 ||
1397 	    type == X86_TYPE_CYRIX_486)
1398 		return ("i486 compatible");
1399 
1400 	switch (type) {
1401 	case X86_TYPE_CYRIX_6x86:
1402 		return ("Cyrix 6x86");
1403 	case X86_TYPE_CYRIX_6x86L:
1404 		return ("Cyrix 6x86L");
1405 	case X86_TYPE_CYRIX_6x86MX:
1406 		return ("Cyrix 6x86MX");
1407 	case X86_TYPE_CYRIX_GXm:
1408 		return ("Cyrix GXm");
1409 	case X86_TYPE_CYRIX_MediaGX:
1410 		return ("Cyrix MediaGX");
1411 	case X86_TYPE_CYRIX_MII:
1412 		return ("Cyrix M2");
1413 	case X86_TYPE_VIA_CYRIX_III:
1414 		return ("VIA Cyrix M3");
1415 	default:
1416 		/*
1417 		 * Have another wild guess ..
1418 		 */
1419 		if (cpi->cpi_family == 4 && cpi->cpi_model == 9)
1420 			return ("Cyrix 5x86");
1421 		else if (cpi->cpi_family == 5) {
1422 			switch (cpi->cpi_model) {
1423 			case 2:
1424 				return ("Cyrix 6x86");	/* Cyrix M1 */
1425 			case 4:
1426 				return ("Cyrix MediaGX");
1427 			default:
1428 				break;
1429 			}
1430 		} else if (cpi->cpi_family == 6) {
1431 			switch (cpi->cpi_model) {
1432 			case 0:
1433 				return ("Cyrix 6x86MX"); /* Cyrix M2? */
1434 			case 5:
1435 			case 6:
1436 			case 7:
1437 			case 8:
1438 			case 9:
1439 				return ("VIA C3");
1440 			default:
1441 				break;
1442 			}
1443 		}
1444 		break;
1445 	}
1446 	return (NULL);
1447 }
1448 
1449 /*
1450  * This only gets called in the case that the CPU extended
1451  * feature brand string (0x80000002, 0x80000003, 0x80000004)
1452  * aren't available, or contain null bytes for some reason.
1453  */
1454 static void
1455 fabricate_brandstr(struct cpuid_info *cpi)
1456 {
1457 	const char *brand = NULL;
1458 
1459 	switch (cpi->cpi_vendor) {
1460 	case X86_VENDOR_Intel:
1461 		brand = intel_cpubrand(cpi);
1462 		break;
1463 	case X86_VENDOR_AMD:
1464 		brand = amd_cpubrand(cpi);
1465 		break;
1466 	case X86_VENDOR_Cyrix:
1467 		brand = cyrix_cpubrand(cpi, x86_type);
1468 		break;
1469 	case X86_VENDOR_NexGen:
1470 		if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
1471 			brand = "NexGen Nx586";
1472 		break;
1473 	case X86_VENDOR_Centaur:
1474 		if (cpi->cpi_family == 5)
1475 			switch (cpi->cpi_model) {
1476 			case 4:
1477 				brand = "Centaur C6";
1478 				break;
1479 			case 8:
1480 				brand = "Centaur C2";
1481 				break;
1482 			case 9:
1483 				brand = "Centaur C3";
1484 				break;
1485 			default:
1486 				break;
1487 			}
1488 		break;
1489 	case X86_VENDOR_Rise:
1490 		if (cpi->cpi_family == 5 &&
1491 		    (cpi->cpi_model == 0 || cpi->cpi_model == 2))
1492 			brand = "Rise mP6";
1493 		break;
1494 	case X86_VENDOR_SiS:
1495 		if (cpi->cpi_family == 5 && cpi->cpi_model == 0)
1496 			brand = "SiS 55x";
1497 		break;
1498 	case X86_VENDOR_TM:
1499 		if (cpi->cpi_family == 5 && cpi->cpi_model == 4)
1500 			brand = "Transmeta Crusoe TM3x00 or TM5x00";
1501 		break;
1502 	case X86_VENDOR_NSC:
1503 	case X86_VENDOR_UMC:
1504 	default:
1505 		break;
1506 	}
1507 	if (brand) {
1508 		(void) strcpy((char *)cpi->cpi_brandstr, brand);
1509 		return;
1510 	}
1511 
1512 	/*
1513 	 * If all else fails ...
1514 	 */
1515 	(void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr),
1516 	    "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family,
1517 	    cpi->cpi_model, cpi->cpi_step);
1518 }
1519 
1520 /*
1521  * This routine is called just after kernel memory allocation
1522  * becomes available on cpu0, and as part of mp_startup() on
1523  * the other cpus.
1524  *
1525  * Fixup the brand string.
1526  */
1527 /*ARGSUSED*/
1528 void
1529 cpuid_pass3(cpu_t *cpu)
1530 {
1531 	struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1532 
1533 	ASSERT(cpi->cpi_pass == 2);
1534 
1535 	if ((cpi->cpi_xmaxeax & 0x80000000) == 0) {
1536 		fabricate_brandstr(cpi);
1537 		goto pass3_done;
1538 	}
1539 
1540 	/*
1541 	 * If we successfully extracted a brand string from the cpuid
1542 	 * instruction, clean it up by removing leading spaces and
1543 	 * similar junk.
1544 	 */
1545 	if (cpi->cpi_brandstr[0]) {
1546 		size_t maxlen = sizeof (cpi->cpi_brandstr);
1547 		char *src, *dst;
1548 
1549 		dst = src = (char *)cpi->cpi_brandstr;
1550 		src[maxlen - 1] = '\0';
1551 		/*
1552 		 * strip leading spaces
1553 		 */
1554 		while (*src == ' ')
1555 			src++;
1556 		/*
1557 		 * Remove any 'Genuine' or "Authentic" prefixes
1558 		 */
1559 		if (strncmp(src, "Genuine ", 8) == 0)
1560 			src += 8;
1561 		if (strncmp(src, "Authentic ", 10) == 0)
1562 			src += 10;
1563 
1564 		/*
1565 		 * Now do an in-place copy.
1566 		 * Map (R) to (r) and (TM) to (tm).
1567 		 * The era of teletypes is long gone, and there's
1568 		 * -really- no need to shout.
1569 		 */
1570 		while (*src != '\0') {
1571 			if (src[0] == '(') {
1572 				if (strncmp(src + 1, "R)", 2) == 0) {
1573 					(void) strncpy(dst, "(r)", 3);
1574 					src += 3;
1575 					dst += 3;
1576 					continue;
1577 				}
1578 				if (strncmp(src + 1, "TM)", 3) == 0) {
1579 					(void) strncpy(dst, "(tm)", 4);
1580 					src += 4;
1581 					dst += 4;
1582 					continue;
1583 				}
1584 			}
1585 			*dst++ = *src++;
1586 		}
1587 		*dst = '\0';
1588 
1589 		/*
1590 		 * Finally, remove any trailing spaces
1591 		 */
1592 		while (--dst > cpi->cpi_brandstr)
1593 			if (*dst == ' ')
1594 				*dst = '\0';
1595 			else
1596 				break;
1597 	} else
1598 		fabricate_brandstr(cpi);
1599 
1600 pass3_done:
1601 	cpi->cpi_pass = 3;
1602 }
1603 
1604 /*
1605  * This routine is called out of bind_hwcap() much later in the life
1606  * of the kernel (post_startup()).  The job of this routine is to resolve
1607  * the hardware feature support and kernel support for those features into
1608  * what we're actually going to tell applications via the aux vector.
1609  */
1610 uint_t
1611 cpuid_pass4(cpu_t *cpu)
1612 {
1613 	struct cpuid_info *cpi;
1614 	uint_t hwcap_flags = 0;
1615 
1616 	if (cpu == NULL)
1617 		cpu = CPU;
1618 	cpi = cpu->cpu_m.mcpu_cpi;
1619 
1620 	ASSERT(cpi->cpi_pass == 3);
1621 
1622 	if (cpi->cpi_maxeax >= 1) {
1623 		uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES];
1624 		uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES];
1625 
1626 		*edx = CPI_FEATURES_EDX(cpi);
1627 		*ecx = CPI_FEATURES_ECX(cpi);
1628 
1629 		/*
1630 		 * [these require explicit kernel support]
1631 		 */
1632 		if ((x86_feature & X86_SEP) == 0)
1633 			*edx &= ~CPUID_INTC_EDX_SEP;
1634 
1635 		if ((x86_feature & X86_SSE) == 0)
1636 			*edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE);
1637 		if ((x86_feature & X86_SSE2) == 0)
1638 			*edx &= ~CPUID_INTC_EDX_SSE2;
1639 
1640 		if ((x86_feature & X86_HTT) == 0)
1641 			*edx &= ~CPUID_INTC_EDX_HTT;
1642 
1643 		if ((x86_feature & X86_SSE3) == 0)
1644 			*ecx &= ~CPUID_INTC_ECX_SSE3;
1645 
1646 		/*
1647 		 * [no explicit support required beyond x87 fp context]
1648 		 */
1649 		if (!fpu_exists)
1650 			*edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX);
1651 
1652 		/*
1653 		 * Now map the supported feature vector to things that we
1654 		 * think userland will care about.
1655 		 */
1656 		if (*edx & CPUID_INTC_EDX_SEP)
1657 			hwcap_flags |= AV_386_SEP;
1658 		if (*edx & CPUID_INTC_EDX_SSE)
1659 			hwcap_flags |= AV_386_FXSR | AV_386_SSE;
1660 		if (*edx & CPUID_INTC_EDX_SSE2)
1661 			hwcap_flags |= AV_386_SSE2;
1662 		if (*ecx & CPUID_INTC_ECX_SSE3)
1663 			hwcap_flags |= AV_386_SSE3;
1664 
1665 		if (*edx & CPUID_INTC_EDX_FPU)
1666 			hwcap_flags |= AV_386_FPU;
1667 		if (*edx & CPUID_INTC_EDX_MMX)
1668 			hwcap_flags |= AV_386_MMX;
1669 
1670 		if (*edx & CPUID_INTC_EDX_TSC)
1671 			hwcap_flags |= AV_386_TSC;
1672 		if (*edx & CPUID_INTC_EDX_CX8)
1673 			hwcap_flags |= AV_386_CX8;
1674 		if (*edx & CPUID_INTC_EDX_CMOV)
1675 			hwcap_flags |= AV_386_CMOV;
1676 		if (*ecx & CPUID_INTC_ECX_MON)
1677 			hwcap_flags |= AV_386_MON;
1678 		if (*ecx & CPUID_INTC_ECX_CX16)
1679 			hwcap_flags |= AV_386_CX16;
1680 	}
1681 
1682 	if (x86_feature & X86_HTT)
1683 		hwcap_flags |= AV_386_PAUSE;
1684 
1685 	if (cpi->cpi_xmaxeax < 0x80000001)
1686 		goto pass4_done;
1687 
1688 	switch (cpi->cpi_vendor) {
1689 		struct cpuid_regs cp;
1690 		uint32_t *edx, *ecx;
1691 
1692 	case X86_VENDOR_Intel:
1693 		/*
1694 		 * Seems like Intel duplicated what we necessary
1695 		 * here to make the initial crop of 64-bit OS's work.
1696 		 * Hopefully, those are the only "extended" bits
1697 		 * they'll add.
1698 		 */
1699 		/*FALLTHROUGH*/
1700 
1701 	case X86_VENDOR_AMD:
1702 		edx = &cpi->cpi_support[AMD_EDX_FEATURES];
1703 		ecx = &cpi->cpi_support[AMD_ECX_FEATURES];
1704 
1705 		*edx = CPI_FEATURES_XTD_EDX(cpi);
1706 		*ecx = CPI_FEATURES_XTD_ECX(cpi);
1707 
1708 		/*
1709 		 * [these features require explicit kernel support]
1710 		 */
1711 		switch (cpi->cpi_vendor) {
1712 		case X86_VENDOR_Intel:
1713 			break;
1714 
1715 		case X86_VENDOR_AMD:
1716 			if ((x86_feature & X86_TSCP) == 0)
1717 				*edx &= ~CPUID_AMD_EDX_TSCP;
1718 			break;
1719 
1720 		default:
1721 			break;
1722 		}
1723 
1724 		/*
1725 		 * [no explicit support required beyond
1726 		 * x87 fp context and exception handlers]
1727 		 */
1728 		if (!fpu_exists)
1729 			*edx &= ~(CPUID_AMD_EDX_MMXamd |
1730 			    CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx);
1731 
1732 		if ((x86_feature & X86_NX) == 0)
1733 			*edx &= ~CPUID_AMD_EDX_NX;
1734 #if !defined(__amd64)
1735 		*edx &= ~CPUID_AMD_EDX_LM;
1736 #endif
1737 		/*
1738 		 * Now map the supported feature vector to
1739 		 * things that we think userland will care about.
1740 		 */
1741 #if defined(__amd64)
1742 		if (*edx & CPUID_AMD_EDX_SYSC)
1743 			hwcap_flags |= AV_386_AMD_SYSC;
1744 #endif
1745 		if (*edx & CPUID_AMD_EDX_MMXamd)
1746 			hwcap_flags |= AV_386_AMD_MMX;
1747 		if (*edx & CPUID_AMD_EDX_3DNow)
1748 			hwcap_flags |= AV_386_AMD_3DNow;
1749 		if (*edx & CPUID_AMD_EDX_3DNowx)
1750 			hwcap_flags |= AV_386_AMD_3DNowx;
1751 
1752 		switch (cpi->cpi_vendor) {
1753 		case X86_VENDOR_AMD:
1754 			if (*edx & CPUID_AMD_EDX_TSCP)
1755 				hwcap_flags |= AV_386_TSCP;
1756 			if (*ecx & CPUID_AMD_ECX_AHF64)
1757 				hwcap_flags |= AV_386_AHF;
1758 			break;
1759 
1760 		case X86_VENDOR_Intel:
1761 			/*
1762 			 * Aarrgh.
1763 			 * Intel uses a different bit in the same word.
1764 			 */
1765 			if (*ecx & CPUID_INTC_ECX_AHF64)
1766 				hwcap_flags |= AV_386_AHF;
1767 			break;
1768 
1769 		default:
1770 			break;
1771 		}
1772 		break;
1773 
1774 	case X86_VENDOR_TM:
1775 		cp.cp_eax = 0x80860001;
1776 		(void) __cpuid_insn(&cp);
1777 		cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx;
1778 		break;
1779 
1780 	default:
1781 		break;
1782 	}
1783 
1784 pass4_done:
1785 	cpi->cpi_pass = 4;
1786 	return (hwcap_flags);
1787 }
1788 
1789 
1790 /*
1791  * Simulate the cpuid instruction using the data we previously
1792  * captured about this CPU.  We try our best to return the truth
1793  * about the hardware, independently of kernel support.
1794  */
1795 uint32_t
1796 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp)
1797 {
1798 	struct cpuid_info *cpi;
1799 	struct cpuid_regs *xcp;
1800 
1801 	if (cpu == NULL)
1802 		cpu = CPU;
1803 	cpi = cpu->cpu_m.mcpu_cpi;
1804 
1805 	ASSERT(cpuid_checkpass(cpu, 3));
1806 
1807 	/*
1808 	 * CPUID data is cached in two separate places: cpi_std for standard
1809 	 * CPUID functions, and cpi_extd for extended CPUID functions.
1810 	 */
1811 	if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD)
1812 		xcp = &cpi->cpi_std[cp->cp_eax];
1813 	else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax &&
1814 	    cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD)
1815 		xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000];
1816 	else
1817 		/*
1818 		 * The caller is asking for data from an input parameter which
1819 		 * the kernel has not cached.  In this case we go fetch from
1820 		 * the hardware and return the data directly to the user.
1821 		 */
1822 		return (__cpuid_insn(cp));
1823 
1824 	cp->cp_eax = xcp->cp_eax;
1825 	cp->cp_ebx = xcp->cp_ebx;
1826 	cp->cp_ecx = xcp->cp_ecx;
1827 	cp->cp_edx = xcp->cp_edx;
1828 	return (cp->cp_eax);
1829 }
1830 
1831 int
1832 cpuid_checkpass(cpu_t *cpu, int pass)
1833 {
1834 	return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL &&
1835 	    cpu->cpu_m.mcpu_cpi->cpi_pass >= pass);
1836 }
1837 
1838 int
1839 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n)
1840 {
1841 	ASSERT(cpuid_checkpass(cpu, 3));
1842 
1843 	return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr));
1844 }
1845 
1846 int
1847 cpuid_is_cmt(cpu_t *cpu)
1848 {
1849 	if (cpu == NULL)
1850 		cpu = CPU;
1851 
1852 	ASSERT(cpuid_checkpass(cpu, 1));
1853 
1854 	return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0);
1855 }
1856 
1857 /*
1858  * AMD and Intel both implement the 64-bit variant of the syscall
1859  * instruction (syscallq), so if there's -any- support for syscall,
1860  * cpuid currently says "yes, we support this".
1861  *
1862  * However, Intel decided to -not- implement the 32-bit variant of the
1863  * syscall instruction, so we provide a predicate to allow our caller
1864  * to test that subtlety here.
1865  */
1866 /*ARGSUSED*/
1867 int
1868 cpuid_syscall32_insn(cpu_t *cpu)
1869 {
1870 	ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1));
1871 
1872 	if (cpu == NULL)
1873 		cpu = CPU;
1874 
1875 	/*CSTYLED*/
1876 	{
1877 		struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1878 
1879 		if (cpi->cpi_vendor == X86_VENDOR_AMD &&
1880 		    cpi->cpi_xmaxeax >= 0x80000001 &&
1881 		    (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC))
1882 			return (1);
1883 	}
1884 	return (0);
1885 }
1886 
1887 int
1888 cpuid_getidstr(cpu_t *cpu, char *s, size_t n)
1889 {
1890 	struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
1891 
1892 	static const char fmt[] =
1893 	    "x86 (%s %X family %d model %d step %d clock %d MHz)";
1894 	static const char fmt_ht[] =
1895 	    "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)";
1896 
1897 	ASSERT(cpuid_checkpass(cpu, 1));
1898 
1899 	if (cpuid_is_cmt(cpu))
1900 		return (snprintf(s, n, fmt_ht, cpi->cpi_chipid,
1901 		    cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
1902 		    cpi->cpi_family, cpi->cpi_model,
1903 		    cpi->cpi_step, cpu->cpu_type_info.pi_clock));
1904 	return (snprintf(s, n, fmt,
1905 	    cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax,
1906 	    cpi->cpi_family, cpi->cpi_model,
1907 	    cpi->cpi_step, cpu->cpu_type_info.pi_clock));
1908 }
1909 
1910 const char *
1911 cpuid_getvendorstr(cpu_t *cpu)
1912 {
1913 	ASSERT(cpuid_checkpass(cpu, 1));
1914 	return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr);
1915 }
1916 
1917 uint_t
1918 cpuid_getvendor(cpu_t *cpu)
1919 {
1920 	ASSERT(cpuid_checkpass(cpu, 1));
1921 	return (cpu->cpu_m.mcpu_cpi->cpi_vendor);
1922 }
1923 
1924 uint_t
1925 cpuid_getfamily(cpu_t *cpu)
1926 {
1927 	ASSERT(cpuid_checkpass(cpu, 1));
1928 	return (cpu->cpu_m.mcpu_cpi->cpi_family);
1929 }
1930 
1931 uint_t
1932 cpuid_getmodel(cpu_t *cpu)
1933 {
1934 	ASSERT(cpuid_checkpass(cpu, 1));
1935 	return (cpu->cpu_m.mcpu_cpi->cpi_model);
1936 }
1937 
1938 uint_t
1939 cpuid_get_ncpu_per_chip(cpu_t *cpu)
1940 {
1941 	ASSERT(cpuid_checkpass(cpu, 1));
1942 	return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip);
1943 }
1944 
1945 uint_t
1946 cpuid_get_ncore_per_chip(cpu_t *cpu)
1947 {
1948 	ASSERT(cpuid_checkpass(cpu, 1));
1949 	return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip);
1950 }
1951 
1952 uint_t
1953 cpuid_getstep(cpu_t *cpu)
1954 {
1955 	ASSERT(cpuid_checkpass(cpu, 1));
1956 	return (cpu->cpu_m.mcpu_cpi->cpi_step);
1957 }
1958 
1959 uint32_t
1960 cpuid_getchiprev(struct cpu *cpu)
1961 {
1962 	ASSERT(cpuid_checkpass(cpu, 1));
1963 	return (cpu->cpu_m.mcpu_cpi->cpi_chiprev);
1964 }
1965 
1966 const char *
1967 cpuid_getchiprevstr(struct cpu *cpu)
1968 {
1969 	ASSERT(cpuid_checkpass(cpu, 1));
1970 	return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr);
1971 }
1972 
1973 uint32_t
1974 cpuid_getsockettype(struct cpu *cpu)
1975 {
1976 	ASSERT(cpuid_checkpass(cpu, 1));
1977 	return (cpu->cpu_m.mcpu_cpi->cpi_socket);
1978 }
1979 
1980 int
1981 cpuid_get_chipid(cpu_t *cpu)
1982 {
1983 	ASSERT(cpuid_checkpass(cpu, 1));
1984 
1985 	if (cpuid_is_cmt(cpu))
1986 		return (cpu->cpu_m.mcpu_cpi->cpi_chipid);
1987 	return (cpu->cpu_id);
1988 }
1989 
1990 id_t
1991 cpuid_get_coreid(cpu_t *cpu)
1992 {
1993 	ASSERT(cpuid_checkpass(cpu, 1));
1994 	return (cpu->cpu_m.mcpu_cpi->cpi_coreid);
1995 }
1996 
1997 int
1998 cpuid_get_clogid(cpu_t *cpu)
1999 {
2000 	ASSERT(cpuid_checkpass(cpu, 1));
2001 	return (cpu->cpu_m.mcpu_cpi->cpi_clogid);
2002 }
2003 
2004 void
2005 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits)
2006 {
2007 	struct cpuid_info *cpi;
2008 
2009 	if (cpu == NULL)
2010 		cpu = CPU;
2011 	cpi = cpu->cpu_m.mcpu_cpi;
2012 
2013 	ASSERT(cpuid_checkpass(cpu, 1));
2014 
2015 	if (pabits)
2016 		*pabits = cpi->cpi_pabits;
2017 	if (vabits)
2018 		*vabits = cpi->cpi_vabits;
2019 }
2020 
2021 /*
2022  * Returns the number of data TLB entries for a corresponding
2023  * pagesize.  If it can't be computed, or isn't known, the
2024  * routine returns zero.  If you ask about an architecturally
2025  * impossible pagesize, the routine will panic (so that the
2026  * hat implementor knows that things are inconsistent.)
2027  */
2028 uint_t
2029 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize)
2030 {
2031 	struct cpuid_info *cpi;
2032 	uint_t dtlb_nent = 0;
2033 
2034 	if (cpu == NULL)
2035 		cpu = CPU;
2036 	cpi = cpu->cpu_m.mcpu_cpi;
2037 
2038 	ASSERT(cpuid_checkpass(cpu, 1));
2039 
2040 	/*
2041 	 * Check the L2 TLB info
2042 	 */
2043 	if (cpi->cpi_xmaxeax >= 0x80000006) {
2044 		struct cpuid_regs *cp = &cpi->cpi_extd[6];
2045 
2046 		switch (pagesize) {
2047 
2048 		case 4 * 1024:
2049 			/*
2050 			 * All zero in the top 16 bits of the register
2051 			 * indicates a unified TLB. Size is in low 16 bits.
2052 			 */
2053 			if ((cp->cp_ebx & 0xffff0000) == 0)
2054 				dtlb_nent = cp->cp_ebx & 0x0000ffff;
2055 			else
2056 				dtlb_nent = BITX(cp->cp_ebx, 27, 16);
2057 			break;
2058 
2059 		case 2 * 1024 * 1024:
2060 			if ((cp->cp_eax & 0xffff0000) == 0)
2061 				dtlb_nent = cp->cp_eax & 0x0000ffff;
2062 			else
2063 				dtlb_nent = BITX(cp->cp_eax, 27, 16);
2064 			break;
2065 
2066 		default:
2067 			panic("unknown L2 pagesize");
2068 			/*NOTREACHED*/
2069 		}
2070 	}
2071 
2072 	if (dtlb_nent != 0)
2073 		return (dtlb_nent);
2074 
2075 	/*
2076 	 * No L2 TLB support for this size, try L1.
2077 	 */
2078 	if (cpi->cpi_xmaxeax >= 0x80000005) {
2079 		struct cpuid_regs *cp = &cpi->cpi_extd[5];
2080 
2081 		switch (pagesize) {
2082 		case 4 * 1024:
2083 			dtlb_nent = BITX(cp->cp_ebx, 23, 16);
2084 			break;
2085 		case 2 * 1024 * 1024:
2086 			dtlb_nent = BITX(cp->cp_eax, 23, 16);
2087 			break;
2088 		default:
2089 			panic("unknown L1 d-TLB pagesize");
2090 			/*NOTREACHED*/
2091 		}
2092 	}
2093 
2094 	return (dtlb_nent);
2095 }
2096 
2097 /*
2098  * Return 0 if the erratum is not present or not applicable, positive
2099  * if it is, and negative if the status of the erratum is unknown.
2100  *
2101  * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm)
2102  * Processors" #25759, Rev 3.57, August 2005
2103  */
2104 int
2105 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum)
2106 {
2107 	struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
2108 	uint_t eax;
2109 
2110 	/*
2111 	 * Bail out if this CPU isn't an AMD CPU, or if it's
2112 	 * a legacy (32-bit) AMD CPU.
2113 	 */
2114 	if (cpi->cpi_vendor != X86_VENDOR_AMD ||
2115 	    CPI_FAMILY(cpi) == 4 || CPI_FAMILY(cpi) == 5 ||
2116 	    CPI_FAMILY(cpi) == 6)
2117 
2118 		return (0);
2119 
2120 	eax = cpi->cpi_std[1].cp_eax;
2121 
2122 #define	SH_B0(eax)	(eax == 0xf40 || eax == 0xf50)
2123 #define	SH_B3(eax) 	(eax == 0xf51)
2124 #define	B(eax)		(SH_B0(eax) || SH_B3(eax))
2125 
2126 #define	SH_C0(eax)	(eax == 0xf48 || eax == 0xf58)
2127 
2128 #define	SH_CG(eax)	(eax == 0xf4a || eax == 0xf5a || eax == 0xf7a)
2129 #define	DH_CG(eax)	(eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0)
2130 #define	CH_CG(eax)	(eax == 0xf82 || eax == 0xfb2)
2131 #define	CG(eax)		(SH_CG(eax) || DH_CG(eax) || CH_CG(eax))
2132 
2133 #define	SH_D0(eax)	(eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70)
2134 #define	DH_D0(eax)	(eax == 0x10fc0 || eax == 0x10ff0)
2135 #define	CH_D0(eax)	(eax == 0x10f80 || eax == 0x10fb0)
2136 #define	D0(eax)		(SH_D0(eax) || DH_D0(eax) || CH_D0(eax))
2137 
2138 #define	SH_E0(eax)	(eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70)
2139 #define	JH_E1(eax)	(eax == 0x20f10)	/* JH8_E0 had 0x20f30 */
2140 #define	DH_E3(eax)	(eax == 0x20fc0 || eax == 0x20ff0)
2141 #define	SH_E4(eax)	(eax == 0x20f51 || eax == 0x20f71)
2142 #define	BH_E4(eax)	(eax == 0x20fb1)
2143 #define	SH_E5(eax)	(eax == 0x20f42)
2144 #define	DH_E6(eax)	(eax == 0x20ff2 || eax == 0x20fc2)
2145 #define	JH_E6(eax)	(eax == 0x20f12 || eax == 0x20f32)
2146 #define	EX(eax)		(SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \
2147 			    SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \
2148 			    DH_E6(eax) || JH_E6(eax))
2149 
2150 	switch (erratum) {
2151 	case 1:
2152 		return (1);
2153 	case 51:	/* what does the asterisk mean? */
2154 		return (B(eax) || SH_C0(eax) || CG(eax));
2155 	case 52:
2156 		return (B(eax));
2157 	case 57:
2158 		return (1);
2159 	case 58:
2160 		return (B(eax));
2161 	case 60:
2162 		return (1);
2163 	case 61:
2164 	case 62:
2165 	case 63:
2166 	case 64:
2167 	case 65:
2168 	case 66:
2169 	case 68:
2170 	case 69:
2171 	case 70:
2172 	case 71:
2173 		return (B(eax));
2174 	case 72:
2175 		return (SH_B0(eax));
2176 	case 74:
2177 		return (B(eax));
2178 	case 75:
2179 		return (1);
2180 	case 76:
2181 		return (B(eax));
2182 	case 77:
2183 		return (1);
2184 	case 78:
2185 		return (B(eax) || SH_C0(eax));
2186 	case 79:
2187 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
2188 	case 80:
2189 	case 81:
2190 	case 82:
2191 		return (B(eax));
2192 	case 83:
2193 		return (B(eax) || SH_C0(eax) || CG(eax));
2194 	case 85:
2195 		return (1);
2196 	case 86:
2197 		return (SH_C0(eax) || CG(eax));
2198 	case 88:
2199 #if !defined(__amd64)
2200 		return (0);
2201 #else
2202 		return (B(eax) || SH_C0(eax));
2203 #endif
2204 	case 89:
2205 		return (1);
2206 	case 90:
2207 		return (B(eax) || SH_C0(eax) || CG(eax));
2208 	case 91:
2209 	case 92:
2210 		return (B(eax) || SH_C0(eax));
2211 	case 93:
2212 		return (SH_C0(eax));
2213 	case 94:
2214 		return (B(eax) || SH_C0(eax) || CG(eax));
2215 	case 95:
2216 #if !defined(__amd64)
2217 		return (0);
2218 #else
2219 		return (B(eax) || SH_C0(eax));
2220 #endif
2221 	case 96:
2222 		return (B(eax) || SH_C0(eax) || CG(eax));
2223 	case 97:
2224 	case 98:
2225 		return (SH_C0(eax) || CG(eax));
2226 	case 99:
2227 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
2228 	case 100:
2229 		return (B(eax) || SH_C0(eax));
2230 	case 101:
2231 	case 103:
2232 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
2233 	case 104:
2234 		return (SH_C0(eax) || CG(eax) || D0(eax));
2235 	case 105:
2236 	case 106:
2237 	case 107:
2238 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
2239 	case 108:
2240 		return (DH_CG(eax));
2241 	case 109:
2242 		return (SH_C0(eax) || CG(eax) || D0(eax));
2243 	case 110:
2244 		return (D0(eax) || EX(eax));
2245 	case 111:
2246 		return (CG(eax));
2247 	case 112:
2248 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
2249 	case 113:
2250 		return (eax == 0x20fc0);
2251 	case 114:
2252 		return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
2253 	case 115:
2254 		return (SH_E0(eax) || JH_E1(eax));
2255 	case 116:
2256 		return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax));
2257 	case 117:
2258 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax));
2259 	case 118:
2260 		return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) ||
2261 		    JH_E6(eax));
2262 	case 121:
2263 		return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax));
2264 	case 122:
2265 		return (1);
2266 	case 123:
2267 		return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax));
2268 	case 131:
2269 		return (1);
2270 	case 6336786:
2271 		/*
2272 		 * Test for AdvPowerMgmtInfo.TscPStateInvariant
2273 		 * if this is a K8 family processor
2274 		 */
2275 		if (CPI_FAMILY(cpi) == 0xf) {
2276 			struct cpuid_regs regs;
2277 			regs.cp_eax = 0x80000007;
2278 			(void) __cpuid_insn(&regs);
2279 			return (!(regs.cp_edx & 0x100));
2280 		}
2281 		return (0);
2282 	case 6323525:
2283 		return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) |
2284 		    (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40);
2285 
2286 	default:
2287 		return (-1);
2288 	}
2289 }
2290 
2291 static const char assoc_str[] = "associativity";
2292 static const char line_str[] = "line-size";
2293 static const char size_str[] = "size";
2294 
2295 static void
2296 add_cache_prop(dev_info_t *devi, const char *label, const char *type,
2297     uint32_t val)
2298 {
2299 	char buf[128];
2300 
2301 	/*
2302 	 * ndi_prop_update_int() is used because it is desirable for
2303 	 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set.
2304 	 */
2305 	if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf))
2306 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val);
2307 }
2308 
2309 /*
2310  * Intel-style cache/tlb description
2311  *
2312  * Standard cpuid level 2 gives a randomly ordered
2313  * selection of tags that index into a table that describes
2314  * cache and tlb properties.
2315  */
2316 
2317 static const char l1_icache_str[] = "l1-icache";
2318 static const char l1_dcache_str[] = "l1-dcache";
2319 static const char l2_cache_str[] = "l2-cache";
2320 static const char l3_cache_str[] = "l3-cache";
2321 static const char itlb4k_str[] = "itlb-4K";
2322 static const char dtlb4k_str[] = "dtlb-4K";
2323 static const char itlb4M_str[] = "itlb-4M";
2324 static const char dtlb4M_str[] = "dtlb-4M";
2325 static const char itlb424_str[] = "itlb-4K-2M-4M";
2326 static const char dtlb44_str[] = "dtlb-4K-4M";
2327 static const char sl1_dcache_str[] = "sectored-l1-dcache";
2328 static const char sl2_cache_str[] = "sectored-l2-cache";
2329 static const char itrace_str[] = "itrace-cache";
2330 static const char sl3_cache_str[] = "sectored-l3-cache";
2331 
2332 static const struct cachetab {
2333 	uint8_t 	ct_code;
2334 	uint8_t		ct_assoc;
2335 	uint16_t 	ct_line_size;
2336 	size_t		ct_size;
2337 	const char	*ct_label;
2338 } intel_ctab[] = {
2339 	/* maintain descending order! */
2340 	{ 0xb4, 4, 0, 256, dtlb4k_str },
2341 	{ 0xb3, 4, 0, 128, dtlb4k_str },
2342 	{ 0xb0, 4, 0, 128, itlb4k_str },
2343 	{ 0x87, 8, 64, 1024*1024, l2_cache_str},
2344 	{ 0x86, 4, 64, 512*1024, l2_cache_str},
2345 	{ 0x85, 8, 32, 2*1024*1024, l2_cache_str},
2346 	{ 0x84, 8, 32, 1024*1024, l2_cache_str},
2347 	{ 0x83, 8, 32, 512*1024, l2_cache_str},
2348 	{ 0x82, 8, 32, 256*1024, l2_cache_str},
2349 	{ 0x7f, 2, 64, 512*1024, l2_cache_str},
2350 	{ 0x7d, 8, 64, 2*1024*1024, sl2_cache_str},
2351 	{ 0x7c, 8, 64, 1024*1024, sl2_cache_str},
2352 	{ 0x7b, 8, 64, 512*1024, sl2_cache_str},
2353 	{ 0x7a, 8, 64, 256*1024, sl2_cache_str},
2354 	{ 0x79, 8, 64, 128*1024, sl2_cache_str},
2355 	{ 0x78, 8, 64, 1024*1024, l2_cache_str},
2356 	{ 0x73, 8, 0, 64*1024, itrace_str},
2357 	{ 0x72, 8, 0, 32*1024, itrace_str},
2358 	{ 0x71, 8, 0, 16*1024, itrace_str},
2359 	{ 0x70, 8, 0, 12*1024, itrace_str},
2360 	{ 0x68, 4, 64, 32*1024, sl1_dcache_str},
2361 	{ 0x67, 4, 64, 16*1024, sl1_dcache_str},
2362 	{ 0x66, 4, 64, 8*1024, sl1_dcache_str},
2363 	{ 0x60, 8, 64, 16*1024, sl1_dcache_str},
2364 	{ 0x5d, 0, 0, 256, dtlb44_str},
2365 	{ 0x5c, 0, 0, 128, dtlb44_str},
2366 	{ 0x5b, 0, 0, 64, dtlb44_str},
2367 	{ 0x52, 0, 0, 256, itlb424_str},
2368 	{ 0x51, 0, 0, 128, itlb424_str},
2369 	{ 0x50, 0, 0, 64, itlb424_str},
2370 	{ 0x4d, 16, 64, 16*1024*1024, l3_cache_str},
2371 	{ 0x4c, 12, 64, 12*1024*1024, l3_cache_str},
2372 	{ 0x4b, 16, 64, 8*1024*1024, l3_cache_str},
2373 	{ 0x4a, 12, 64, 6*1024*1024, l3_cache_str},
2374 	{ 0x49, 16, 64, 4*1024*1024, l3_cache_str},
2375 	{ 0x47, 8, 64, 8*1024*1024, l3_cache_str},
2376 	{ 0x46, 4, 64, 4*1024*1024, l3_cache_str},
2377 	{ 0x45, 4, 32, 2*1024*1024, l2_cache_str},
2378 	{ 0x44, 4, 32, 1024*1024, l2_cache_str},
2379 	{ 0x43, 4, 32, 512*1024, l2_cache_str},
2380 	{ 0x42, 4, 32, 256*1024, l2_cache_str},
2381 	{ 0x41, 4, 32, 128*1024, l2_cache_str},
2382 	{ 0x3e, 4, 64, 512*1024, sl2_cache_str},
2383 	{ 0x3d, 6, 64, 384*1024, sl2_cache_str},
2384 	{ 0x3c, 4, 64, 256*1024, sl2_cache_str},
2385 	{ 0x3b, 2, 64, 128*1024, sl2_cache_str},
2386 	{ 0x3a, 6, 64, 192*1024, sl2_cache_str},
2387 	{ 0x39, 4, 64, 128*1024, sl2_cache_str},
2388 	{ 0x30, 8, 64, 32*1024, l1_icache_str},
2389 	{ 0x2c, 8, 64, 32*1024, l1_dcache_str},
2390 	{ 0x29, 8, 64, 4096*1024, sl3_cache_str},
2391 	{ 0x25, 8, 64, 2048*1024, sl3_cache_str},
2392 	{ 0x23, 8, 64, 1024*1024, sl3_cache_str},
2393 	{ 0x22, 4, 64, 512*1024, sl3_cache_str},
2394 	{ 0x0c, 4, 32, 16*1024, l1_dcache_str},
2395 	{ 0x0b, 4, 0, 4, itlb4M_str},
2396 	{ 0x0a, 2, 32, 8*1024, l1_dcache_str},
2397 	{ 0x08, 4, 32, 16*1024, l1_icache_str},
2398 	{ 0x06, 4, 32, 8*1024, l1_icache_str},
2399 	{ 0x04, 4, 0, 8, dtlb4M_str},
2400 	{ 0x03, 4, 0, 64, dtlb4k_str},
2401 	{ 0x02, 4, 0, 2, itlb4M_str},
2402 	{ 0x01, 4, 0, 32, itlb4k_str},
2403 	{ 0 }
2404 };
2405 
2406 static const struct cachetab cyrix_ctab[] = {
2407 	{ 0x70, 4, 0, 32, "tlb-4K" },
2408 	{ 0x80, 4, 16, 16*1024, "l1-cache" },
2409 	{ 0 }
2410 };
2411 
2412 /*
2413  * Search a cache table for a matching entry
2414  */
2415 static const struct cachetab *
2416 find_cacheent(const struct cachetab *ct, uint_t code)
2417 {
2418 	if (code != 0) {
2419 		for (; ct->ct_code != 0; ct++)
2420 			if (ct->ct_code <= code)
2421 				break;
2422 		if (ct->ct_code == code)
2423 			return (ct);
2424 	}
2425 	return (NULL);
2426 }
2427 
2428 /*
2429  * Walk the cacheinfo descriptor, applying 'func' to every valid element
2430  * The walk is terminated if the walker returns non-zero.
2431  */
2432 static void
2433 intel_walk_cacheinfo(struct cpuid_info *cpi,
2434     void *arg, int (*func)(void *, const struct cachetab *))
2435 {
2436 	const struct cachetab *ct;
2437 	uint8_t *dp;
2438 	int i;
2439 
2440 	if ((dp = cpi->cpi_cacheinfo) == NULL)
2441 		return;
2442 	for (i = 0; i < cpi->cpi_ncache; i++, dp++)
2443 		if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
2444 			if (func(arg, ct) != 0)
2445 				break;
2446 		}
2447 }
2448 
2449 /*
2450  * (Like the Intel one, except for Cyrix CPUs)
2451  */
2452 static void
2453 cyrix_walk_cacheinfo(struct cpuid_info *cpi,
2454     void *arg, int (*func)(void *, const struct cachetab *))
2455 {
2456 	const struct cachetab *ct;
2457 	uint8_t *dp;
2458 	int i;
2459 
2460 	if ((dp = cpi->cpi_cacheinfo) == NULL)
2461 		return;
2462 	for (i = 0; i < cpi->cpi_ncache; i++, dp++) {
2463 		/*
2464 		 * Search Cyrix-specific descriptor table first ..
2465 		 */
2466 		if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) {
2467 			if (func(arg, ct) != 0)
2468 				break;
2469 			continue;
2470 		}
2471 		/*
2472 		 * .. else fall back to the Intel one
2473 		 */
2474 		if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) {
2475 			if (func(arg, ct) != 0)
2476 				break;
2477 			continue;
2478 		}
2479 	}
2480 }
2481 
2482 /*
2483  * A cacheinfo walker that adds associativity, line-size, and size properties
2484  * to the devinfo node it is passed as an argument.
2485  */
2486 static int
2487 add_cacheent_props(void *arg, const struct cachetab *ct)
2488 {
2489 	dev_info_t *devi = arg;
2490 
2491 	add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc);
2492 	if (ct->ct_line_size != 0)
2493 		add_cache_prop(devi, ct->ct_label, line_str,
2494 		    ct->ct_line_size);
2495 	add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size);
2496 	return (0);
2497 }
2498 
2499 static const char fully_assoc[] = "fully-associative?";
2500 
2501 /*
2502  * AMD style cache/tlb description
2503  *
2504  * Extended functions 5 and 6 directly describe properties of
2505  * tlbs and various cache levels.
2506  */
2507 static void
2508 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc)
2509 {
2510 	switch (assoc) {
2511 	case 0:	/* reserved; ignore */
2512 		break;
2513 	default:
2514 		add_cache_prop(devi, label, assoc_str, assoc);
2515 		break;
2516 	case 0xff:
2517 		add_cache_prop(devi, label, fully_assoc, 1);
2518 		break;
2519 	}
2520 }
2521 
2522 static void
2523 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
2524 {
2525 	if (size == 0)
2526 		return;
2527 	add_cache_prop(devi, label, size_str, size);
2528 	add_amd_assoc(devi, label, assoc);
2529 }
2530 
2531 static void
2532 add_amd_cache(dev_info_t *devi, const char *label,
2533     uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
2534 {
2535 	if (size == 0 || line_size == 0)
2536 		return;
2537 	add_amd_assoc(devi, label, assoc);
2538 	/*
2539 	 * Most AMD parts have a sectored cache. Multiple cache lines are
2540 	 * associated with each tag. A sector consists of all cache lines
2541 	 * associated with a tag. For example, the AMD K6-III has a sector
2542 	 * size of 2 cache lines per tag.
2543 	 */
2544 	if (lines_per_tag != 0)
2545 		add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
2546 	add_cache_prop(devi, label, line_str, line_size);
2547 	add_cache_prop(devi, label, size_str, size * 1024);
2548 }
2549 
2550 static void
2551 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc)
2552 {
2553 	switch (assoc) {
2554 	case 0:	/* off */
2555 		break;
2556 	case 1:
2557 	case 2:
2558 	case 4:
2559 		add_cache_prop(devi, label, assoc_str, assoc);
2560 		break;
2561 	case 6:
2562 		add_cache_prop(devi, label, assoc_str, 8);
2563 		break;
2564 	case 8:
2565 		add_cache_prop(devi, label, assoc_str, 16);
2566 		break;
2567 	case 0xf:
2568 		add_cache_prop(devi, label, fully_assoc, 1);
2569 		break;
2570 	default: /* reserved; ignore */
2571 		break;
2572 	}
2573 }
2574 
2575 static void
2576 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size)
2577 {
2578 	if (size == 0 || assoc == 0)
2579 		return;
2580 	add_amd_l2_assoc(devi, label, assoc);
2581 	add_cache_prop(devi, label, size_str, size);
2582 }
2583 
2584 static void
2585 add_amd_l2_cache(dev_info_t *devi, const char *label,
2586     uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size)
2587 {
2588 	if (size == 0 || assoc == 0 || line_size == 0)
2589 		return;
2590 	add_amd_l2_assoc(devi, label, assoc);
2591 	if (lines_per_tag != 0)
2592 		add_cache_prop(devi, label, "lines-per-tag", lines_per_tag);
2593 	add_cache_prop(devi, label, line_str, line_size);
2594 	add_cache_prop(devi, label, size_str, size * 1024);
2595 }
2596 
2597 static void
2598 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi)
2599 {
2600 	struct cpuid_regs *cp;
2601 
2602 	if (cpi->cpi_xmaxeax < 0x80000005)
2603 		return;
2604 	cp = &cpi->cpi_extd[5];
2605 
2606 	/*
2607 	 * 4M/2M L1 TLB configuration
2608 	 *
2609 	 * We report the size for 2M pages because AMD uses two
2610 	 * TLB entries for one 4M page.
2611 	 */
2612 	add_amd_tlb(devi, "dtlb-2M",
2613 	    BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16));
2614 	add_amd_tlb(devi, "itlb-2M",
2615 	    BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0));
2616 
2617 	/*
2618 	 * 4K L1 TLB configuration
2619 	 */
2620 
2621 	switch (cpi->cpi_vendor) {
2622 		uint_t nentries;
2623 	case X86_VENDOR_TM:
2624 		if (cpi->cpi_family >= 5) {
2625 			/*
2626 			 * Crusoe processors have 256 TLB entries, but
2627 			 * cpuid data format constrains them to only
2628 			 * reporting 255 of them.
2629 			 */
2630 			if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255)
2631 				nentries = 256;
2632 			/*
2633 			 * Crusoe processors also have a unified TLB
2634 			 */
2635 			add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24),
2636 			    nentries);
2637 			break;
2638 		}
2639 		/*FALLTHROUGH*/
2640 	default:
2641 		add_amd_tlb(devi, itlb4k_str,
2642 		    BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16));
2643 		add_amd_tlb(devi, dtlb4k_str,
2644 		    BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0));
2645 		break;
2646 	}
2647 
2648 	/*
2649 	 * data L1 cache configuration
2650 	 */
2651 
2652 	add_amd_cache(devi, l1_dcache_str,
2653 	    BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16),
2654 	    BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0));
2655 
2656 	/*
2657 	 * code L1 cache configuration
2658 	 */
2659 
2660 	add_amd_cache(devi, l1_icache_str,
2661 	    BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16),
2662 	    BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0));
2663 
2664 	if (cpi->cpi_xmaxeax < 0x80000006)
2665 		return;
2666 	cp = &cpi->cpi_extd[6];
2667 
2668 	/* Check for a unified L2 TLB for large pages */
2669 
2670 	if (BITX(cp->cp_eax, 31, 16) == 0)
2671 		add_amd_l2_tlb(devi, "l2-tlb-2M",
2672 		    BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
2673 	else {
2674 		add_amd_l2_tlb(devi, "l2-dtlb-2M",
2675 		    BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
2676 		add_amd_l2_tlb(devi, "l2-itlb-2M",
2677 		    BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
2678 	}
2679 
2680 	/* Check for a unified L2 TLB for 4K pages */
2681 
2682 	if (BITX(cp->cp_ebx, 31, 16) == 0) {
2683 		add_amd_l2_tlb(devi, "l2-tlb-4K",
2684 		    BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
2685 	} else {
2686 		add_amd_l2_tlb(devi, "l2-dtlb-4K",
2687 		    BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16));
2688 		add_amd_l2_tlb(devi, "l2-itlb-4K",
2689 		    BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0));
2690 	}
2691 
2692 	add_amd_l2_cache(devi, l2_cache_str,
2693 	    BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12),
2694 	    BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0));
2695 }
2696 
2697 /*
2698  * There are two basic ways that the x86 world describes it cache
2699  * and tlb architecture - Intel's way and AMD's way.
2700  *
2701  * Return which flavor of cache architecture we should use
2702  */
2703 static int
2704 x86_which_cacheinfo(struct cpuid_info *cpi)
2705 {
2706 	switch (cpi->cpi_vendor) {
2707 	case X86_VENDOR_Intel:
2708 		if (cpi->cpi_maxeax >= 2)
2709 			return (X86_VENDOR_Intel);
2710 		break;
2711 	case X86_VENDOR_AMD:
2712 		/*
2713 		 * The K5 model 1 was the first part from AMD that reported
2714 		 * cache sizes via extended cpuid functions.
2715 		 */
2716 		if (cpi->cpi_family > 5 ||
2717 		    (cpi->cpi_family == 5 && cpi->cpi_model >= 1))
2718 			return (X86_VENDOR_AMD);
2719 		break;
2720 	case X86_VENDOR_TM:
2721 		if (cpi->cpi_family >= 5)
2722 			return (X86_VENDOR_AMD);
2723 		/*FALLTHROUGH*/
2724 	default:
2725 		/*
2726 		 * If they have extended CPU data for 0x80000005
2727 		 * then we assume they have AMD-format cache
2728 		 * information.
2729 		 *
2730 		 * If not, and the vendor happens to be Cyrix,
2731 		 * then try our-Cyrix specific handler.
2732 		 *
2733 		 * If we're not Cyrix, then assume we're using Intel's
2734 		 * table-driven format instead.
2735 		 */
2736 		if (cpi->cpi_xmaxeax >= 0x80000005)
2737 			return (X86_VENDOR_AMD);
2738 		else if (cpi->cpi_vendor == X86_VENDOR_Cyrix)
2739 			return (X86_VENDOR_Cyrix);
2740 		else if (cpi->cpi_maxeax >= 2)
2741 			return (X86_VENDOR_Intel);
2742 		break;
2743 	}
2744 	return (-1);
2745 }
2746 
2747 /*
2748  * create a node for the given cpu under the prom root node.
2749  * Also, create a cpu node in the device tree.
2750  */
2751 static dev_info_t *cpu_nex_devi = NULL;
2752 static kmutex_t cpu_node_lock;
2753 
2754 /*
2755  * Called from post_startup() and mp_startup()
2756  */
2757 void
2758 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi)
2759 {
2760 	dev_info_t *cpu_devi;
2761 	int create;
2762 
2763 	mutex_enter(&cpu_node_lock);
2764 
2765 	/*
2766 	 * create a nexus node for all cpus identified as 'cpu_id' under
2767 	 * the root node.
2768 	 */
2769 	if (cpu_nex_devi == NULL) {
2770 		if (ndi_devi_alloc(ddi_root_node(), "cpus",
2771 		    (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) {
2772 			mutex_exit(&cpu_node_lock);
2773 			return;
2774 		}
2775 		(void) ndi_devi_online(cpu_nex_devi, 0);
2776 	}
2777 
2778 	/*
2779 	 * create a child node for cpu identified as 'cpu_id'
2780 	 */
2781 	cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID,
2782 		cpu_id);
2783 	if (cpu_devi == NULL) {
2784 		mutex_exit(&cpu_node_lock);
2785 		return;
2786 	}
2787 
2788 	/* device_type */
2789 
2790 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
2791 	    "device_type", "cpu");
2792 
2793 	/* reg */
2794 
2795 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2796 	    "reg", cpu_id);
2797 
2798 	/* cpu-mhz, and clock-frequency */
2799 
2800 	if (cpu_freq > 0) {
2801 		long long mul;
2802 
2803 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2804 		    "cpu-mhz", cpu_freq);
2805 
2806 		if ((mul = cpu_freq * 1000000LL) <= INT_MAX)
2807 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2808 			    "clock-frequency", (int)mul);
2809 	}
2810 
2811 	(void) ndi_devi_online(cpu_devi, 0);
2812 
2813 	if ((x86_feature & X86_CPUID) == 0) {
2814 		mutex_exit(&cpu_node_lock);
2815 		return;
2816 	}
2817 
2818 	/* vendor-id */
2819 
2820 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
2821 		"vendor-id", cpi->cpi_vendorstr);
2822 
2823 	if (cpi->cpi_maxeax == 0) {
2824 		mutex_exit(&cpu_node_lock);
2825 		return;
2826 	}
2827 
2828 	/*
2829 	 * family, model, and step
2830 	 */
2831 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2832 		"family", CPI_FAMILY(cpi));
2833 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2834 		"cpu-model", CPI_MODEL(cpi));
2835 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2836 		"stepping-id", CPI_STEP(cpi));
2837 
2838 	/* type */
2839 
2840 	switch (cpi->cpi_vendor) {
2841 	case X86_VENDOR_Intel:
2842 		create = 1;
2843 		break;
2844 	default:
2845 		create = 0;
2846 		break;
2847 	}
2848 	if (create)
2849 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2850 			"type", CPI_TYPE(cpi));
2851 
2852 	/* ext-family */
2853 
2854 	switch (cpi->cpi_vendor) {
2855 	case X86_VENDOR_Intel:
2856 	case X86_VENDOR_AMD:
2857 		create = cpi->cpi_family >= 0xf;
2858 		break;
2859 	default:
2860 		create = 0;
2861 		break;
2862 	}
2863 	if (create)
2864 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2865 		    "ext-family", CPI_FAMILY_XTD(cpi));
2866 
2867 	/* ext-model */
2868 
2869 	switch (cpi->cpi_vendor) {
2870 	case X86_VENDOR_Intel:
2871 		create = CPI_MODEL(cpi) == 0xf;
2872 		break;
2873 	case X86_VENDOR_AMD:
2874 		create = CPI_FAMILY(cpi) == 0xf;
2875 		break;
2876 	default:
2877 		create = 0;
2878 		break;
2879 	}
2880 	if (create)
2881 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2882 			"ext-model", CPI_MODEL_XTD(cpi));
2883 
2884 	/* generation */
2885 
2886 	switch (cpi->cpi_vendor) {
2887 	case X86_VENDOR_AMD:
2888 		/*
2889 		 * AMD K5 model 1 was the first part to support this
2890 		 */
2891 		create = cpi->cpi_xmaxeax >= 0x80000001;
2892 		break;
2893 	default:
2894 		create = 0;
2895 		break;
2896 	}
2897 	if (create)
2898 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2899 		    "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8));
2900 
2901 	/* brand-id */
2902 
2903 	switch (cpi->cpi_vendor) {
2904 	case X86_VENDOR_Intel:
2905 		/*
2906 		 * brand id first appeared on Pentium III Xeon model 8,
2907 		 * and Celeron model 8 processors and Opteron
2908 		 */
2909 		create = cpi->cpi_family > 6 ||
2910 		    (cpi->cpi_family == 6 && cpi->cpi_model >= 8);
2911 		break;
2912 	case X86_VENDOR_AMD:
2913 		create = cpi->cpi_family >= 0xf;
2914 		break;
2915 	default:
2916 		create = 0;
2917 		break;
2918 	}
2919 	if (create && cpi->cpi_brandid != 0) {
2920 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2921 		    "brand-id", cpi->cpi_brandid);
2922 	}
2923 
2924 	/* chunks, and apic-id */
2925 
2926 	switch (cpi->cpi_vendor) {
2927 		/*
2928 		 * first available on Pentium IV and Opteron (K8)
2929 		 */
2930 	case X86_VENDOR_Intel:
2931 		create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
2932 		break;
2933 	case X86_VENDOR_AMD:
2934 		create = cpi->cpi_family >= 0xf;
2935 		break;
2936 	default:
2937 		create = 0;
2938 		break;
2939 	}
2940 	if (create) {
2941 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2942 			"chunks", CPI_CHUNKS(cpi));
2943 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2944 			"apic-id", CPI_APIC_ID(cpi));
2945 		if (cpi->cpi_chipid >= 0) {
2946 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2947 			    "chip#", cpi->cpi_chipid);
2948 			(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2949 			    "clog#", cpi->cpi_clogid);
2950 		}
2951 	}
2952 
2953 	/* cpuid-features */
2954 
2955 	(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2956 	    "cpuid-features", CPI_FEATURES_EDX(cpi));
2957 
2958 
2959 	/* cpuid-features-ecx */
2960 
2961 	switch (cpi->cpi_vendor) {
2962 	case X86_VENDOR_Intel:
2963 		create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf;
2964 		break;
2965 	default:
2966 		create = 0;
2967 		break;
2968 	}
2969 	if (create)
2970 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2971 		    "cpuid-features-ecx", CPI_FEATURES_ECX(cpi));
2972 
2973 	/* ext-cpuid-features */
2974 
2975 	switch (cpi->cpi_vendor) {
2976 	case X86_VENDOR_Intel:
2977 	case X86_VENDOR_AMD:
2978 	case X86_VENDOR_Cyrix:
2979 	case X86_VENDOR_TM:
2980 	case X86_VENDOR_Centaur:
2981 		create = cpi->cpi_xmaxeax >= 0x80000001;
2982 		break;
2983 	default:
2984 		create = 0;
2985 		break;
2986 	}
2987 	if (create) {
2988 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2989 			"ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi));
2990 		(void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi,
2991 			"ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi));
2992 	}
2993 
2994 	/*
2995 	 * Brand String first appeared in Intel Pentium IV, AMD K5
2996 	 * model 1, and Cyrix GXm.  On earlier models we try and
2997 	 * simulate something similar .. so this string should always
2998 	 * same -something- about the processor, however lame.
2999 	 */
3000 	(void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi,
3001 	    "brand-string", cpi->cpi_brandstr);
3002 
3003 	/*
3004 	 * Finally, cache and tlb information
3005 	 */
3006 	switch (x86_which_cacheinfo(cpi)) {
3007 	case X86_VENDOR_Intel:
3008 		intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
3009 		break;
3010 	case X86_VENDOR_Cyrix:
3011 		cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props);
3012 		break;
3013 	case X86_VENDOR_AMD:
3014 		amd_cache_info(cpi, cpu_devi);
3015 		break;
3016 	default:
3017 		break;
3018 	}
3019 
3020 	mutex_exit(&cpu_node_lock);
3021 }
3022 
3023 struct l2info {
3024 	int *l2i_csz;
3025 	int *l2i_lsz;
3026 	int *l2i_assoc;
3027 	int l2i_ret;
3028 };
3029 
3030 /*
3031  * A cacheinfo walker that fetches the size, line-size and associativity
3032  * of the L2 cache
3033  */
3034 static int
3035 intel_l2cinfo(void *arg, const struct cachetab *ct)
3036 {
3037 	struct l2info *l2i = arg;
3038 	int *ip;
3039 
3040 	if (ct->ct_label != l2_cache_str &&
3041 	    ct->ct_label != sl2_cache_str)
3042 		return (0);	/* not an L2 -- keep walking */
3043 
3044 	if ((ip = l2i->l2i_csz) != NULL)
3045 		*ip = ct->ct_size;
3046 	if ((ip = l2i->l2i_lsz) != NULL)
3047 		*ip = ct->ct_line_size;
3048 	if ((ip = l2i->l2i_assoc) != NULL)
3049 		*ip = ct->ct_assoc;
3050 	l2i->l2i_ret = ct->ct_size;
3051 	return (1);		/* was an L2 -- terminate walk */
3052 }
3053 
3054 static void
3055 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i)
3056 {
3057 	struct cpuid_regs *cp;
3058 	uint_t size, assoc;
3059 	int *ip;
3060 
3061 	if (cpi->cpi_xmaxeax < 0x80000006)
3062 		return;
3063 	cp = &cpi->cpi_extd[6];
3064 
3065 	if ((assoc = BITX(cp->cp_ecx, 15, 12)) != 0 &&
3066 	    (size = BITX(cp->cp_ecx, 31, 16)) != 0) {
3067 		uint_t cachesz = size * 1024;
3068 
3069 
3070 		if ((ip = l2i->l2i_csz) != NULL)
3071 			*ip = cachesz;
3072 		if ((ip = l2i->l2i_lsz) != NULL)
3073 			*ip = BITX(cp->cp_ecx, 7, 0);
3074 		if ((ip = l2i->l2i_assoc) != NULL)
3075 			*ip = assoc;
3076 		l2i->l2i_ret = cachesz;
3077 	}
3078 }
3079 
3080 int
3081 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc)
3082 {
3083 	struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi;
3084 	struct l2info __l2info, *l2i = &__l2info;
3085 
3086 	l2i->l2i_csz = csz;
3087 	l2i->l2i_lsz = lsz;
3088 	l2i->l2i_assoc = assoc;
3089 	l2i->l2i_ret = -1;
3090 
3091 	switch (x86_which_cacheinfo(cpi)) {
3092 	case X86_VENDOR_Intel:
3093 		intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
3094 		break;
3095 	case X86_VENDOR_Cyrix:
3096 		cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo);
3097 		break;
3098 	case X86_VENDOR_AMD:
3099 		amd_l2cacheinfo(cpi, l2i);
3100 		break;
3101 	default:
3102 		break;
3103 	}
3104 	return (l2i->l2i_ret);
3105 }
3106