1 /* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 /* 22 * Copyright 2009 Sun Microsystems, Inc. All rights reserved. 23 * Use is subject to license terms. 24 */ 25 26 /* 27 * Various routines to handle identification 28 * and classification of x86 processors. 29 */ 30 31 #include <sys/types.h> 32 #include <sys/archsystm.h> 33 #include <sys/x86_archext.h> 34 #include <sys/kmem.h> 35 #include <sys/systm.h> 36 #include <sys/cmn_err.h> 37 #include <sys/sunddi.h> 38 #include <sys/sunndi.h> 39 #include <sys/cpuvar.h> 40 #include <sys/processor.h> 41 #include <sys/sysmacros.h> 42 #include <sys/pg.h> 43 #include <sys/fp.h> 44 #include <sys/controlregs.h> 45 #include <sys/auxv_386.h> 46 #include <sys/bitmap.h> 47 #include <sys/memnode.h> 48 49 #ifdef __xpv 50 #include <sys/hypervisor.h> 51 #else 52 #include <sys/ontrap.h> 53 #endif 54 55 /* 56 * Pass 0 of cpuid feature analysis happens in locore. It contains special code 57 * to recognize Cyrix processors that are not cpuid-compliant, and to deal with 58 * them accordingly. For most modern processors, feature detection occurs here 59 * in pass 1. 60 * 61 * Pass 1 of cpuid feature analysis happens just at the beginning of mlsetup() 62 * for the boot CPU and does the basic analysis that the early kernel needs. 63 * x86_feature is set based on the return value of cpuid_pass1() of the boot 64 * CPU. 65 * 66 * Pass 1 includes: 67 * 68 * o Determining vendor/model/family/stepping and setting x86_type and 69 * x86_vendor accordingly. 70 * o Processing the feature flags returned by the cpuid instruction while 71 * applying any workarounds or tricks for the specific processor. 72 * o Mapping the feature flags into Solaris feature bits (X86_*). 73 * o Processing extended feature flags if supported by the processor, 74 * again while applying specific processor knowledge. 75 * o Determining the CMT characteristics of the system. 76 * 77 * Pass 1 is done on non-boot CPUs during their initialization and the results 78 * are used only as a meager attempt at ensuring that all processors within the 79 * system support the same features. 80 * 81 * Pass 2 of cpuid feature analysis happens just at the beginning 82 * of startup(). It just copies in and corrects the remainder 83 * of the cpuid data we depend on: standard cpuid functions that we didn't 84 * need for pass1 feature analysis, and extended cpuid functions beyond the 85 * simple feature processing done in pass1. 86 * 87 * Pass 3 of cpuid analysis is invoked after basic kernel services; in 88 * particular kernel memory allocation has been made available. It creates a 89 * readable brand string based on the data collected in the first two passes. 90 * 91 * Pass 4 of cpuid analysis is invoked after post_startup() when all 92 * the support infrastructure for various hardware features has been 93 * initialized. It determines which processor features will be reported 94 * to userland via the aux vector. 95 * 96 * All passes are executed on all CPUs, but only the boot CPU determines what 97 * features the kernel will use. 98 * 99 * Much of the worst junk in this file is for the support of processors 100 * that didn't really implement the cpuid instruction properly. 101 * 102 * NOTE: The accessor functions (cpuid_get*) are aware of, and ASSERT upon, 103 * the pass numbers. Accordingly, changes to the pass code may require changes 104 * to the accessor code. 105 */ 106 107 uint_t x86_feature = 0; 108 uint_t x86_vendor = X86_VENDOR_IntelClone; 109 uint_t x86_type = X86_TYPE_OTHER; 110 uint_t x86_clflush_size = 0; 111 112 uint_t pentiumpro_bug4046376; 113 uint_t pentiumpro_bug4064495; 114 115 uint_t enable486; 116 117 /* 118 * monitor/mwait info. 119 * 120 * size_actual and buf_actual are the real address and size allocated to get 121 * proper mwait_buf alignement. buf_actual and size_actual should be passed 122 * to kmem_free(). Currently kmem_alloc() and mwait happen to both use 123 * processor cache-line alignment, but this is not guarantied in the furture. 124 */ 125 struct mwait_info { 126 size_t mon_min; /* min size to avoid missed wakeups */ 127 size_t mon_max; /* size to avoid false wakeups */ 128 size_t size_actual; /* size actually allocated */ 129 void *buf_actual; /* memory actually allocated */ 130 uint32_t support; /* processor support of monitor/mwait */ 131 }; 132 133 /* 134 * These constants determine how many of the elements of the 135 * cpuid we cache in the cpuid_info data structure; the 136 * remaining elements are accessible via the cpuid instruction. 137 */ 138 139 #define NMAX_CPI_STD 6 /* eax = 0 .. 5 */ 140 #define NMAX_CPI_EXTD 9 /* eax = 0x80000000 .. 0x80000008 */ 141 142 struct cpuid_info { 143 uint_t cpi_pass; /* last pass completed */ 144 /* 145 * standard function information 146 */ 147 uint_t cpi_maxeax; /* fn 0: %eax */ 148 char cpi_vendorstr[13]; /* fn 0: %ebx:%ecx:%edx */ 149 uint_t cpi_vendor; /* enum of cpi_vendorstr */ 150 151 uint_t cpi_family; /* fn 1: extended family */ 152 uint_t cpi_model; /* fn 1: extended model */ 153 uint_t cpi_step; /* fn 1: stepping */ 154 chipid_t cpi_chipid; /* fn 1: %ebx: chip # on ht cpus */ 155 uint_t cpi_brandid; /* fn 1: %ebx: brand ID */ 156 int cpi_clogid; /* fn 1: %ebx: thread # */ 157 uint_t cpi_ncpu_per_chip; /* fn 1: %ebx: logical cpu count */ 158 uint8_t cpi_cacheinfo[16]; /* fn 2: intel-style cache desc */ 159 uint_t cpi_ncache; /* fn 2: number of elements */ 160 uint_t cpi_ncpu_shr_last_cache; /* fn 4: %eax: ncpus sharing cache */ 161 id_t cpi_last_lvl_cacheid; /* fn 4: %eax: derived cache id */ 162 uint_t cpi_std_4_size; /* fn 4: number of fn 4 elements */ 163 struct cpuid_regs **cpi_std_4; /* fn 4: %ecx == 0 .. fn4_size */ 164 struct cpuid_regs cpi_std[NMAX_CPI_STD]; /* 0 .. 5 */ 165 /* 166 * extended function information 167 */ 168 uint_t cpi_xmaxeax; /* fn 0x80000000: %eax */ 169 char cpi_brandstr[49]; /* fn 0x8000000[234] */ 170 uint8_t cpi_pabits; /* fn 0x80000006: %eax */ 171 uint8_t cpi_vabits; /* fn 0x80000006: %eax */ 172 struct cpuid_regs cpi_extd[NMAX_CPI_EXTD]; /* 0x8000000[0-8] */ 173 id_t cpi_coreid; /* same coreid => strands share core */ 174 int cpi_pkgcoreid; /* core number within single package */ 175 uint_t cpi_ncore_per_chip; /* AMD: fn 0x80000008: %ecx[7-0] */ 176 /* Intel: fn 4: %eax[31-26] */ 177 /* 178 * supported feature information 179 */ 180 uint32_t cpi_support[5]; 181 #define STD_EDX_FEATURES 0 182 #define AMD_EDX_FEATURES 1 183 #define TM_EDX_FEATURES 2 184 #define STD_ECX_FEATURES 3 185 #define AMD_ECX_FEATURES 4 186 /* 187 * Synthesized information, where known. 188 */ 189 uint32_t cpi_chiprev; /* See X86_CHIPREV_* in x86_archext.h */ 190 const char *cpi_chiprevstr; /* May be NULL if chiprev unknown */ 191 uint32_t cpi_socket; /* Chip package/socket type */ 192 193 struct mwait_info cpi_mwait; /* fn 5: monitor/mwait info */ 194 uint32_t cpi_apicid; 195 }; 196 197 198 static struct cpuid_info cpuid_info0; 199 200 /* 201 * These bit fields are defined by the Intel Application Note AP-485 202 * "Intel Processor Identification and the CPUID Instruction" 203 */ 204 #define CPI_FAMILY_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 27, 20) 205 #define CPI_MODEL_XTD(cpi) BITX((cpi)->cpi_std[1].cp_eax, 19, 16) 206 #define CPI_TYPE(cpi) BITX((cpi)->cpi_std[1].cp_eax, 13, 12) 207 #define CPI_FAMILY(cpi) BITX((cpi)->cpi_std[1].cp_eax, 11, 8) 208 #define CPI_STEP(cpi) BITX((cpi)->cpi_std[1].cp_eax, 3, 0) 209 #define CPI_MODEL(cpi) BITX((cpi)->cpi_std[1].cp_eax, 7, 4) 210 211 #define CPI_FEATURES_EDX(cpi) ((cpi)->cpi_std[1].cp_edx) 212 #define CPI_FEATURES_ECX(cpi) ((cpi)->cpi_std[1].cp_ecx) 213 #define CPI_FEATURES_XTD_EDX(cpi) ((cpi)->cpi_extd[1].cp_edx) 214 #define CPI_FEATURES_XTD_ECX(cpi) ((cpi)->cpi_extd[1].cp_ecx) 215 216 #define CPI_BRANDID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 7, 0) 217 #define CPI_CHUNKS(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 15, 7) 218 #define CPI_CPU_COUNT(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 23, 16) 219 #define CPI_APIC_ID(cpi) BITX((cpi)->cpi_std[1].cp_ebx, 31, 24) 220 221 #define CPI_MAXEAX_MAX 0x100 /* sanity control */ 222 #define CPI_XMAXEAX_MAX 0x80000100 223 #define CPI_FN4_ECX_MAX 0x20 /* sanity: max fn 4 levels */ 224 #define CPI_FNB_ECX_MAX 0x20 /* sanity: max fn B levels */ 225 226 /* 227 * Function 4 (Deterministic Cache Parameters) macros 228 * Defined by Intel Application Note AP-485 229 */ 230 #define CPI_NUM_CORES(regs) BITX((regs)->cp_eax, 31, 26) 231 #define CPI_NTHR_SHR_CACHE(regs) BITX((regs)->cp_eax, 25, 14) 232 #define CPI_FULL_ASSOC_CACHE(regs) BITX((regs)->cp_eax, 9, 9) 233 #define CPI_SELF_INIT_CACHE(regs) BITX((regs)->cp_eax, 8, 8) 234 #define CPI_CACHE_LVL(regs) BITX((regs)->cp_eax, 7, 5) 235 #define CPI_CACHE_TYPE(regs) BITX((regs)->cp_eax, 4, 0) 236 #define CPI_CPU_LEVEL_TYPE(regs) BITX((regs)->cp_ecx, 15, 8) 237 238 #define CPI_CACHE_WAYS(regs) BITX((regs)->cp_ebx, 31, 22) 239 #define CPI_CACHE_PARTS(regs) BITX((regs)->cp_ebx, 21, 12) 240 #define CPI_CACHE_COH_LN_SZ(regs) BITX((regs)->cp_ebx, 11, 0) 241 242 #define CPI_CACHE_SETS(regs) BITX((regs)->cp_ecx, 31, 0) 243 244 #define CPI_PREFCH_STRIDE(regs) BITX((regs)->cp_edx, 9, 0) 245 246 247 /* 248 * A couple of shorthand macros to identify "later" P6-family chips 249 * like the Pentium M and Core. First, the "older" P6-based stuff 250 * (loosely defined as "pre-Pentium-4"): 251 * P6, PII, Mobile PII, PII Xeon, PIII, Mobile PIII, PIII Xeon 252 */ 253 254 #define IS_LEGACY_P6(cpi) ( \ 255 cpi->cpi_family == 6 && \ 256 (cpi->cpi_model == 1 || \ 257 cpi->cpi_model == 3 || \ 258 cpi->cpi_model == 5 || \ 259 cpi->cpi_model == 6 || \ 260 cpi->cpi_model == 7 || \ 261 cpi->cpi_model == 8 || \ 262 cpi->cpi_model == 0xA || \ 263 cpi->cpi_model == 0xB) \ 264 ) 265 266 /* A "new F6" is everything with family 6 that's not the above */ 267 #define IS_NEW_F6(cpi) ((cpi->cpi_family == 6) && !IS_LEGACY_P6(cpi)) 268 269 /* Extended family/model support */ 270 #define IS_EXTENDED_MODEL_INTEL(cpi) (cpi->cpi_family == 0x6 || \ 271 cpi->cpi_family >= 0xf) 272 273 /* 274 * Info for monitor/mwait idle loop. 275 * 276 * See cpuid section of "Intel 64 and IA-32 Architectures Software Developer's 277 * Manual Volume 2A: Instruction Set Reference, A-M" #25366-022US, November 278 * 2006. 279 * See MONITOR/MWAIT section of "AMD64 Architecture Programmer's Manual 280 * Documentation Updates" #33633, Rev 2.05, December 2006. 281 */ 282 #define MWAIT_SUPPORT (0x00000001) /* mwait supported */ 283 #define MWAIT_EXTENSIONS (0x00000002) /* extenstion supported */ 284 #define MWAIT_ECX_INT_ENABLE (0x00000004) /* ecx 1 extension supported */ 285 #define MWAIT_SUPPORTED(cpi) ((cpi)->cpi_std[1].cp_ecx & CPUID_INTC_ECX_MON) 286 #define MWAIT_INT_ENABLE(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x2) 287 #define MWAIT_EXTENSION(cpi) ((cpi)->cpi_std[5].cp_ecx & 0x1) 288 #define MWAIT_SIZE_MIN(cpi) BITX((cpi)->cpi_std[5].cp_eax, 15, 0) 289 #define MWAIT_SIZE_MAX(cpi) BITX((cpi)->cpi_std[5].cp_ebx, 15, 0) 290 /* 291 * Number of sub-cstates for a given c-state. 292 */ 293 #define MWAIT_NUM_SUBC_STATES(cpi, c_state) \ 294 BITX((cpi)->cpi_std[5].cp_edx, c_state + 3, c_state) 295 296 /* 297 * Functions we consune from cpuid_subr.c; don't publish these in a header 298 * file to try and keep people using the expected cpuid_* interfaces. 299 */ 300 extern uint32_t _cpuid_skt(uint_t, uint_t, uint_t, uint_t); 301 extern uint32_t _cpuid_chiprev(uint_t, uint_t, uint_t, uint_t); 302 extern const char *_cpuid_chiprevstr(uint_t, uint_t, uint_t, uint_t); 303 extern uint_t _cpuid_vendorstr_to_vendorcode(char *); 304 305 /* 306 * Apply up various platform-dependent restrictions where the 307 * underlying platform restrictions mean the CPU can be marked 308 * as less capable than its cpuid instruction would imply. 309 */ 310 #if defined(__xpv) 311 static void 312 platform_cpuid_mangle(uint_t vendor, uint32_t eax, struct cpuid_regs *cp) 313 { 314 switch (eax) { 315 case 1: { 316 uint32_t mcamask = DOMAIN_IS_INITDOMAIN(xen_info) ? 317 0 : CPUID_INTC_EDX_MCA; 318 cp->cp_edx &= 319 ~(mcamask | 320 CPUID_INTC_EDX_PSE | 321 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 322 CPUID_INTC_EDX_SEP | CPUID_INTC_EDX_MTRR | 323 CPUID_INTC_EDX_PGE | CPUID_INTC_EDX_PAT | 324 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 325 CPUID_INTC_EDX_PSE36 | CPUID_INTC_EDX_HTT); 326 break; 327 } 328 329 case 0x80000001: 330 cp->cp_edx &= 331 ~(CPUID_AMD_EDX_PSE | 332 CPUID_INTC_EDX_VME | CPUID_INTC_EDX_DE | 333 CPUID_AMD_EDX_MTRR | CPUID_AMD_EDX_PGE | 334 CPUID_AMD_EDX_PAT | CPUID_AMD_EDX_PSE36 | 335 CPUID_AMD_EDX_SYSC | CPUID_INTC_EDX_SEP | 336 CPUID_AMD_EDX_TSCP); 337 cp->cp_ecx &= ~CPUID_AMD_ECX_CMP_LGCY; 338 break; 339 default: 340 break; 341 } 342 343 switch (vendor) { 344 case X86_VENDOR_Intel: 345 switch (eax) { 346 case 4: 347 /* 348 * Zero out the (ncores-per-chip - 1) field 349 */ 350 cp->cp_eax &= 0x03fffffff; 351 break; 352 default: 353 break; 354 } 355 break; 356 case X86_VENDOR_AMD: 357 switch (eax) { 358 case 0x80000008: 359 /* 360 * Zero out the (ncores-per-chip - 1) field 361 */ 362 cp->cp_ecx &= 0xffffff00; 363 break; 364 default: 365 break; 366 } 367 break; 368 default: 369 break; 370 } 371 } 372 #else 373 #define platform_cpuid_mangle(vendor, eax, cp) /* nothing */ 374 #endif 375 376 /* 377 * Some undocumented ways of patching the results of the cpuid 378 * instruction to permit running Solaris 10 on future cpus that 379 * we don't currently support. Could be set to non-zero values 380 * via settings in eeprom. 381 */ 382 383 uint32_t cpuid_feature_ecx_include; 384 uint32_t cpuid_feature_ecx_exclude; 385 uint32_t cpuid_feature_edx_include; 386 uint32_t cpuid_feature_edx_exclude; 387 388 void 389 cpuid_alloc_space(cpu_t *cpu) 390 { 391 /* 392 * By convention, cpu0 is the boot cpu, which is set up 393 * before memory allocation is available. All other cpus get 394 * their cpuid_info struct allocated here. 395 */ 396 ASSERT(cpu->cpu_id != 0); 397 cpu->cpu_m.mcpu_cpi = 398 kmem_zalloc(sizeof (*cpu->cpu_m.mcpu_cpi), KM_SLEEP); 399 } 400 401 void 402 cpuid_free_space(cpu_t *cpu) 403 { 404 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 405 int i; 406 407 ASSERT(cpu->cpu_id != 0); 408 409 /* 410 * Free up any function 4 related dynamic storage 411 */ 412 for (i = 1; i < cpi->cpi_std_4_size; i++) 413 kmem_free(cpi->cpi_std_4[i], sizeof (struct cpuid_regs)); 414 if (cpi->cpi_std_4_size > 0) 415 kmem_free(cpi->cpi_std_4, 416 cpi->cpi_std_4_size * sizeof (struct cpuid_regs *)); 417 418 kmem_free(cpu->cpu_m.mcpu_cpi, sizeof (*cpu->cpu_m.mcpu_cpi)); 419 } 420 421 #if !defined(__xpv) 422 423 static void 424 check_for_hvm() 425 { 426 struct cpuid_regs cp; 427 char *xen_str; 428 uint32_t xen_signature[4]; 429 extern int xpv_is_hvm; 430 431 /* 432 * In a fully virtualized domain, Xen's pseudo-cpuid function 433 * 0x40000000 returns a string representing the Xen signature in 434 * %ebx, %ecx, and %edx. %eax contains the maximum supported cpuid 435 * function. 436 */ 437 cp.cp_eax = 0x40000000; 438 (void) __cpuid_insn(&cp); 439 xen_signature[0] = cp.cp_ebx; 440 xen_signature[1] = cp.cp_ecx; 441 xen_signature[2] = cp.cp_edx; 442 xen_signature[3] = 0; 443 xen_str = (char *)xen_signature; 444 if (strcmp("XenVMMXenVMM", xen_str) == 0 && cp.cp_eax <= 0x40000002) 445 xpv_is_hvm = 1; 446 } 447 #endif /* __xpv */ 448 449 uint_t 450 cpuid_pass1(cpu_t *cpu) 451 { 452 uint32_t mask_ecx, mask_edx; 453 uint_t feature = X86_CPUID; 454 struct cpuid_info *cpi; 455 struct cpuid_regs *cp; 456 int xcpuid; 457 #if !defined(__xpv) 458 extern int idle_cpu_prefer_mwait; 459 #endif 460 461 /* 462 * Space statically allocated for cpu0, ensure pointer is set 463 */ 464 if (cpu->cpu_id == 0) 465 cpu->cpu_m.mcpu_cpi = &cpuid_info0; 466 cpi = cpu->cpu_m.mcpu_cpi; 467 ASSERT(cpi != NULL); 468 cp = &cpi->cpi_std[0]; 469 cp->cp_eax = 0; 470 cpi->cpi_maxeax = __cpuid_insn(cp); 471 { 472 uint32_t *iptr = (uint32_t *)cpi->cpi_vendorstr; 473 *iptr++ = cp->cp_ebx; 474 *iptr++ = cp->cp_edx; 475 *iptr++ = cp->cp_ecx; 476 *(char *)&cpi->cpi_vendorstr[12] = '\0'; 477 } 478 479 cpi->cpi_vendor = _cpuid_vendorstr_to_vendorcode(cpi->cpi_vendorstr); 480 x86_vendor = cpi->cpi_vendor; /* for compatibility */ 481 482 /* 483 * Limit the range in case of weird hardware 484 */ 485 if (cpi->cpi_maxeax > CPI_MAXEAX_MAX) 486 cpi->cpi_maxeax = CPI_MAXEAX_MAX; 487 if (cpi->cpi_maxeax < 1) 488 goto pass1_done; 489 490 cp = &cpi->cpi_std[1]; 491 cp->cp_eax = 1; 492 (void) __cpuid_insn(cp); 493 494 /* 495 * Extract identifying constants for easy access. 496 */ 497 cpi->cpi_model = CPI_MODEL(cpi); 498 cpi->cpi_family = CPI_FAMILY(cpi); 499 500 if (cpi->cpi_family == 0xf) 501 cpi->cpi_family += CPI_FAMILY_XTD(cpi); 502 503 /* 504 * Beware: AMD uses "extended model" iff base *FAMILY* == 0xf. 505 * Intel, and presumably everyone else, uses model == 0xf, as 506 * one would expect (max value means possible overflow). Sigh. 507 */ 508 509 switch (cpi->cpi_vendor) { 510 case X86_VENDOR_Intel: 511 if (IS_EXTENDED_MODEL_INTEL(cpi)) 512 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 513 break; 514 case X86_VENDOR_AMD: 515 if (CPI_FAMILY(cpi) == 0xf) 516 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 517 break; 518 default: 519 if (cpi->cpi_model == 0xf) 520 cpi->cpi_model += CPI_MODEL_XTD(cpi) << 4; 521 break; 522 } 523 524 cpi->cpi_step = CPI_STEP(cpi); 525 cpi->cpi_brandid = CPI_BRANDID(cpi); 526 527 /* 528 * *default* assumptions: 529 * - believe %edx feature word 530 * - ignore %ecx feature word 531 * - 32-bit virtual and physical addressing 532 */ 533 mask_edx = 0xffffffff; 534 mask_ecx = 0; 535 536 cpi->cpi_pabits = cpi->cpi_vabits = 32; 537 538 switch (cpi->cpi_vendor) { 539 case X86_VENDOR_Intel: 540 if (cpi->cpi_family == 5) 541 x86_type = X86_TYPE_P5; 542 else if (IS_LEGACY_P6(cpi)) { 543 x86_type = X86_TYPE_P6; 544 pentiumpro_bug4046376 = 1; 545 pentiumpro_bug4064495 = 1; 546 /* 547 * Clear the SEP bit when it was set erroneously 548 */ 549 if (cpi->cpi_model < 3 && cpi->cpi_step < 3) 550 cp->cp_edx &= ~CPUID_INTC_EDX_SEP; 551 } else if (IS_NEW_F6(cpi) || cpi->cpi_family == 0xf) { 552 x86_type = X86_TYPE_P4; 553 /* 554 * We don't currently depend on any of the %ecx 555 * features until Prescott, so we'll only check 556 * this from P4 onwards. We might want to revisit 557 * that idea later. 558 */ 559 mask_ecx = 0xffffffff; 560 } else if (cpi->cpi_family > 0xf) 561 mask_ecx = 0xffffffff; 562 /* 563 * We don't support MONITOR/MWAIT if leaf 5 is not available 564 * to obtain the monitor linesize. 565 */ 566 if (cpi->cpi_maxeax < 5) 567 mask_ecx &= ~CPUID_INTC_ECX_MON; 568 break; 569 case X86_VENDOR_IntelClone: 570 default: 571 break; 572 case X86_VENDOR_AMD: 573 #if defined(OPTERON_ERRATUM_108) 574 if (cpi->cpi_family == 0xf && cpi->cpi_model == 0xe) { 575 cp->cp_eax = (0xf0f & cp->cp_eax) | 0xc0; 576 cpi->cpi_model = 0xc; 577 } else 578 #endif 579 if (cpi->cpi_family == 5) { 580 /* 581 * AMD K5 and K6 582 * 583 * These CPUs have an incomplete implementation 584 * of MCA/MCE which we mask away. 585 */ 586 mask_edx &= ~(CPUID_INTC_EDX_MCE | CPUID_INTC_EDX_MCA); 587 588 /* 589 * Model 0 uses the wrong (APIC) bit 590 * to indicate PGE. Fix it here. 591 */ 592 if (cpi->cpi_model == 0) { 593 if (cp->cp_edx & 0x200) { 594 cp->cp_edx &= ~0x200; 595 cp->cp_edx |= CPUID_INTC_EDX_PGE; 596 } 597 } 598 599 /* 600 * Early models had problems w/ MMX; disable. 601 */ 602 if (cpi->cpi_model < 6) 603 mask_edx &= ~CPUID_INTC_EDX_MMX; 604 } 605 606 /* 607 * For newer families, SSE3 and CX16, at least, are valid; 608 * enable all 609 */ 610 if (cpi->cpi_family >= 0xf) 611 mask_ecx = 0xffffffff; 612 /* 613 * We don't support MONITOR/MWAIT if leaf 5 is not available 614 * to obtain the monitor linesize. 615 */ 616 if (cpi->cpi_maxeax < 5) 617 mask_ecx &= ~CPUID_INTC_ECX_MON; 618 619 #if !defined(__xpv) 620 /* 621 * Do not use MONITOR/MWAIT to halt in the idle loop on any AMD 622 * processors. AMD does not intend MWAIT to be used in the cpu 623 * idle loop on current and future processors. 10h and future 624 * AMD processors use more power in MWAIT than HLT. 625 * Pre-family-10h Opterons do not have the MWAIT instruction. 626 */ 627 idle_cpu_prefer_mwait = 0; 628 #endif 629 630 break; 631 case X86_VENDOR_TM: 632 /* 633 * workaround the NT workaround in CMS 4.1 634 */ 635 if (cpi->cpi_family == 5 && cpi->cpi_model == 4 && 636 (cpi->cpi_step == 2 || cpi->cpi_step == 3)) 637 cp->cp_edx |= CPUID_INTC_EDX_CX8; 638 break; 639 case X86_VENDOR_Centaur: 640 /* 641 * workaround the NT workarounds again 642 */ 643 if (cpi->cpi_family == 6) 644 cp->cp_edx |= CPUID_INTC_EDX_CX8; 645 break; 646 case X86_VENDOR_Cyrix: 647 /* 648 * We rely heavily on the probing in locore 649 * to actually figure out what parts, if any, 650 * of the Cyrix cpuid instruction to believe. 651 */ 652 switch (x86_type) { 653 case X86_TYPE_CYRIX_486: 654 mask_edx = 0; 655 break; 656 case X86_TYPE_CYRIX_6x86: 657 mask_edx = 0; 658 break; 659 case X86_TYPE_CYRIX_6x86L: 660 mask_edx = 661 CPUID_INTC_EDX_DE | 662 CPUID_INTC_EDX_CX8; 663 break; 664 case X86_TYPE_CYRIX_6x86MX: 665 mask_edx = 666 CPUID_INTC_EDX_DE | 667 CPUID_INTC_EDX_MSR | 668 CPUID_INTC_EDX_CX8 | 669 CPUID_INTC_EDX_PGE | 670 CPUID_INTC_EDX_CMOV | 671 CPUID_INTC_EDX_MMX; 672 break; 673 case X86_TYPE_CYRIX_GXm: 674 mask_edx = 675 CPUID_INTC_EDX_MSR | 676 CPUID_INTC_EDX_CX8 | 677 CPUID_INTC_EDX_CMOV | 678 CPUID_INTC_EDX_MMX; 679 break; 680 case X86_TYPE_CYRIX_MediaGX: 681 break; 682 case X86_TYPE_CYRIX_MII: 683 case X86_TYPE_VIA_CYRIX_III: 684 mask_edx = 685 CPUID_INTC_EDX_DE | 686 CPUID_INTC_EDX_TSC | 687 CPUID_INTC_EDX_MSR | 688 CPUID_INTC_EDX_CX8 | 689 CPUID_INTC_EDX_PGE | 690 CPUID_INTC_EDX_CMOV | 691 CPUID_INTC_EDX_MMX; 692 break; 693 default: 694 break; 695 } 696 break; 697 } 698 699 #if defined(__xpv) 700 /* 701 * Do not support MONITOR/MWAIT under a hypervisor 702 */ 703 mask_ecx &= ~CPUID_INTC_ECX_MON; 704 #endif /* __xpv */ 705 706 /* 707 * Now we've figured out the masks that determine 708 * which bits we choose to believe, apply the masks 709 * to the feature words, then map the kernel's view 710 * of these feature words into its feature word. 711 */ 712 cp->cp_edx &= mask_edx; 713 cp->cp_ecx &= mask_ecx; 714 715 /* 716 * apply any platform restrictions (we don't call this 717 * immediately after __cpuid_insn here, because we need the 718 * workarounds applied above first) 719 */ 720 platform_cpuid_mangle(cpi->cpi_vendor, 1, cp); 721 722 /* 723 * fold in overrides from the "eeprom" mechanism 724 */ 725 cp->cp_edx |= cpuid_feature_edx_include; 726 cp->cp_edx &= ~cpuid_feature_edx_exclude; 727 728 cp->cp_ecx |= cpuid_feature_ecx_include; 729 cp->cp_ecx &= ~cpuid_feature_ecx_exclude; 730 731 if (cp->cp_edx & CPUID_INTC_EDX_PSE) 732 feature |= X86_LARGEPAGE; 733 if (cp->cp_edx & CPUID_INTC_EDX_TSC) 734 feature |= X86_TSC; 735 if (cp->cp_edx & CPUID_INTC_EDX_MSR) 736 feature |= X86_MSR; 737 if (cp->cp_edx & CPUID_INTC_EDX_MTRR) 738 feature |= X86_MTRR; 739 if (cp->cp_edx & CPUID_INTC_EDX_PGE) 740 feature |= X86_PGE; 741 if (cp->cp_edx & CPUID_INTC_EDX_CMOV) 742 feature |= X86_CMOV; 743 if (cp->cp_edx & CPUID_INTC_EDX_MMX) 744 feature |= X86_MMX; 745 if ((cp->cp_edx & CPUID_INTC_EDX_MCE) != 0 && 746 (cp->cp_edx & CPUID_INTC_EDX_MCA) != 0) 747 feature |= X86_MCA; 748 if (cp->cp_edx & CPUID_INTC_EDX_PAE) 749 feature |= X86_PAE; 750 if (cp->cp_edx & CPUID_INTC_EDX_CX8) 751 feature |= X86_CX8; 752 if (cp->cp_ecx & CPUID_INTC_ECX_CX16) 753 feature |= X86_CX16; 754 if (cp->cp_edx & CPUID_INTC_EDX_PAT) 755 feature |= X86_PAT; 756 if (cp->cp_edx & CPUID_INTC_EDX_SEP) 757 feature |= X86_SEP; 758 if (cp->cp_edx & CPUID_INTC_EDX_FXSR) { 759 /* 760 * In our implementation, fxsave/fxrstor 761 * are prerequisites before we'll even 762 * try and do SSE things. 763 */ 764 if (cp->cp_edx & CPUID_INTC_EDX_SSE) 765 feature |= X86_SSE; 766 if (cp->cp_edx & CPUID_INTC_EDX_SSE2) 767 feature |= X86_SSE2; 768 if (cp->cp_ecx & CPUID_INTC_ECX_SSE3) 769 feature |= X86_SSE3; 770 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 771 if (cp->cp_ecx & CPUID_INTC_ECX_SSSE3) 772 feature |= X86_SSSE3; 773 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_1) 774 feature |= X86_SSE4_1; 775 if (cp->cp_ecx & CPUID_INTC_ECX_SSE4_2) 776 feature |= X86_SSE4_2; 777 } 778 } 779 if (cp->cp_edx & CPUID_INTC_EDX_DE) 780 feature |= X86_DE; 781 #if !defined(__xpv) 782 if (cp->cp_ecx & CPUID_INTC_ECX_MON) { 783 784 /* 785 * We require the CLFLUSH instruction for erratum workaround 786 * to use MONITOR/MWAIT. 787 */ 788 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 789 cpi->cpi_mwait.support |= MWAIT_SUPPORT; 790 feature |= X86_MWAIT; 791 } else { 792 extern int idle_cpu_assert_cflush_monitor; 793 794 /* 795 * All processors we are aware of which have 796 * MONITOR/MWAIT also have CLFLUSH. 797 */ 798 if (idle_cpu_assert_cflush_monitor) { 799 ASSERT((cp->cp_ecx & CPUID_INTC_ECX_MON) && 800 (cp->cp_edx & CPUID_INTC_EDX_CLFSH)); 801 } 802 } 803 } 804 #endif /* __xpv */ 805 806 /* 807 * Only need it first time, rest of the cpus would follow suite. 808 * we only capture this for the bootcpu. 809 */ 810 if (cp->cp_edx & CPUID_INTC_EDX_CLFSH) { 811 feature |= X86_CLFSH; 812 x86_clflush_size = (BITX(cp->cp_ebx, 15, 8) * 8); 813 } 814 815 if (feature & X86_PAE) 816 cpi->cpi_pabits = 36; 817 818 /* 819 * Hyperthreading configuration is slightly tricky on Intel 820 * and pure clones, and even trickier on AMD. 821 * 822 * (AMD chose to set the HTT bit on their CMP processors, 823 * even though they're not actually hyperthreaded. Thus it 824 * takes a bit more work to figure out what's really going 825 * on ... see the handling of the CMP_LGCY bit below) 826 */ 827 if (cp->cp_edx & CPUID_INTC_EDX_HTT) { 828 cpi->cpi_ncpu_per_chip = CPI_CPU_COUNT(cpi); 829 if (cpi->cpi_ncpu_per_chip > 1) 830 feature |= X86_HTT; 831 } else { 832 cpi->cpi_ncpu_per_chip = 1; 833 } 834 835 /* 836 * Work on the "extended" feature information, doing 837 * some basic initialization for cpuid_pass2() 838 */ 839 xcpuid = 0; 840 switch (cpi->cpi_vendor) { 841 case X86_VENDOR_Intel: 842 if (IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf) 843 xcpuid++; 844 break; 845 case X86_VENDOR_AMD: 846 if (cpi->cpi_family > 5 || 847 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 848 xcpuid++; 849 break; 850 case X86_VENDOR_Cyrix: 851 /* 852 * Only these Cyrix CPUs are -known- to support 853 * extended cpuid operations. 854 */ 855 if (x86_type == X86_TYPE_VIA_CYRIX_III || 856 x86_type == X86_TYPE_CYRIX_GXm) 857 xcpuid++; 858 break; 859 case X86_VENDOR_Centaur: 860 case X86_VENDOR_TM: 861 default: 862 xcpuid++; 863 break; 864 } 865 866 if (xcpuid) { 867 cp = &cpi->cpi_extd[0]; 868 cp->cp_eax = 0x80000000; 869 cpi->cpi_xmaxeax = __cpuid_insn(cp); 870 } 871 872 if (cpi->cpi_xmaxeax & 0x80000000) { 873 874 if (cpi->cpi_xmaxeax > CPI_XMAXEAX_MAX) 875 cpi->cpi_xmaxeax = CPI_XMAXEAX_MAX; 876 877 switch (cpi->cpi_vendor) { 878 case X86_VENDOR_Intel: 879 case X86_VENDOR_AMD: 880 if (cpi->cpi_xmaxeax < 0x80000001) 881 break; 882 cp = &cpi->cpi_extd[1]; 883 cp->cp_eax = 0x80000001; 884 (void) __cpuid_insn(cp); 885 886 if (cpi->cpi_vendor == X86_VENDOR_AMD && 887 cpi->cpi_family == 5 && 888 cpi->cpi_model == 6 && 889 cpi->cpi_step == 6) { 890 /* 891 * K6 model 6 uses bit 10 to indicate SYSC 892 * Later models use bit 11. Fix it here. 893 */ 894 if (cp->cp_edx & 0x400) { 895 cp->cp_edx &= ~0x400; 896 cp->cp_edx |= CPUID_AMD_EDX_SYSC; 897 } 898 } 899 900 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000001, cp); 901 902 /* 903 * Compute the additions to the kernel's feature word. 904 */ 905 if (cp->cp_edx & CPUID_AMD_EDX_NX) 906 feature |= X86_NX; 907 908 /* 909 * Regardless whether or not we boot 64-bit, 910 * we should have a way to identify whether 911 * the CPU is capable of running 64-bit. 912 */ 913 if (cp->cp_edx & CPUID_AMD_EDX_LM) 914 feature |= X86_64; 915 916 #if defined(__amd64) 917 /* 1 GB large page - enable only for 64 bit kernel */ 918 if (cp->cp_edx & CPUID_AMD_EDX_1GPG) 919 feature |= X86_1GPG; 920 #endif 921 922 if ((cpi->cpi_vendor == X86_VENDOR_AMD) && 923 (cpi->cpi_std[1].cp_edx & CPUID_INTC_EDX_FXSR) && 924 (cp->cp_ecx & CPUID_AMD_ECX_SSE4A)) 925 feature |= X86_SSE4A; 926 927 /* 928 * If both the HTT and CMP_LGCY bits are set, 929 * then we're not actually HyperThreaded. Read 930 * "AMD CPUID Specification" for more details. 931 */ 932 if (cpi->cpi_vendor == X86_VENDOR_AMD && 933 (feature & X86_HTT) && 934 (cp->cp_ecx & CPUID_AMD_ECX_CMP_LGCY)) { 935 feature &= ~X86_HTT; 936 feature |= X86_CMP; 937 } 938 #if defined(__amd64) 939 /* 940 * It's really tricky to support syscall/sysret in 941 * the i386 kernel; we rely on sysenter/sysexit 942 * instead. In the amd64 kernel, things are -way- 943 * better. 944 */ 945 if (cp->cp_edx & CPUID_AMD_EDX_SYSC) 946 feature |= X86_ASYSC; 947 948 /* 949 * While we're thinking about system calls, note 950 * that AMD processors don't support sysenter 951 * in long mode at all, so don't try to program them. 952 */ 953 if (x86_vendor == X86_VENDOR_AMD) 954 feature &= ~X86_SEP; 955 #endif 956 if (cp->cp_edx & CPUID_AMD_EDX_TSCP) 957 feature |= X86_TSCP; 958 break; 959 default: 960 break; 961 } 962 963 /* 964 * Get CPUID data about processor cores and hyperthreads. 965 */ 966 switch (cpi->cpi_vendor) { 967 case X86_VENDOR_Intel: 968 if (cpi->cpi_maxeax >= 4) { 969 cp = &cpi->cpi_std[4]; 970 cp->cp_eax = 4; 971 cp->cp_ecx = 0; 972 (void) __cpuid_insn(cp); 973 platform_cpuid_mangle(cpi->cpi_vendor, 4, cp); 974 } 975 /*FALLTHROUGH*/ 976 case X86_VENDOR_AMD: 977 if (cpi->cpi_xmaxeax < 0x80000008) 978 break; 979 cp = &cpi->cpi_extd[8]; 980 cp->cp_eax = 0x80000008; 981 (void) __cpuid_insn(cp); 982 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000008, cp); 983 984 /* 985 * Virtual and physical address limits from 986 * cpuid override previously guessed values. 987 */ 988 cpi->cpi_pabits = BITX(cp->cp_eax, 7, 0); 989 cpi->cpi_vabits = BITX(cp->cp_eax, 15, 8); 990 break; 991 default: 992 break; 993 } 994 995 /* 996 * Derive the number of cores per chip 997 */ 998 switch (cpi->cpi_vendor) { 999 case X86_VENDOR_Intel: 1000 if (cpi->cpi_maxeax < 4) { 1001 cpi->cpi_ncore_per_chip = 1; 1002 break; 1003 } else { 1004 cpi->cpi_ncore_per_chip = 1005 BITX((cpi)->cpi_std[4].cp_eax, 31, 26) + 1; 1006 } 1007 break; 1008 case X86_VENDOR_AMD: 1009 if (cpi->cpi_xmaxeax < 0x80000008) { 1010 cpi->cpi_ncore_per_chip = 1; 1011 break; 1012 } else { 1013 /* 1014 * On family 0xf cpuid fn 2 ECX[7:0] "NC" is 1015 * 1 less than the number of physical cores on 1016 * the chip. In family 0x10 this value can 1017 * be affected by "downcoring" - it reflects 1018 * 1 less than the number of cores actually 1019 * enabled on this node. 1020 */ 1021 cpi->cpi_ncore_per_chip = 1022 BITX((cpi)->cpi_extd[8].cp_ecx, 7, 0) + 1; 1023 } 1024 break; 1025 default: 1026 cpi->cpi_ncore_per_chip = 1; 1027 break; 1028 } 1029 1030 /* 1031 * Get CPUID data about TSC Invariance in Deep C-State. 1032 */ 1033 switch (cpi->cpi_vendor) { 1034 case X86_VENDOR_Intel: 1035 if (cpi->cpi_maxeax >= 7) { 1036 cp = &cpi->cpi_extd[7]; 1037 cp->cp_eax = 0x80000007; 1038 cp->cp_ecx = 0; 1039 (void) __cpuid_insn(cp); 1040 } 1041 break; 1042 default: 1043 break; 1044 } 1045 } else { 1046 cpi->cpi_ncore_per_chip = 1; 1047 } 1048 1049 /* 1050 * If more than one core, then this processor is CMP. 1051 */ 1052 if (cpi->cpi_ncore_per_chip > 1) 1053 feature |= X86_CMP; 1054 1055 /* 1056 * If the number of cores is the same as the number 1057 * of CPUs, then we cannot have HyperThreading. 1058 */ 1059 if (cpi->cpi_ncpu_per_chip == cpi->cpi_ncore_per_chip) 1060 feature &= ~X86_HTT; 1061 1062 if ((feature & (X86_HTT | X86_CMP)) == 0) { 1063 /* 1064 * Single-core single-threaded processors. 1065 */ 1066 cpi->cpi_chipid = -1; 1067 cpi->cpi_clogid = 0; 1068 cpi->cpi_coreid = cpu->cpu_id; 1069 cpi->cpi_pkgcoreid = 0; 1070 } else if (cpi->cpi_ncpu_per_chip > 1) { 1071 uint_t i; 1072 uint_t chipid_shift = 0; 1073 uint_t coreid_shift = 0; 1074 uint_t apic_id = CPI_APIC_ID(cpi); 1075 1076 for (i = 1; i < cpi->cpi_ncpu_per_chip; i <<= 1) 1077 chipid_shift++; 1078 cpi->cpi_chipid = apic_id >> chipid_shift; 1079 cpi->cpi_clogid = apic_id & ((1 << chipid_shift) - 1); 1080 1081 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 1082 if (feature & X86_CMP) { 1083 /* 1084 * Multi-core (and possibly multi-threaded) 1085 * processors. 1086 */ 1087 uint_t ncpu_per_core; 1088 if (cpi->cpi_ncore_per_chip == 1) 1089 ncpu_per_core = cpi->cpi_ncpu_per_chip; 1090 else if (cpi->cpi_ncore_per_chip > 1) 1091 ncpu_per_core = cpi->cpi_ncpu_per_chip / 1092 cpi->cpi_ncore_per_chip; 1093 /* 1094 * 8bit APIC IDs on dual core Pentiums 1095 * look like this: 1096 * 1097 * +-----------------------+------+------+ 1098 * | Physical Package ID | MC | HT | 1099 * +-----------------------+------+------+ 1100 * <------- chipid --------> 1101 * <------- coreid ---------------> 1102 * <--- clogid --> 1103 * <------> 1104 * pkgcoreid 1105 * 1106 * Where the number of bits necessary to 1107 * represent MC and HT fields together equals 1108 * to the minimum number of bits necessary to 1109 * store the value of cpi->cpi_ncpu_per_chip. 1110 * Of those bits, the MC part uses the number 1111 * of bits necessary to store the value of 1112 * cpi->cpi_ncore_per_chip. 1113 */ 1114 for (i = 1; i < ncpu_per_core; i <<= 1) 1115 coreid_shift++; 1116 cpi->cpi_coreid = apic_id >> coreid_shift; 1117 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> 1118 coreid_shift; 1119 } else if (feature & X86_HTT) { 1120 /* 1121 * Single-core multi-threaded processors. 1122 */ 1123 cpi->cpi_coreid = cpi->cpi_chipid; 1124 cpi->cpi_pkgcoreid = 0; 1125 } 1126 } else if (cpi->cpi_vendor == X86_VENDOR_AMD) { 1127 /* 1128 * AMD CMP chips currently have a single thread per 1129 * core, with 2 cores on family 0xf and 2, 3 or 4 1130 * cores on family 0x10. 1131 * 1132 * Since no two cpus share a core we must assign a 1133 * distinct coreid per cpu, and we do this by using 1134 * the cpu_id. This scheme does not, however, 1135 * guarantee that sibling cores of a chip will have 1136 * sequential coreids starting at a multiple of the 1137 * number of cores per chip - that is usually the 1138 * case, but if the ACPI MADT table is presented 1139 * in a different order then we need to perform a 1140 * few more gymnastics for the pkgcoreid. 1141 * 1142 * In family 0xf CMPs there are 2 cores on all nodes 1143 * present - no mixing of single and dual core parts. 1144 * 1145 * In family 0x10 CMPs cpuid fn 2 ECX[15:12] 1146 * "ApicIdCoreIdSize[3:0]" tells us how 1147 * many least-significant bits in the ApicId 1148 * are used to represent the core number 1149 * within the node. Cores are always 1150 * numbered sequentially from 0 regardless 1151 * of how many or which are disabled, and 1152 * there seems to be no way to discover the 1153 * real core id when some are disabled. 1154 */ 1155 cpi->cpi_coreid = cpu->cpu_id; 1156 1157 if (cpi->cpi_family == 0x10 && 1158 cpi->cpi_xmaxeax >= 0x80000008) { 1159 int coreidsz = 1160 BITX((cpi)->cpi_extd[8].cp_ecx, 15, 12); 1161 1162 cpi->cpi_pkgcoreid = 1163 apic_id & ((1 << coreidsz) - 1); 1164 } else { 1165 cpi->cpi_pkgcoreid = cpi->cpi_clogid; 1166 } 1167 } else { 1168 /* 1169 * All other processors are currently 1170 * assumed to have single cores. 1171 */ 1172 cpi->cpi_coreid = cpi->cpi_chipid; 1173 cpi->cpi_pkgcoreid = 0; 1174 } 1175 } 1176 1177 cpi->cpi_apicid = CPI_APIC_ID(cpi); 1178 1179 /* 1180 * Synthesize chip "revision" and socket type 1181 */ 1182 cpi->cpi_chiprev = _cpuid_chiprev(cpi->cpi_vendor, cpi->cpi_family, 1183 cpi->cpi_model, cpi->cpi_step); 1184 cpi->cpi_chiprevstr = _cpuid_chiprevstr(cpi->cpi_vendor, 1185 cpi->cpi_family, cpi->cpi_model, cpi->cpi_step); 1186 cpi->cpi_socket = _cpuid_skt(cpi->cpi_vendor, cpi->cpi_family, 1187 cpi->cpi_model, cpi->cpi_step); 1188 1189 pass1_done: 1190 #if !defined(__xpv) 1191 check_for_hvm(); 1192 #endif 1193 cpi->cpi_pass = 1; 1194 return (feature); 1195 } 1196 1197 /* 1198 * Make copies of the cpuid table entries we depend on, in 1199 * part for ease of parsing now, in part so that we have only 1200 * one place to correct any of it, in part for ease of 1201 * later export to userland, and in part so we can look at 1202 * this stuff in a crash dump. 1203 */ 1204 1205 /*ARGSUSED*/ 1206 void 1207 cpuid_pass2(cpu_t *cpu) 1208 { 1209 uint_t n, nmax; 1210 int i; 1211 struct cpuid_regs *cp; 1212 uint8_t *dp; 1213 uint32_t *iptr; 1214 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1215 1216 ASSERT(cpi->cpi_pass == 1); 1217 1218 if (cpi->cpi_maxeax < 1) 1219 goto pass2_done; 1220 1221 if ((nmax = cpi->cpi_maxeax + 1) > NMAX_CPI_STD) 1222 nmax = NMAX_CPI_STD; 1223 /* 1224 * (We already handled n == 0 and n == 1 in pass 1) 1225 */ 1226 for (n = 2, cp = &cpi->cpi_std[2]; n < nmax; n++, cp++) { 1227 cp->cp_eax = n; 1228 1229 /* 1230 * CPUID function 4 expects %ecx to be initialized 1231 * with an index which indicates which cache to return 1232 * information about. The OS is expected to call function 4 1233 * with %ecx set to 0, 1, 2, ... until it returns with 1234 * EAX[4:0] set to 0, which indicates there are no more 1235 * caches. 1236 * 1237 * Here, populate cpi_std[4] with the information returned by 1238 * function 4 when %ecx == 0, and do the rest in cpuid_pass3() 1239 * when dynamic memory allocation becomes available. 1240 * 1241 * Note: we need to explicitly initialize %ecx here, since 1242 * function 4 may have been previously invoked. 1243 */ 1244 if (n == 4) 1245 cp->cp_ecx = 0; 1246 1247 (void) __cpuid_insn(cp); 1248 platform_cpuid_mangle(cpi->cpi_vendor, n, cp); 1249 switch (n) { 1250 case 2: 1251 /* 1252 * "the lower 8 bits of the %eax register 1253 * contain a value that identifies the number 1254 * of times the cpuid [instruction] has to be 1255 * executed to obtain a complete image of the 1256 * processor's caching systems." 1257 * 1258 * How *do* they make this stuff up? 1259 */ 1260 cpi->cpi_ncache = sizeof (*cp) * 1261 BITX(cp->cp_eax, 7, 0); 1262 if (cpi->cpi_ncache == 0) 1263 break; 1264 cpi->cpi_ncache--; /* skip count byte */ 1265 1266 /* 1267 * Well, for now, rather than attempt to implement 1268 * this slightly dubious algorithm, we just look 1269 * at the first 15 .. 1270 */ 1271 if (cpi->cpi_ncache > (sizeof (*cp) - 1)) 1272 cpi->cpi_ncache = sizeof (*cp) - 1; 1273 1274 dp = cpi->cpi_cacheinfo; 1275 if (BITX(cp->cp_eax, 31, 31) == 0) { 1276 uint8_t *p = (void *)&cp->cp_eax; 1277 for (i = 1; i < 4; i++) 1278 if (p[i] != 0) 1279 *dp++ = p[i]; 1280 } 1281 if (BITX(cp->cp_ebx, 31, 31) == 0) { 1282 uint8_t *p = (void *)&cp->cp_ebx; 1283 for (i = 0; i < 4; i++) 1284 if (p[i] != 0) 1285 *dp++ = p[i]; 1286 } 1287 if (BITX(cp->cp_ecx, 31, 31) == 0) { 1288 uint8_t *p = (void *)&cp->cp_ecx; 1289 for (i = 0; i < 4; i++) 1290 if (p[i] != 0) 1291 *dp++ = p[i]; 1292 } 1293 if (BITX(cp->cp_edx, 31, 31) == 0) { 1294 uint8_t *p = (void *)&cp->cp_edx; 1295 for (i = 0; i < 4; i++) 1296 if (p[i] != 0) 1297 *dp++ = p[i]; 1298 } 1299 break; 1300 1301 case 3: /* Processor serial number, if PSN supported */ 1302 break; 1303 1304 case 4: /* Deterministic cache parameters */ 1305 break; 1306 1307 case 5: /* Monitor/Mwait parameters */ 1308 { 1309 size_t mwait_size; 1310 1311 /* 1312 * check cpi_mwait.support which was set in cpuid_pass1 1313 */ 1314 if (!(cpi->cpi_mwait.support & MWAIT_SUPPORT)) 1315 break; 1316 1317 /* 1318 * Protect ourself from insane mwait line size. 1319 * Workaround for incomplete hardware emulator(s). 1320 */ 1321 mwait_size = (size_t)MWAIT_SIZE_MAX(cpi); 1322 if (mwait_size < sizeof (uint32_t) || 1323 !ISP2(mwait_size)) { 1324 #if DEBUG 1325 cmn_err(CE_NOTE, "Cannot handle cpu %d mwait " 1326 "size %ld", cpu->cpu_id, (long)mwait_size); 1327 #endif 1328 break; 1329 } 1330 1331 cpi->cpi_mwait.mon_min = (size_t)MWAIT_SIZE_MIN(cpi); 1332 cpi->cpi_mwait.mon_max = mwait_size; 1333 if (MWAIT_EXTENSION(cpi)) { 1334 cpi->cpi_mwait.support |= MWAIT_EXTENSIONS; 1335 if (MWAIT_INT_ENABLE(cpi)) 1336 cpi->cpi_mwait.support |= 1337 MWAIT_ECX_INT_ENABLE; 1338 } 1339 break; 1340 } 1341 default: 1342 break; 1343 } 1344 } 1345 1346 if (cpi->cpi_maxeax >= 0xB && cpi->cpi_vendor == X86_VENDOR_Intel) { 1347 struct cpuid_regs regs; 1348 1349 cp = ®s; 1350 cp->cp_eax = 0xB; 1351 cp->cp_edx = cp->cp_ebx = cp->cp_ecx = 0; 1352 1353 (void) __cpuid_insn(cp); 1354 1355 /* 1356 * Check CPUID.EAX=0BH, ECX=0H:EBX is non-zero, which 1357 * indicates that the extended topology enumeration leaf is 1358 * available. 1359 */ 1360 if (cp->cp_ebx) { 1361 uint32_t x2apic_id; 1362 uint_t coreid_shift = 0; 1363 uint_t ncpu_per_core = 1; 1364 uint_t chipid_shift = 0; 1365 uint_t ncpu_per_chip = 1; 1366 uint_t i; 1367 uint_t level; 1368 1369 for (i = 0; i < CPI_FNB_ECX_MAX; i++) { 1370 cp->cp_eax = 0xB; 1371 cp->cp_ecx = i; 1372 1373 (void) __cpuid_insn(cp); 1374 level = CPI_CPU_LEVEL_TYPE(cp); 1375 1376 if (level == 1) { 1377 x2apic_id = cp->cp_edx; 1378 coreid_shift = BITX(cp->cp_eax, 4, 0); 1379 ncpu_per_core = BITX(cp->cp_ebx, 15, 0); 1380 } else if (level == 2) { 1381 x2apic_id = cp->cp_edx; 1382 chipid_shift = BITX(cp->cp_eax, 4, 0); 1383 ncpu_per_chip = BITX(cp->cp_ebx, 15, 0); 1384 } 1385 } 1386 1387 cpi->cpi_apicid = x2apic_id; 1388 cpi->cpi_ncpu_per_chip = ncpu_per_chip; 1389 cpi->cpi_ncore_per_chip = ncpu_per_chip / 1390 ncpu_per_core; 1391 cpi->cpi_chipid = x2apic_id >> chipid_shift; 1392 cpi->cpi_clogid = x2apic_id & ((1 << chipid_shift) - 1); 1393 cpi->cpi_coreid = x2apic_id >> coreid_shift; 1394 cpi->cpi_pkgcoreid = cpi->cpi_clogid >> coreid_shift; 1395 } 1396 1397 /* Make cp NULL so that we don't stumble on others */ 1398 cp = NULL; 1399 } 1400 1401 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) 1402 goto pass2_done; 1403 1404 if ((nmax = cpi->cpi_xmaxeax - 0x80000000 + 1) > NMAX_CPI_EXTD) 1405 nmax = NMAX_CPI_EXTD; 1406 /* 1407 * Copy the extended properties, fixing them as we go. 1408 * (We already handled n == 0 and n == 1 in pass 1) 1409 */ 1410 iptr = (void *)cpi->cpi_brandstr; 1411 for (n = 2, cp = &cpi->cpi_extd[2]; n < nmax; cp++, n++) { 1412 cp->cp_eax = 0x80000000 + n; 1413 (void) __cpuid_insn(cp); 1414 platform_cpuid_mangle(cpi->cpi_vendor, 0x80000000 + n, cp); 1415 switch (n) { 1416 case 2: 1417 case 3: 1418 case 4: 1419 /* 1420 * Extract the brand string 1421 */ 1422 *iptr++ = cp->cp_eax; 1423 *iptr++ = cp->cp_ebx; 1424 *iptr++ = cp->cp_ecx; 1425 *iptr++ = cp->cp_edx; 1426 break; 1427 case 5: 1428 switch (cpi->cpi_vendor) { 1429 case X86_VENDOR_AMD: 1430 /* 1431 * The Athlon and Duron were the first 1432 * parts to report the sizes of the 1433 * TLB for large pages. Before then, 1434 * we don't trust the data. 1435 */ 1436 if (cpi->cpi_family < 6 || 1437 (cpi->cpi_family == 6 && 1438 cpi->cpi_model < 1)) 1439 cp->cp_eax = 0; 1440 break; 1441 default: 1442 break; 1443 } 1444 break; 1445 case 6: 1446 switch (cpi->cpi_vendor) { 1447 case X86_VENDOR_AMD: 1448 /* 1449 * The Athlon and Duron were the first 1450 * AMD parts with L2 TLB's. 1451 * Before then, don't trust the data. 1452 */ 1453 if (cpi->cpi_family < 6 || 1454 cpi->cpi_family == 6 && 1455 cpi->cpi_model < 1) 1456 cp->cp_eax = cp->cp_ebx = 0; 1457 /* 1458 * AMD Duron rev A0 reports L2 1459 * cache size incorrectly as 1K 1460 * when it is really 64K 1461 */ 1462 if (cpi->cpi_family == 6 && 1463 cpi->cpi_model == 3 && 1464 cpi->cpi_step == 0) { 1465 cp->cp_ecx &= 0xffff; 1466 cp->cp_ecx |= 0x400000; 1467 } 1468 break; 1469 case X86_VENDOR_Cyrix: /* VIA C3 */ 1470 /* 1471 * VIA C3 processors are a bit messed 1472 * up w.r.t. encoding cache sizes in %ecx 1473 */ 1474 if (cpi->cpi_family != 6) 1475 break; 1476 /* 1477 * model 7 and 8 were incorrectly encoded 1478 * 1479 * xxx is model 8 really broken? 1480 */ 1481 if (cpi->cpi_model == 7 || 1482 cpi->cpi_model == 8) 1483 cp->cp_ecx = 1484 BITX(cp->cp_ecx, 31, 24) << 16 | 1485 BITX(cp->cp_ecx, 23, 16) << 12 | 1486 BITX(cp->cp_ecx, 15, 8) << 8 | 1487 BITX(cp->cp_ecx, 7, 0); 1488 /* 1489 * model 9 stepping 1 has wrong associativity 1490 */ 1491 if (cpi->cpi_model == 9 && cpi->cpi_step == 1) 1492 cp->cp_ecx |= 8 << 12; 1493 break; 1494 case X86_VENDOR_Intel: 1495 /* 1496 * Extended L2 Cache features function. 1497 * First appeared on Prescott. 1498 */ 1499 default: 1500 break; 1501 } 1502 break; 1503 default: 1504 break; 1505 } 1506 } 1507 1508 pass2_done: 1509 cpi->cpi_pass = 2; 1510 } 1511 1512 static const char * 1513 intel_cpubrand(const struct cpuid_info *cpi) 1514 { 1515 int i; 1516 1517 if ((x86_feature & X86_CPUID) == 0 || 1518 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1519 return ("i486"); 1520 1521 switch (cpi->cpi_family) { 1522 case 5: 1523 return ("Intel Pentium(r)"); 1524 case 6: 1525 switch (cpi->cpi_model) { 1526 uint_t celeron, xeon; 1527 const struct cpuid_regs *cp; 1528 case 0: 1529 case 1: 1530 case 2: 1531 return ("Intel Pentium(r) Pro"); 1532 case 3: 1533 case 4: 1534 return ("Intel Pentium(r) II"); 1535 case 6: 1536 return ("Intel Celeron(r)"); 1537 case 5: 1538 case 7: 1539 celeron = xeon = 0; 1540 cp = &cpi->cpi_std[2]; /* cache info */ 1541 1542 for (i = 1; i < 4; i++) { 1543 uint_t tmp; 1544 1545 tmp = (cp->cp_eax >> (8 * i)) & 0xff; 1546 if (tmp == 0x40) 1547 celeron++; 1548 if (tmp >= 0x44 && tmp <= 0x45) 1549 xeon++; 1550 } 1551 1552 for (i = 0; i < 2; i++) { 1553 uint_t tmp; 1554 1555 tmp = (cp->cp_ebx >> (8 * i)) & 0xff; 1556 if (tmp == 0x40) 1557 celeron++; 1558 else if (tmp >= 0x44 && tmp <= 0x45) 1559 xeon++; 1560 } 1561 1562 for (i = 0; i < 4; i++) { 1563 uint_t tmp; 1564 1565 tmp = (cp->cp_ecx >> (8 * i)) & 0xff; 1566 if (tmp == 0x40) 1567 celeron++; 1568 else if (tmp >= 0x44 && tmp <= 0x45) 1569 xeon++; 1570 } 1571 1572 for (i = 0; i < 4; i++) { 1573 uint_t tmp; 1574 1575 tmp = (cp->cp_edx >> (8 * i)) & 0xff; 1576 if (tmp == 0x40) 1577 celeron++; 1578 else if (tmp >= 0x44 && tmp <= 0x45) 1579 xeon++; 1580 } 1581 1582 if (celeron) 1583 return ("Intel Celeron(r)"); 1584 if (xeon) 1585 return (cpi->cpi_model == 5 ? 1586 "Intel Pentium(r) II Xeon(tm)" : 1587 "Intel Pentium(r) III Xeon(tm)"); 1588 return (cpi->cpi_model == 5 ? 1589 "Intel Pentium(r) II or Pentium(r) II Xeon(tm)" : 1590 "Intel Pentium(r) III or Pentium(r) III Xeon(tm)"); 1591 default: 1592 break; 1593 } 1594 default: 1595 break; 1596 } 1597 1598 /* BrandID is present if the field is nonzero */ 1599 if (cpi->cpi_brandid != 0) { 1600 static const struct { 1601 uint_t bt_bid; 1602 const char *bt_str; 1603 } brand_tbl[] = { 1604 { 0x1, "Intel(r) Celeron(r)" }, 1605 { 0x2, "Intel(r) Pentium(r) III" }, 1606 { 0x3, "Intel(r) Pentium(r) III Xeon(tm)" }, 1607 { 0x4, "Intel(r) Pentium(r) III" }, 1608 { 0x6, "Mobile Intel(r) Pentium(r) III" }, 1609 { 0x7, "Mobile Intel(r) Celeron(r)" }, 1610 { 0x8, "Intel(r) Pentium(r) 4" }, 1611 { 0x9, "Intel(r) Pentium(r) 4" }, 1612 { 0xa, "Intel(r) Celeron(r)" }, 1613 { 0xb, "Intel(r) Xeon(tm)" }, 1614 { 0xc, "Intel(r) Xeon(tm) MP" }, 1615 { 0xe, "Mobile Intel(r) Pentium(r) 4" }, 1616 { 0xf, "Mobile Intel(r) Celeron(r)" }, 1617 { 0x11, "Mobile Genuine Intel(r)" }, 1618 { 0x12, "Intel(r) Celeron(r) M" }, 1619 { 0x13, "Mobile Intel(r) Celeron(r)" }, 1620 { 0x14, "Intel(r) Celeron(r)" }, 1621 { 0x15, "Mobile Genuine Intel(r)" }, 1622 { 0x16, "Intel(r) Pentium(r) M" }, 1623 { 0x17, "Mobile Intel(r) Celeron(r)" } 1624 }; 1625 uint_t btblmax = sizeof (brand_tbl) / sizeof (brand_tbl[0]); 1626 uint_t sgn; 1627 1628 sgn = (cpi->cpi_family << 8) | 1629 (cpi->cpi_model << 4) | cpi->cpi_step; 1630 1631 for (i = 0; i < btblmax; i++) 1632 if (brand_tbl[i].bt_bid == cpi->cpi_brandid) 1633 break; 1634 if (i < btblmax) { 1635 if (sgn == 0x6b1 && cpi->cpi_brandid == 3) 1636 return ("Intel(r) Celeron(r)"); 1637 if (sgn < 0xf13 && cpi->cpi_brandid == 0xb) 1638 return ("Intel(r) Xeon(tm) MP"); 1639 if (sgn < 0xf13 && cpi->cpi_brandid == 0xe) 1640 return ("Intel(r) Xeon(tm)"); 1641 return (brand_tbl[i].bt_str); 1642 } 1643 } 1644 1645 return (NULL); 1646 } 1647 1648 static const char * 1649 amd_cpubrand(const struct cpuid_info *cpi) 1650 { 1651 if ((x86_feature & X86_CPUID) == 0 || 1652 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5) 1653 return ("i486 compatible"); 1654 1655 switch (cpi->cpi_family) { 1656 case 5: 1657 switch (cpi->cpi_model) { 1658 case 0: 1659 case 1: 1660 case 2: 1661 case 3: 1662 case 4: 1663 case 5: 1664 return ("AMD-K5(r)"); 1665 case 6: 1666 case 7: 1667 return ("AMD-K6(r)"); 1668 case 8: 1669 return ("AMD-K6(r)-2"); 1670 case 9: 1671 return ("AMD-K6(r)-III"); 1672 default: 1673 return ("AMD (family 5)"); 1674 } 1675 case 6: 1676 switch (cpi->cpi_model) { 1677 case 1: 1678 return ("AMD-K7(tm)"); 1679 case 0: 1680 case 2: 1681 case 4: 1682 return ("AMD Athlon(tm)"); 1683 case 3: 1684 case 7: 1685 return ("AMD Duron(tm)"); 1686 case 6: 1687 case 8: 1688 case 10: 1689 /* 1690 * Use the L2 cache size to distinguish 1691 */ 1692 return ((cpi->cpi_extd[6].cp_ecx >> 16) >= 256 ? 1693 "AMD Athlon(tm)" : "AMD Duron(tm)"); 1694 default: 1695 return ("AMD (family 6)"); 1696 } 1697 default: 1698 break; 1699 } 1700 1701 if (cpi->cpi_family == 0xf && cpi->cpi_model == 5 && 1702 cpi->cpi_brandid != 0) { 1703 switch (BITX(cpi->cpi_brandid, 7, 5)) { 1704 case 3: 1705 return ("AMD Opteron(tm) UP 1xx"); 1706 case 4: 1707 return ("AMD Opteron(tm) DP 2xx"); 1708 case 5: 1709 return ("AMD Opteron(tm) MP 8xx"); 1710 default: 1711 return ("AMD Opteron(tm)"); 1712 } 1713 } 1714 1715 return (NULL); 1716 } 1717 1718 static const char * 1719 cyrix_cpubrand(struct cpuid_info *cpi, uint_t type) 1720 { 1721 if ((x86_feature & X86_CPUID) == 0 || 1722 cpi->cpi_maxeax < 1 || cpi->cpi_family < 5 || 1723 type == X86_TYPE_CYRIX_486) 1724 return ("i486 compatible"); 1725 1726 switch (type) { 1727 case X86_TYPE_CYRIX_6x86: 1728 return ("Cyrix 6x86"); 1729 case X86_TYPE_CYRIX_6x86L: 1730 return ("Cyrix 6x86L"); 1731 case X86_TYPE_CYRIX_6x86MX: 1732 return ("Cyrix 6x86MX"); 1733 case X86_TYPE_CYRIX_GXm: 1734 return ("Cyrix GXm"); 1735 case X86_TYPE_CYRIX_MediaGX: 1736 return ("Cyrix MediaGX"); 1737 case X86_TYPE_CYRIX_MII: 1738 return ("Cyrix M2"); 1739 case X86_TYPE_VIA_CYRIX_III: 1740 return ("VIA Cyrix M3"); 1741 default: 1742 /* 1743 * Have another wild guess .. 1744 */ 1745 if (cpi->cpi_family == 4 && cpi->cpi_model == 9) 1746 return ("Cyrix 5x86"); 1747 else if (cpi->cpi_family == 5) { 1748 switch (cpi->cpi_model) { 1749 case 2: 1750 return ("Cyrix 6x86"); /* Cyrix M1 */ 1751 case 4: 1752 return ("Cyrix MediaGX"); 1753 default: 1754 break; 1755 } 1756 } else if (cpi->cpi_family == 6) { 1757 switch (cpi->cpi_model) { 1758 case 0: 1759 return ("Cyrix 6x86MX"); /* Cyrix M2? */ 1760 case 5: 1761 case 6: 1762 case 7: 1763 case 8: 1764 case 9: 1765 return ("VIA C3"); 1766 default: 1767 break; 1768 } 1769 } 1770 break; 1771 } 1772 return (NULL); 1773 } 1774 1775 /* 1776 * This only gets called in the case that the CPU extended 1777 * feature brand string (0x80000002, 0x80000003, 0x80000004) 1778 * aren't available, or contain null bytes for some reason. 1779 */ 1780 static void 1781 fabricate_brandstr(struct cpuid_info *cpi) 1782 { 1783 const char *brand = NULL; 1784 1785 switch (cpi->cpi_vendor) { 1786 case X86_VENDOR_Intel: 1787 brand = intel_cpubrand(cpi); 1788 break; 1789 case X86_VENDOR_AMD: 1790 brand = amd_cpubrand(cpi); 1791 break; 1792 case X86_VENDOR_Cyrix: 1793 brand = cyrix_cpubrand(cpi, x86_type); 1794 break; 1795 case X86_VENDOR_NexGen: 1796 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1797 brand = "NexGen Nx586"; 1798 break; 1799 case X86_VENDOR_Centaur: 1800 if (cpi->cpi_family == 5) 1801 switch (cpi->cpi_model) { 1802 case 4: 1803 brand = "Centaur C6"; 1804 break; 1805 case 8: 1806 brand = "Centaur C2"; 1807 break; 1808 case 9: 1809 brand = "Centaur C3"; 1810 break; 1811 default: 1812 break; 1813 } 1814 break; 1815 case X86_VENDOR_Rise: 1816 if (cpi->cpi_family == 5 && 1817 (cpi->cpi_model == 0 || cpi->cpi_model == 2)) 1818 brand = "Rise mP6"; 1819 break; 1820 case X86_VENDOR_SiS: 1821 if (cpi->cpi_family == 5 && cpi->cpi_model == 0) 1822 brand = "SiS 55x"; 1823 break; 1824 case X86_VENDOR_TM: 1825 if (cpi->cpi_family == 5 && cpi->cpi_model == 4) 1826 brand = "Transmeta Crusoe TM3x00 or TM5x00"; 1827 break; 1828 case X86_VENDOR_NSC: 1829 case X86_VENDOR_UMC: 1830 default: 1831 break; 1832 } 1833 if (brand) { 1834 (void) strcpy((char *)cpi->cpi_brandstr, brand); 1835 return; 1836 } 1837 1838 /* 1839 * If all else fails ... 1840 */ 1841 (void) snprintf(cpi->cpi_brandstr, sizeof (cpi->cpi_brandstr), 1842 "%s %d.%d.%d", cpi->cpi_vendorstr, cpi->cpi_family, 1843 cpi->cpi_model, cpi->cpi_step); 1844 } 1845 1846 /* 1847 * This routine is called just after kernel memory allocation 1848 * becomes available on cpu0, and as part of mp_startup() on 1849 * the other cpus. 1850 * 1851 * Fixup the brand string, and collect any information from cpuid 1852 * that requires dynamicically allocated storage to represent. 1853 */ 1854 /*ARGSUSED*/ 1855 void 1856 cpuid_pass3(cpu_t *cpu) 1857 { 1858 int i, max, shft, level, size; 1859 struct cpuid_regs regs; 1860 struct cpuid_regs *cp; 1861 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 1862 1863 ASSERT(cpi->cpi_pass == 2); 1864 1865 /* 1866 * Function 4: Deterministic cache parameters 1867 * 1868 * Take this opportunity to detect the number of threads 1869 * sharing the last level cache, and construct a corresponding 1870 * cache id. The respective cpuid_info members are initialized 1871 * to the default case of "no last level cache sharing". 1872 */ 1873 cpi->cpi_ncpu_shr_last_cache = 1; 1874 cpi->cpi_last_lvl_cacheid = cpu->cpu_id; 1875 1876 if (cpi->cpi_maxeax >= 4 && cpi->cpi_vendor == X86_VENDOR_Intel) { 1877 1878 /* 1879 * Find the # of elements (size) returned by fn 4, and along 1880 * the way detect last level cache sharing details. 1881 */ 1882 bzero(®s, sizeof (regs)); 1883 cp = ®s; 1884 for (i = 0, max = 0; i < CPI_FN4_ECX_MAX; i++) { 1885 cp->cp_eax = 4; 1886 cp->cp_ecx = i; 1887 1888 (void) __cpuid_insn(cp); 1889 1890 if (CPI_CACHE_TYPE(cp) == 0) 1891 break; 1892 level = CPI_CACHE_LVL(cp); 1893 if (level > max) { 1894 max = level; 1895 cpi->cpi_ncpu_shr_last_cache = 1896 CPI_NTHR_SHR_CACHE(cp) + 1; 1897 } 1898 } 1899 cpi->cpi_std_4_size = size = i; 1900 1901 /* 1902 * Allocate the cpi_std_4 array. The first element 1903 * references the regs for fn 4, %ecx == 0, which 1904 * cpuid_pass2() stashed in cpi->cpi_std[4]. 1905 */ 1906 if (size > 0) { 1907 cpi->cpi_std_4 = 1908 kmem_alloc(size * sizeof (cp), KM_SLEEP); 1909 cpi->cpi_std_4[0] = &cpi->cpi_std[4]; 1910 1911 /* 1912 * Allocate storage to hold the additional regs 1913 * for function 4, %ecx == 1 .. cpi_std_4_size. 1914 * 1915 * The regs for fn 4, %ecx == 0 has already 1916 * been allocated as indicated above. 1917 */ 1918 for (i = 1; i < size; i++) { 1919 cp = cpi->cpi_std_4[i] = 1920 kmem_zalloc(sizeof (regs), KM_SLEEP); 1921 cp->cp_eax = 4; 1922 cp->cp_ecx = i; 1923 1924 (void) __cpuid_insn(cp); 1925 } 1926 } 1927 /* 1928 * Determine the number of bits needed to represent 1929 * the number of CPUs sharing the last level cache. 1930 * 1931 * Shift off that number of bits from the APIC id to 1932 * derive the cache id. 1933 */ 1934 shft = 0; 1935 for (i = 1; i < cpi->cpi_ncpu_shr_last_cache; i <<= 1) 1936 shft++; 1937 cpi->cpi_last_lvl_cacheid = cpi->cpi_apicid >> shft; 1938 } 1939 1940 /* 1941 * Now fixup the brand string 1942 */ 1943 if ((cpi->cpi_xmaxeax & 0x80000000) == 0) { 1944 fabricate_brandstr(cpi); 1945 } else { 1946 1947 /* 1948 * If we successfully extracted a brand string from the cpuid 1949 * instruction, clean it up by removing leading spaces and 1950 * similar junk. 1951 */ 1952 if (cpi->cpi_brandstr[0]) { 1953 size_t maxlen = sizeof (cpi->cpi_brandstr); 1954 char *src, *dst; 1955 1956 dst = src = (char *)cpi->cpi_brandstr; 1957 src[maxlen - 1] = '\0'; 1958 /* 1959 * strip leading spaces 1960 */ 1961 while (*src == ' ') 1962 src++; 1963 /* 1964 * Remove any 'Genuine' or "Authentic" prefixes 1965 */ 1966 if (strncmp(src, "Genuine ", 8) == 0) 1967 src += 8; 1968 if (strncmp(src, "Authentic ", 10) == 0) 1969 src += 10; 1970 1971 /* 1972 * Now do an in-place copy. 1973 * Map (R) to (r) and (TM) to (tm). 1974 * The era of teletypes is long gone, and there's 1975 * -really- no need to shout. 1976 */ 1977 while (*src != '\0') { 1978 if (src[0] == '(') { 1979 if (strncmp(src + 1, "R)", 2) == 0) { 1980 (void) strncpy(dst, "(r)", 3); 1981 src += 3; 1982 dst += 3; 1983 continue; 1984 } 1985 if (strncmp(src + 1, "TM)", 3) == 0) { 1986 (void) strncpy(dst, "(tm)", 4); 1987 src += 4; 1988 dst += 4; 1989 continue; 1990 } 1991 } 1992 *dst++ = *src++; 1993 } 1994 *dst = '\0'; 1995 1996 /* 1997 * Finally, remove any trailing spaces 1998 */ 1999 while (--dst > cpi->cpi_brandstr) 2000 if (*dst == ' ') 2001 *dst = '\0'; 2002 else 2003 break; 2004 } else 2005 fabricate_brandstr(cpi); 2006 } 2007 cpi->cpi_pass = 3; 2008 } 2009 2010 /* 2011 * This routine is called out of bind_hwcap() much later in the life 2012 * of the kernel (post_startup()). The job of this routine is to resolve 2013 * the hardware feature support and kernel support for those features into 2014 * what we're actually going to tell applications via the aux vector. 2015 */ 2016 uint_t 2017 cpuid_pass4(cpu_t *cpu) 2018 { 2019 struct cpuid_info *cpi; 2020 uint_t hwcap_flags = 0; 2021 2022 if (cpu == NULL) 2023 cpu = CPU; 2024 cpi = cpu->cpu_m.mcpu_cpi; 2025 2026 ASSERT(cpi->cpi_pass == 3); 2027 2028 if (cpi->cpi_maxeax >= 1) { 2029 uint32_t *edx = &cpi->cpi_support[STD_EDX_FEATURES]; 2030 uint32_t *ecx = &cpi->cpi_support[STD_ECX_FEATURES]; 2031 2032 *edx = CPI_FEATURES_EDX(cpi); 2033 *ecx = CPI_FEATURES_ECX(cpi); 2034 2035 /* 2036 * [these require explicit kernel support] 2037 */ 2038 if ((x86_feature & X86_SEP) == 0) 2039 *edx &= ~CPUID_INTC_EDX_SEP; 2040 2041 if ((x86_feature & X86_SSE) == 0) 2042 *edx &= ~(CPUID_INTC_EDX_FXSR|CPUID_INTC_EDX_SSE); 2043 if ((x86_feature & X86_SSE2) == 0) 2044 *edx &= ~CPUID_INTC_EDX_SSE2; 2045 2046 if ((x86_feature & X86_HTT) == 0) 2047 *edx &= ~CPUID_INTC_EDX_HTT; 2048 2049 if ((x86_feature & X86_SSE3) == 0) 2050 *ecx &= ~CPUID_INTC_ECX_SSE3; 2051 2052 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2053 if ((x86_feature & X86_SSSE3) == 0) 2054 *ecx &= ~CPUID_INTC_ECX_SSSE3; 2055 if ((x86_feature & X86_SSE4_1) == 0) 2056 *ecx &= ~CPUID_INTC_ECX_SSE4_1; 2057 if ((x86_feature & X86_SSE4_2) == 0) 2058 *ecx &= ~CPUID_INTC_ECX_SSE4_2; 2059 } 2060 2061 /* 2062 * [no explicit support required beyond x87 fp context] 2063 */ 2064 if (!fpu_exists) 2065 *edx &= ~(CPUID_INTC_EDX_FPU | CPUID_INTC_EDX_MMX); 2066 2067 /* 2068 * Now map the supported feature vector to things that we 2069 * think userland will care about. 2070 */ 2071 if (*edx & CPUID_INTC_EDX_SEP) 2072 hwcap_flags |= AV_386_SEP; 2073 if (*edx & CPUID_INTC_EDX_SSE) 2074 hwcap_flags |= AV_386_FXSR | AV_386_SSE; 2075 if (*edx & CPUID_INTC_EDX_SSE2) 2076 hwcap_flags |= AV_386_SSE2; 2077 if (*ecx & CPUID_INTC_ECX_SSE3) 2078 hwcap_flags |= AV_386_SSE3; 2079 if (cpi->cpi_vendor == X86_VENDOR_Intel) { 2080 if (*ecx & CPUID_INTC_ECX_SSSE3) 2081 hwcap_flags |= AV_386_SSSE3; 2082 if (*ecx & CPUID_INTC_ECX_SSE4_1) 2083 hwcap_flags |= AV_386_SSE4_1; 2084 if (*ecx & CPUID_INTC_ECX_SSE4_2) 2085 hwcap_flags |= AV_386_SSE4_2; 2086 if (*ecx & CPUID_INTC_ECX_MOVBE) 2087 hwcap_flags |= AV_386_MOVBE; 2088 } 2089 if (*ecx & CPUID_INTC_ECX_POPCNT) 2090 hwcap_flags |= AV_386_POPCNT; 2091 if (*edx & CPUID_INTC_EDX_FPU) 2092 hwcap_flags |= AV_386_FPU; 2093 if (*edx & CPUID_INTC_EDX_MMX) 2094 hwcap_flags |= AV_386_MMX; 2095 2096 if (*edx & CPUID_INTC_EDX_TSC) 2097 hwcap_flags |= AV_386_TSC; 2098 if (*edx & CPUID_INTC_EDX_CX8) 2099 hwcap_flags |= AV_386_CX8; 2100 if (*edx & CPUID_INTC_EDX_CMOV) 2101 hwcap_flags |= AV_386_CMOV; 2102 if (*ecx & CPUID_INTC_ECX_MON) 2103 hwcap_flags |= AV_386_MON; 2104 if (*ecx & CPUID_INTC_ECX_CX16) 2105 hwcap_flags |= AV_386_CX16; 2106 } 2107 2108 if (x86_feature & X86_HTT) 2109 hwcap_flags |= AV_386_PAUSE; 2110 2111 if (cpi->cpi_xmaxeax < 0x80000001) 2112 goto pass4_done; 2113 2114 switch (cpi->cpi_vendor) { 2115 struct cpuid_regs cp; 2116 uint32_t *edx, *ecx; 2117 2118 case X86_VENDOR_Intel: 2119 /* 2120 * Seems like Intel duplicated what we necessary 2121 * here to make the initial crop of 64-bit OS's work. 2122 * Hopefully, those are the only "extended" bits 2123 * they'll add. 2124 */ 2125 /*FALLTHROUGH*/ 2126 2127 case X86_VENDOR_AMD: 2128 edx = &cpi->cpi_support[AMD_EDX_FEATURES]; 2129 ecx = &cpi->cpi_support[AMD_ECX_FEATURES]; 2130 2131 *edx = CPI_FEATURES_XTD_EDX(cpi); 2132 *ecx = CPI_FEATURES_XTD_ECX(cpi); 2133 2134 /* 2135 * [these features require explicit kernel support] 2136 */ 2137 switch (cpi->cpi_vendor) { 2138 case X86_VENDOR_Intel: 2139 if ((x86_feature & X86_TSCP) == 0) 2140 *edx &= ~CPUID_AMD_EDX_TSCP; 2141 break; 2142 2143 case X86_VENDOR_AMD: 2144 if ((x86_feature & X86_TSCP) == 0) 2145 *edx &= ~CPUID_AMD_EDX_TSCP; 2146 if ((x86_feature & X86_SSE4A) == 0) 2147 *ecx &= ~CPUID_AMD_ECX_SSE4A; 2148 break; 2149 2150 default: 2151 break; 2152 } 2153 2154 /* 2155 * [no explicit support required beyond 2156 * x87 fp context and exception handlers] 2157 */ 2158 if (!fpu_exists) 2159 *edx &= ~(CPUID_AMD_EDX_MMXamd | 2160 CPUID_AMD_EDX_3DNow | CPUID_AMD_EDX_3DNowx); 2161 2162 if ((x86_feature & X86_NX) == 0) 2163 *edx &= ~CPUID_AMD_EDX_NX; 2164 #if !defined(__amd64) 2165 *edx &= ~CPUID_AMD_EDX_LM; 2166 #endif 2167 /* 2168 * Now map the supported feature vector to 2169 * things that we think userland will care about. 2170 */ 2171 #if defined(__amd64) 2172 if (*edx & CPUID_AMD_EDX_SYSC) 2173 hwcap_flags |= AV_386_AMD_SYSC; 2174 #endif 2175 if (*edx & CPUID_AMD_EDX_MMXamd) 2176 hwcap_flags |= AV_386_AMD_MMX; 2177 if (*edx & CPUID_AMD_EDX_3DNow) 2178 hwcap_flags |= AV_386_AMD_3DNow; 2179 if (*edx & CPUID_AMD_EDX_3DNowx) 2180 hwcap_flags |= AV_386_AMD_3DNowx; 2181 2182 switch (cpi->cpi_vendor) { 2183 case X86_VENDOR_AMD: 2184 if (*edx & CPUID_AMD_EDX_TSCP) 2185 hwcap_flags |= AV_386_TSCP; 2186 if (*ecx & CPUID_AMD_ECX_AHF64) 2187 hwcap_flags |= AV_386_AHF; 2188 if (*ecx & CPUID_AMD_ECX_SSE4A) 2189 hwcap_flags |= AV_386_AMD_SSE4A; 2190 if (*ecx & CPUID_AMD_ECX_LZCNT) 2191 hwcap_flags |= AV_386_AMD_LZCNT; 2192 break; 2193 2194 case X86_VENDOR_Intel: 2195 if (*edx & CPUID_AMD_EDX_TSCP) 2196 hwcap_flags |= AV_386_TSCP; 2197 /* 2198 * Aarrgh. 2199 * Intel uses a different bit in the same word. 2200 */ 2201 if (*ecx & CPUID_INTC_ECX_AHF64) 2202 hwcap_flags |= AV_386_AHF; 2203 break; 2204 2205 default: 2206 break; 2207 } 2208 break; 2209 2210 case X86_VENDOR_TM: 2211 cp.cp_eax = 0x80860001; 2212 (void) __cpuid_insn(&cp); 2213 cpi->cpi_support[TM_EDX_FEATURES] = cp.cp_edx; 2214 break; 2215 2216 default: 2217 break; 2218 } 2219 2220 pass4_done: 2221 cpi->cpi_pass = 4; 2222 return (hwcap_flags); 2223 } 2224 2225 2226 /* 2227 * Simulate the cpuid instruction using the data we previously 2228 * captured about this CPU. We try our best to return the truth 2229 * about the hardware, independently of kernel support. 2230 */ 2231 uint32_t 2232 cpuid_insn(cpu_t *cpu, struct cpuid_regs *cp) 2233 { 2234 struct cpuid_info *cpi; 2235 struct cpuid_regs *xcp; 2236 2237 if (cpu == NULL) 2238 cpu = CPU; 2239 cpi = cpu->cpu_m.mcpu_cpi; 2240 2241 ASSERT(cpuid_checkpass(cpu, 3)); 2242 2243 /* 2244 * CPUID data is cached in two separate places: cpi_std for standard 2245 * CPUID functions, and cpi_extd for extended CPUID functions. 2246 */ 2247 if (cp->cp_eax <= cpi->cpi_maxeax && cp->cp_eax < NMAX_CPI_STD) 2248 xcp = &cpi->cpi_std[cp->cp_eax]; 2249 else if (cp->cp_eax >= 0x80000000 && cp->cp_eax <= cpi->cpi_xmaxeax && 2250 cp->cp_eax < 0x80000000 + NMAX_CPI_EXTD) 2251 xcp = &cpi->cpi_extd[cp->cp_eax - 0x80000000]; 2252 else 2253 /* 2254 * The caller is asking for data from an input parameter which 2255 * the kernel has not cached. In this case we go fetch from 2256 * the hardware and return the data directly to the user. 2257 */ 2258 return (__cpuid_insn(cp)); 2259 2260 cp->cp_eax = xcp->cp_eax; 2261 cp->cp_ebx = xcp->cp_ebx; 2262 cp->cp_ecx = xcp->cp_ecx; 2263 cp->cp_edx = xcp->cp_edx; 2264 return (cp->cp_eax); 2265 } 2266 2267 int 2268 cpuid_checkpass(cpu_t *cpu, int pass) 2269 { 2270 return (cpu != NULL && cpu->cpu_m.mcpu_cpi != NULL && 2271 cpu->cpu_m.mcpu_cpi->cpi_pass >= pass); 2272 } 2273 2274 int 2275 cpuid_getbrandstr(cpu_t *cpu, char *s, size_t n) 2276 { 2277 ASSERT(cpuid_checkpass(cpu, 3)); 2278 2279 return (snprintf(s, n, "%s", cpu->cpu_m.mcpu_cpi->cpi_brandstr)); 2280 } 2281 2282 int 2283 cpuid_is_cmt(cpu_t *cpu) 2284 { 2285 if (cpu == NULL) 2286 cpu = CPU; 2287 2288 ASSERT(cpuid_checkpass(cpu, 1)); 2289 2290 return (cpu->cpu_m.mcpu_cpi->cpi_chipid >= 0); 2291 } 2292 2293 /* 2294 * AMD and Intel both implement the 64-bit variant of the syscall 2295 * instruction (syscallq), so if there's -any- support for syscall, 2296 * cpuid currently says "yes, we support this". 2297 * 2298 * However, Intel decided to -not- implement the 32-bit variant of the 2299 * syscall instruction, so we provide a predicate to allow our caller 2300 * to test that subtlety here. 2301 * 2302 * XXPV Currently, 32-bit syscall instructions don't work via the hypervisor, 2303 * even in the case where the hardware would in fact support it. 2304 */ 2305 /*ARGSUSED*/ 2306 int 2307 cpuid_syscall32_insn(cpu_t *cpu) 2308 { 2309 ASSERT(cpuid_checkpass((cpu == NULL ? CPU : cpu), 1)); 2310 2311 #if !defined(__xpv) 2312 if (cpu == NULL) 2313 cpu = CPU; 2314 2315 /*CSTYLED*/ 2316 { 2317 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2318 2319 if (cpi->cpi_vendor == X86_VENDOR_AMD && 2320 cpi->cpi_xmaxeax >= 0x80000001 && 2321 (CPI_FEATURES_XTD_EDX(cpi) & CPUID_AMD_EDX_SYSC)) 2322 return (1); 2323 } 2324 #endif 2325 return (0); 2326 } 2327 2328 int 2329 cpuid_getidstr(cpu_t *cpu, char *s, size_t n) 2330 { 2331 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2332 2333 static const char fmt[] = 2334 "x86 (%s %X family %d model %d step %d clock %d MHz)"; 2335 static const char fmt_ht[] = 2336 "x86 (chipid 0x%x %s %X family %d model %d step %d clock %d MHz)"; 2337 2338 ASSERT(cpuid_checkpass(cpu, 1)); 2339 2340 if (cpuid_is_cmt(cpu)) 2341 return (snprintf(s, n, fmt_ht, cpi->cpi_chipid, 2342 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2343 cpi->cpi_family, cpi->cpi_model, 2344 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2345 return (snprintf(s, n, fmt, 2346 cpi->cpi_vendorstr, cpi->cpi_std[1].cp_eax, 2347 cpi->cpi_family, cpi->cpi_model, 2348 cpi->cpi_step, cpu->cpu_type_info.pi_clock)); 2349 } 2350 2351 const char * 2352 cpuid_getvendorstr(cpu_t *cpu) 2353 { 2354 ASSERT(cpuid_checkpass(cpu, 1)); 2355 return ((const char *)cpu->cpu_m.mcpu_cpi->cpi_vendorstr); 2356 } 2357 2358 uint_t 2359 cpuid_getvendor(cpu_t *cpu) 2360 { 2361 ASSERT(cpuid_checkpass(cpu, 1)); 2362 return (cpu->cpu_m.mcpu_cpi->cpi_vendor); 2363 } 2364 2365 uint_t 2366 cpuid_getfamily(cpu_t *cpu) 2367 { 2368 ASSERT(cpuid_checkpass(cpu, 1)); 2369 return (cpu->cpu_m.mcpu_cpi->cpi_family); 2370 } 2371 2372 uint_t 2373 cpuid_getmodel(cpu_t *cpu) 2374 { 2375 ASSERT(cpuid_checkpass(cpu, 1)); 2376 return (cpu->cpu_m.mcpu_cpi->cpi_model); 2377 } 2378 2379 uint_t 2380 cpuid_get_ncpu_per_chip(cpu_t *cpu) 2381 { 2382 ASSERT(cpuid_checkpass(cpu, 1)); 2383 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_per_chip); 2384 } 2385 2386 uint_t 2387 cpuid_get_ncore_per_chip(cpu_t *cpu) 2388 { 2389 ASSERT(cpuid_checkpass(cpu, 1)); 2390 return (cpu->cpu_m.mcpu_cpi->cpi_ncore_per_chip); 2391 } 2392 2393 uint_t 2394 cpuid_get_ncpu_sharing_last_cache(cpu_t *cpu) 2395 { 2396 ASSERT(cpuid_checkpass(cpu, 2)); 2397 return (cpu->cpu_m.mcpu_cpi->cpi_ncpu_shr_last_cache); 2398 } 2399 2400 id_t 2401 cpuid_get_last_lvl_cacheid(cpu_t *cpu) 2402 { 2403 ASSERT(cpuid_checkpass(cpu, 2)); 2404 return (cpu->cpu_m.mcpu_cpi->cpi_last_lvl_cacheid); 2405 } 2406 2407 uint_t 2408 cpuid_getstep(cpu_t *cpu) 2409 { 2410 ASSERT(cpuid_checkpass(cpu, 1)); 2411 return (cpu->cpu_m.mcpu_cpi->cpi_step); 2412 } 2413 2414 uint_t 2415 cpuid_getsig(struct cpu *cpu) 2416 { 2417 ASSERT(cpuid_checkpass(cpu, 1)); 2418 return (cpu->cpu_m.mcpu_cpi->cpi_std[1].cp_eax); 2419 } 2420 2421 uint32_t 2422 cpuid_getchiprev(struct cpu *cpu) 2423 { 2424 ASSERT(cpuid_checkpass(cpu, 1)); 2425 return (cpu->cpu_m.mcpu_cpi->cpi_chiprev); 2426 } 2427 2428 const char * 2429 cpuid_getchiprevstr(struct cpu *cpu) 2430 { 2431 ASSERT(cpuid_checkpass(cpu, 1)); 2432 return (cpu->cpu_m.mcpu_cpi->cpi_chiprevstr); 2433 } 2434 2435 uint32_t 2436 cpuid_getsockettype(struct cpu *cpu) 2437 { 2438 ASSERT(cpuid_checkpass(cpu, 1)); 2439 return (cpu->cpu_m.mcpu_cpi->cpi_socket); 2440 } 2441 2442 int 2443 cpuid_get_chipid(cpu_t *cpu) 2444 { 2445 ASSERT(cpuid_checkpass(cpu, 1)); 2446 2447 if (cpuid_is_cmt(cpu)) 2448 return (cpu->cpu_m.mcpu_cpi->cpi_chipid); 2449 return (cpu->cpu_id); 2450 } 2451 2452 id_t 2453 cpuid_get_coreid(cpu_t *cpu) 2454 { 2455 ASSERT(cpuid_checkpass(cpu, 1)); 2456 return (cpu->cpu_m.mcpu_cpi->cpi_coreid); 2457 } 2458 2459 int 2460 cpuid_get_pkgcoreid(cpu_t *cpu) 2461 { 2462 ASSERT(cpuid_checkpass(cpu, 1)); 2463 return (cpu->cpu_m.mcpu_cpi->cpi_pkgcoreid); 2464 } 2465 2466 int 2467 cpuid_get_clogid(cpu_t *cpu) 2468 { 2469 ASSERT(cpuid_checkpass(cpu, 1)); 2470 return (cpu->cpu_m.mcpu_cpi->cpi_clogid); 2471 } 2472 2473 void 2474 cpuid_get_addrsize(cpu_t *cpu, uint_t *pabits, uint_t *vabits) 2475 { 2476 struct cpuid_info *cpi; 2477 2478 if (cpu == NULL) 2479 cpu = CPU; 2480 cpi = cpu->cpu_m.mcpu_cpi; 2481 2482 ASSERT(cpuid_checkpass(cpu, 1)); 2483 2484 if (pabits) 2485 *pabits = cpi->cpi_pabits; 2486 if (vabits) 2487 *vabits = cpi->cpi_vabits; 2488 } 2489 2490 /* 2491 * Returns the number of data TLB entries for a corresponding 2492 * pagesize. If it can't be computed, or isn't known, the 2493 * routine returns zero. If you ask about an architecturally 2494 * impossible pagesize, the routine will panic (so that the 2495 * hat implementor knows that things are inconsistent.) 2496 */ 2497 uint_t 2498 cpuid_get_dtlb_nent(cpu_t *cpu, size_t pagesize) 2499 { 2500 struct cpuid_info *cpi; 2501 uint_t dtlb_nent = 0; 2502 2503 if (cpu == NULL) 2504 cpu = CPU; 2505 cpi = cpu->cpu_m.mcpu_cpi; 2506 2507 ASSERT(cpuid_checkpass(cpu, 1)); 2508 2509 /* 2510 * Check the L2 TLB info 2511 */ 2512 if (cpi->cpi_xmaxeax >= 0x80000006) { 2513 struct cpuid_regs *cp = &cpi->cpi_extd[6]; 2514 2515 switch (pagesize) { 2516 2517 case 4 * 1024: 2518 /* 2519 * All zero in the top 16 bits of the register 2520 * indicates a unified TLB. Size is in low 16 bits. 2521 */ 2522 if ((cp->cp_ebx & 0xffff0000) == 0) 2523 dtlb_nent = cp->cp_ebx & 0x0000ffff; 2524 else 2525 dtlb_nent = BITX(cp->cp_ebx, 27, 16); 2526 break; 2527 2528 case 2 * 1024 * 1024: 2529 if ((cp->cp_eax & 0xffff0000) == 0) 2530 dtlb_nent = cp->cp_eax & 0x0000ffff; 2531 else 2532 dtlb_nent = BITX(cp->cp_eax, 27, 16); 2533 break; 2534 2535 default: 2536 panic("unknown L2 pagesize"); 2537 /*NOTREACHED*/ 2538 } 2539 } 2540 2541 if (dtlb_nent != 0) 2542 return (dtlb_nent); 2543 2544 /* 2545 * No L2 TLB support for this size, try L1. 2546 */ 2547 if (cpi->cpi_xmaxeax >= 0x80000005) { 2548 struct cpuid_regs *cp = &cpi->cpi_extd[5]; 2549 2550 switch (pagesize) { 2551 case 4 * 1024: 2552 dtlb_nent = BITX(cp->cp_ebx, 23, 16); 2553 break; 2554 case 2 * 1024 * 1024: 2555 dtlb_nent = BITX(cp->cp_eax, 23, 16); 2556 break; 2557 default: 2558 panic("unknown L1 d-TLB pagesize"); 2559 /*NOTREACHED*/ 2560 } 2561 } 2562 2563 return (dtlb_nent); 2564 } 2565 2566 /* 2567 * Return 0 if the erratum is not present or not applicable, positive 2568 * if it is, and negative if the status of the erratum is unknown. 2569 * 2570 * See "Revision Guide for AMD Athlon(tm) 64 and AMD Opteron(tm) 2571 * Processors" #25759, Rev 3.57, August 2005 2572 */ 2573 int 2574 cpuid_opteron_erratum(cpu_t *cpu, uint_t erratum) 2575 { 2576 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 2577 uint_t eax; 2578 2579 /* 2580 * Bail out if this CPU isn't an AMD CPU, or if it's 2581 * a legacy (32-bit) AMD CPU. 2582 */ 2583 if (cpi->cpi_vendor != X86_VENDOR_AMD || 2584 cpi->cpi_family == 4 || cpi->cpi_family == 5 || 2585 cpi->cpi_family == 6) 2586 2587 return (0); 2588 2589 eax = cpi->cpi_std[1].cp_eax; 2590 2591 #define SH_B0(eax) (eax == 0xf40 || eax == 0xf50) 2592 #define SH_B3(eax) (eax == 0xf51) 2593 #define B(eax) (SH_B0(eax) || SH_B3(eax)) 2594 2595 #define SH_C0(eax) (eax == 0xf48 || eax == 0xf58) 2596 2597 #define SH_CG(eax) (eax == 0xf4a || eax == 0xf5a || eax == 0xf7a) 2598 #define DH_CG(eax) (eax == 0xfc0 || eax == 0xfe0 || eax == 0xff0) 2599 #define CH_CG(eax) (eax == 0xf82 || eax == 0xfb2) 2600 #define CG(eax) (SH_CG(eax) || DH_CG(eax) || CH_CG(eax)) 2601 2602 #define SH_D0(eax) (eax == 0x10f40 || eax == 0x10f50 || eax == 0x10f70) 2603 #define DH_D0(eax) (eax == 0x10fc0 || eax == 0x10ff0) 2604 #define CH_D0(eax) (eax == 0x10f80 || eax == 0x10fb0) 2605 #define D0(eax) (SH_D0(eax) || DH_D0(eax) || CH_D0(eax)) 2606 2607 #define SH_E0(eax) (eax == 0x20f50 || eax == 0x20f40 || eax == 0x20f70) 2608 #define JH_E1(eax) (eax == 0x20f10) /* JH8_E0 had 0x20f30 */ 2609 #define DH_E3(eax) (eax == 0x20fc0 || eax == 0x20ff0) 2610 #define SH_E4(eax) (eax == 0x20f51 || eax == 0x20f71) 2611 #define BH_E4(eax) (eax == 0x20fb1) 2612 #define SH_E5(eax) (eax == 0x20f42) 2613 #define DH_E6(eax) (eax == 0x20ff2 || eax == 0x20fc2) 2614 #define JH_E6(eax) (eax == 0x20f12 || eax == 0x20f32) 2615 #define EX(eax) (SH_E0(eax) || JH_E1(eax) || DH_E3(eax) || \ 2616 SH_E4(eax) || BH_E4(eax) || SH_E5(eax) || \ 2617 DH_E6(eax) || JH_E6(eax)) 2618 2619 #define DR_AX(eax) (eax == 0x100f00 || eax == 0x100f01 || eax == 0x100f02) 2620 #define DR_B0(eax) (eax == 0x100f20) 2621 #define DR_B1(eax) (eax == 0x100f21) 2622 #define DR_BA(eax) (eax == 0x100f2a) 2623 #define DR_B2(eax) (eax == 0x100f22) 2624 #define DR_B3(eax) (eax == 0x100f23) 2625 #define RB_C0(eax) (eax == 0x100f40) 2626 2627 switch (erratum) { 2628 case 1: 2629 return (cpi->cpi_family < 0x10); 2630 case 51: /* what does the asterisk mean? */ 2631 return (B(eax) || SH_C0(eax) || CG(eax)); 2632 case 52: 2633 return (B(eax)); 2634 case 57: 2635 return (cpi->cpi_family <= 0x11); 2636 case 58: 2637 return (B(eax)); 2638 case 60: 2639 return (cpi->cpi_family <= 0x11); 2640 case 61: 2641 case 62: 2642 case 63: 2643 case 64: 2644 case 65: 2645 case 66: 2646 case 68: 2647 case 69: 2648 case 70: 2649 case 71: 2650 return (B(eax)); 2651 case 72: 2652 return (SH_B0(eax)); 2653 case 74: 2654 return (B(eax)); 2655 case 75: 2656 return (cpi->cpi_family < 0x10); 2657 case 76: 2658 return (B(eax)); 2659 case 77: 2660 return (cpi->cpi_family <= 0x11); 2661 case 78: 2662 return (B(eax) || SH_C0(eax)); 2663 case 79: 2664 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2665 case 80: 2666 case 81: 2667 case 82: 2668 return (B(eax)); 2669 case 83: 2670 return (B(eax) || SH_C0(eax) || CG(eax)); 2671 case 85: 2672 return (cpi->cpi_family < 0x10); 2673 case 86: 2674 return (SH_C0(eax) || CG(eax)); 2675 case 88: 2676 #if !defined(__amd64) 2677 return (0); 2678 #else 2679 return (B(eax) || SH_C0(eax)); 2680 #endif 2681 case 89: 2682 return (cpi->cpi_family < 0x10); 2683 case 90: 2684 return (B(eax) || SH_C0(eax) || CG(eax)); 2685 case 91: 2686 case 92: 2687 return (B(eax) || SH_C0(eax)); 2688 case 93: 2689 return (SH_C0(eax)); 2690 case 94: 2691 return (B(eax) || SH_C0(eax) || CG(eax)); 2692 case 95: 2693 #if !defined(__amd64) 2694 return (0); 2695 #else 2696 return (B(eax) || SH_C0(eax)); 2697 #endif 2698 case 96: 2699 return (B(eax) || SH_C0(eax) || CG(eax)); 2700 case 97: 2701 case 98: 2702 return (SH_C0(eax) || CG(eax)); 2703 case 99: 2704 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2705 case 100: 2706 return (B(eax) || SH_C0(eax)); 2707 case 101: 2708 case 103: 2709 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2710 case 104: 2711 return (SH_C0(eax) || CG(eax) || D0(eax)); 2712 case 105: 2713 case 106: 2714 case 107: 2715 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2716 case 108: 2717 return (DH_CG(eax)); 2718 case 109: 2719 return (SH_C0(eax) || CG(eax) || D0(eax)); 2720 case 110: 2721 return (D0(eax) || EX(eax)); 2722 case 111: 2723 return (CG(eax)); 2724 case 112: 2725 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2726 case 113: 2727 return (eax == 0x20fc0); 2728 case 114: 2729 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2730 case 115: 2731 return (SH_E0(eax) || JH_E1(eax)); 2732 case 116: 2733 return (SH_E0(eax) || JH_E1(eax) || DH_E3(eax)); 2734 case 117: 2735 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax)); 2736 case 118: 2737 return (SH_E0(eax) || JH_E1(eax) || SH_E4(eax) || BH_E4(eax) || 2738 JH_E6(eax)); 2739 case 121: 2740 return (B(eax) || SH_C0(eax) || CG(eax) || D0(eax) || EX(eax)); 2741 case 122: 2742 return (cpi->cpi_family < 0x10 || cpi->cpi_family == 0x11); 2743 case 123: 2744 return (JH_E1(eax) || BH_E4(eax) || JH_E6(eax)); 2745 case 131: 2746 return (cpi->cpi_family < 0x10); 2747 case 6336786: 2748 /* 2749 * Test for AdvPowerMgmtInfo.TscPStateInvariant 2750 * if this is a K8 family or newer processor 2751 */ 2752 if (CPI_FAMILY(cpi) == 0xf) { 2753 struct cpuid_regs regs; 2754 regs.cp_eax = 0x80000007; 2755 (void) __cpuid_insn(®s); 2756 return (!(regs.cp_edx & 0x100)); 2757 } 2758 return (0); 2759 case 6323525: 2760 return (((((eax >> 12) & 0xff00) + (eax & 0xf00)) | 2761 (((eax >> 4) & 0xf) | ((eax >> 12) & 0xf0))) < 0xf40); 2762 2763 case 6671130: 2764 /* 2765 * check for processors (pre-Shanghai) that do not provide 2766 * optimal management of 1gb ptes in its tlb. 2767 */ 2768 return (cpi->cpi_family == 0x10 && cpi->cpi_model < 4); 2769 2770 case 298: 2771 return (DR_AX(eax) || DR_B0(eax) || DR_B1(eax) || DR_BA(eax) || 2772 DR_B2(eax) || RB_C0(eax)); 2773 2774 default: 2775 return (-1); 2776 2777 } 2778 } 2779 2780 /* 2781 * Determine if specified erratum is present via OSVW (OS Visible Workaround). 2782 * Return 1 if erratum is present, 0 if not present and -1 if indeterminate. 2783 */ 2784 int 2785 osvw_opteron_erratum(cpu_t *cpu, uint_t erratum) 2786 { 2787 struct cpuid_info *cpi; 2788 uint_t osvwid; 2789 static int osvwfeature = -1; 2790 uint64_t osvwlength; 2791 2792 2793 cpi = cpu->cpu_m.mcpu_cpi; 2794 2795 /* confirm OSVW supported */ 2796 if (osvwfeature == -1) { 2797 osvwfeature = cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW; 2798 } else { 2799 /* assert that osvw feature setting is consistent on all cpus */ 2800 ASSERT(osvwfeature == 2801 (cpi->cpi_extd[1].cp_ecx & CPUID_AMD_ECX_OSVW)); 2802 } 2803 if (!osvwfeature) 2804 return (-1); 2805 2806 osvwlength = rdmsr(MSR_AMD_OSVW_ID_LEN) & OSVW_ID_LEN_MASK; 2807 2808 switch (erratum) { 2809 case 298: /* osvwid is 0 */ 2810 osvwid = 0; 2811 if (osvwlength <= (uint64_t)osvwid) { 2812 /* osvwid 0 is unknown */ 2813 return (-1); 2814 } 2815 2816 /* 2817 * Check the OSVW STATUS MSR to determine the state 2818 * of the erratum where: 2819 * 0 - fixed by HW 2820 * 1 - BIOS has applied the workaround when BIOS 2821 * workaround is available. (Or for other errata, 2822 * OS workaround is required.) 2823 * For a value of 1, caller will confirm that the 2824 * erratum 298 workaround has indeed been applied by BIOS. 2825 * 2826 * A 1 may be set in cpus that have a HW fix 2827 * in a mixed cpu system. Regarding erratum 298: 2828 * In a multiprocessor platform, the workaround above 2829 * should be applied to all processors regardless of 2830 * silicon revision when an affected processor is 2831 * present. 2832 */ 2833 2834 return (rdmsr(MSR_AMD_OSVW_STATUS + 2835 (osvwid / OSVW_ID_CNT_PER_MSR)) & 2836 (1ULL << (osvwid % OSVW_ID_CNT_PER_MSR))); 2837 2838 default: 2839 return (-1); 2840 } 2841 } 2842 2843 static const char assoc_str[] = "associativity"; 2844 static const char line_str[] = "line-size"; 2845 static const char size_str[] = "size"; 2846 2847 static void 2848 add_cache_prop(dev_info_t *devi, const char *label, const char *type, 2849 uint32_t val) 2850 { 2851 char buf[128]; 2852 2853 /* 2854 * ndi_prop_update_int() is used because it is desirable for 2855 * DDI_PROP_HW_DEF and DDI_PROP_DONTSLEEP to be set. 2856 */ 2857 if (snprintf(buf, sizeof (buf), "%s-%s", label, type) < sizeof (buf)) 2858 (void) ndi_prop_update_int(DDI_DEV_T_NONE, devi, buf, val); 2859 } 2860 2861 /* 2862 * Intel-style cache/tlb description 2863 * 2864 * Standard cpuid level 2 gives a randomly ordered 2865 * selection of tags that index into a table that describes 2866 * cache and tlb properties. 2867 */ 2868 2869 static const char l1_icache_str[] = "l1-icache"; 2870 static const char l1_dcache_str[] = "l1-dcache"; 2871 static const char l2_cache_str[] = "l2-cache"; 2872 static const char l3_cache_str[] = "l3-cache"; 2873 static const char itlb4k_str[] = "itlb-4K"; 2874 static const char dtlb4k_str[] = "dtlb-4K"; 2875 static const char itlb2M_str[] = "itlb-2M"; 2876 static const char itlb4M_str[] = "itlb-4M"; 2877 static const char dtlb4M_str[] = "dtlb-4M"; 2878 static const char dtlb24_str[] = "dtlb0-2M-4M"; 2879 static const char itlb424_str[] = "itlb-4K-2M-4M"; 2880 static const char itlb24_str[] = "itlb-2M-4M"; 2881 static const char dtlb44_str[] = "dtlb-4K-4M"; 2882 static const char sl1_dcache_str[] = "sectored-l1-dcache"; 2883 static const char sl2_cache_str[] = "sectored-l2-cache"; 2884 static const char itrace_str[] = "itrace-cache"; 2885 static const char sl3_cache_str[] = "sectored-l3-cache"; 2886 static const char sh_l2_tlb4k_str[] = "shared-l2-tlb-4k"; 2887 2888 static const struct cachetab { 2889 uint8_t ct_code; 2890 uint8_t ct_assoc; 2891 uint16_t ct_line_size; 2892 size_t ct_size; 2893 const char *ct_label; 2894 } intel_ctab[] = { 2895 /* 2896 * maintain descending order! 2897 * 2898 * Codes ignored - Reason 2899 * ---------------------- 2900 * 40H - intel_cpuid_4_cache_info() disambiguates l2/l3 cache 2901 * f0H/f1H - Currently we do not interpret prefetch size by design 2902 */ 2903 { 0xe4, 16, 64, 8*1024*1024, l3_cache_str}, 2904 { 0xe3, 16, 64, 4*1024*1024, l3_cache_str}, 2905 { 0xe2, 16, 64, 2*1024*1024, l3_cache_str}, 2906 { 0xde, 12, 64, 6*1024*1024, l3_cache_str}, 2907 { 0xdd, 12, 64, 3*1024*1024, l3_cache_str}, 2908 { 0xdc, 12, 64, ((1*1024*1024)+(512*1024)), l3_cache_str}, 2909 { 0xd8, 8, 64, 4*1024*1024, l3_cache_str}, 2910 { 0xd7, 8, 64, 2*1024*1024, l3_cache_str}, 2911 { 0xd6, 8, 64, 1*1024*1024, l3_cache_str}, 2912 { 0xd2, 4, 64, 2*1024*1024, l3_cache_str}, 2913 { 0xd1, 4, 64, 1*1024*1024, l3_cache_str}, 2914 { 0xd0, 4, 64, 512*1024, l3_cache_str}, 2915 { 0xca, 4, 0, 512, sh_l2_tlb4k_str}, 2916 { 0xc0, 4, 0, 8, dtlb44_str }, 2917 { 0xba, 4, 0, 64, dtlb4k_str }, 2918 { 0xb4, 4, 0, 256, dtlb4k_str }, 2919 { 0xb3, 4, 0, 128, dtlb4k_str }, 2920 { 0xb2, 4, 0, 64, itlb4k_str }, 2921 { 0xb0, 4, 0, 128, itlb4k_str }, 2922 { 0x87, 8, 64, 1024*1024, l2_cache_str}, 2923 { 0x86, 4, 64, 512*1024, l2_cache_str}, 2924 { 0x85, 8, 32, 2*1024*1024, l2_cache_str}, 2925 { 0x84, 8, 32, 1024*1024, l2_cache_str}, 2926 { 0x83, 8, 32, 512*1024, l2_cache_str}, 2927 { 0x82, 8, 32, 256*1024, l2_cache_str}, 2928 { 0x80, 8, 64, 512*1024, l2_cache_str}, 2929 { 0x7f, 2, 64, 512*1024, l2_cache_str}, 2930 { 0x7d, 8, 64, 2*1024*1024, sl2_cache_str}, 2931 { 0x7c, 8, 64, 1024*1024, sl2_cache_str}, 2932 { 0x7b, 8, 64, 512*1024, sl2_cache_str}, 2933 { 0x7a, 8, 64, 256*1024, sl2_cache_str}, 2934 { 0x79, 8, 64, 128*1024, sl2_cache_str}, 2935 { 0x78, 8, 64, 1024*1024, l2_cache_str}, 2936 { 0x73, 8, 0, 64*1024, itrace_str}, 2937 { 0x72, 8, 0, 32*1024, itrace_str}, 2938 { 0x71, 8, 0, 16*1024, itrace_str}, 2939 { 0x70, 8, 0, 12*1024, itrace_str}, 2940 { 0x68, 4, 64, 32*1024, sl1_dcache_str}, 2941 { 0x67, 4, 64, 16*1024, sl1_dcache_str}, 2942 { 0x66, 4, 64, 8*1024, sl1_dcache_str}, 2943 { 0x60, 8, 64, 16*1024, sl1_dcache_str}, 2944 { 0x5d, 0, 0, 256, dtlb44_str}, 2945 { 0x5c, 0, 0, 128, dtlb44_str}, 2946 { 0x5b, 0, 0, 64, dtlb44_str}, 2947 { 0x5a, 4, 0, 32, dtlb24_str}, 2948 { 0x59, 0, 0, 16, dtlb4k_str}, 2949 { 0x57, 4, 0, 16, dtlb4k_str}, 2950 { 0x56, 4, 0, 16, dtlb4M_str}, 2951 { 0x55, 0, 0, 7, itlb24_str}, 2952 { 0x52, 0, 0, 256, itlb424_str}, 2953 { 0x51, 0, 0, 128, itlb424_str}, 2954 { 0x50, 0, 0, 64, itlb424_str}, 2955 { 0x4f, 0, 0, 32, itlb4k_str}, 2956 { 0x4e, 24, 64, 6*1024*1024, l2_cache_str}, 2957 { 0x4d, 16, 64, 16*1024*1024, l3_cache_str}, 2958 { 0x4c, 12, 64, 12*1024*1024, l3_cache_str}, 2959 { 0x4b, 16, 64, 8*1024*1024, l3_cache_str}, 2960 { 0x4a, 12, 64, 6*1024*1024, l3_cache_str}, 2961 { 0x49, 16, 64, 4*1024*1024, l3_cache_str}, 2962 { 0x48, 12, 64, 3*1024*1024, l2_cache_str}, 2963 { 0x47, 8, 64, 8*1024*1024, l3_cache_str}, 2964 { 0x46, 4, 64, 4*1024*1024, l3_cache_str}, 2965 { 0x45, 4, 32, 2*1024*1024, l2_cache_str}, 2966 { 0x44, 4, 32, 1024*1024, l2_cache_str}, 2967 { 0x43, 4, 32, 512*1024, l2_cache_str}, 2968 { 0x42, 4, 32, 256*1024, l2_cache_str}, 2969 { 0x41, 4, 32, 128*1024, l2_cache_str}, 2970 { 0x3e, 4, 64, 512*1024, sl2_cache_str}, 2971 { 0x3d, 6, 64, 384*1024, sl2_cache_str}, 2972 { 0x3c, 4, 64, 256*1024, sl2_cache_str}, 2973 { 0x3b, 2, 64, 128*1024, sl2_cache_str}, 2974 { 0x3a, 6, 64, 192*1024, sl2_cache_str}, 2975 { 0x39, 4, 64, 128*1024, sl2_cache_str}, 2976 { 0x30, 8, 64, 32*1024, l1_icache_str}, 2977 { 0x2c, 8, 64, 32*1024, l1_dcache_str}, 2978 { 0x29, 8, 64, 4096*1024, sl3_cache_str}, 2979 { 0x25, 8, 64, 2048*1024, sl3_cache_str}, 2980 { 0x23, 8, 64, 1024*1024, sl3_cache_str}, 2981 { 0x22, 4, 64, 512*1024, sl3_cache_str}, 2982 { 0x0e, 6, 64, 24*1024, l1_dcache_str}, 2983 { 0x0d, 4, 32, 16*1024, l1_dcache_str}, 2984 { 0x0c, 4, 32, 16*1024, l1_dcache_str}, 2985 { 0x0b, 4, 0, 4, itlb4M_str}, 2986 { 0x0a, 2, 32, 8*1024, l1_dcache_str}, 2987 { 0x08, 4, 32, 16*1024, l1_icache_str}, 2988 { 0x06, 4, 32, 8*1024, l1_icache_str}, 2989 { 0x05, 4, 0, 32, dtlb4M_str}, 2990 { 0x04, 4, 0, 8, dtlb4M_str}, 2991 { 0x03, 4, 0, 64, dtlb4k_str}, 2992 { 0x02, 4, 0, 2, itlb4M_str}, 2993 { 0x01, 4, 0, 32, itlb4k_str}, 2994 { 0 } 2995 }; 2996 2997 static const struct cachetab cyrix_ctab[] = { 2998 { 0x70, 4, 0, 32, "tlb-4K" }, 2999 { 0x80, 4, 16, 16*1024, "l1-cache" }, 3000 { 0 } 3001 }; 3002 3003 /* 3004 * Search a cache table for a matching entry 3005 */ 3006 static const struct cachetab * 3007 find_cacheent(const struct cachetab *ct, uint_t code) 3008 { 3009 if (code != 0) { 3010 for (; ct->ct_code != 0; ct++) 3011 if (ct->ct_code <= code) 3012 break; 3013 if (ct->ct_code == code) 3014 return (ct); 3015 } 3016 return (NULL); 3017 } 3018 3019 /* 3020 * Populate cachetab entry with L2 or L3 cache-information using 3021 * cpuid function 4. This function is called from intel_walk_cacheinfo() 3022 * when descriptor 0x49 is encountered. It returns 0 if no such cache 3023 * information is found. 3024 */ 3025 static int 3026 intel_cpuid_4_cache_info(struct cachetab *ct, struct cpuid_info *cpi) 3027 { 3028 uint32_t level, i; 3029 int ret = 0; 3030 3031 for (i = 0; i < cpi->cpi_std_4_size; i++) { 3032 level = CPI_CACHE_LVL(cpi->cpi_std_4[i]); 3033 3034 if (level == 2 || level == 3) { 3035 ct->ct_assoc = CPI_CACHE_WAYS(cpi->cpi_std_4[i]) + 1; 3036 ct->ct_line_size = 3037 CPI_CACHE_COH_LN_SZ(cpi->cpi_std_4[i]) + 1; 3038 ct->ct_size = ct->ct_assoc * 3039 (CPI_CACHE_PARTS(cpi->cpi_std_4[i]) + 1) * 3040 ct->ct_line_size * 3041 (cpi->cpi_std_4[i]->cp_ecx + 1); 3042 3043 if (level == 2) { 3044 ct->ct_label = l2_cache_str; 3045 } else if (level == 3) { 3046 ct->ct_label = l3_cache_str; 3047 } 3048 ret = 1; 3049 } 3050 } 3051 3052 return (ret); 3053 } 3054 3055 /* 3056 * Walk the cacheinfo descriptor, applying 'func' to every valid element 3057 * The walk is terminated if the walker returns non-zero. 3058 */ 3059 static void 3060 intel_walk_cacheinfo(struct cpuid_info *cpi, 3061 void *arg, int (*func)(void *, const struct cachetab *)) 3062 { 3063 const struct cachetab *ct; 3064 struct cachetab des_49_ct, des_b1_ct; 3065 uint8_t *dp; 3066 int i; 3067 3068 if ((dp = cpi->cpi_cacheinfo) == NULL) 3069 return; 3070 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3071 /* 3072 * For overloaded descriptor 0x49 we use cpuid function 4 3073 * if supported by the current processor, to create 3074 * cache information. 3075 * For overloaded descriptor 0xb1 we use X86_PAE flag 3076 * to disambiguate the cache information. 3077 */ 3078 if (*dp == 0x49 && cpi->cpi_maxeax >= 0x4 && 3079 intel_cpuid_4_cache_info(&des_49_ct, cpi) == 1) { 3080 ct = &des_49_ct; 3081 } else if (*dp == 0xb1) { 3082 des_b1_ct.ct_code = 0xb1; 3083 des_b1_ct.ct_assoc = 4; 3084 des_b1_ct.ct_line_size = 0; 3085 if (x86_feature & X86_PAE) { 3086 des_b1_ct.ct_size = 8; 3087 des_b1_ct.ct_label = itlb2M_str; 3088 } else { 3089 des_b1_ct.ct_size = 4; 3090 des_b1_ct.ct_label = itlb4M_str; 3091 } 3092 ct = &des_b1_ct; 3093 } else { 3094 if ((ct = find_cacheent(intel_ctab, *dp)) == NULL) { 3095 continue; 3096 } 3097 } 3098 3099 if (func(arg, ct) != 0) { 3100 break; 3101 } 3102 } 3103 } 3104 3105 /* 3106 * (Like the Intel one, except for Cyrix CPUs) 3107 */ 3108 static void 3109 cyrix_walk_cacheinfo(struct cpuid_info *cpi, 3110 void *arg, int (*func)(void *, const struct cachetab *)) 3111 { 3112 const struct cachetab *ct; 3113 uint8_t *dp; 3114 int i; 3115 3116 if ((dp = cpi->cpi_cacheinfo) == NULL) 3117 return; 3118 for (i = 0; i < cpi->cpi_ncache; i++, dp++) { 3119 /* 3120 * Search Cyrix-specific descriptor table first .. 3121 */ 3122 if ((ct = find_cacheent(cyrix_ctab, *dp)) != NULL) { 3123 if (func(arg, ct) != 0) 3124 break; 3125 continue; 3126 } 3127 /* 3128 * .. else fall back to the Intel one 3129 */ 3130 if ((ct = find_cacheent(intel_ctab, *dp)) != NULL) { 3131 if (func(arg, ct) != 0) 3132 break; 3133 continue; 3134 } 3135 } 3136 } 3137 3138 /* 3139 * A cacheinfo walker that adds associativity, line-size, and size properties 3140 * to the devinfo node it is passed as an argument. 3141 */ 3142 static int 3143 add_cacheent_props(void *arg, const struct cachetab *ct) 3144 { 3145 dev_info_t *devi = arg; 3146 3147 add_cache_prop(devi, ct->ct_label, assoc_str, ct->ct_assoc); 3148 if (ct->ct_line_size != 0) 3149 add_cache_prop(devi, ct->ct_label, line_str, 3150 ct->ct_line_size); 3151 add_cache_prop(devi, ct->ct_label, size_str, ct->ct_size); 3152 return (0); 3153 } 3154 3155 3156 static const char fully_assoc[] = "fully-associative?"; 3157 3158 /* 3159 * AMD style cache/tlb description 3160 * 3161 * Extended functions 5 and 6 directly describe properties of 3162 * tlbs and various cache levels. 3163 */ 3164 static void 3165 add_amd_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3166 { 3167 switch (assoc) { 3168 case 0: /* reserved; ignore */ 3169 break; 3170 default: 3171 add_cache_prop(devi, label, assoc_str, assoc); 3172 break; 3173 case 0xff: 3174 add_cache_prop(devi, label, fully_assoc, 1); 3175 break; 3176 } 3177 } 3178 3179 static void 3180 add_amd_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3181 { 3182 if (size == 0) 3183 return; 3184 add_cache_prop(devi, label, size_str, size); 3185 add_amd_assoc(devi, label, assoc); 3186 } 3187 3188 static void 3189 add_amd_cache(dev_info_t *devi, const char *label, 3190 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3191 { 3192 if (size == 0 || line_size == 0) 3193 return; 3194 add_amd_assoc(devi, label, assoc); 3195 /* 3196 * Most AMD parts have a sectored cache. Multiple cache lines are 3197 * associated with each tag. A sector consists of all cache lines 3198 * associated with a tag. For example, the AMD K6-III has a sector 3199 * size of 2 cache lines per tag. 3200 */ 3201 if (lines_per_tag != 0) 3202 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3203 add_cache_prop(devi, label, line_str, line_size); 3204 add_cache_prop(devi, label, size_str, size * 1024); 3205 } 3206 3207 static void 3208 add_amd_l2_assoc(dev_info_t *devi, const char *label, uint_t assoc) 3209 { 3210 switch (assoc) { 3211 case 0: /* off */ 3212 break; 3213 case 1: 3214 case 2: 3215 case 4: 3216 add_cache_prop(devi, label, assoc_str, assoc); 3217 break; 3218 case 6: 3219 add_cache_prop(devi, label, assoc_str, 8); 3220 break; 3221 case 8: 3222 add_cache_prop(devi, label, assoc_str, 16); 3223 break; 3224 case 0xf: 3225 add_cache_prop(devi, label, fully_assoc, 1); 3226 break; 3227 default: /* reserved; ignore */ 3228 break; 3229 } 3230 } 3231 3232 static void 3233 add_amd_l2_tlb(dev_info_t *devi, const char *label, uint_t assoc, uint_t size) 3234 { 3235 if (size == 0 || assoc == 0) 3236 return; 3237 add_amd_l2_assoc(devi, label, assoc); 3238 add_cache_prop(devi, label, size_str, size); 3239 } 3240 3241 static void 3242 add_amd_l2_cache(dev_info_t *devi, const char *label, 3243 uint_t size, uint_t assoc, uint_t lines_per_tag, uint_t line_size) 3244 { 3245 if (size == 0 || assoc == 0 || line_size == 0) 3246 return; 3247 add_amd_l2_assoc(devi, label, assoc); 3248 if (lines_per_tag != 0) 3249 add_cache_prop(devi, label, "lines-per-tag", lines_per_tag); 3250 add_cache_prop(devi, label, line_str, line_size); 3251 add_cache_prop(devi, label, size_str, size * 1024); 3252 } 3253 3254 static void 3255 amd_cache_info(struct cpuid_info *cpi, dev_info_t *devi) 3256 { 3257 struct cpuid_regs *cp; 3258 3259 if (cpi->cpi_xmaxeax < 0x80000005) 3260 return; 3261 cp = &cpi->cpi_extd[5]; 3262 3263 /* 3264 * 4M/2M L1 TLB configuration 3265 * 3266 * We report the size for 2M pages because AMD uses two 3267 * TLB entries for one 4M page. 3268 */ 3269 add_amd_tlb(devi, "dtlb-2M", 3270 BITX(cp->cp_eax, 31, 24), BITX(cp->cp_eax, 23, 16)); 3271 add_amd_tlb(devi, "itlb-2M", 3272 BITX(cp->cp_eax, 15, 8), BITX(cp->cp_eax, 7, 0)); 3273 3274 /* 3275 * 4K L1 TLB configuration 3276 */ 3277 3278 switch (cpi->cpi_vendor) { 3279 uint_t nentries; 3280 case X86_VENDOR_TM: 3281 if (cpi->cpi_family >= 5) { 3282 /* 3283 * Crusoe processors have 256 TLB entries, but 3284 * cpuid data format constrains them to only 3285 * reporting 255 of them. 3286 */ 3287 if ((nentries = BITX(cp->cp_ebx, 23, 16)) == 255) 3288 nentries = 256; 3289 /* 3290 * Crusoe processors also have a unified TLB 3291 */ 3292 add_amd_tlb(devi, "tlb-4K", BITX(cp->cp_ebx, 31, 24), 3293 nentries); 3294 break; 3295 } 3296 /*FALLTHROUGH*/ 3297 default: 3298 add_amd_tlb(devi, itlb4k_str, 3299 BITX(cp->cp_ebx, 31, 24), BITX(cp->cp_ebx, 23, 16)); 3300 add_amd_tlb(devi, dtlb4k_str, 3301 BITX(cp->cp_ebx, 15, 8), BITX(cp->cp_ebx, 7, 0)); 3302 break; 3303 } 3304 3305 /* 3306 * data L1 cache configuration 3307 */ 3308 3309 add_amd_cache(devi, l1_dcache_str, 3310 BITX(cp->cp_ecx, 31, 24), BITX(cp->cp_ecx, 23, 16), 3311 BITX(cp->cp_ecx, 15, 8), BITX(cp->cp_ecx, 7, 0)); 3312 3313 /* 3314 * code L1 cache configuration 3315 */ 3316 3317 add_amd_cache(devi, l1_icache_str, 3318 BITX(cp->cp_edx, 31, 24), BITX(cp->cp_edx, 23, 16), 3319 BITX(cp->cp_edx, 15, 8), BITX(cp->cp_edx, 7, 0)); 3320 3321 if (cpi->cpi_xmaxeax < 0x80000006) 3322 return; 3323 cp = &cpi->cpi_extd[6]; 3324 3325 /* Check for a unified L2 TLB for large pages */ 3326 3327 if (BITX(cp->cp_eax, 31, 16) == 0) 3328 add_amd_l2_tlb(devi, "l2-tlb-2M", 3329 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3330 else { 3331 add_amd_l2_tlb(devi, "l2-dtlb-2M", 3332 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3333 add_amd_l2_tlb(devi, "l2-itlb-2M", 3334 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3335 } 3336 3337 /* Check for a unified L2 TLB for 4K pages */ 3338 3339 if (BITX(cp->cp_ebx, 31, 16) == 0) { 3340 add_amd_l2_tlb(devi, "l2-tlb-4K", 3341 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3342 } else { 3343 add_amd_l2_tlb(devi, "l2-dtlb-4K", 3344 BITX(cp->cp_eax, 31, 28), BITX(cp->cp_eax, 27, 16)); 3345 add_amd_l2_tlb(devi, "l2-itlb-4K", 3346 BITX(cp->cp_eax, 15, 12), BITX(cp->cp_eax, 11, 0)); 3347 } 3348 3349 add_amd_l2_cache(devi, l2_cache_str, 3350 BITX(cp->cp_ecx, 31, 16), BITX(cp->cp_ecx, 15, 12), 3351 BITX(cp->cp_ecx, 11, 8), BITX(cp->cp_ecx, 7, 0)); 3352 } 3353 3354 /* 3355 * There are two basic ways that the x86 world describes it cache 3356 * and tlb architecture - Intel's way and AMD's way. 3357 * 3358 * Return which flavor of cache architecture we should use 3359 */ 3360 static int 3361 x86_which_cacheinfo(struct cpuid_info *cpi) 3362 { 3363 switch (cpi->cpi_vendor) { 3364 case X86_VENDOR_Intel: 3365 if (cpi->cpi_maxeax >= 2) 3366 return (X86_VENDOR_Intel); 3367 break; 3368 case X86_VENDOR_AMD: 3369 /* 3370 * The K5 model 1 was the first part from AMD that reported 3371 * cache sizes via extended cpuid functions. 3372 */ 3373 if (cpi->cpi_family > 5 || 3374 (cpi->cpi_family == 5 && cpi->cpi_model >= 1)) 3375 return (X86_VENDOR_AMD); 3376 break; 3377 case X86_VENDOR_TM: 3378 if (cpi->cpi_family >= 5) 3379 return (X86_VENDOR_AMD); 3380 /*FALLTHROUGH*/ 3381 default: 3382 /* 3383 * If they have extended CPU data for 0x80000005 3384 * then we assume they have AMD-format cache 3385 * information. 3386 * 3387 * If not, and the vendor happens to be Cyrix, 3388 * then try our-Cyrix specific handler. 3389 * 3390 * If we're not Cyrix, then assume we're using Intel's 3391 * table-driven format instead. 3392 */ 3393 if (cpi->cpi_xmaxeax >= 0x80000005) 3394 return (X86_VENDOR_AMD); 3395 else if (cpi->cpi_vendor == X86_VENDOR_Cyrix) 3396 return (X86_VENDOR_Cyrix); 3397 else if (cpi->cpi_maxeax >= 2) 3398 return (X86_VENDOR_Intel); 3399 break; 3400 } 3401 return (-1); 3402 } 3403 3404 /* 3405 * create a node for the given cpu under the prom root node. 3406 * Also, create a cpu node in the device tree. 3407 */ 3408 static dev_info_t *cpu_nex_devi = NULL; 3409 static kmutex_t cpu_node_lock; 3410 3411 /* 3412 * Called from post_startup() and mp_startup() 3413 */ 3414 void 3415 add_cpunode2devtree(processorid_t cpu_id, struct cpuid_info *cpi) 3416 { 3417 dev_info_t *cpu_devi; 3418 int create; 3419 3420 mutex_enter(&cpu_node_lock); 3421 3422 /* 3423 * create a nexus node for all cpus identified as 'cpu_id' under 3424 * the root node. 3425 */ 3426 if (cpu_nex_devi == NULL) { 3427 if (ndi_devi_alloc(ddi_root_node(), "cpus", 3428 (pnode_t)DEVI_SID_NODEID, &cpu_nex_devi) != NDI_SUCCESS) { 3429 mutex_exit(&cpu_node_lock); 3430 return; 3431 } 3432 (void) ndi_devi_online(cpu_nex_devi, 0); 3433 } 3434 3435 /* 3436 * create a child node for cpu identified as 'cpu_id' 3437 */ 3438 cpu_devi = ddi_add_child(cpu_nex_devi, "cpu", DEVI_SID_NODEID, 3439 cpu_id); 3440 if (cpu_devi == NULL) { 3441 mutex_exit(&cpu_node_lock); 3442 return; 3443 } 3444 3445 /* device_type */ 3446 3447 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3448 "device_type", "cpu"); 3449 3450 /* reg */ 3451 3452 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3453 "reg", cpu_id); 3454 3455 /* cpu-mhz, and clock-frequency */ 3456 3457 if (cpu_freq > 0) { 3458 long long mul; 3459 3460 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3461 "cpu-mhz", cpu_freq); 3462 3463 if ((mul = cpu_freq * 1000000LL) <= INT_MAX) 3464 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3465 "clock-frequency", (int)mul); 3466 } 3467 3468 (void) ndi_devi_online(cpu_devi, 0); 3469 3470 if ((x86_feature & X86_CPUID) == 0) { 3471 mutex_exit(&cpu_node_lock); 3472 return; 3473 } 3474 3475 /* vendor-id */ 3476 3477 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3478 "vendor-id", cpi->cpi_vendorstr); 3479 3480 if (cpi->cpi_maxeax == 0) { 3481 mutex_exit(&cpu_node_lock); 3482 return; 3483 } 3484 3485 /* 3486 * family, model, and step 3487 */ 3488 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3489 "family", CPI_FAMILY(cpi)); 3490 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3491 "cpu-model", CPI_MODEL(cpi)); 3492 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3493 "stepping-id", CPI_STEP(cpi)); 3494 3495 /* type */ 3496 3497 switch (cpi->cpi_vendor) { 3498 case X86_VENDOR_Intel: 3499 create = 1; 3500 break; 3501 default: 3502 create = 0; 3503 break; 3504 } 3505 if (create) 3506 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3507 "type", CPI_TYPE(cpi)); 3508 3509 /* ext-family */ 3510 3511 switch (cpi->cpi_vendor) { 3512 case X86_VENDOR_Intel: 3513 case X86_VENDOR_AMD: 3514 create = cpi->cpi_family >= 0xf; 3515 break; 3516 default: 3517 create = 0; 3518 break; 3519 } 3520 if (create) 3521 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3522 "ext-family", CPI_FAMILY_XTD(cpi)); 3523 3524 /* ext-model */ 3525 3526 switch (cpi->cpi_vendor) { 3527 case X86_VENDOR_Intel: 3528 create = IS_EXTENDED_MODEL_INTEL(cpi); 3529 break; 3530 case X86_VENDOR_AMD: 3531 create = CPI_FAMILY(cpi) == 0xf; 3532 break; 3533 default: 3534 create = 0; 3535 break; 3536 } 3537 if (create) 3538 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3539 "ext-model", CPI_MODEL_XTD(cpi)); 3540 3541 /* generation */ 3542 3543 switch (cpi->cpi_vendor) { 3544 case X86_VENDOR_AMD: 3545 /* 3546 * AMD K5 model 1 was the first part to support this 3547 */ 3548 create = cpi->cpi_xmaxeax >= 0x80000001; 3549 break; 3550 default: 3551 create = 0; 3552 break; 3553 } 3554 if (create) 3555 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3556 "generation", BITX((cpi)->cpi_extd[1].cp_eax, 11, 8)); 3557 3558 /* brand-id */ 3559 3560 switch (cpi->cpi_vendor) { 3561 case X86_VENDOR_Intel: 3562 /* 3563 * brand id first appeared on Pentium III Xeon model 8, 3564 * and Celeron model 8 processors and Opteron 3565 */ 3566 create = cpi->cpi_family > 6 || 3567 (cpi->cpi_family == 6 && cpi->cpi_model >= 8); 3568 break; 3569 case X86_VENDOR_AMD: 3570 create = cpi->cpi_family >= 0xf; 3571 break; 3572 default: 3573 create = 0; 3574 break; 3575 } 3576 if (create && cpi->cpi_brandid != 0) { 3577 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3578 "brand-id", cpi->cpi_brandid); 3579 } 3580 3581 /* chunks, and apic-id */ 3582 3583 switch (cpi->cpi_vendor) { 3584 /* 3585 * first available on Pentium IV and Opteron (K8) 3586 */ 3587 case X86_VENDOR_Intel: 3588 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3589 break; 3590 case X86_VENDOR_AMD: 3591 create = cpi->cpi_family >= 0xf; 3592 break; 3593 default: 3594 create = 0; 3595 break; 3596 } 3597 if (create) { 3598 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3599 "chunks", CPI_CHUNKS(cpi)); 3600 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3601 "apic-id", cpi->cpi_apicid); 3602 if (cpi->cpi_chipid >= 0) { 3603 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3604 "chip#", cpi->cpi_chipid); 3605 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3606 "clog#", cpi->cpi_clogid); 3607 } 3608 } 3609 3610 /* cpuid-features */ 3611 3612 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3613 "cpuid-features", CPI_FEATURES_EDX(cpi)); 3614 3615 3616 /* cpuid-features-ecx */ 3617 3618 switch (cpi->cpi_vendor) { 3619 case X86_VENDOR_Intel: 3620 create = IS_NEW_F6(cpi) || cpi->cpi_family >= 0xf; 3621 break; 3622 default: 3623 create = 0; 3624 break; 3625 } 3626 if (create) 3627 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3628 "cpuid-features-ecx", CPI_FEATURES_ECX(cpi)); 3629 3630 /* ext-cpuid-features */ 3631 3632 switch (cpi->cpi_vendor) { 3633 case X86_VENDOR_Intel: 3634 case X86_VENDOR_AMD: 3635 case X86_VENDOR_Cyrix: 3636 case X86_VENDOR_TM: 3637 case X86_VENDOR_Centaur: 3638 create = cpi->cpi_xmaxeax >= 0x80000001; 3639 break; 3640 default: 3641 create = 0; 3642 break; 3643 } 3644 if (create) { 3645 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3646 "ext-cpuid-features", CPI_FEATURES_XTD_EDX(cpi)); 3647 (void) ndi_prop_update_int(DDI_DEV_T_NONE, cpu_devi, 3648 "ext-cpuid-features-ecx", CPI_FEATURES_XTD_ECX(cpi)); 3649 } 3650 3651 /* 3652 * Brand String first appeared in Intel Pentium IV, AMD K5 3653 * model 1, and Cyrix GXm. On earlier models we try and 3654 * simulate something similar .. so this string should always 3655 * same -something- about the processor, however lame. 3656 */ 3657 (void) ndi_prop_update_string(DDI_DEV_T_NONE, cpu_devi, 3658 "brand-string", cpi->cpi_brandstr); 3659 3660 /* 3661 * Finally, cache and tlb information 3662 */ 3663 switch (x86_which_cacheinfo(cpi)) { 3664 case X86_VENDOR_Intel: 3665 intel_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3666 break; 3667 case X86_VENDOR_Cyrix: 3668 cyrix_walk_cacheinfo(cpi, cpu_devi, add_cacheent_props); 3669 break; 3670 case X86_VENDOR_AMD: 3671 amd_cache_info(cpi, cpu_devi); 3672 break; 3673 default: 3674 break; 3675 } 3676 3677 mutex_exit(&cpu_node_lock); 3678 } 3679 3680 struct l2info { 3681 int *l2i_csz; 3682 int *l2i_lsz; 3683 int *l2i_assoc; 3684 int l2i_ret; 3685 }; 3686 3687 /* 3688 * A cacheinfo walker that fetches the size, line-size and associativity 3689 * of the L2 cache 3690 */ 3691 static int 3692 intel_l2cinfo(void *arg, const struct cachetab *ct) 3693 { 3694 struct l2info *l2i = arg; 3695 int *ip; 3696 3697 if (ct->ct_label != l2_cache_str && 3698 ct->ct_label != sl2_cache_str) 3699 return (0); /* not an L2 -- keep walking */ 3700 3701 if ((ip = l2i->l2i_csz) != NULL) 3702 *ip = ct->ct_size; 3703 if ((ip = l2i->l2i_lsz) != NULL) 3704 *ip = ct->ct_line_size; 3705 if ((ip = l2i->l2i_assoc) != NULL) 3706 *ip = ct->ct_assoc; 3707 l2i->l2i_ret = ct->ct_size; 3708 return (1); /* was an L2 -- terminate walk */ 3709 } 3710 3711 /* 3712 * AMD L2/L3 Cache and TLB Associativity Field Definition: 3713 * 3714 * Unlike the associativity for the L1 cache and tlb where the 8 bit 3715 * value is the associativity, the associativity for the L2 cache and 3716 * tlb is encoded in the following table. The 4 bit L2 value serves as 3717 * an index into the amd_afd[] array to determine the associativity. 3718 * -1 is undefined. 0 is fully associative. 3719 */ 3720 3721 static int amd_afd[] = 3722 {-1, 1, 2, -1, 4, -1, 8, -1, 16, -1, 32, 48, 64, 96, 128, 0}; 3723 3724 static void 3725 amd_l2cacheinfo(struct cpuid_info *cpi, struct l2info *l2i) 3726 { 3727 struct cpuid_regs *cp; 3728 uint_t size, assoc; 3729 int i; 3730 int *ip; 3731 3732 if (cpi->cpi_xmaxeax < 0x80000006) 3733 return; 3734 cp = &cpi->cpi_extd[6]; 3735 3736 if ((i = BITX(cp->cp_ecx, 15, 12)) != 0 && 3737 (size = BITX(cp->cp_ecx, 31, 16)) != 0) { 3738 uint_t cachesz = size * 1024; 3739 assoc = amd_afd[i]; 3740 3741 ASSERT(assoc != -1); 3742 3743 if ((ip = l2i->l2i_csz) != NULL) 3744 *ip = cachesz; 3745 if ((ip = l2i->l2i_lsz) != NULL) 3746 *ip = BITX(cp->cp_ecx, 7, 0); 3747 if ((ip = l2i->l2i_assoc) != NULL) 3748 *ip = assoc; 3749 l2i->l2i_ret = cachesz; 3750 } 3751 } 3752 3753 int 3754 getl2cacheinfo(cpu_t *cpu, int *csz, int *lsz, int *assoc) 3755 { 3756 struct cpuid_info *cpi = cpu->cpu_m.mcpu_cpi; 3757 struct l2info __l2info, *l2i = &__l2info; 3758 3759 l2i->l2i_csz = csz; 3760 l2i->l2i_lsz = lsz; 3761 l2i->l2i_assoc = assoc; 3762 l2i->l2i_ret = -1; 3763 3764 switch (x86_which_cacheinfo(cpi)) { 3765 case X86_VENDOR_Intel: 3766 intel_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3767 break; 3768 case X86_VENDOR_Cyrix: 3769 cyrix_walk_cacheinfo(cpi, l2i, intel_l2cinfo); 3770 break; 3771 case X86_VENDOR_AMD: 3772 amd_l2cacheinfo(cpi, l2i); 3773 break; 3774 default: 3775 break; 3776 } 3777 return (l2i->l2i_ret); 3778 } 3779 3780 #if !defined(__xpv) 3781 3782 uint32_t * 3783 cpuid_mwait_alloc(cpu_t *cpu) 3784 { 3785 uint32_t *ret; 3786 size_t mwait_size; 3787 3788 ASSERT(cpuid_checkpass(cpu, 2)); 3789 3790 mwait_size = cpu->cpu_m.mcpu_cpi->cpi_mwait.mon_max; 3791 if (mwait_size == 0) 3792 return (NULL); 3793 3794 /* 3795 * kmem_alloc() returns cache line size aligned data for mwait_size 3796 * allocations. mwait_size is currently cache line sized. Neither 3797 * of these implementation details are guarantied to be true in the 3798 * future. 3799 * 3800 * First try allocating mwait_size as kmem_alloc() currently returns 3801 * correctly aligned memory. If kmem_alloc() does not return 3802 * mwait_size aligned memory, then use mwait_size ROUNDUP. 3803 * 3804 * Set cpi_mwait.buf_actual and cpi_mwait.size_actual in case we 3805 * decide to free this memory. 3806 */ 3807 ret = kmem_zalloc(mwait_size, KM_SLEEP); 3808 if (ret == (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size)) { 3809 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3810 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size; 3811 *ret = MWAIT_RUNNING; 3812 return (ret); 3813 } else { 3814 kmem_free(ret, mwait_size); 3815 ret = kmem_zalloc(mwait_size * 2, KM_SLEEP); 3816 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = ret; 3817 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = mwait_size * 2; 3818 ret = (uint32_t *)P2ROUNDUP((uintptr_t)ret, mwait_size); 3819 *ret = MWAIT_RUNNING; 3820 return (ret); 3821 } 3822 } 3823 3824 void 3825 cpuid_mwait_free(cpu_t *cpu) 3826 { 3827 ASSERT(cpuid_checkpass(cpu, 2)); 3828 3829 if (cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual != NULL && 3830 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual > 0) { 3831 kmem_free(cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual, 3832 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual); 3833 } 3834 3835 cpu->cpu_m.mcpu_cpi->cpi_mwait.buf_actual = NULL; 3836 cpu->cpu_m.mcpu_cpi->cpi_mwait.size_actual = 0; 3837 } 3838 3839 void 3840 patch_tsc_read(int flag) 3841 { 3842 size_t cnt; 3843 3844 switch (flag) { 3845 case X86_NO_TSC: 3846 cnt = &_no_rdtsc_end - &_no_rdtsc_start; 3847 (void) memcpy((void *)tsc_read, (void *)&_no_rdtsc_start, cnt); 3848 break; 3849 case X86_HAVE_TSCP: 3850 cnt = &_tscp_end - &_tscp_start; 3851 (void) memcpy((void *)tsc_read, (void *)&_tscp_start, cnt); 3852 break; 3853 case X86_TSC_MFENCE: 3854 cnt = &_tsc_mfence_end - &_tsc_mfence_start; 3855 (void) memcpy((void *)tsc_read, 3856 (void *)&_tsc_mfence_start, cnt); 3857 break; 3858 case X86_TSC_LFENCE: 3859 cnt = &_tsc_lfence_end - &_tsc_lfence_start; 3860 (void) memcpy((void *)tsc_read, 3861 (void *)&_tsc_lfence_start, cnt); 3862 break; 3863 default: 3864 break; 3865 } 3866 } 3867 3868 int 3869 cpuid_deep_cstates_supported(void) 3870 { 3871 struct cpuid_info *cpi; 3872 struct cpuid_regs regs; 3873 3874 ASSERT(cpuid_checkpass(CPU, 1)); 3875 3876 cpi = CPU->cpu_m.mcpu_cpi; 3877 3878 if (!(x86_feature & X86_CPUID)) 3879 return (0); 3880 3881 switch (cpi->cpi_vendor) { 3882 case X86_VENDOR_Intel: 3883 if (cpi->cpi_xmaxeax < 0x80000007) 3884 return (0); 3885 3886 /* 3887 * TSC run at a constant rate in all ACPI C-states? 3888 */ 3889 regs.cp_eax = 0x80000007; 3890 (void) __cpuid_insn(®s); 3891 return (regs.cp_edx & CPUID_TSC_CSTATE_INVARIANCE); 3892 3893 default: 3894 return (0); 3895 } 3896 } 3897 3898 #endif /* !__xpv */ 3899 3900 void 3901 post_startup_cpu_fixups(void) 3902 { 3903 #ifndef __xpv 3904 /* 3905 * Some AMD processors support C1E state. Entering this state will 3906 * cause the local APIC timer to stop, which we can't deal with at 3907 * this time. 3908 */ 3909 if (cpuid_getvendor(CPU) == X86_VENDOR_AMD) { 3910 on_trap_data_t otd; 3911 uint64_t reg; 3912 3913 if (!on_trap(&otd, OT_DATA_ACCESS)) { 3914 reg = rdmsr(MSR_AMD_INT_PENDING_CMP_HALT); 3915 /* Disable C1E state if it is enabled by BIOS */ 3916 if ((reg >> AMD_ACTONCMPHALT_SHIFT) & 3917 AMD_ACTONCMPHALT_MASK) { 3918 reg &= ~(AMD_ACTONCMPHALT_MASK << 3919 AMD_ACTONCMPHALT_SHIFT); 3920 wrmsr(MSR_AMD_INT_PENDING_CMP_HALT, reg); 3921 } 3922 } 3923 no_trap(); 3924 } 3925 #endif /* !__xpv */ 3926 } 3927 3928 #if defined(__amd64) && !defined(__xpv) 3929 /* 3930 * Patch in versions of bcopy for high performance Intel Nhm processors 3931 * and later... 3932 */ 3933 void 3934 patch_memops(uint_t vendor) 3935 { 3936 size_t cnt, i; 3937 caddr_t to, from; 3938 3939 if ((vendor == X86_VENDOR_Intel) && ((x86_feature & X86_SSE4_2) != 0)) { 3940 cnt = &bcopy_patch_end - &bcopy_patch_start; 3941 to = &bcopy_ck_size; 3942 from = &bcopy_patch_start; 3943 for (i = 0; i < cnt; i++) { 3944 *to++ = *from++; 3945 } 3946 } 3947 } 3948 #endif /* __amd64 && !__xpv */ 3949