1/* 2 * CDDL HEADER START 3 * 4 * The contents of this file are subject to the terms of the 5 * Common Development and Distribution License (the "License"). 6 * You may not use this file except in compliance with the License. 7 * 8 * You can obtain a copy of the license at usr/src/OPENSOLARIS.LICENSE 9 * or http://www.opensolaris.org/os/licensing. 10 * See the License for the specific language governing permissions 11 * and limitations under the License. 12 * 13 * When distributing Covered Code, include this CDDL HEADER in each 14 * file and include the License file at usr/src/OPENSOLARIS.LICENSE. 15 * If applicable, add the following below this CDDL HEADER, with the 16 * fields enclosed by brackets "[]" replaced with your own identifying 17 * information: Portions Copyright [yyyy] [name of copyright owner] 18 * 19 * CDDL HEADER END 20 */ 21 22/* 23 * Copyright 2007 Sun Microsystems, Inc. All rights reserved. 24 * Use is subject to license terms. 25 */ 26 27#pragma ident "%Z%%M% %I% %E% SMI" 28 29/ 30/ Inline functions specific to the i86pc kernel running on bare metal. 31/ 32 33/ 34/ return value of cr3 register 35/ 36 .inline getcr3,0 37 movq %cr3, %rax 38 .end 39 40/ 41/ reload cr3 register with its current value 42/ 43 .inline reload_cr3,0 44 movq %cr3, %rdi 45 movq %rdi, %cr3 46 .end 47 48/ 49/ return value of cr8 register 50/ 51 .inline getcr8,0 52 movq %cr8, %rax 53 .end 54 55/ 56/ set cr8 register 57/ 58 .inline setcr8,0 59 movq %rdi, %cr8 60 .end 61 62/ 63/ enable interrupts 64/ 65 .inline sti,0 66 sti 67 .end 68 69/ 70/ disable interrupts 71/ 72 .inline cli,0 73 cli 74 .end 75 76/ 77/ disable interrupts and return value describing if interrupts were enabled 78/ 79 .inline clear_int_flag,0 80 pushfq 81 cli 82 popq %rax 83 .end 84 85 .inline intr_clear,0 86 pushfq 87 cli 88 popq %rax 89 .end 90 91/ 92/ return the value of the flags register 93/ 94 .inline getflags,0 95 pushfq 96 popq %rax 97 .end 98 99/ 100/ restore interrupt enable flag to value returned from 'clear_int_flag' above 101/ 102 .inline restore_int_flag,4 103 pushq %rdi 104 popfq 105 .end 106 107 .inline intr_restore,4 108 pushq %rdi 109 popfq 110 .end 111 112/ 113/ in and out 114/ 115 .inline inb,4 116 movq %rdi, %rdx 117 xorq %rax, %rax 118 inb (%dx) 119 .end 120 121 .inline inw,4 122 movq %rdi, %rdx 123 xorq %rax, %rax 124 inw (%dx) 125 .end 126 127 .inline inl,4 128 movq %rdi, %rdx 129 xorq %rax, %rax 130 inl (%dx) 131 .end 132 133 .inline outb,8 134 movq %rdi, %rdx 135 movq %rsi, %rax 136 outb (%dx) 137 .end 138 139 .inline outw,8 140 movq %rdi, %rdx 141 movq %rsi, %rax 142 outw (%dx) 143 .end 144 145 .inline outl,8 146 movq %rdi, %rdx 147 movq %rsi, %rax 148 outl (%dx) 149 .end 150 151/* 152 * Read Time Stamp Counter 153 * uint64_t tsc_read(); 154 * 155 * usage: 156 * uint64_t cycles = tsc_read(); 157 */ 158 .inline tsc_read, 0 159 rdtsc / %edx:%eax = RDTSC 160 shlq $32, %rdx 161 orq %rdx, %rax 162 .end 163 164/* 165 * Call the halt instruction. This will put the CPU to sleep until 166 * it is again awoken via an interrupt. 167 * This function should be called with interrupts already disabled 168 * for the CPU. 169 * Note that "sti" will only enable interrupts at the end of the 170 * subsequent instruction...in this case: "hlt". 171 */ 172 .inline i86_halt,0 173 sti 174 hlt 175 .end 176/ 177/ execute the bsrw instruction 178/ 179 .inline bsrw_insn,4 180 xorl %eax, %eax 181 bsrw %di, %ax 182 .end 183 184